W155

W155 Spread Spectrum Frequency Timing Generator Features • Generates a spread spectrum timing signal (SYSCLK) and a non-spread signal (USBCLK) • Requires a 14.318-MHz crystal for operation • Supports MIPS microprocessor clock frequencies • Reduces peak EMI by as much as 12 dB • Integrated loop filter components • Cycle-to-cycle jitter = 250 ps (max) • Operates with a 3.3 or 5.0V power supply • Spread output is selectable from 10 to 133 MHz • TEST mode supports modulation off (High-Z) and special test input reference frequency • Guaranteed 45/55 duty cycle • Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline Integrated Circuit) Table 1. Frequency Selection (14.318-MHz Reference) FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SYSCLK (Output Freq.) 133.3 MHz 120 MHz 100 MHz 74.77 MHz 70 MHz 66.6 MHz 60 MHz 50 MHz 40 MHz 33.33 MHz 30 MHz 25 MHz 20 MHz 16.67 MHz 12 MHz 10 MHz Overview The W155 incorporates the latest advances in PLL-based spread spectrum frequency synthesizer technology. By frequency modulating the SYSCLK output with a low-frequency carrier, peak EMI can be greatly reduced in a system. Use of this technique allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system that uses the W155, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to SYSCLK. Therefore, the benefits of using this technique increase with the number of address and data lines in the system. The W155 is specifically targeted toward MIPS microprocessor based systems where EMI is of particular concern. Each device uses a single 14.318-MHz crystal to generate a selectable spread spectrum output and an unmodulated 48-MHz USB Output. The spreading function can be disabled by taking the SSON# pin high. Spread percentage can be selected with the SS% input (see Table 2 below). Table 2. Spread Percentage Selection SS% 0 1 [1] Spread Percentage –1.25% –3.75% Pin Configuration VDD X1 X2 GND FS3* VDD FS2* FS1* 1 2 16 15 W155 14 13 12 11 10 9 TEST VDD USBCLK/SS%* GND SYSCLK GND FS0* SSON#^ 3 4 5 6 7 8 Note: 1. Internal pull-up resistor present on inputs marked with ‘*’ and pull-down resistor present on input marked with ‘^’. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 29, 1999, rev. ** W155 Pin Definitions Pin Name USBCLK/ SS% Pin No. 14 Pin Type I/O Pin Description USB Clock Output/Modulation Width Selection Input: When an input; if spread spectrum feature is enabled, this pin is used to select the amount of frequency variation on the SYSCLK output (see Table 2). Wider variations result in greater peak EMI reduction. When an output: supplies a non-spread 48-MHz signal for USB support. System Clock Output: Frequency is selected per Table 1. Spread spectrum feature is controlled by pins 9 & 14. Frequency Select Pins: These pins set the frequency of the signal provided at the SYSCLK output. Spread Spectrum Control (active LOW): Pulling this input signal HIGH turns the internal modulating waveform off. This pin has an internal pull-down resistor. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as either an external crystal connection, or as an external reference frequency input. Crystal Connection: If using an external reference, this pin must be left unconnected. Test Mode: For normal operation, tie this pin to ground. Power Connection: Connected to either 3.3V or 5.0V power supply. All VDD pins must be the same voltage level. Ground Connection: Connect to the common system ground plane. SYSCLK FS0:3 SSON# X1 12 10, 8, 7, 5 9 2 O I I I X2 TEST VDD GND 3 16 1, 6, 15 4, 11, 13 I I P G 2 W155 Functional Description I/O Pin Operation Pin 14 is a dual purpose l/O pin. Upon power-up each I/O pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and each pin then becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-kΩ “strapping” resistor is connected between each l/O pin and ground or VDD. Connection to ground sets a “0” bit, connection to V DD sets a “1” bit. See Figure 1. Upon W155 power-up, the first 2 ms of operation is used for input logic selection. During this period, each clock output buffer is three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next the output buffer is enabled converting all l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is