W163

W163 Spread Aware™, Zero Delay Buffer Features • Spread Aware™—designed to work with SSFTG reference signals • Outputs may be three-stated • Available in 8-pin SOIC package • Extra strength output drive available (-15 version) • Internal feedback maximized the number of outputs available in 8-pin package Key Specifications Operating Voltage: ................................................ 3.3V±10% Operating Range: ................................ 10 < fOUT < 133 MHz Cycle-to-Cycle Jitter: ..................................................200 ps Output-to-Output Skew: ..............................................250 ps Device-to-Device Skew: ..............................................700 ps Propagation Delay:......................................................350 ps Block Diagram Pin Configuration SOIC REF Q0 1 2 3 4 8 7 6 5 QFB Q3 VDD Q2 REF PLL QFB Q0 Q1 Q2 Q3 Q1 GND Spread Aware is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-07149 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 02 W163 Pin Definitions Pin Name REF Q0:3 QFB VDD GND Pin No. 1 2, 3, 5, 7 8 6 4 Pin Type I O O P P Pin Description Reference Input: The output signals Q0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. Outputs: These signals will be synchronous and of equal frequency to the signal input at pin 1. Feedback Output: This output signal does not vary from signals Q0:3 in function, but is noted as the signal used to establish the propagation delay of nearly 0. Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. Ground Connections: Connect all grounds to the common system ground plane. which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress Application note titled, “EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.” Overview The W163 products are five-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signal and provide five copies of that same signal out. The internal feedback to the PLL provides outputs in phase with the reference inputs. Schematic Spread Aware Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew REF Q0 Q1 GND QFB Q3 VDD Q2 Ferrite Bead 0.1 µF 10 µF VDD Document #: 38-07149 Rev. *A Page 2 of 5 W163 Absolute Maximum Ratings[1] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating –0.5 to +7.0 –65 to +150 0 to +70 –55 to +125 0.5 Unit V °C °C °C W Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10% Parameter IDD VIL VIH VOL VOH IIL IIH Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current IOL = 12 mA (-15) IOL = 8 mA (-5) IOL = 12 mA (-15) IOL = 8 mA (-5) VIN = 0V VIN = VDD 2.4 50 100 2.0 0.4 Test Condition Unloaded, 100 MHz Min Typ Max 40 0.8 Unit mA V V V V µA µA AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10% Parameter fIN fOUT tR tF tICLKR tICLKF tPD tSK tSKDD tD tLOCK tJC Description Input Frequency Output Frequency Output Rise Time (-05) Output Rise Time (-15) Output Fall Time (-05) Input Clock Rise Time Input Clock Fall Time FBIN to REF Skew [2] [2] Test Condition 15-pF load[6] 2.0 to 0.8V, 15-pF load 2.0 to 0.8V, 20-pF load 2.0 to 0.8V, 15-pF load 2.0 to 0.8V, 20-pF load Min 10 10 Typ Max 133 133 2.5 1.5 2.5 1.5 ? ? Unit MHz MHz ns ns ns ns ns ns ps ps ps % ms ps [2] Output Rise Time (-15)[2] [2] [2] [3, 4] Measured at VDD/2 All outputs loaded equally Measured at FBIN pins, VDD/2 15-pF load[5] Power supply stable and –350 –250 –700 45 0 0 0 50 350 250 700 55 1.0 200 Output to Output Skew Device to Device Skew Duty Cycle PLL Lock Time Jitter, Cycle-to-Cycle Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. For the higher drive -15, the load is 20 pF. Document #: 38-07149 Rev. *A Page 3 of 5 W163 Ordering Information Ordering Code W163 Option -05, -15 Package Name G Package Type 8-pin Plastic SOIC (150-mil) Package Diagram 8-Pin Small Outline Integrated Circuit (SOIC, 150-mil) Document #: 38-07149 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W163 Document Title: W163 Spread Aware™, Zero Delay Buffer Document Number: 38-07149 REV. ** *A ECN NO. 110258 122798 Issue Date 12/15/01 12/14/02 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-00787 to 38-07149 Add Power up Requirements to Operating Conditions Information Document #: 38-07149 Rev. *A Page 5 of 5