W194

W194 Frequency Multiplier and Zero Delay Buffer Features • Two outputs • Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs • Available in 8-pin SOIC package Table 1. Configuration Options FBIN OUT1 OUT1 OUT1 OUT1 OUT2 Operating Voltage: .............................. 3.3V±5% or 5.0±10% Operating Range: .......................10 MHz < fOUT1 < 133 MHz Absolute Jitter: ......................................................... ±500 ps Output to Output Skew: .............................................. 250 ps Propagation Delay: ................................................... ±350 ps Propagation delay is affected by input rise time. OUT2 OUT2 OUT2 FS0 0 1 0 1 0 1 0 1 FS1 0 0 1 1 0 0 1 1 OUT1 2 X REF 4 X REF REF 8 X REF 4 X REF 8 X REF 2 X REF 16 X REF OUT2 REF 2 X REF REF/2 4 X REF 2 X REF 4 X REF REF 8 X REF Key Specifications Block Diagram FBIN External feedback connection to OUT1 or OUT2, not both Pin Configuration SOIC FBIN IN GND 1 2 3 4 8 7 6 5 OUT2 VDD OUT1 FS1 FS0 FS1 ÷Q FS0 IN Reference Input Phase Detector Charge Pump Loop Filter Output Buffer VCO ÷2 Output Buffer OUT1 OUT2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 5, 2000, rev. *A W194 Pin Definitions Pin Name IN FBIN Pin No. 2 1 Pin Type I I Pin Description Reference Input: The output signals will be synchronized to this signal. Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the REF signal input (IN). Output 1: The frequency of the signal provided by this pin is determined by the feedback signal connected to FBIN, and the FS0:1 inputs (see Table 1). Output 2: The frequency of the signal provided by this pin is one-half of the frequency of OUT1. See Table 1. Power Connections: C onnect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance. Ground Connection: Connect all grounds to the common system ground plane. Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” The W194-70 is a pin-compatible upgrade of the Cypress W42C70-01. The W194-70 addresses some application dependent problems experienced by users of the older device. OUT1 OUT2 VDD 6 8 7 O O P GND FS0:1 3 4, 5 P I Overview The W194-70 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data sheet titled CA G 10 µF Ferrite Bead V+ C8 G 0.01 µF Power Supply Connection OUT 2 FBIN 1 8 VDD 22Ω OUTPUT 2 C9 = 0.1 µF G IN 7 2 3 GND G 6 OUT 1 22Ω OUTPUT 1 FS0 4 5 FS1 Figure 1. Schematic/Suggested Layout 2 W194 How to Implement Zero Delay Typically, zero delay buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. The PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feedback and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/Buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay from the ZDB output to the ASIC/Buffer output must be accounted for. Reference Signal Feedback Input Zero Delay Buffer ASIC/ Buffer A Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. This implementation can be applied to any Figure 2. 6 Output Buffer in the Feedback Path 3 W194 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating –0.5 to +7.0 –65 to +150 0 to +70 –55 to +125 0.5 Unit V °C °C °C W Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation DC Electrical Characteristics: TA = 0°C to 70°C, VDD = 3.3V ±5% Parameter IDD VIL VIH VOL VOH IIL IIH Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current IOL = 12 mA IOL = 8 mA IOL = 12 mA IOL = 8 mA VIN = 0V VIN = VDD 2.4 5 5 2.0 0.4 Test Condition Unloaded, 100 MHz Min Typ 17 Max 35 0.8 Unit mA V V V V µA µA DC Electrical Characteristics: TA = 0°C to 70°C, VDD = 5V ±10% Parameter IDD VIL VIH VOL VOH IIL IIH Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current IOL = 12 mA IOL = 8 mA IOL = 12 mA IOL = 8 mA VIN = 0V VIN = VDD 2.4 5 5 2.0 0.4 Test Condition Unloaded, 100 MHz Min Typ 17 Max 35 0.8 Unit mA V V V V µA µA 4 W194 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% Parameter fIN fOUT tR tF tICLKR tICLKF tPD tD tLOCK tJC Description Input Frequency [1] Test Condition OUT2 = REF OUT1 15-pF load [6] Min Typ Max Unit MHz Output Frequency Output Rise Time Output Fall Time Input Clock Rise Time Input Clock Fall Time FBIN to REF Skew Duty Cycle PLL Lock Time Jitter, Cycle-to-Cycle [2] [2] 10 133 3.5 2.5 10 10 MHz ns ns ns ns ns % ms ps 2.0V to 0.8V, 15-pF load 2.0V to 0.8V, 15-pF load [3, 4] Measured at VDD/2 15-pF load [5] –2 40 0.6 50 2 60 1.0 300 Power supply stable AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5.0V ±10% Parameter fIN fOUT tR tF tICLKR tICLKF tPD tD tLOCK tJC Description Input Frequency [1] Test Condition OUT2 = REF OUT1 15-pF load [6] Min Typ Max Unit MHz Output Frequency Output Rise Time Output Fall Time Input Clock Rise Time Input Clock Fall Time FBIN to REF Skew Duty Cycle PLL Lock Time Jitter, Cycle-to-Cycle [2] [2] 10 133 2.5 1.5 10 10 MHz ns ns ns ns ns % ms ps 2.0V to 0.8V, 15-pF load 2.0V to 0.8V, 15-pF load [3, 4] Measured at VDD/2 15-pF load [5, 7] –2 40 0.6 50 2 60 1.0 200 Power supply stable Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. For the higher drive -11, the load is 20 pF. 7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case. Ordering Information Ordering Code W194 Document #: 38-00794-A Option -70 Package Name G Package Type 8-pin SOIC (150-mil) 5 W194 Package Diagram 8-Pin Small Outlined Integrated Circuit (SOIC, 150-mil) © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.