W216

PRELIMINARY W216 Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 Features • Maximized EMI Suppression using Cypress’s Spread Spectrum Technology • Single chip system FTG for Intel® 440BX AGPset and VIA Apollo Pro-133 • Three copies of CPU output • Seven copies of PCI output • One 48-MHz output for USB / One 24-MHz for SIO • Two buffered reference outputs • Two IOAPIC outputs • Seventeen SDRAM outputs provide support for 4 DIMMs • Supports frequencies up to 150 MHz • I2C™ interface for programming • Power management control inputs Table 1. Mode Input Table Mode 0 1 Pin 3 PCI_STOP# REF0 Key Specifications CPU Cycle-to-Cycle Jitter: .......................................... 250 ps CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew: ............................................ 500 ps SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ. VDDQ3: .................................................................... 3.3V±5% VDDQ2: .................................................................... 2.5V±5% SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ. Table 2. Pin Selectable Frequency Input Address CPU_F, 1:2 PCI_F, 0:5 FS3 FS2 FS1 FS0 (MHz) (MHz) 1 1 1 1 133.3 33.3 (CPU/4) 1 1 1 0 124 31 (CPU/4) 1 1 0 1 150 37.5 (CPU/4) 1 1 0 0 140 35 (CPU/4) 1 0 1 1 105 35 (CPU/3) 1 0 1 0 110 36.7 (CPU/3) 1 0 0 1 115 38.3 (CPU/3) 1 0 0 0 120 40 (CPU/3) 0 1 1 1 100 33.3 (CPU/3) 0 1 1 0 Reserved 0 1 0 1 112 37.3 (CPU/3) 0 1 0 0 103 34.3 (CPU/3) 0 0 1 1 66.8 33.4 (CPU/2) 0 0 1 0 83.3 41.7 (CPU/2) 0 0 0 1 75 37.5 (CPU/2) 0 0 0 0 Reserved Block Diagram VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC REF1/FS2 PLL Ref Freq Stop Clock Control Pin Configuration VDDQ3 REF1/FS2 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI0/FS3 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 SDRAMIN SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 [1] I/O Pin Control CLK_STOP# VDDQ2 IOAPIC_F IOAPIC0 VDDQ2 CPU_F PLL 1 ÷2,3,4 Stop Clock Control CPU1 CPU2 VDDQ3 PCI_F/MODE PCI0/FS3 PCI1 PCI2 PCI3 Stop Clock Control SDATA SCLK I2C Logic PCI4 PCI5 VDDQ3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 IOAPIC0 IOAPIC_F GND CPU_F CPU1 VDDQ2 CPU2 GND CLK_STOP# SDRAM_F VDDQ3 SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 VDDQ3 24MHz/FS0 48MHz/FS1 PLL2 Stop Clock Control 48MHz/FS1 24MHz/FS0 VDDQ3 SDRAM0:15 16 SDRAM_F SDRAMIN Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor. W216 Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 27, 1999, rev. ** PRELIMINARY Pin Definitions Pin Name CPU1:2 CPU_F PCI1:5 PCI0/FS3 Pin No. 51, 49 52 11, 12, 13, 14, 16 9 W216 PCI_F/MODE 8 CLK_STOP# 47 IOAPIC_F 54 IOAPIC0 48MHz/FS1 55 29 24MHz/FS0 30 REF1/FS2 REF0 (PCI_STOP#) 2 3 SDRAMIN SDRAM0:15 17 44, 43, 41, 40, 39, 38, 36, 35, 22, 21, 19, 18, 33, 32, 25, 24 46 28 27 5 Pin Type Pin Description CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input O interface, see Tables 2 and 6. These outputs are affected by the CLK_STOP# input. Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input O interface, see Tables 2 and 6. This output is not affected by the CLK_STOP# input. PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input O interface, see Tables 2 and 6. These outputs are affected by the PCI_STOP# input. I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When an input, selects function of pin 3 as described in Table 1. CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after comI pleting a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs start beginning with a full clock cycle (2–3 CPU clock latency). Free-running IOAPIC Output: This output is a buffered version of the reference input O which is not affected by the CPU_STOP# logic input. It’s swing is set by voltage applied to VDDQ2. I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW. I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be latched, setting output frequencies as described in Table 2. I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched, setting output frequencies as described in Table 2. I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input will be latched, setting output frequencies as described in Table 2. I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz). Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs I (SDRAM0:15, SDRAM_F). Buffered Outputs: These sixteen dedicated outputs provide copies of the signal proO vided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. O I I/O I Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input. Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs buffers, PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Connect to 3.3V. Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. SDRAM_F SCLK SDATA X1 X2 VDDQ3 6 1, 7, 15, 20, 31, 37, 45 50, 56 I P VDDQ2 P 2 PRELIMINARY Pin Definitions (continued) Pin Name GND W216 Pin Pin No. Type Pin Description Ground Connections: Connect all ground pins to the common system ground plane. 4, 10, 23, 26, G 34, 42, 48, 53 tor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output (