W254B

W254B 133-MHz Spread Spectrum FTG for Mobile Pentium® III Platforms Features • Maximized EMI suppression using Cypress’s Spread Spectrum technology (–0.5% and ±0.5%) • Single chip system FTG for Mobile Intel® Platforms • Two CPU outputs • Seven copies of PCI clock (one Free Running) • Seven SDRAM clock (one DCLK for Memory Hub) • Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video DOT clock • Three 3V66 Hublink/AGP outputs • One VCH clock (48-MHz non-SSC or 66.67-MHz SSC) • One APIC outputs • One buffered reference output • Supports frequencies up to 133 MHz • SMBus interface for programming • Power management control inputs APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ...................................................500 ps CPU Output Skew: ......................................................150 ps 3V66 Output Skew: .....................................................175 ps APIC, SDRAM Output Skew: ......................................250 ps PCI Output Skew:........................................................500 ps VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM): ......... 3.3V±5% VDDQ2 (CPU, APIC):....... 2.5V±5%in Selectable Frequency Table 1. Pin Selectable Frequency Input Address FS1 FS0 0 0 0 1 1 0 1 1 Output Frequencies CPU SDRAM 48MHz PCI APIC REF 3V66 66 100 48 33 14.318 66 100 100 MHz MHz MHz MHz 133 133 133 100 Key Specifications CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps Block Diagram X1 X2 Pin Configuration PLL Ref Freq VDD_REF REF XTAL OSC PLL 1 Divider Network Stop Clock Control VDD_CPU CPU CPU_F CPU_STP# VDD_APIC APIC VDD_SDRAM DCLK SDRAM0:5 VDD_PCI PCI_F/FS0 PWR_DWN# Stop Clock Control PCI1/FS1 PCI2:6 PCI_STP# VDD_3V66 3V66_0:1 3V66_AGP VDD_48 PLL2 USB (48MHz) DOT (48MHz) VDD_REF X1 X2 GND_REF GND_PCI PCI_F/FS0^ PCI1/FS1^ PCI2 VDD_PCI PCI3 PCI4 PCI5 PCI6 VDD_3V66 3V66_0 3V66_1 3V66_AGP GND_3V66 VCH_CLK GND_48 USB DOT VDD_48 GND_CORE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF APIC VDD_APIC VDD_CPU CPU CPU_F GND_CPU GND_SDRAM SDRAM0 SDRAM1 VDD_SDRAM SDRAM2 SDRAM3 GND_SDRAM SDRAM4 SDRAM5 DCLK VDD_SDRAM CPU_STP# PCI_STP# PWR_DWN# SCLK SDATA VDD_CORE SDATA SCLK SMBus Logic VCH_CLK Note: 1. Internal pull-down or pull-up resistors present on inputs marked with * or ^ respectively. Design should not rely solely on internal pull-up or pull-down resistor to set I/O pins HIGH or LOW respectively. W254B Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07233 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 22, 2002 W254B Pin Definitions Pin Name CPU CPU_F PCI1:6, PCI_F/FS0, PCI1/FS1 APIC SDRAM0:5, DCLK 3V66_0:1, 3V66_AGP USB DOT REF VCH_CLK PWR_DWN# CPU_STP# PCI_STP# SCLK SDATA X1 Pin No. 44, 43 8, 10, 11, 12, 13, 6, 7 Pin Type O I/O Pin Description CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial input interface. The CPU output is gated by the CLK_STOP# input. 33-MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by the PCI_STOP# input. Upon power up, FS0 and FS1 is configured momentarily as input latches allowing various output frequencies to be selected. See Table 2. APIC Output: 2.5V fixed 33.3-MHz clock. This output is synchronous to the CPU clock. SDRAM Output Clocks: 3.3V outputs running at either 100 MHz or 133 MHz depending on the setting of FS0:1 inputs. DCLK is a free-running clock. 66-MHz Clock Outputs: 3.3V fixed 66-MHz clock. USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output. Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal. Reference Clock: 3.3V 14.318-MHz clock output. Video Control Hub Clock Output: 3.3V selectable 48-MHz non-spread spectrum or 66.67-MHz spread spectrum clock output. Power-Down Control: 3.3V LVTTL-compatible input that places the device in power-down mode when held LOW. CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0 clock. Output remains in the LOW state. PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks. Output remains in the LOW state. SMBus Clock Input: Clock pin for SMBus circuitry. SMBus Data Input: Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 47 40, 39, 37, 36, 34, 33, 32 15, 16, 17 21 22 48 19 28 30 29 27 26 2 O O O O O O O I I I I I/O I X2 VDD_REF, VDD_PCI, VDD _3V66, VDD_48, VDD_CORE, VDD_SDRAM, VDD_SDRAM VDD_APIC, VDD_CPU GND_REF, GND_PCI, GND_3V66, GND_48, GND_CORE GND_SDRAM, GND_SDRAM, GND_CPU 3 1, 9, 14, 23, 25, 31, 38 O P 45, 46 4, 5, 18, 20, 24, 35, 41, 42 P G 2.5V Power Connection: Power for APIC and CPU output buffers. Connect to 2.5V. Ground Connection: Connect all ground pins to the common system ground plane. Document #: 38-07233 Rev. *A Page 2 of 17 W254B VDD Output Strapping Resistor 10 kΩ (Load Option 1) W254B Power-on Reset Timer Output Buffer Output Three-state Q Series Termination Resistor Clock Load Hold Output Low D 10 kΩ (Load Option 0) Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Overview The W254B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics-integrated core logic. ing clock outputs. The 2-ms timer starts when VDDQ3 reaches 2.0V. The input bits can only be reset by turning VDDQ3 off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock output is 40Ω (nominal), which is minimally affected by the 10-kΩ strap to ground or VDDQ3. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDDQ3 should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered, assuming that VDDQ3 has stabilized. If VDDQ3 has not yet reached full value, output frequency initially may be below target but will increase to target once VDDQ3 voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Functional Description I/O Pin Operation Pins 6 and 7 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-kΩ “strapping” resistor is connected between each l/O pin and ground or VDDQ3. Connection to ground sets a latch to “0”, connection to VDDQ3 sets a latch to “1”. Figure 1 shows one suggested method for strapping resistor connection. Upon W254B power-up, the first 2 ms of operation is used for input logic selection. During this period, the PCI_F and PCI1 clock output buffers are three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or logic LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O is pin is latched. Next the output buffers are enabled, converting all l/O pins into operatTable 2. Frequency Select Truth Table[2] Input Address FS1 0 0 1 1 FS0 0 1 0 1 CPU 66 100 133 133 SDRAM 100 100 133 100 48 MHz 48 MHz [3] CPU/ SDRAM Frequency Selection CPU output frequency is selected with I/O pins 6 and 7. For CPU/SDRAM frequency programming information refer to Table 2. Alternatively, frequency selections are available through the serial data interface. Output Frequencies PCI APIC REF 3V66 33 MHz 14.318 MHz 66 MHz Notes: 2. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 3. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. Document #: 38-07233 Rev. *A Page 3 of 17 W254B Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W254B when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, 0 ns 10 ns Cycle Repeats respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs. 20 ns 30 ns 40 ns CPU 66-MHz SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 2. Group Offset Waveforms (66 Mhz CPU/100 MHz SDRAM Clock) Table 3. 66 MHz Group Timing Relationships and Tolerances CPU to SDRAM Offset Tolerance –2.5 ns 500 ps CPU to 3V66 7.5 ns 500 ps SDRAM to 3V66 0.0 ns 500 ps 3V66 to PCI 1.5-3.5 ns 500 ps PCI to APIC 0.0 ns 1.0 ns USB & DOT Async N/A 0 ns 10 ns Cycle Repeats 20 ns 30 ns 40 ns CPU 100-MHz SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 3. Group Offset Waveforms (100 MHz CPU/100 MHz SDRAM Clock) Document #: 38-07233 Rev. *A Page 4 of 17 W254B Table 4. 100 MHz Group Timing Relationships and Tolerances CPU to SDRAM Offset Tolerance 5.0 ns 500 ps CPU to 3V66 5.0ns 500 ps SDRAM to 3V66 0.0 ns 500 ps 3V66 to PCI 1.5-3.5 ns 500 ps PCI to APIC 0.0 ns 1.0 ns USB & DOT Async N/A 0 ns 10 ns Cycle Repeats 20 ns 30 ns 40 ns CPU 133-MHz SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock) Table 5. 133 MHz/SDRAM 100 MHz Group Timing Relationships and Tolerances CPU to SDRAM Offset Tolerance 0.0 ns 500 ps CPU to 3V66 0.0 ns 500 ps SDRAM to 3V66 0.0 ns 500 ps 3V66 to PCI 1.5-3.5 ns 500 ps PCI to APIC 0.0 ns 1.0 ns USB & DOT Async N/A 0 ns 10 ns Cycle Repeats 20 ns 30 ns 40 ns CPU 133-MHz SDRAM 133-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 5. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock) Document #: 38-07233 Rev. *A Page 5 of 17 W254B Table 6. 133 MHz/SDRAM Test Mode Group Timing Relationships and Tolerance CPU to SDRAM Offset Tolerance Power-Down Control W254B provides one PWR_DWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW. 3.75 ns 500 ps CPU to 3V66 0.0 ns 500 ps SDRAM to 3V66 3.75 ns 500 ps 3V66 to PCI 1.5-3.5 ns 500 ps PCI to APIC 0.0 ns 1.0 ns USB& DOT Async N/A 0 ns 25 ns 50 ns 75 ns Center 1 VCO Internal CPU 100-MHz 3V66 66-MHz PCI 33 MHz APIC 33-MHz PwrDwn SDRAM 100-MHz REF 14.318-MHz USB 48-MHz 2 Figure 6. W254B PWR_DWN# Timing Diagram[4, 5, 6, 7] Table 7. W254B Maximum Allowed Current Max. 2.5V supply consumption Max. discrete cap loads, VDDQ2 = 2.625V All static inputs = VDDQ3 or VSS < 1 mA 70 mA 100 mA 100 mA Max. 3.3V supply consumption Max. discrete cap loads VDDQ3 = 3.465V All static inputs = VDDQ3 or VSS < 1 mA 280 mA 280 mA 280 mA W254B Condition Powerdown Mode (PWR_DWN# = 0) Full Active 66 MHz FS1:0 = 00 (PWR_DWN# =1) Full Active 100 MHz FS1:0 = 01 (PWR_DWN# =1) Full Active 133 MHz FS1:0 = 11 (PWR_DWN# =1) Notes: 4. Once the PWR_DWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 5. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W254B. 6. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states. 7. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz. Document #: 38-07233 Rev. *A Page 6 of 17 W254B Spread Spectrum Frequency Timing Generation The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 7. As shown in Figure 7, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 8. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is +0.5% or –0.5% of the selected frequency. Figure 8 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the SMBus data stream. Refer to page 9 for more details. EMI Reduction SSFTG Typical Clock Amplitude (dB) Amplitude (dB) Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) Center Spread Frequency Span (MHz) Down Spread Figure 7. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MAX. FREQUENCY 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% MIN. Figure 8. Typical Modulation Profile Document #: 38-07233 Rev. *A 100% Page 7 of 17 W254B 1 bit Start bit 7 bits Slave Address 1 R/W 1 Ack 8 bits Command Code 1 Ack Byte Count = N Ack 1 bit Data Byte 1 8 bits Ack 1 Data Byte 2 8 bits Ack 1 ... Data Byte N 8 bits Ack 1 Stop 1 Figure 9. An Example of a Block Write[8] Serial Data Interface The W254B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to Table 8. Example of Possible Byte Count Value Byte Count Byte MSB 0000 0000 0000 0000 0000 0000 0000 0000 0010 LSB 0000 0001 0010 0011 0100 0101 0110 0111 0000 Not allowed. Must have at least one byte Data for functional and frequency select register (currently byte 0 in spec) Writes first two bytes of data (byte 0 then byte 1) Writes first three bytes (byte 0, 1, 2 in order) Writes first four bytes (byte 0, 1, 2, 3 in order) Writes first five bytes (byte 0, 1, 2, 3, 4 in order) Writes first six bytes (byte 0, 1, 2, 3, 4, 5 in order) Writes first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) Max. byte count supported = 32 Notes transfer a maximum of 32 data bytes. The slave receiver address for W254B is 11010010. Figure 9 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W254B expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 8 shows an example of a possible byte count value. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W254B. However, these bytes must be included in the data write sequence to maintain proper byte allocation. Note: 8. The acknowledgment bit is returned by the slave/receiver (W254B). Document #: 38-07233 Rev. *A Page 8 of 17 W254B W254B Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0 = Disable)[9] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 19 -43 44 -22 21 -VCH_CLK Reserved Drive to ’0’ CPU_F CPU Spread Spectrum (1 = On; 0 = Off) DOT (48 MHz) USB (48 MHz) Reserved Drive to ’0’ Name (Active/Inactive) (Active/Inactive) (Disabled/Enabled) (Disabled/Enabled) (Active/Inactive) (Disabled/Enabled) (Disabled/Enabled) (Active/Inactive) Pin Description 2. All unused register bits (reserved and N/A) should be written to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. Byte 1: Control Register (1 = Enable, 0 = Disable)[9] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --33 34 36 37 39 40 Name Reserved Drive to ’0’ Reserved Drive to ’0’ SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 (Active/Inactive) (Active/Inactive) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) Pin Description Byte 2: Control Register (1 = Enable, 0 = Disable)[9] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 17 16 15 -----3V66_AGP 3V66_1 3V66_0 Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Name Pin Description (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Note: 9. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. Document #: 38-07233 Rev. *A Page 9 of 17 W254B Byte 3: Control Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 13 12 11 10 8 7 -PCI6 PCI5 PCI4 PCI3 PCI2 PCI1/FS1 SDRAM 133-MHz Mode Enable Name Reserved Drive to ’0’ Pin Description (Active/Inactive) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) (Disabled/Enabled) Default is Disabled = ‘0’, Enabled = ’1’ Byte 4: Control Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 19 Name VCH_CLK SSC Mode 0 = 48 MHz non-SSC (default) 1 = 66 MHz SSC Pin Description (Disabled/Enabled) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Byte 5: Control Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Reserved Drive to ‘0’ Spread Spectrum and Overclocking Mode Select. See Table 9 Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ’0’ Reserved Drive to ‘0’ Reserved Drive to ‘0’ Pin Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) By enabling Byte 5, (bits 5 and 6) spread spectrum can be increased to +0.5% and /or overclocking of either 5%, 10% or 15% can be enabled. It is not necessary to access Byte 5 if these additional features are not implemented. All outputs will default to 0% overclocking upon power up, with either 0% or –0.5% spread spectrum. Byte 5 has been provided as an optional register to enable a greater degree of spread spectrum and overclocking performance for all PLL1 outputs. (CPU, SDRAM, DCLK, APIC, PCI, 3V66 and VCH_CLK) Document #: 38-07233 Rev. *A Page 10 of 17 W254B Table 9. Spread Spectrum and Overclocking Mode Select Byte 0 Bit 3 Spread Spectrum ON 0 0 1 1 0 Spread Spectrum OFF 0 1 1 Byte 5 Bit 5 Bit 6 0 1 0 1 0 1 0 1 SS % –0.5% ±0.5% –0.5% ±0.5% Overclock % 0% 0% 5% [10] Description and Comments No overclocking (Default) No overclocking 5% [10] 0% 10% [10] 5% [10] 15% [10] No overclocking Note: 10. Overclocking not tested; characterized at room temperature only. Base Frequency determined through hardware select pins, FS0 & FS1. Document #: 38-07233 Rev. *A Page 11 of 17 W254B DC Electrical Characteristics [11] Absolute Maximum DC Power Supply Parameter VDD3 VDDQ2 VDDQ3 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage 3.3V Supply Voltage Storage Temperature Min. –0.5 –0.5 –0.5 –65 Max. 4.6 3.6 4.6 150 Unit V V V °C Absolute Maximum DC I/O Parameter Vih3 Vil3 ESD prot. Description 3.3V Input High Voltage 3.3V Input Low Voltage Input ESD Protection Min. –0.5 –0.5 2000 Max. 4.6 Unit V V V DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V±5% Vih3 Vil3 Iil VDDQ2 = 2.5V±5% Voh2 Vol2 VDDQ3 = 3.3V±5% Voh3 Vol3 VDDQ3 = 3.3V±5% Vpoh3 Vpol3 Cin Cxtal Cout Lpin PCI Bus Output High Voltage PCI Bus Output Low Voltage Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance 0 13.5 Ioh = (–1 mA) Iol = (1 mA) 2.4 0.55 5 22.5 6 7 V V pF pF pF nH °C 3.3V Output High Voltage 3.3V Output Low Voltage Ioh = (–1 mA) Iol = (1 mA) 2.4 0.4 V V 2.5V Output High Voltage 2.5V Output Low Voltage Ioh = (–1 mA) Iol = (1 mA) 2.0 0.4 V V 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current[12] 0