W40S01-04H

1W40S01-04 W40S01-04 SDRAM Buffer - 4 DIMM Features Key Specifications • Eighteen skew controlled CMOS outputs (SDRAM0:17) • Supports four SDRAM DIMMs • Ideal for high-performance systems designed around Intel®’s 440BX chip set • SMBus serial configuration interface • Output skew between any two outputs is less than 250 ps • 1 to 5 ns propagation delay • DC to 133-MHz operation • Single 3.3V supply voltage • Low power CMOS design packaged in a 48-pin SSOP (Small Shrink Outline Package) Overview Supply Voltages:..................................... VDDQ3 = 3.3V ± 5% Operating Temperature:.................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: ...................................VDDQ3 + 0.5V Input Frequency:............................................... 0 to 133 MHz BUF_IN to SDRAM0:17 Propagation Delay: ......1.0 to 5.0 ns Output Edge Rate:.................................................. >1.5 V/ns Output Skew: ............................................................ ±250 ps Output Duty Cycle: .................................. 45/55% worst case Output Impedance:...............................................15Ω typical Output Type: ................................................ CMOS rail-to-rail The Cypress W40S01-04 is a low-voltage, eighteen-output signal buffer. Output buffer impedance is approximately 15Ω which is ideal for driving SDRAM DIMMs. Part to Part Skew:........................................................700 ps Pin Configuration Block Diagram SDATA SCLOCK Serial Port Device Control OE SSOP SDRAM0 NC NC VDDQ3 SDRAM0 SDRAM1 GND VDDQ3 SDRAM2 SDRAM3 GND BUF_IN VDDQ3 SDRAM4 SDRAM5 GND VDDQ3 SDRAM6 SDRAM7 GND VDDQ3 SDRAM16 GND VDDQ3 SDATA [1] SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 NC NC VDDQ3 SDRAM15 SDRAM14 GND VDDQ3 SDRAM13 SDRAM12 GND OE [1] VDDQ3 SDRAM11 SDRAM10 GND VDDQ3 SDRAM9 SDRAM8 GND VDDQ3 SDRAM17 GND GND [1] SCLOCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDRAM16 SDRAM17 Note: 1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs (not CMOS level). Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 5, 2001 W40S01-04 Pin Definitions Pin No. Pin Type 4, 5, 8, 9, 13, 14, 17, 18, 21, 28, 31, 32, 35, 36, 40, 41, 44, 45 O SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. BUF_IN 11 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SDATA 24 I/O SMBus Data Input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor. SCLOCK 25 I SMBus clock Input: The SMBus data clock should be presented to this input as described in the SMBus section of this data sheet. Internal 250-kΩ pull-up resistor. VDDQ3 3, 7, 12, 16, 20, 23, 29, 33, 37, 42, 46 P Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. GND 6, 10, 15, 19, 22, 26, 27, 30, 34, 39, 43 G Ground Connection: Connect all ground pins to the common system ground plane. OE 38 I Output Enable: Internal 250-kΩ pull-up resistor. Three-states outputs when LOW. NC 1, 2, 47, 48 - No Connect: Do not connect. Pin Name SDRAM0:17 Pin Description 2 W40S01-04 Functional Description Output Drivers The W40S01-04 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15Ω. Output Control Pins Outputs three-stated when OE = 0, and toggle when OE = 1. Outputs are in phase with BUF_IN but are phase delayed by 1 to 5 ns. Outputs can also be controlled via the SMBus interface. Operation Data is written to the W40S01-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1. Table 1. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Commands the W40S01-04 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S01-04 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W40S01-04, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W40S01-04, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 2 5 Data Byte 1 6 Data Byte 2 The data bits in these bytes set internal W40S01-04 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. 7 Data Byte 3 Don’t Care Refer to Cypress clock drivers. 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 Bit Sequence Byte Description 3 W40S01-04 Writing Data Bytes Table 2 gives the bit formats for registers located in Data Bytes 0–6. Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 2. Data Bytes 0–2 Serial Configuration Map[2] Affected Pin Bit(s) Pin No. Pin Name Bit Control Control Function 0 1 Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 18 SDRAM7 Clock Output Disable Low Active 6 17 SDRAM6 Clock Output Disable Low Active 5 14 SDRAM5 Clock Output Disable Low Active 4 13 SDRAM4 Clock Output Disable Low Active 3 9 SDRAM3 Clock Output Disable Low Active 2 8 SDRAM2 Clock Output Disable Low Active 1 5 SDRAM1 Clock Output Disable Low Active 0 4 SDRAM0 Clock Output Disable Low Active Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 45 SDRAM15 Clock Output Disable Low Active 6 44 SDRAM14 Clock Output Disable Low Active 5 41 SDRAM13 Clock Output Disable Low Active 4 40 SDRAM12 Clock Output Disable Low Active 3 36 SDRAM11 Clock Output Disable Low Active 2 35 SDRAM10 Clock Output Disable Low Active 1 32 SDRAM9 Clock Output Disable Low Active 0 31 SDRAM8 Clock Output Disable Low Active Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 28 SDRAM17 Clock Output Disable Low Active 6 21 SDRAM16 Clock Output Disable Low Active 5 N/A Reserved (Reserved) -- -- 4 N/A Reserved (Reserved) -- -- 3 N/A Reserved (Reserved) -- -- 2 N/A Reserved (Reserved) -- -- 1 N/A Reserved (Reserved) -- -- 0 N/A Reserved (Reserved) -- -- Note: 2. At power-up all SDRAM outputs are enabled and active. Program Reserved bits to 0. 4 W40S01-04 How To Use the Serial Data Interface logic 1. All bus devices generally have logic inputs to receive data. Electrical Requirements Although the W40S01-04 is a receive-only device (no data write-back capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. Figure 1 illustrates electrical characteristics for the serial interface bus used with the W40S01-04. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. VDD VDD ~ 2k Ω Ω ~ 2kΩ SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT SDATA SCLOCK DATA IN N DATA OUT CLOCK IN N DATA IN DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 1. Serial Interface Bus Electrical Characteristics 5 SDATA N W40S01-04 Signaling Requirements Sending Data to the W40S01-04 As shown in Figure 2, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). A write sequence is initiated by a “start bit” as shown in Figure 3. A “stop bit” signifies that a transmission has ended. As stated previously, the W40S01-04 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 4. SDATA SCLOCK Valid Data Bit Change of Data Allowed Figure 2. Serial Data Bus Valid Data Bit SDATA SCLOCK Start Bit Stop Bit Figure 3. Serial Data Bus Start and Stop Bit 6 Figure 4. Serial Data Bus Write Sequence 7 SCLOCK SDATA 1 SCLOCK 2 1 tSTHD tR tLOW Signaling by Clock Device SDATA MSB 1 SDATA 3 0 tF tHIGH 4 1 5 0 Slave Address (First Byte) Signaling from System Core Logic Start Condition 6 0 tDSU 7 1 8 LSB 0 A tDHD 1 MSB 2 4 5 6 tSP Acknowledgment Bit from Clock Device 3 Command Code (Second Byte) 7 8 LSB A 1 2 tSPSU MSB 3 4 tSTHD Byte Count (Third Byte) 1 MSB 2 4 tSPSU 3 6 tSPF 5 Last Data Byte (Last Byte) 7 8 LSB A Stop Condition W40S01-04 Figure 5. Serial Data Bus Timing Diagram W40S01-04 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V ± 5% Parameter Description Test Condition/ Comments Min. Typ. Max. Unit IDD 3.3V Supply Current BUF_IN = 100 MHz 320 mA IDD Tristate 3.3V Supply Current in Three-state BUF_IN = 100 MHz 5 mA Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) VIL Input Low Voltage GND–0.3 0.8 VIH Input High Voltage 2.0 VDDQ3+0.5 V IILEAK Input Leakage Current, BUF_IN –5 +5 µA IILEAK Input Leakage Current[3] –20 +5 µA 50 mV Logic Outputs (SDRAM0:17) V [4] VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 70 110 185 mA IOH Output High Current VOH = 1.5V 65 100 160 mA 5 pF V Pin Capacitance/Inductance CIN Input Pin Capacitance (Except BUF_IN) COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Notes: 3. OE, SCLOCK, and SDATA logic pins have a 250-kΩ internal pull-up resistor (not CMOS level). 4. Outputs loaded by 6" 60Ω transmission lines with 20-pF capacitors. 8 W40S01-04 AC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V ± 5% (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition Min. Typ. Max. Unit 0 133 MHz 4.0 V/ns fIN Input Frequency tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4.0 V/ns tSR Output Skew, Rising Edges 250 ps tSF Output Skew, Falling Edges 250 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 1.0 5.0 ns tPF Falling Edge Propagation Delay 1.0 5.0 ns tD Duty Cycle 45 55 % Zo AC Output Impedance TSPP Part to Part Skew 700 ps Measured at 1.5V Ordering Information Ordering Code W40S01 Ω 15 Freq. Mask Code Package Name 04 H Package Type 48-pin SSOP (300 mils) Document #: 38-00811-*A 9 W40S01-04 Layout Example +3.3V Supply NC NC G G G G G SDATA G G V V G G G G V V G G G V G G V W40S01-04 G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G V G G V G G G G V V G G V G G 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C = 0.1 µF G = VIA to GND plane layer V =VIA to supply plane layer 10 NC NC G G G G G SCLOCK s01-04: 7/99 Revision: April 5, 2001 W40S01-04 Package Diagram 48-Pin Shrink Small Outline Package (SSOP, 0.300 inch) © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.