PRELIMINARY
W48S87-04
Spread Spectrum 3 DIMM Desktop Clock
Features
• Outputs — 4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz) — 7 PCI (3.3V) — 1 48-MHz for USB (3.3V) — 1 24-MHz for Super I/O (3.3V) — 2 REF (3.3V) — 1 IOAPIC (2.5V or 3.3V) — 12 SDRAM • Serial data interface provides additional frequency selection, individual clock output disable, and other functions • Smooth transition supports dynamic frequency assignment • Frequency selection not affected during power down/up cycle • Supports a variety of power-saving options • 3.3V operation • Available in 48-pin SSOP (300 mils)
Key Specifications
±0.5% Spread Spectrum Modulation: ......................... ±0.5% Jitter (Cycle-to-Cycle): .................................................250 ps Duty Cycle: ................................................................ 45-55% CPU-PCI Skew: ........................................................ 1 to 4 ns PCI-PCI or CPU-CPU Skew: .......................................250 ps Table 1. Pin Selectable Frequency[1] Input Address FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU, SDRAM Clocks (MHz) 50.0 75.0 83.3 68.5 55.0 75.0 60.0 66.8 PCI Clocks (MHz) 25.0 32.0 41.65 34.25 27.5 37.5 30.0 33.4
Block Diagram
SDATA SCLOCK Serial Port Device Control PLL Ref Freq X1 X2 CPU3.3#_2.5 FS0 FS1 FS2 XTAL OSC CPU Clock Mode Control Freq Select I/O MODE VDDL1 IOAPIC PLL1 VDDL2 Stop Clock Cntrl CPU_STOP# ÷2 4 CPU0:3 VDD3 12 SDRAM0:11 VDD2 I/O I/O 4 PCI_F/FS1 PCI0/FS2 PCI1:4 PCI5(PWR_DWN#) VDD1 I/O I/O 48MHZ/FS0 24MHZ/MODE VDD1 REF0/CPU3.3#_2.5 REF1(CPU_STOP#)
Pin Configuration [2]
VDD1 REF0/CPU3.3#_2.5 GND X1 X2 VDD2 PCI_F/FS1 PCI0/FS2 GND PCI1 PCI2 PCI3 PCI4 VDD2 PCI5(PWR_DWN#) GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1(CPU_STOP#) GND CPU0 CPU1 VDDL2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 GND 48MHZ/FS0 24MHZ/MODE
W48S87-04
PWR_DWN#
Power Down Control ÷2 PLL2 ÷4
MODE
Notes: 1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 10. 2. Signal names in parenthesis denotes function is selectable through mode pin register strapping.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600 October 19, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:3 Pin No. 44, 43, 41, 40 Pin Type O Pin Description
W48S87-04
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDL2 and output characteristics are adjusted by input CPU3.3#_2.5. Fixed PCI Clock Output and Frequency Selection Bit 1: As an output, this pin works in conjunction with PCI0:5. Output voltage swing is controlled by voltage applied to VDD2. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
PCI_F/FS1
7
I/O
PCI0/FS2
8
I/O
PCI Bus Clock Output 0 and Frequency Selection Bit 2: As an output, this pin works in conjunction with PCI1:5 and PCI_F. Output voltage swing is controlled by voltage applied to VDD2. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
PCI1:4 PCI5(PWR_DWN#)
10, 11, 12, 13 15
O I/O
PCI Bus Clock Outputs 1 through 4: Output voltage swing is controlled by voltage applied to VDD2. PCI Bus Clock Output 5 or Power-Down Control: As an output, this pin works in conjunction with PCI0:4 and PCI_F. Output voltage swing is controlled by voltage applied to VDD2. If programmed as an input (refer to MODE pin description), this pin is used for power-down control. When LOW, the device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency).
SDRAM0:11
38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 47 26
O
SDRAM Clock Outputs 0 through 11: These twelve SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDD3. I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDL1. 48-MHz Output and Frequency Selection Bit 0: Fixed clock output that defaults to 48 MHz following device power-up. Output voltage swing is controlled by voltage applied to VDD1. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
IOAPIC 48MHZ/FS0
O I/O
24MHZ/MODE
25
I/O
24-MHz Output and Mode Control Input: Fixed clock output that defaults to 24 MHz following device power-up. Output voltage swing is controlled by voltage applied to VDD1. When an input, this pin is used for pin programming selection. It determines the functions for pins 15 and 46: MODE 0 1 Pin 15 PWR_DWN# (input) PCI5 (output) Pin 46 CPU_STOP# (input) REF1 (output)
2
PRELIMINARY
Pin Definitions (continued)
Pin Name REF0/CPU3.3#_2.5 Pin No. 2 Pin Type I/O Pin Description
W48S87-04
Fixed 14.318-MHz Output 0 and CPU Output Voltage Swing Selection Input: As an output, this pin is used for various system applications. Output voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA slots. When an input, this pin selects the CPU clock output buffer characteristics that are optimized for either 3.3V or 2.5V operation. CPU3.3#_2.5 0 1 VDDQ2 Voltage (CPU0:3 Swing) 3.3V 2.5V
This input adjusts CPU clock output impedance so that a nominal 20Ω output impedance is maintained. This eliminates or reduces the need to adjust external clock tuning components when changing VDDL2 voltage. CPU clock phase is also adjusted so that both CPU and SDRAM and CPU-to-PCI clock skew is maintained over the two VDDL2 voltage options. This input does not adjust IOAPIC clock output characteristics. REF1(CPU_Stop#) 46 I/O Fixed 14.318-MHz Output 0 or CPU Clock Output Stop Control: Used for various system applications. Output voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA slots. If programmed as an input (refer to MODE pin description), this pin is used for stopping the CPU clock outputs. When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are starting beginning with a full clock cycle (2–3 CPU clock latency). X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. Power Connection: Power supply for crystal oscillator and REF0:1 output buffers. Connected to 3.3V supply. Power Connection: Power supply for PCI clock output buffers. Connected to 3.3V supply. Power Connection: Power supply for IOAPIC output buffer. Connected to 2.5V or 3.3V supply. Power Connection: Power supply for CPU clock output buffers. Connected to 2.5V or 3.3V supply. Power Connection: Power supply for SDRAM clock output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane.
X2 SDATA SCLOCK VDD1 VDD2 VDDL1 VDDL2 VDD3 GND
5 23 24 1 6,14 48 42 19, 30, 36 3, 9, 16, 22, 27, 33, 39, 45
I I I P P P P P G
3
PRELIMINARY
Overview
The W48S87-04, a motherboard clock synthesizer, can provide either a 2.5V or 3.3V CPU clock swing, making it suitable for a variety of CPU options. Twelve SDRAM clocks are provided in phase with the CPU clock outputs. This provides clock support for up to three SDRAM DlMMs. Fixed output frequency clocks are provided for other system functions.
W48S87-04
I/O pins are three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O is pin is then latched. Next the output buffers are enabled, which converts the l/O pins into operating clock outputs. The 2-ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of both clock outputs is
