ES51966

ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Features External crystal oscillator 4MHz: count up to 44,000 counts (input range: ±440mV) 10MHz: count up to 440,000 counts (input range: ±440mV) Four selectable conversion rates: 20, 10, 5, 2 conversion/sec On chip resistance switches for range Changing. Voltage (DC/AC), current(DC/AC), resistor, diode, capacitance, frequency and duty cycle measurement 400mV independent input on chip OP amp’ for AC/DC conversion Auto zeroing function Peak hold function with calibration mode X10 function I/O port for microprocessor Capacitance measurement -4nF to 40mF, count up to 40,000 counts -Discharging indication 400MHz Frequency counter and 1MHz duty cycle measurement On chip buzzer driving: 2KHz Single 5V DC power supply (V+ to V-) Low battery detection SLEEP mode Description The ES51966 is a 44,000/440,000-count dual-slope analog-to-digital converter (ADC) with X10 and PEAK Hold functions. The ES51966 also include capacitance, frequency and duty cycle measurement. The conversion rate and resolution can be selected/decided by external microprocessor. In additional, other functions are also provided for low battery detection, on chip buzzer driving, and I/O port with microprocessor. 64-pin QFP 1 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Absolute Maximum Ratings Characteristic Positive Supply Voltage (V+ to AGND) Negative Supply Voltage (V- to AGND) Analog I/O Voltage Digital I/O Voltage Power Dissipation Operating Temperature Storage Temperature Lead Temperature (soldering, 10sec) Rating 3.5V -3.5V ((V-) - 0.5V) to ((V+) + 0.5V) ((V-) - 0.5V) to ((V+) + 0.5V) 800mW 0°C to 70°C -25°C to 125°C 270°C Electrical Characteristics TA=25°C, DGND=AGND=0V Symbol Parameter Test Condition V+ VI(V+) I(GND) Zero NLV1 REV1 NLV10 REV10 V12 LBATT Positive Power Supply Negative Power Supply Operation Supply Current Supply Current of DGND to VZero Input Reading Nonlinearity (Voltage x1) Rollover Error (Voltage x1) Nonlinearity (Voltage x10) Rollover Error (Voltage x10) Band Gap Voltage Reference Low Battery Detection PEAK Hold value accuracy (10us) Reference Voltage (V12) Temperature Coefficient Normal power on (V+ to V-) ∆V between DGND and V- is 0.2V 1 MΩ input resistor, null to zero by uP. Best case straight line 1 MΩ input resistor Best case straight line 1 MΩ input resistor 100 kΩ between V12 and AGND LBATT to V12 使用 10nF 聚㆚酯薄膜電容 (polyester, Mylar) 100 kΩ between V12 and AGND (0°C to 70°C) Min. 2.3 -2.3 5 -0 -0.01 -0.01 -0.1 -0.1 -1.31 -60 -1.2 -25 - Typ. Max. Unit 2.5 -2.5 1.0 10 0 -1.23 0 50 2.7 -2.7 1.7 +0 0.01 0.01 0.1 0.1 -1.10 V V mA mA count %F.S. %F.S. %F.S. %F.S. V TCRF 60 mV +1.2 %F.S. +25 ±count ppm/°C 2 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Pin configuration QFP-64pin L B A TVV T++ A G N D A G N D 60 O S D C G N V V4 D- - M S C L K S T A TVE UC O SCC 55 50 CAZ RAZ BUF BUFX10 CrefCref+ NC IVSH IVSL TEST5 ACVL ACVH ADI ADO NC OVX OVH NC 1 CINT 5 45 10 40 15 35 20 25 30 OSC2 OSC1 BUZOUT BUZIN NC FREQ NC CACA+ R1K R9K CCMP NC VR VRH NC PMAX PMIN NC OO V V V V N S N VN V N VR R R R R C G C R C 4 C S1 5 4 3 2 N1 0 0 G D m ES51966 Pin Description Pin No. Symbol Type Description O O O O O I/O I/O I I I/O O O I O Auto-zero capacitor connection Auto-zero resistance connection Integration capacitor connection Integration resistor connection output Integration resistor connection output Negative connection for reference capacitor Positive connection for reference capacito High current measurement input Low current measurement input Test Pin Negative output of AC to DC converter Positive output of AC to DC converter. Negative input of internal AC to DC OpAmp Output of internal AC to DC OpAmp. 1 CAZ 2 RAZ 3 CINT 4 BUF 5 BUFX10 6 Cref7 Cref+ 9 IVSH 10 IVSL 11 TEST5 12 ACVL 13 ACVH 14 ADI 15 ADO Continued on next page 3 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Pin No. 17 18 20 21 22 23 24 25 27 29 31 34 35 37 38 40 41 42 43 44 46 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol OVX OVH OVSG OR1 VR5 VR4 VR3 VR2 SGND VR1 V400m PMIN PMAX VRH VR CCMP R9K R1K CACA+ FREQ BUZIN BUZOUT OSC1 OSC2 EOC VCC STATUS SCLK OSC4M VVDGND AGND AGND V+ V+ LBATT Type Description I I I O O O O O G I I O O O O I O O I/O I/O I I O I O O I I/O I I P P G G G P P I Input high voltage for resistance measurement. Output connection for resistance measurement. Sense low voltage for resistance measurement. Reference resistor connection for 399.9Ω range. Voltage measurement ÷ 10000 attenuator (4000V.) Voltage measurement ÷ 1000 attenuator (400.0V.) Voltage measurement ÷ 100 attenuator (40.00V.) Voltage measurement ÷ 10 attenuator (4.000V.) Signal Ground. Measurement input. 400mV independent input. Minimum peak hold output. Maximum peak hold output. Output of band-gap voltage reference. Typically -1.2V Reference input voltage connection. Typically -200mV In capacitor mode, a compensation capacitor is connected. Connect to a 9KΩ resistor for capacitor measurement Connect to a 1KΩ resistor for capacitor measurement. Negative auto-zero capacitor connection for capacitor measurement. Positive auto-zero capacitor connection for capacitor measurement. Frequency counter input, offset to V-/2 Enables the buzzer. High action. Outputs a 2KHz audio frequency signal for driving piezoelectric buzzer when BUZIN is High. Crystal oscillator input connection. Crystal oscillator output connection. End of conversion indicator The high level of digital I/O signals, which is connected to VCC pin of microprocessor. ES51966 sends current status to microprocessor or receives controlled status from microprocessor. Clock input from microprocessor. Crystal oscillator selection. NC for 4MHz; connect to V- for 10MHz. Negative supply voltage, connected to cathode of battery typically. Negative supply voltage, connected to cathode of battery typically. Digital Ground ( Output of on-chip DC-DC converter ), VDGND = ( V+ - V- ) / 2 Analog Ground Analog Ground Positive supply voltage Positive supply voltage Low battery voltage detection 8 , 16 , 19 , 26 , 28 , 30 , 32 , 33 , No connected 36 , 39 , 45 , 47 P: Power, G: Ground, I: Input, O: Output 4 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Operation Mode (1) Digital Interface between ES51966 and Microprocessor The EOC, SCLK and STATUS of the ES51966 are used as digital communicating interface between ES51966 and microprocessor. The STATUS pin is bi-directional, and the others are unilateral: EOC is from ES51966 to microprocessor and SCLK is from microprocessor to ES51966. The timing and data of the communication are as follows: mode 1: ES51966 receives controlled status from microprocessor. Force A/D entering into AZ phase t1 t6 t7 SCLK(I) t2 START t3 t4 t5 t5 END t8 E t9 D F (VCC) (V-) STATUS(I/O) A BC status (VCC) (V-) Timing of the above figure: t1 (1040 ~ 4096) T t2 512 T t3 (4 ~ 256) T t4 > 4 T t5 (16 ~ 1024) T (T = 0.25µs) t6 t7 t8 t9 (32 ~ 512) T (520 ~ 1020) T (0 ~ 256) T 520 T Note: 1. At START: After time A, ES51966 enter into AZ phase. And at the same time, STATUS is changed from output pin to input pin with a 3uA pull low current provided by ES51966 internally. Then microprocessor can send control status to STATUS. It is suggested that microprocessor begins to drive STATUS between B and C. 2. At END: The microprocessor stopped driving STATUS between D and E, and ES51966 will begin to drive STATUS after F. 5 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) 3. The detail timing between SCLK and STATUS is as follow: (32 ~ 512)T with 30 ~ 70% duty cycle (VCC) (V-) SCLK STATUS S0 S1 Sn-1 Sn S14 (VCC) (V-) Serial Data Format (STATUS): F0 0 F1 1 F2 2 Q0 3 PEAK 11 Q1 4 PHCAL 12 Q2 5 X10 13 C0 6 SLEEP 14 C1 7 C2 AC ZERO 8 9 10 (All defaults are ‘0’) F0 0 0 0 0 1 1 1 1 1 F0, F1, F2 measurement selection. F1 0 0 1 1 0 0 1 1 F2 0 1 0 1 0 1 0 1 Measurement Voltage2 Voltage with frequency3 Current2 Current with frequency3 Resistance Diode Frequency and duty cycle1 Capacitance In Frequency and duty cycle measurement, ES51966 measures both the frequency and duty cycle of the input signal FREQ (pin 45) simultaneously. 2 In Voltage/Current measurement, only voltage/current is measured. 3 In Voltage/Current with frequency measurement, the frequency of FREQ is also measured in addition to voltage/current. Detailed descriptions of these measurement modes, please see the following sections. Q0, Q1, Q2 Q0 0 0 0 0 1 1 1 1 1 range selection. Q2 0 1 0 1 0 1 0 1 V1 440mV 4.4V 44V 440V 4400V A1 IVSL (pin15)4 IVSH (pin 14) 4 Ω1 420Ω 4.2KΩ 42KΩ 420KΩ 4.2MΩ 42MΩ F3 40Hz 400Hz 4KHz 40KHz 400KHz 4MHz 40MHz 400MHz C2 4.2nF 42nF 420nF 4200nF 40uF 400uF 4000uF 40000uF Q1 0 0 1 1 0 0 1 1 When oscillator is 4MHz, voltage/current can be counted up to 44,000, and resistance can be counted up to 42,000. When oscillator is 10MHz, voltage/current can be counted up to 440,000, and resistance can be counted up to 420,000. 2 The ranges from 4.2nF to 4200nF have a maximum counts of 42000. The other ranges 6 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) from 40uF to 40000uF could only be counted up to 40,000 regardless the oscillator frequency. 3 Frequency could only be counted up to 40,000 regardless the oscillator frequency. In 40Hz range, ES51966 can count from 0.5Hz to 40Hz; in 400Hz range, it can count from 2.5Hz to 400Hz; in 4000Hz, it can count from 25Hz to 4000Hz. 4 In Current measurement, two input pins (IVSH and IVSL) are provided and can be selected by Q2. C0, C1, C2 In voltage (F[0:2] = “000”) and current (“010”) measurement, C0 & C1 are used for conversion rate selection: C0 0 0 1 1 C1 1 0 0 1 Conversion/sec 20 10 5 2 Conversion period 50ms 100ms 200ms 500ms 10, 5, and 2 conversion/sec are 50Hz rejection, while 2 conversion/sec is both of 50 Hz and 60Hz rejections. In resistance measurement, the conversion period is: C0 0 0 1 1 C1 1 0 0 1 Conversion period 70ms 140ms 280ms 700ms When PEAK or PHCAL function is ON, the conversion period becomes: C0 0 0 1 1 C1 1 0 0 1 Conversion period 55ms 110ms 220ms 550ms In frequency and duty cycle (F[0:2] = “110”) measurement, only C0 is used for conversion period selection. When the range is from 40Hz to 4000Hz, the conversion periods are not selectable (see the description in Frequency and duty cycle measurement); and when the range is from 40KHz to 400MHz, the conversion period is decided by C0: C0 0 1 Conversion period 110ms 1.1s In voltage/current with frequency mode (F[0:2] = “001” and “011”), the conversion period is fixed at 110ms, and C0, C1 & C2 decide the range of the frequency measurement: C0 0 1 C1 0 C2 0 7 Range 40KHz 400KHz 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) 1 1 1 0 1 1 1 0 1 4MHz 40MHz 400MHz In capacitance measurement, these bits are no use. AC ‘L’ for DC; ‘H’ for AC in Voltage/Current measurement. If not in voltage or current measurement, this bit will be ignored. ZERO ‘H’ for zero calibration. PEAK ‘H’ for PEAK Hold function in Voltage/Current measurement. PHCAL ‘H’ for PEAK Hold calibration mode in Voltage/Current measurement. X10 ‘H’ for X10 function. SLEEP ‘H’ for DMM in sleep mode. mode 2: ES51966 sends the status and counts ( counter from DINT ) to uP. one conversion period t0 EOC(O) t2 t1 (VCC) (V-) (V-CC) (V-) (VCC) (V-) SCLK(I) STATUS(O) status & counts t0 is at least 5ms and t1 must be (32 ~ 512)T, where T = 0.25µs. t2 is the time from the falling edge of EOC to the last data been transferred. t2 is no more than 4.9ms. That is, all results must be transferred within 4.9ms from the falling edge of EOC. The detail timing between SCLK and STATUS is as follow: (32 ~ 512)T with 30 ~ 70% duty cycle (VCC) (V-) SCLK STATUS S0 S1 Sn-1 Sn Sfinal (VCC) (V-) Serial Data Format (STATUS): - Voltage (“000”), current (“010”), resistance (“100”) and diode (“101”) 8 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) measurement SIGN 0 PMAX 1 BATT 2 D0 (20 bits) 3 ~ 22 SIGN ‘H’ for negative; ‘L’ for positive. In AC, Ω and diode measurement, this bit can be ignored. PMAX When PEAK or PHCAL is executed, ‘H’ for PEAK MAX. measurement, ‘L’ for PEAK MIN. measurement. BATT ‘H’ for battery-low indication. D0 Conversion results (magnitude). The format is binary code. LSB outputs first. When oscillator is 4MHz, D0 is up to 44,000 counts. When oscillator is 10MHz, if the conversion rate is 20/sec, it counts to 220,000; if the conversion rate is not 20/sec, it counts to 440,000. - Capacitance (“111”) measurement: DISCH 0 0 1 BATT 2 D0 (20 bits) 3 ~ 22 DISCH ‘H’ indicates that DMM is under discharging. If this bit is ‘H’, ES51966 enters AZ mode, and discharges the capacitor automatically. However, discharging through ES51966 is slow, and the customer had better discharge by shorting two pins of the capacitor. When DISCH is ‘H’, all the STATUS never outputs (EOC is never high), but the status of DISCH will be on the STATUS pin. Therefore, uP should keep an eye on the STATUS pin when capacitance measurement to know if the capacitor needs to be discharged. 0 This bit is always zero. BATT ‘H’ for battery-low indication. D0 Conversion results (magnitude). The format is binary code. LSB outputs first. - Voltage/current with frequency (“001” & “010”) measurement: SIGN 0 PMAX 1 BATT 2 D0 (20 bits) 3 ~ 22 D1 (18 bits) 23 ~ 40 SIGN For voltage/current measurement. ‘H’ for negative; ‘L’ for positive. In AC, Ω and diode measurement, this bit can be ignored. PMAX For voltage/current measurement. When PEAK or PHCAL is executed, ‘H’ for PEAK MAX. measurement, ‘L’ for PEAK MIN. measurement. BATT ‘H’ for battery-low indication. 9 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) D0 D1 Conversion result of voltage or current measurement. Conversion result of frequency measurement. - Frequency (“110”) measurement: OL 0 UL 1 BATT 2 D0 (20 bits) 3 ~ 22 D1 (18 bits) 23 ~ 40 D2 (6 bits) 41 ~ 46 OL Overflow when in 40, 400 and 4000Hz ranges. UL Underflow when in 40, 400 and 4000Hz ranges. BATT ‘H’ for battery-low indication. D0, D1, D2 Please see the description in frequency and duty cycle measurement. (2) Dual Slope A/D—four phases timing The ES51966’s measurement cycle contains four phases, ZI, AZ, INT, and DINT. The timing will be changed as conversion rate changed. There are some examples as follow, and the others are alike. ES51966 is a dual-slope analog-to-digital converter (ADC). Figure 2.1 is a structure of dual-slope integrator. Its measurement cycle has two distinct phases: input signal integration (INT) phase and reference voltage integration (DINT) phase. In INT phase, the input signal is integrated for a fixed time period, then A/D enters DINT phase in which an opposite polarity constant reference voltage is integrated until the integrator output voltage becomes to zero. Since both the time for input signal integration and the reference voltage are fixed, the de-integration time is proportional to the input signal. Hence, we can define the mathematical equation about input signal, reference voltage integration (see Figure 2.1): TINT 1 1 ∫0 V IN (t )dt = Buf × C int × VREF × TDINT Buf × C int where, V IN (t ) = input signal V REF = reference voltage T INT = integration time (fixed) TDINT = de-integration time (proportional to V IN (t ) ) If V IN (t ) is a constant, we can rewrite above equation: TDINT = T INT × V IN V REF Besides the INT phase and DINT phase, ES51966 exploits auto zero (AZ) phase and zero 10 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) integration (ZI) phase to achieve accurate measurement. In AZ phase, the system offset is stored. The offset error will be eliminated in DINT phase. Thus a higher accuracy could be obtained. In ZI phase, the internal status will be recovered quickly to that of zero input. Thus the succeeding measurements won’t be disturbed by current measurement especially in case of overload. Cint Buf Raz input signal < 0 different input fixed slope input signal reference voltage integrator output integrator output integration time fixed slope different input integrator output input signal > 0 Fixed Variable integration deintegration time time Fixed Variable integration deintegration time time integration time Figure 2.1 the structure of dual-slope integrator and its output waveform. As mentioned above, the measurement cycle of ES51966 contains four phases: (1) auto zero phase (AZ) (2) input signal integration phase (INT) (3) reference voltage integration phase (DINT) (4) zero integration phase (ZI) Normally, the time ratios of these four phases, AZ, INT, DINT and ZI to the entire measurement cycle are 20%, 20%, 44% and 16% respectively. However the actual duration of each phase depends on conversion rate. The time of each conversion rate are shown in the table below in which voltage/current (without PEAK HOLD or frequency), and diode measurement use this conversion time. C[0:1] 01 00 10 11 CR (times/sec) 20 10 5 2 ZI (ms) 8 16 32 80 AZ (ms) 10 20 40 100 INT (ms) 10 20 40 100 DINT (ms) 22 44 88 220 Note: Vref = -200 mV. 11 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) (3) Component Value Selection for ADC For various application requirements on conversion rate and input full range, we suggest nominal values for external components of ADC in Figure 2.1 to obtain better performance. Under default condition with operating clock = 4 MHz: (1) conversion rate = 10 times/sec (2) reference voltage = -200 mV (3) input signal full scale = 440 mV (sensitivity = 10 uV) we suggest that Cint = 33 nF, Buf = 200 kΩ, Raz = 200 kΩ. If a user selects a different conversion rate rather than default, the integration capacitor Cint value must be changed according to the following rule for better performance: Cint × (conversion rate) = (33 nF) × (10 times/sec). It is important that the actual Cint value should be no less than the nominal value. A smaller Cint reduces the input full range. However a larger Cint might have weaker noise immunity than the suggested one. A user could enlarge the input full range by changing reference voltage (Vref) and the amount of integration resistor (Buf and Raz). For example, if Vref, Buf and Raz are enlarged as twice than the default values then the input full range becomes 880 mV. The input full range can be enlarged up to 1.1V (2.5 times than the default case). We list general rules in below which might be helpful in determining component values. Buf / (reference voltage) = 200 kΩ / (-200 mV) (4) Voltage Measurement DC/AC voltage measurement A re-configurable voltage divider provides a suitable full-scale range voltage measurement mode. The following table summarizes the full-scale ranges in each configuration. Configuration VR1 VR2 VR3 VR3 VR5 Full Scale Range 440.00mV 4.4000V 44.000V 440.00V 4400.0V Divider Ratio 1 1/10 1/100 1/1000 1/10000 Resister Connection R2 / (R1+R2) R3 / (R1+R3) R4 / (R1+R4) R5 / (R1+R5) In configuration VR1, the full range is 440mV, and the voltage inputs from V400m pin to prevent the influence of noise when floating. In other configurations, the voltage inputs 12 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) from VR1 pin. Pin 19 to 23 are used for AC measurement. Figure 4.1 is the AC-to-DC circuit. ACto-DC circuit extracts the AC part of the voltage (ADO - TEST5). ADC then converts the voltage of (ACVH – ACVL) to acquire the AC value of input voltage. Variable resistor 5KΩ is used to adjust the DC offset. Light shielding for diode D1 and D2 is required to prevent leakage current. This circuit works properly only when the input voltage is sinusoidal. If the input is not sinusoidal (e.g., square waves), a true RMS-to-DC converter chip will be needed to obtain the correct true RMS value of input signal. If ADO and ADI short directly, ADI is the divided voltage of the input signal. Therefore, it can be used for oscillator display. AGND OVSG 100 1K 10K 101K 1.11M D1 15K 1u 10K D2 0.47u 1u 15K 0.1u 88M OR1 VR5 VR4 VR3 VR2 ADO ADI ACVH ACVL TEST5 V R 1 10M V R 5K -100mV Voltage input Figure 4.1 AC-to-DC circuit The measurement of true RMS using ES636 If ES636 is used for true RMS measurement, the suggested application circuit is shown in Figure 4.2. When ES636 is used for true RMS, ADO and ADI pin short together, TEST5 pin keeps floating, and ACVL pin connects to AGND. And the OVSG pin short to AGND through a switch. 13 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Pin 2 connects to –Vs for normal operation, or connects to +Vs for sleep mode -Vs +Vs ACV Cav 100 1K 10K 101K 1.11M OVSG OR1 VR5 VR4 VR3 VR2 ACVL ACVH 1 14 13 200 -Vs +Vs 2 ES636 3 4 5 6 7 12 11 10 9 8 +Vs 4.7uF 150 470K ADI ADO 500K -Vs Figure 4.2 AC-to-DC circuit using ES636 (5) Diode Measurement Diode measurement mode shares the same configuration with 4.4000V voltage mode. The range select bits Q0, Q1 and Q2 are not active in this mode. (6) Current measurement Current measurement has three mode. The following table summarizes the full scale range of each mode. Mode Range Selection Full scale uA IVSL / IVSH 440.00uA / 4400.0uA mA IVSL / IVSH 44.000mA / 440.00mA 10A IVSH 44.000A *Operation Mode is based on application circuit . *Range selection : IVSL ( Q0,Q1,Q2 ) = ( 0,0,0 ) IVSH ( Q0,Q1,Q2 ) = ( 0,0,1 ) 14 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) (7) Multiplying by 10 (X10) Function ES51966 includes X10 function. In X10 function mode, the output will be increasing tenfold. But the input range will be reduced to ±44mV. For example, if X10 function is enabled and the input is 10mV, output will be 10,000 counts, rather than 1,000 counts. To achieve X10 function, the integration resistor is 20KΩ, not 200KΩ at INT phase, and remains 200 kΩ at DINT phase. Because the resistor (20KΩ) requires exactly 1/10 of 200K BUF BUFX10 VR 18K Figure 5.1 X10 function integration resistor (200KΩ), a variable resistor VR is used to compensate these two resisters. Resistor scheme of AZ/INT/DINT phases In ES51966, an on-chip resistor is used for AZ mode. The internal chip is about 10 kΩ. The connection is shown in the following Figure 5.2. ES51966 CINT(5) CAZ(6) 200K BUF(7) BUFX10(8) A B C 10K Rx 20K RAZ(9) Figure 5.2 Resistor scheme of AZ phase The status of switches A, B and C are described in the following table. X10 function is OFF switch INT phase DINT phase AZ phase A ON ON ON B OFF OFF ON C OFF OFF ON 15 X10 function is ON INT phase DINT phase AZ phase OFF ON ON ON OFF ON OFF OFF ON 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) In AZ phase, all the switches is ON, the effective resistor is all the resistors in parallel. The effective resistor is therefore less than 10 kΩ. If X10 function is never used, the matching between 200 kΩ and ( VR + 18 kΩ) is not necessary. In this situation, (VR + 18 kΩ) can be replaced by a resistor about 20 kΩ, or simply omitted. (8) ZERO Calibration In ES51966, the inherent delay of the OPAMP will introduce a few counts to the output. The method to prevent this problem is zero calibration. When zero calibration is ON, ES51966 shorts the input to SGND internally. uP needs to save the results of zero input. After zero calibration is OFF, the result of zero input is then deduct from the counts of the following measurements. Zero calibration can be enabled on any measurement. When the ZERO bit is set by uP, ES51966 begins to execute zero calibration. ES51966 stops executing zero calibration until the ZERO bit is reset by uP. In voltage/current/diode/capacitance measurement, the de-integration voltage is fixed, therefore zero calibration needs only be enabled once. The results could be used for all the following voltage/current/diode/capacitance measurement. However, in resistance measurement, the de-integration voltage is not fixed, and varies with the resistance to be measured. That is, zero calibration must be re-done if the resistance to be measured changes. For convenience, the result of zero input in voltage measurement could be used in resistance measurement. (9) PEAK Hold Function Only when voltage and current measurement (F[0:2] = “000” to “011”) could the PEAK HOLD function be executed. In PEAK HOLD measurement, the instant maximum and minimum values of the input voltage (or current) are stored and transferred to digital data through ADC. Pmax and Pmin are measured alternately while Pmax first. PEAK HOLD calibration measures the offset voltages (Vos) of Pmax and Pmin alternately and the ES51966 will count them to digital data. Then ES51966 sends the counts to microprocessor, and microprocessor must record them. Because of existence of the offset voltage, the DINT time of voltage measurement with PEAK HOLD requires longer than that of voltage measurement without PEAK HOLD. The time of each phase when PEAK HOLD is executed at various conversion rate are as follow: 16 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) C[0:1] 01 00 10 11 ZI (ms) 8 16 32 80 AZ (ms) 10 20 40 100 INT (ms) 10 20 40 100 DINT (ms) 27 54 108 270 Total time (ms) 55 110 220 550 If zero and peak functions are set to ON at the same time by uP, peak function will be disabled by zero function. If peak function is set to ON at non-voltage/current measurement, it will also be disabled. 17 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) PEAK Hold calibration: EOC MODE 2 (uP to A/D) MODE 1 (A/D to uP) END (VCC) (V-)+2.1V (V-) (V-)+0.8V (VCC) V (V-)+2.1 (V-) (V-)+0.8V SCLK calibration STATUS START set Pcal (S6) to H S12 (VCC) (V-)+2.1V D0~D15 D0~D19 D0~D19 D0~D15 (V-)+0.8V D0~D15 D0~D15 D0~D19 (V-) D0~D19 S0~S15 S0~S15 S0~S15 S0~S15 (V-)+2.1V (VCC) (V-)+0.8V (V-) Pmax Pmin Pmax Pmin Vos Vos Vos Vos Note: it is not necessary to set PEAK to H at the same time. To active PEAK Hold after calibration: EOC MODE 2 (uP to A/D) MODE 1 (A/D to uP) END (VCC) (V-)+2.1V (V-)+0.8V (V-) (VCC) V (V-)+2.1 (V-)+0.8V (V-) (VCC) V (V-)+2.1 (V-)+0.8V (V-) (V-)+2.1 (VCC) V (V-)+0.8V (V-) SCLK START set PEAK (S5) to H S11 PEAK Hold (Pmax) STATUS D0~D15 D0~D19 D0~D19 D0~D19 D0~D19 D0~D15 D0~D15 D0~D15 S0~S15 S0~S15 S0~S15 S0~S15 (Pmin) (Pmax) (Pmin) To cancel PEAK Hold function: EOC MODE 1 (A/D to uP) MODE 2 (uP to A/D) MODE 1 (A/D to uP) (VCC) V (V-)+2.1 (V-)+0.8V (V-) (VCC) V (V-)+2.1 (V-)+0.8V (V-) (VCC) V (V-)+2.1 (V-) (V-)+0.8V (V-)+2.1 (VCC) V (V-)+0.8V (V-) SCLK PEAK Hold (Pmax) STATUS D0~D15 D0~D19 D0~D15 D0~D19 S0~S15 S0~S15 (Pmin) START END set PEAK (S5) to L S11 D0~D15 D0~D19 S0~S15 Note: After changing X10 mode, if we want to active PEAK Hold function, we must active calibration again. 18 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) (10)Frequency and duty cycle When F[0:2] = “110”, ES51966 calculates frequency and duty cycle of FREQ at the same time. However, some more computations are required to obtain both the results. There are three output data at this measurement: D0, D1, and D2 which can be obtained from the serial output. ▪ 40Hz range: Frequency = ▪ 400Hz range Frequency = ▪ 4000Hz range (D2+1)×107 100×D0 % , Duty cycle = 150,950+D1 150,950+D1 ▪ 40KHz to 400MHz range (D2 is not needed.) when C[0] = 0 D0 % Frequency = 10×D1 , Duty cycle = 200 when C[0] = 1 D0 % Frequency = D1 , Duty cycle = 200 Frequency = ES51966 can measure frequency from 0.5Hz to 409.6MHz. For each range, the measurable frequencies and resolution are shown in the following table: Range 40Hz 400Hz 4000Hz 40KHz 400KHz 4MHz 40MHz 400MHz Measured frequency range 0.5Hz ~ 40Hz 2.5Hz ~ 400Hz 25Hz ~ 4000Hz 0 ~ 40.96KHz 0 ~ 409.6KHz 0 ~ 4.096MHz 0 ~ 40.96MHz 0 ~ 409.6MHz Resolutions 0.001Hz 0.01Hz 0.1Hz 1Hz 10Hz 100Hz 1KHz 10KHz (D2+1)×106 150,950+D1 , Duty cycle = 100×D0 % 150,950+D1 (D2+1)×106 5×(150,950+D1) , Duty cycle = 100×D0 % 150950+D1 At 40/400/4000Hz, if the input frequency is less than its measurable range, it’s underflow, and UL will set to ‘H’. At the same ranges, if the input frequency is greater than its measurable range, it’s overflow, and OL will set to ‘H’. When UL or OL occur, the data D0, D1, and D2 will not be correct, please ignore them. At 40KHz ~ 400MHz ranges, OL and UL are always ‘L’, but it’s overflow when the output counts is 40,960. 19 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) At different range, the conversion time is different. At 40/400/4000Hz, the conversion time is according to the input frequency. At other ranges, the conversion time is fixed at 110ms or 1.1s with C[0] = 0 or 1, respectively. Range 40Hz 400Hz 4000Hz 40KHz 400KHz 4MHz 40MHz 400MHz Conversion time C[0] = 0 C[0] = 1 0.8s ~ 2s 0.16s ~ 0.4s 0.16s ~ 0.4s 110ms 1.1s 110ms 1.1s 110ms 1.1s 110ms 1.1s 110ms 1.1s (11)Voltage/Current Measurement with Frequency Counter When F[0:2] = “001” or “011”, ES51966 measures frequency of input together with voltage/current. At this measurement mode, voltage (or current) input is VR1/400mV (or IVSH/IVSL), and frequency input is FREQ. Q[0:2] is the range of voltage/current measurement, and C[0:2] is the range of frequency measurement. Only 40K to 400MHz ranges are selectable here. Unlike frequency measurement (F[0:2] = “110”), duty cycle is not measured in this mode. The conversion time is fixed at 110ms. Voltage/current can count up to 54,000 (or 540,000 when 10MHz OSC is used). AC and PEAK can still be active. D0 is the output of voltage/current, and (10×D1) is the result of frequency. (12) Capacitance Measurement ES51966 measures capacitance with 8 ranges. Capacitance can only be counted to about 40,000 counts, no matter the oscillator frequency. The conversion time, measurement range and resolution are as the following table. Range Conversion time Measured frequency range 4nF 0.7sec 4.0000nF 40nF 0.7sec 40.000nF 400nF 0.7sec 400.00nF 4uF 0.7sec 4.0000uF 40uF 0.75sec 40.000uF 400uF 1.5sec 400.00uF 4000uF 3.75sec 4000.0uF 40000uF 7.5sec 40000uF 20 Resolutions 0.1pF 1pF 10pF 100pF 1nF 10nF 100nF 1uF 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) If needed, ES51966 can discharge the capacitor automatically before measuring until this chip can guarantee that it can obtain proper values in next two measurements. However, discharging by chip is slow, especially when capacitor is large or there is high voltage on the capacitor. This is because ES51966 must discharge the capacitor through the PTC resistor (about 1.5KΩ) for safety consideration. Therefore, it is strongly suggested that the user discharges the capacitor by himself when needed. If discharging occurs, the STATUS pin is pulled high immediately, and uP can check the STATUS to know if ES51966 is in discharging. The application circuit of capacitance measurement is as Figure 10.1, the 9KΩ and 1KΩ resistors connected to R9K and R1K pins should be precision resistors. Because there exists parasitic capacitor in the chip and the PCB board (about 200 ~300pF), compensation is required to prevent offset error at lower ranges (4n ~ 400nF ranges). There are two methods to compensate the effect of the parasitic capacitors. One method is to measure the parasitic capacitors directly by opening the input (i.e., the input capacitance is zero) and record this value for EACH RANGE (especially 4nF/40nF/400nF), and then subtracting the value of that range after each measurement. Another method is to connect a compensation capacitor CCMP on the CCMP pin as the OVH OVX 220p 10K 1.5K PTC 100K 101K 1.11M 10M 100K CCMP OVSG VR4 VR3 VR2 VR1 CCMP R9K R1K CA+ CASGND 100 ES51966 9K 470n 1u 1K Figure 10.1 Application circuit of capacitance measurement 21 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) figure above, and then ES51966 will execute the compensation automatically. The value of CCMP relates to the parasitic capacitor. The adequate value of CCMP is to let the display digits show about tens counts when input opens. (13) SLEEP mode If SLEEP bit is set ‘H’ by uP, ES51966 enters sleep mode. In sleep mode, if SCLK keeps low, all the circuit is shut down, and the supply current is about 0.1uA. If SCLK is high in sleep mode, only the oscillator is active to prepare for the following re-power operation. (14) Digital Signals Rising and Falling times The digital signals include EOC, SCLK, and STATUS, and those rising and falling times are defined as follow: EOC and STATUS are output to microprocessor: V+ (V-)+2.1V (V-)+0.8V V- tro SCLK and STATUS are input from microprocessor: Vcc (V-)+2.1V (V-)+0.8V tfo Vss tri tfi Note: Vss = V- Symbol tro tfo tri tfi Condition A/D to uP A/D to uP uP to A/D uP to A/D Min - Max 20 20 20 20 Units ns ns ns ns 22 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Application Circuit 820K + 9V 0.1u 5V Regulator Vc 7.5V + + uA mA 900 uA uA 180K DGND AGND AGND VVOSC4M SCLK STATUS VCC EOC OSC2 OSC1 BUZOUT BUZIN + 0.1u 0.1u 10u1 + + 4.7u2 4.7u Vss Vc 8051 serial 90 9 mA mA 10A SGN 0.99 0.01 5K 470n 100K 100K 5K 15K + V+ V+ 0.47uLBATT *33n *200K 18K CAZ RAZ 10A CINT BUFX10 BUF 5.6V V- ES51966 CrefCref+ IVSH IVSL TEST5 ACVL ACVH ADI ADO OVX OVH OVSG FREQ NC CA+ CAR1K R9K CCMP VR VRH NC PMAX PMIN NC V400m VR1 NC SGND 200 2.2u 470n 9K + 1.5K PTC 10K 15K + 0.1u 1u D2 0.47u 88M 100K 1.5K PTC 220pF 100 1K 10K 100K *Cp + 1u D1 1u 20K 91K 10n 10n 1u C V- CR Zener 6V 100 OR1 1K VR5 10K VR4 101K VR3 1.11M VR2 C 100K 10M 23 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Note: 1.In PEAK mode, the wire of SCLK STATUS EOC must be shielded to prevent from the noise. 2.In capacitance mode, a 10kΩ resistor must be applied between V- and COM. 3.For the X10 feature, the BuffX10 resistor must be precisely adjusted to a tenth part of the Buffer resistor or the additional error will rice. (Rbuff = 10 RbuffX10) 4.If use the AC-to-DC circuit as above schematic, the reading out will get a minus sign. Please ignore the minus sign instead of displaying. And the polarity of diode must not be changed. 5.The compensation capacitor Cp is used to compensate the error risen by the parasitic capacitance on PCB. The value of Cp should be approximately equal to the filter capacitor applied at pin OVX. 6.The Zener Diodes are used for IC protection, and MUST be soldered on PCB first before soldering IC. *In capacitance mode, change 33nF to 220nF or change 200KΩ to 1MΩ. 1.Tantalum capacitor 2.Tantalum capacitor 24 06/04/25 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) Package 64 pins QFP package size 25 06/04/25