LM317E3

CYStech Electronics Corp. Three Terminal Adjustable Output Positive Voltage Regulators Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 1/10 LM317E3 The LM317E3 is an adjustable 3–terminal positive voltage regulator capable of supplying in excess of 1.5 A over an output voltage range of 1.2 V to 37 V. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317E3 serves a wide variety of applications including local, on-card regulation. This device can also be used to make a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the LM317E3 can be used as a precision current regulator. ● Output Current in Excess of 1.5 A ● Output Adjustable between 1.2 V and 37 V ● Internal Thermal Overload Protection ● Internal Short Circuit Current Limiting Constant with Temperature ● Output Transistor Safe–Area Compensation ● Floating Operation for High Voltage Applications ● Eliminates Stocking many Fixed Voltages TO-220AB Standard Application Vin PL317 LM317 + Vout R1 + ＊Cin is required if regulator is located an appreciate distance from power supply filter. ＊＊Cout is not needed for stability, however, it does improve transient response. IAdj R2 Cin Cout 0.1µF 1.0µF Vout=1.25(1+R2/R1)+IAdjR2 Since IAdj is controlled to less than 100 µA, the error associated with this term is negligible in most applications. Maximum Ratings Rating Input-Output Voltage Differential Power Dissipation TA=25℃ Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Operating Junction Temperature Range Storage Temperature Range LM317E3 Symbol VI-VO PD θJA θJC TJ Tstg Value 40 Internally Limited 65 5.0 -40 to +125 -65 to +150 Unit V W ℃/W ℃/W ℃ ℃ CYStek Product Specification CYStech Electronics Corp. Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 2/10 Electrical Characteristics(VI-VO=5V,IO=0.5A,TJ=0 to 125℃, unless otherwise noted) Characteristics Line Regulation(Note 1) Load Regulation(Note 1) Symbol Conditions Reg line TA=25℃,3.0V≤VI-VO≤40V Reg load TA=25℃,10mA≤IO≤1.5A VO≤5.0V VO≥5.0V Thermal Regulation(Note 4) Reg therm TA=25℃, 20ms pulse Adjust Pin Current IAdj 2.5V≤VI-VO≤40V,10mA≤IL≤1.5A Adjust Pin Current Change ∆IAdj PD≤20W 3.0V≤VI-VO≤40V,10mA≤IO≤1.5A Reference Voltage Vref PD≤20W Temperature Stability Ts 0≤TJ≤125℃ Minimum Load Current to ILmin VI-VO=40V maintain Regulation Maximum Output Current Imax VI-VO≤15V,PD≤20W VI-VO≤40V,PD≤20W,TA=25℃ % of VO,TA=25℃,10Hz≤f≤10kHz RMS Noise N Ripple Rejection(Note 2) RR VO=10V,f=120Hz Without CAdj CAdj=10µF Long-Term Stability(Note 3) S TJ=125℃,TA=25℃ for endpoint measurements Min 1.2 1. 5 0.15 66 Typ 0.01 5.0 0.1 0.03 50 0.2 1.25 0.7 3.5 2.2 0.4 0.003 65 80 0.3 Max 0.04 25 0.5 0.07 100 5.0 1.3 10 1.0 Unit %/V mV %VO %VO/W µA µA V %VO mA A %VO dB %/1.0k Hrs Notes:1.Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. 2.CAdj, when used, is connected between the adjustment pin and ground. 3.Since long-term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 4.Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC components on the die. These effects can be minimized by proper integrated circuit design and layout techniques. Thermal regulation is the effect of these temperature gradients on the output voltage and is expressed in percentage of output change per watt of power change in a specified time. LM317E3 CYStek Product Specification CYStech Electronics Corp. Characteristic Curves Reference Voltage vs Temperature Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 3/10 Adjustment Current vs Temperature 1.26 1.255 1.25 1.245 1.24 1.235 -50 -25 0 25 50 75 100 125 Adjustment Current---Iadj(μA) 60 55 50 45 40 35 -50 -25 0 25 50 75 100 125 Reference Voltage---Vref(V) Temperature(℃) Temperature(℃) Dropout Voltage vs Input-Output Voltage Difference Input-Output Voltage Difference(V) 3 △Vo=100mA 2.5 2 1.5 1 0 25 50 75 100 125 Temperature(℃) LM317E3 CYStek Product Specification CYStech Electronics Corp. Representative Schematic Diagram Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 4/10 Vin Vout Adjust ∣VOH-VOL∣ Line Regulation(%/V)= Vcc VIH VIL Vin PL317 LM317 Vout ×100 ∣VOL∣ VOH VOL Pulse testing required 1% Duty Cycle is suggested Cin 0.1µF Adjust IAdj R1 1% Co + 1µF RL R2 1% Fig 1. Line Regulation and ∆IAdj/Line test circuit LM317E3 CYStek Product Specification CYStech Electronics Corp. Vin VI PL317 LM317 Adjust IAdj Cin 0.1µF R2 1% R1 1% Co + Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 5/10 Vout IL * 1µF RL (max load) Vo(min load) Vo(max load) RL (min load) *Pulse testing required. 1% Duty Cycle is suggest Vo(min load)-Vo(max load) Load Regulation(mV)=Vo(min load)-Vo(max load) Load Regulation(%Vo)= Vo(min load) ×100 Fig 2. Load Regulation and ∆IAdj/Load test circuit Vin LM317 PL317 Vout IL R1 1% Adjust IAdj Cin VI ISET 0.1µF Vref + 1µF Co RL Vo R2 1% ＊ Pulse testing required. 1% Duty Cycle is suggested. To calculate R2: Vout=ISETR2+1.250V Assume ISET=5.25mA Fig 3. Standard Test Circuit LM317E3 CYStek Product Specification CYStech Electronics Corp. 24V 14V f=120Hz Vin PL317 LM317 Adjust R1 1% D1 * 1N4002 + Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 6/10 Vout Cin 0.1µF 1µF Co RL Vout=10V Vo R2 1% CAdj + 10µF * D1 Discharges CAdj if output is shorted to ground Fig 4. Ripple Rejection Test Circuit Application Information Basic Circuit Operation The LM317 is a 3-terminal floating regulator. In operation, the LM317 develops and maintains a nominal 1.25V reference (Vref) between its output and adjustment terminals. This reference voltage is converted to a programming current (Iprog) by R1(see Fig 5), and this constant current flows through R2 to ground. The regulated output voltage is given by: Vout=Vref(1+R2/R1)+IAdjR2 Since the current from the adjustment terminal (IAdj) represents an error term in the equation, the LM317 was designed to control IAdj to less than 100 µA and keep it constant. To do this, all quiescent operating current is returned to the output terminal. This imposes the requirement for a minimum load current. If the load current is less than this minimum, the output voltage will rise. Since the LM317 is a floating regulator, it is only the voltage differential across the circuit which is important to performance, and operation at high voltages with respect to ground is possible. Vin PL317 LM317 Adjust Vref R1 Iprog Vout Vout IAdj R2 Vref=1.25V typical Fig 5. Basic Circuit Configuration LM317E3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 7/10 Load Regulation The LM317 is capable of providing extremely good load regulation, but a few precautions are needed to obtain maximum performance. For best performance, the programming resistor (R1) should be connected as close to the regulator as possible to minimize line drops which effectively appear in series with the reference, thereby degrading regulation. The ground end of R2 can be returned near the load ground to provide remote ground sensing and improve load regulation. External Capacitors A 0.1µF disc or 1.0µF tantalum input bypass capacitor (Cin) is recommended to reduce the sensitivity to input line impedance. The adjustment terminal may be bypassed to ground to improve ripple rejection. This capacitor (CAdj) prevents ripple from being amplified as the output voltage is increased. A 10µF capacitor should improve ripple rejection about 15 dB at 120 Hz in a 10V application. Although the LM317 is stable with no output capacitance, like any feedback circuit, certain values of external capacitance can cause excessive ringing. An output capacitance (Co) in the form of a 1.0µF tantalum or 25µF aluminum electrolytic capacitor on the output swamps this effect and insures stability. Protection Diodes When external capacitors are used with any IC regulator, it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Fig 6 shows the LM317 with the recommended protection diodes for output voltages in excess of 25V or high capacitance values (Co>25µF,CAdj>10µF). Diode D1 prevents Co from discharging thru the IC during an input short circuit. Diode D2 protects against capacitor CAdj discharging through the IC during an output short circuit. The combination of diodes D1 and D2 prevents CAdj from discharging through the IC during an input short circuit. D1 1N4002 PL317 LM317 Cin Adjust R1 D2 1N4002 + Vin Vout Co R2 CAdj Fig 6. Voltage Regulator with Protection Diodes LM317E3 CYStek Product Specification CYStech Electronics Corp. Application Circuits D6* 1N4002 Vout Vin 32V to 40 V Vin 1 LM317 PL317 ((1) 1) Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date :2005.05.17 Page No. : 8/10 RSC Vin 2 LM317 PL317 (2) (2) Vout 2 D5 1N4001 + Iout Vout Adjust 1 0.1µF Current Limit Adjust 1.0k D1 1N4001 D2 1N4001 5.0k 240 Adjust 2 Voltage Adjust + 10µF 1.0µF Tantalum Q1 2N3822 D3 Output Range:0≦Vo≦25V 1N4001 0≦Io≦1.5A D4 1N4001 Q2 2N5640 -10V Diodes D1 and D2 and transistor Q2 are added to allow adjustment of output voltage to 0V. * D6 protects both LM317's during an input short circuit. -10V Fig 7. “Laboratory” Power Supply with Adjustable Current Limit and Output Voltage +25V Vin Vout PL317 LM317 Adjust R1 1.25 Iout D1* Vin 1N4002 LM317 PL317 Vout 120 R2 D1 1N4001 D2 1N4001 + 100 *To provide current limiting of Io to the system groung, the source of the FET must be tied to a negative voltage below -1.25V. 2N5640 Adjust 720 MPS2222 1.0k 1.0µF TTL Control R1=Vref/(Iomax+IDSS) R2≤Vref/IDSS Vo