19-5360; Rev 3; 9/11
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
GENERAL DESCRIPTION
FEATURES
The 71M6513 is a highly integrated system-on-chip SoC with an MPU core,
real-time clock (RTC), flash, and LCD driver. Our Single Converter
Technology® with a 21-bit delta-sigma ADC, six analog inputs, digital temperature compensation, precision voltage reference, and 32-bit computation
engine (CE) supports a wide range of poly-phase metering applications with
very few low-cost external components. A 32kHz crystal time base for the
entire system and internal battery-backup support for RAM and RTC further
reduce system cost.
2
Maximum design flexibility is supported with multiple UARTs, I C, a powerfail comparator, a 5V LCD charge pump, up to 22 DIO pins, and an insystem programmable flash. The device is offered in high (0.1%) and
standard (0.5%) accuracy versions for multifunction residential/commercial
meter applications requiring multiple voltage/current inputs and complex
LCD or DIO configurations.
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of meters that
meet most demanding worldwide electricity metering standards.
LIVE
CT /COIL
LOAD
NEUTRAL
LIVE
LIVE
POWER SUPPLY
CONVERTER
V3.3A V3.3D GNDA GNDD
IA
5V BOOST
VA
TERIDIAN
71M6513
IB
VB
VDRV
REGULATOR
VBAT
IC
VC
VOLTAGE REF
VREF
TEMP SENSOR
VLCD
COM0..3
SERIAL PORTS
IR
TX
RX
SENSE
DRIVE
RX
V1
V2
COMPUTE
ENGINE
SEG0..23
SEG 24..27
DIO 0..11
FLASH
SEG 32..41
DIO 12..21
3/5V LCD
88.88.8888
MISC
TX
COMPARATOR
POWER
FAULT
Etc.
LCD DRIVER
DIO, PULSE
RAM
VBIAS
AMR
BATTERY
V2.5
Wh Accuracy < 0.1% Over 2,000:1
Current Range
Exceeds IEC 62053/ANSIC 12.20
Voltage Reference
< 10ppm/°C (71M6513H)
< 40ppm/°C (71M6513)
Six Sensor Inputs—VDD Referenced
Auxiliary Analog Input for Neutral
Current
Low Jitter Wh/VARh Pulse Outputs
Pulse Count For Pulse Outputs
Four-Quadrant Metering
Phase Sequencing
Line Frequency Count for RTC
Digital Temperature Compensation
Sag Detection
Independent 32-Bit Compute Engine
40-70Hz Line Frequency Range with
Same Calibration
Phase Compensation (±7°)
Battery Backup for RAM and RTC
22mW at 3.3V, 7.2µW Backup
Flash Memory Option with Security
8-Bit MPU (80515)—One Clock
Cycle per Instruction
LCD Driver (≤ 168 Pixels)
High-Speed SSI Serial Output
RTC for Time-of-Use Functions
Hardware Watchdog Timer
Up to 22 General-Purpose I/O Pins
64KB Flash, 7KB RAM
Two UARTs for IR and AMR
100-Pin LQFP Package
MPU
RTC
TIMERS
EEPROM
OSC/PLL
XIN
32 kHz
V3
XOUT
ICE
Single Converter Technology is a registered trademark of
Maxim Integrated Products, Inc.
© 2005-2011 Teridian Semiconductor Corporation
Page: 1 of 104
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Table of Contents
FEATURES ............................................................................................................................ 1
HARDWARE DESCRIPTION ................................................................................................................ 9
Hardware Overview ................................................................................................................. 9
Analog Front End (AFE) .......................................................................................................... 9
Multiplexer................................................................................................................. 9
ADC .......................................................................................................................... 10
FIR Filter ................................................................................................................... 10
Voltage Reference ..................................................................................................... 10
Temperature Sensor .................................................................................................. 11
V3 ............................................................................................................................. 11
Functional Description ............................................................................................... 11
Computation Engine (CE) ........................................................................................................ 12
Meter Equations ........................................................................................................ 12
Pulse Generator ........................................................................................................ 13
Real-Time Monitor ..................................................................................................... 13
CE Functional Overview ............................................................................................ 13
80515 MPU Core .................................................................................................................... 16
80515 Overview ........................................................................................................ 16
Memory Organization ................................................................................................ 16
Special Function Registers (SFRs) ............................................................................. 18
Special Function Registers (Generic 80515 SFRs) ..................................................... 19
Special Function Registers Specific to the 71M6513 ................................................... 22
Instruction Set ........................................................................................................... 23
UART ........................................................................................................................ 23
Timers and Counters ................................................................................................. 26
WD Timer (Software Watchdog Timer) ....................................................................... 28
Interrupts................................................................................................................... 31
External Interrupts ..................................................................................................... 34
Interrupt Priority Level Structure ................................................................................. 35
Interrupt Sources and Vectors.................................................................................... 37
On-Chip Resources................................................................................................................. 39
DIO Ports .................................................................................................................. 39
Page: 2 of 104
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
Physical Memory ....................................................................................................... 41
Oscillator ................................................................................................................... 42
Real-Time Clock (RTC).............................................................................................. 42
Comparators (V2, V3) ................................................................................................ 42
LCD Drivers .............................................................................................................. 43
LCD Voltage Boost Circuitry....................................................................................... 43
UART (UART0) and Optical Port (UART1).................................................................. 44
Hardware Reset Mechanisms .................................................................................... 44
Reset Pin (RESETZ).................................................................................................. 44
Hardware Watchdog Timer ........................................................................................ 44
Crystal Frequency Monitor ......................................................................................... 44
V1 Pin ....................................................................................................................... 44
Internal Clocks and Clock Dividers ............................................................................. 45
I2C Interface (EEPROM) ........................................................................................... 45
Battery ...................................................................................................................... 47
Internal Voltages (VBIAS, VBAT, V2P5) ..................................................................... 47
Test Ports ................................................................................................................. 47
FUNCTIONAL DESCRIPTION .............................................................................................................. 49
Theory of Operation ................................................................................................................ 49
System Timing Summary......................................................................................................... 50
Data Flow ............................................................................................................................... 52
CE/MPU Communication......................................................................................................... 52
Fault, Reset, Power-Up ........................................................................................................... 53
Battery Operation .................................................................................................................... 54
Power Save Modes ................................................................................................................. 54
Chopping Circuitry................................................................................................................... 55
Internal/External Pulse Generation and Pulse Counting ............................................................ 57
Program Security .................................................................................................................... 58
FIRMWARE INTERFACE ..................................................................................................................... 59
I/O RAM MAP – In Numerical Order ......................................................................................... 59
SFR MAP (SFRs Specific to Teridian 80515) – In Numerical Order ........................................... 60
I/O RAM (Configuration RAM) – Alphabetical Order.................................................................. 61
CE Program and Environment ................................................................................................. 67
CE Program .............................................................................................................. 67
Formats..................................................................................................................... 67
© 2005-2011 Teridian Semiconductor Corporation
Page: 3 of 104
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Constants.................................................................................................................. 67
Environment .............................................................................................................. 67
CE Calculations......................................................................................................... 68
CE RAM Locations .................................................................................................... 68
CE Front End Data (Raw Data) .................................................................................. 69
CE Status Word......................................................................................................... 69
CE Transfer Variables ............................................................................................... 70
TYPICAL PERFORMANCE DATA......................................................................................................... 77
Wh Accuracy at Room Temperature ........................................................................................ 77
VARh Accuracy at Room Temperature .................................................................................... 77
Harmonic Performance............................................................................................................ 78
APPLICATION INFORMATION ............................................................................................................. 79
Connection of Sensors (CT, Resistive Shunt, Rogowski Coil) ................................................... 79
Distinction between 71M6513 and 71M6513H Parts................................................................. 79
Temperature Compensation and Mains Frequency Stabilization for the RTC............................. 80
External Temperature Compensation....................................................................................... 81
Temperature Measurement ..................................................................................................... 81
Crystal Oscillator ..................................................................................................................... 83
Connecting LCDs .................................................................................................................... 84
Connecting I2C EEPROMs...................................................................................................... 85
Connecting 5V Devices ........................................................................................................... 85
Optical Interface ...................................................................................................................... 87
Connecting V1 and Reset Pins ................................................................................................ 87
Connecting the V3 Pin............................................................................................................. 88
Connecting a Battery ............................................................................................................... 88
Flash Programming ................................................................................................................. 89
MPU Firmware Library............................................................................................................. 89
SPECIFICATIONS ................................................................................................................................ 90
Electrical Specifications ........................................................................................................... 90
LOGIC LEVELS......................................................................................................... 91
VREF, VBIAS ............................................................................................................ 93
CRYSTAL OSCILLATOR........................................................................................... 93
LCD BOOST ............................................................................................................. 95
LCD DRIVERS .......................................................................................................... 95
RTC .......................................................................................................................... 95
Page: 4 of 104
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
RESETZ.................................................................................................................... 95
COMPARATORS ...................................................................................................... 96
RAM AND FLASH MEMORY ..................................................................................... 96
FLASH MEMORY TIMING ......................................................................................... 96
EEPROM INTERFACE .............................................................................................. 96
Recommended External Components ...................................................................................... 97
Packaging Information............................................................................................................. 98
Pinout (Top View) ...................................................................................................... 99
Pin Descriptions ........................................................................................................ 100
I/O Equivalent Circuits: .............................................................................................. 102
ORDERING INFORMATION ................................................................................................... 103
Figures
Figure 1: IC Functional Block Diagram .......................................................................................................................... 8
Figure 2: General Topology of a Chopped Amplifier ..................................................................................................... 10
Figure 3: AFE Block Diagram...................................................................................................................................... 11
Figure 4: Samples in Multiplexer Cycle ....................................................................................................................... 14
Figure 5: Accumulation Interval.................................................................................................................................. 14
Figure 6: Memory Map .............................................................................................................................................. 16
Figure 7: Interrupt Structure ...................................................................................................................................... 38
Figure 8: DIO Ports Block Diagram ............................................................................................................................. 39
Figure 9: Oscillator Circuit ......................................................................................................................................... 42
Figure 10: LCD Voltage Boost Circuitry....................................................................................................................... 43
Figure 11: Voltage Range for V1 ................................................................................................................................ 45
Figure 12: Voltage. Current, Momentary and Accumulated Energy................................................................................ 49
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers ................................................................ 50
Figure 14: RTM Output Format .................................................................................................................................. 51
Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ............................................................................................ 51
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY) ................................................................. 51
Figure 17: MPU/CE Data Flow .................................................................................................................................... 52
Figure 18: MPU/CE Communication (Functional)......................................................................................................... 53
Figure 19: MPU/CE Communication (Processing Sequence) ........................................................................................ 53
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up................................................. 54
Figure 21: Chop Polarity w/ Automatic Chopping ........................................................................................................ 56
Figure 22: Sequence with Alternate Multiplexer Cycles ................................................................................................ 56
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping ........................................................... 57
Figure 24: Wh Accuracy, 0.3A - 200A/240V ................................................................................................................ 77
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance ................................................................................... 78
Figure 27: Meter Accuracy over Harmonics at 240V, 30A ............................................................................................ 78
Figure 29: Resistive Voltage Divider (left), Current Transformer (right) ......................................................................... 79
Figure 30: Resistive Shunt (left), Rogowski Coil (right) ............................................................................................... 79
Figure 31: Crystal Frequency over Temperature .......................................................................................................... 80
Figure 32: Crystal Compensation ............................................................................................................................... 81
Figure 33: Error Band for VREF over Temperature (Regular-Accuracy Parts)................................................................. 83
© 2005-2011 Teridian Semiconductor Corporation
Page: 5 of 104
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Figure 34: Error Band for VREF over Temperature (High-Accuracy Parts) ..................................................................... 83
Figure 33: Connecting LCDs ...................................................................................................................................... 84
Figure 34: LCD Boost Circuit...................................................................................................................................... 85
Figure 35: EEPROM Connection ................................................................................................................................. 85
Figure 36: Interfacing RX to a 0-5V Signal .................................................................................................................. 86
Figure 37: Connection for Optical Components ........................................................................................................... 87
Figure 38: Voltage Divider for V1 ............................................................................................................................... 87
Figure 39: External Components for RESETZ .............................................................................................................. 88
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles.......................................................... 9
Table 2: CE DRAM Locations for ADC Results ......................................................................................... 12
Table 3: Standard Meter Equations (inputs shown gray are scanned but not used for calculation) .............. 13
Table 4: Stretch Memory Cycle Width ...................................................................................................... 17
Table 5: Internal Data Memory Map ......................................................................................................... 18
Table 6: Special Function Registers Locations ......................................................................................... 18
Table 7: Special Function Registers Reset Values.................................................................................... 20
Table 8: PSW Register Flags................................................................................................................... 20
Table 9: PSW bit functions ...................................................................................................................... 21
Table 10: Port Registers .......................................................................................................................... 22
Table 11: Special Function Registers ....................................................................................................... 23
Table 12: Baud Rate Generation.............................................................................................................. 24
Table 13: UART Modes ........................................................................................................................... 24
Table 14: The S0CON Register................................................................................................................. 24
Table 15: The S1CON register .................................................................................................................. 25
Table 16: The S0CON Bit Functions.......................................................................................................... 25
Table 17: The S1CON Bit Functions.......................................................................................................... 26
Table 18: The TMOD Register ................................................................................................................. 26
Table 19: TMOD Register Bit Description ................................................................................................. 27
Table 20: Timers/Counters Mode Description ........................................................................................... 27
Table 21: The TCON Register .................................................................................................................. 27
Table 22: The TCON Register Bit Functions ............................................................................................. 28
Table 23: Timer Modes............................................................................................................................ 28
Table 24: The PCON Register ................................................................................................................. 28
Table 25: The IEN0 Register (see also Table 32) ...................................................................................... 29
Table 26: The IEN0 Bit Functions (see also Table 32) ............................................................................... 29
Table 27: The IEN1 Register (see also Tables 30/31) ............................................................................... 29
Table 28: The IEN1 Bit Functions (see also Tables 30/31) ........................................................................ 29
Table 29: The IP0 Register (see also Table 45) ........................................................................................ 30
Table 30: The IP0 bit Functions (see also Table 45) ................................................................................. 30
Table 31: The WDTREL Register............................................................................................................. 30
Table 32: The WDTREL Bit Functions...................................................................................................... 30
Table 33: The IEN0 Register .................................................................................................................... 32
Table 34: The IEN0 Bit Functions ............................................................................................................. 32
Table 35: The IEN1 Register ................................................................................................................... 32
Table 36: The IEN1 Bit Functions ............................................................................................................ 32
Table 37: The IEN2 Register ................................................................................................................... 33
Table 38: The IEN2 Bit Functions ............................................................................................................ 33
Page: 6 of 104
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
Table 39: The TCON Register .................................................................................................................. 33
Table 40: The TCON Bit Functions ........................................................................................................... 33
Table 41: The IRCON Register ................................................................................................................. 33
Table 42: The IRCON Bit Functions .......................................................................................................... 34
Table 43: External MPU Interrupts ........................................................................................................... 34
Table 44: Control Bits for External Interrupts ............................................................................................ 35
Table 45: Priority Level Groups................................................................................................................ 35
Table 46: The IP0 Register: ..................................................................................................................... 36
Table 47: The IP1 Register: ..................................................................................................................... 36
Table 48: Priority Levels .......................................................................................................................... 36
Table 49: Interrupt Polling Sequence ....................................................................................................... 36
Table 50: Interrupt Vectors ...................................................................................................................... 37
Table 51: Data Registers, Direction Registers and Internal Resources for DIO Pin Groups ........................ 39
Table 52: DIO_DIR Control Bit ................................................................................................................. 40
Table 53: Selectable Controls using the DIO_DIR Bits .............................................................................. 40
Table 54: MPU Data Memory Map ........................................................................................................... 41
Table 55: Liquid Crystal Display Segment Table (Typical)......................................................................... 43
Table 56: EECTRL Status Bits .................................................................................................................. 46
Table 57: TMUX[3:0] Selections .............................................................................................................. 47
Table 58: SSI Pin Assignment ................................................................................................................. 48
Table 59: Power Saving Measures........................................................................................................... 54
Table 60: CHOP_EN Bits.......................................................................................................................... 55
Table 61: Frequency over Temperature ................................................................................................... 80
© 2005-2011 Teridian Semiconductor Corporation
Page: 7 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
VREF
IA
VA
IB
VB
IC
VC
V3P3A GNDA GNDA
VBIAS
∆Σ ADC
CONVERTER
VBIAS
MUX
V3P3A
VOLTAGE
BOOST
FIR
FILTER
+
VREF
V3
MUX
CTRL
EQU
MUX_ALT
GNDD
FIR_LEN
VREF
CHOP_EN
VREF_DIS
TEMP
CK32
VOLT
REG
MUX_DIV
XIN
OSC
(32KHz)
XOUT
VDRV
LCD_IBST
LCD_BSTEN
V3P3D
VBAT
CK32
MCK
PLL
RTCLK
GNDD
GNDD
OSC_DIS
V2P5
CK_EN
CKTEST
CKFIR
4.9MHz
4.9MHz
CK_GEN
VLCD
CE DATA
RAM
(1KB)
ECK_DIS
MPU_DIV
MUX_SYNC
CE
WPULSE
VARPULSE
RTM
32-bit Compute
Engine
DATA
00-FF
STRT
CKCE
4.9MHz
TEST
EQU
PRE_SAMPS
SUM_CYCLES
MEMORY
SHARE
CE_RUN
3000-3FFF
I/O RAM
XFER BUSY
WPULSE
VARPULSE
CE PROG
RAM
(4KB)
CE_LOAD
CKMPU
SCL
SDA
TX
OPTICAL
I/F
PROG
0000-FFFF
OPT_TXDIS
POWER FAULT
GENERATOR AND
COMPARATORS
V2
COMP_STAT
COMP_INT
V3
MPU XRAM
(2KB)
FLASH
(64KB)
EERDSLOW
EEWRSLOW
VBIAS
V1
XFER_BUSY
CE_BUSY
0000-07FF
WAKE
V3P3
SEG6/SRDY
SEG0..2, SEG3/SCLK,
SEG4/SSDATA,
SEG5/SFR, SEG7..19
SEG24/DIO4 ..
SEG27/DIO7
SEG28/DIO8 ..
SEG31/DIO11
SEG32/DIO12 ..
SEG41/DIO21
DIO_0..3
RTCLK
CONFIGURATION
PARAMETERS
DMUX
F
E
RTCLK
D
reserved
CK_MPU
CK_10M
MUX_SYNC
OPTRX
V3 OK
V2 OK
C
B
WDTR_EN
5
4
RTM
EMULATOR
PORT
FAULTZ
SEG20..23
RTC
RTC_HOLD
RTC_SET
CONFIG
RAM
(I/O RAM)
DATA
0000-FFFF
MPU
(80515)
OPT_RX
EEPROM
INTERFACE
2000-20FF
UART
RX
COM0..3
LCD DISPLAY
DRIVER
LCD_EN
LCD_FS
LCD_MODE
LCD_NUM
LCD_MODE
LCD_CLK
LCD_EN
DIGITAL I/O
DIO_EEX
PULSEV/W
DIO_IN
DIO_OUT
LCD_NUM
DIO_GP
1000-13FF
RTM_EN
CE_EN
CE_BUSY
SSI
MUX
PROG
000-7FF
CE
CONTROL
A
9
PLL_2.5V
IBIAS
3
2
1
DGND
0
VBIAS
DIGITAL
8
7
6
ANALOG
TMUX
V3
RESETZ
Figure 1: IC Functional Block Diagram
Page: 8 of 104
V2P5
2.5V to logic
CKOUT_EN
OPT_TX
GNDD
© 2005-2011 Teridian Semiconductor Corporation
September 19, 2005
TMUXOUT
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
HARDWARE DESCRIPTION
Hardware Overview
The 71M6513 single-chip polyphase meter integrates all primary functional blocks required to implement a solid-state
electricity meter. Included on chip are an analog front end (AFE), an 8051-compatible microprocessor (MPU) which executes
one instruction per clock cycle (80515), an independent 32-bit digital computation engine (CE), a voltage reference, a
temperature sensor, LCD drivers, RAM, flash memory, a real time clock (RTC), and a variety of I/O pins. Various current
sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils.
In addition to advanced measurement functions, the real time clock function allows the 71M6513/6513H to record time of use
(TOU) metering information for multi-rate applications. Measurements can be displayed on either a 3V or a 5V LCD. Flexible
mapping of LCD display segments will facilitate integration with any LCD format. The design trade-off between the number of
LCD segments and DIO pins can be flexibly configured using memory-mapped I/O to accommodate various requirements.
The 71M6513 includes several I/O peripheral functions that improve the functionality of the device and reduce the component
count for most meter applications. The I/O peripherals include two UARTs, digital I/O, comparator inputs, LCD display drivers,
2
I C interface and an optical/IR interface.
One of the two internal UARTs (UART1) is adapted to support an Infrared LED with internal drive output and sense input but it
can also function as a standard UART.
A block diagram of the chip is shown in Figure 1. A detailed description of various hardware blocks follows.
Analog Front End (AFE)
The AFE of the 71M6513 Power Meter IC is comprised of an input multiplexer, a delta-sigma A/D converter with a voltage
reference, followed by an FIR filter. A block diagram of the AFE is shown in Figure 3.
Multiplexer
The input multiplexer supports eight input signals that are applied to the pins IA, VA, IB, VB, IC, VC, and V3 plus the output of
the internal temperature sensor. The multiplexer can be operated in two modes:
•
•
During a normal multiplexer cycle, the signals from the six pins IA, VA, IB, VB, IC, and VC are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the additional monitor input, V3, are
selected, along with the other signal sources shown in Table 1: Inputs Selected in Regular and Alternate Multiplexer
Cycles.
Alternate multiplexer cycles are usually performed infrequently (every second or so). VA, VB, and VC are not replaced in the
alternate multiplexer cycles. In some equations, currents must be delayed in allpass networks and therefore cannot be
replaced in the alternate selection. Missing samples due to alternate multiplexer cycles are automatically interpolated by the
CE.
Regular multiplexer sequence
Mux State:
Alternate multiplexer sequence
Mux State:
0
1
2
3
4
5
0
1
2
3
4
5
IA
VA
IB
VB
IC
VC
TEMP
VA
V3
VB
IC
VC
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
In a typical application, the IA, IB, and IC inputs are connected to current transformers that sense the current on each phase of
the line voltage. VA, VB, and VC are typically connected to voltage sensors through resistor dividers.
The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is
governed by the I/O RAM registers MUX_ALT (0x2005[2]), EQU (0x2000[7:5]), and MUX_DIV (0x2002[7:6]). MUX_DIV controls
the number of samples per cycle. It can request 2, 3, 4, or 6 multiplexer states per cycle.
© 2005-2011 Teridian Semiconductor Corporation
Page: 9 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
The MUX_ALT bit requests an alternate multiplexer cycle. The bit may be asserted on any MPU cycle and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the Control Circuit to wait
until the next multiplexer cycle and implement a single alternate cycle.
Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The
Multiplexer Control Circuit is clocked by CK32, the 32768Hz clock from the PLL block, and launches each pass through the CE
program.
ADC
A single 21/22-bit delta-sigma A/D converter digitizes the power inputs to the AFE. The resolution of the ADC is programmable
using the I/O RAM register FIR_LEN register (0x2005[4]). ADC resolution may be selected to be 21 bits (FIR_LEN=0), or 22
bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1.
Accuracy, timing and functional specifications in this data sheet are based on FIR_LEN = 0 (two CK32 cycles).
Initiation of each ADC conversion is controlled by the Multiplexer Control Circuit as described previously.
FIR Filter
The finite impulse response (FIR) filter is an integral part of the ADC and it is optimized for use with the multiplexer. The
purpose of the FIR is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output
data of the FIR filter (raw data) is stored into the CE DRAM location determined by the multiplexer selection. The location of
the raw data in the CE DRAM is specified in the CE Program and Environment Section.
Voltage Reference
The 71M6513/6513H includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The
reference of the 71M6513H is trimmed in production to minimize errors caused by component mismatch and drift. The result is
a voltage output with a predictable temperature coefficient.
The voltage reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_EN
(0x2002[5:4]). The two bits in the CHOP_EN register enable the MPU to operate the chopper circuit in regular or inverted
operation, or in “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the
measured signals will automatically be averaged out.
The general topology of a chopped amplifier is given in Figure 2.
A
Vinp
B
A
Vinn
A
+
G
-
B
Voutp
B
A
Voutn
B
CROSS
Figure 2: General Topology of a Chopped Amplifier
It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in
the “A” position, the output voltage is:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
Page: 10 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
With all switches set to the “B” position by applying the inverted CROSS signal, the output voltage is:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the output as positive and
negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude.
The Functional Description Section contains a chapter with a detailed description on controlling the CHOP_EN register.
Temperature Sensor
The 71M6513/6513H includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine
the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by
asserting MUX_ALT.
The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in
the system (see section titled “Temperature Compensation”).
The zero reference for the temperature sensor is VBIAS.
V3
V3 is an additional analog monitor input that can be used for analog measurements, such as neutral current. It is sampled
when the multiplexer performs an alternate multiplexer cycle. The zero reference for the V3 input is VBIAS.
V3 is also routed into the comparator block where it is compared to VBIAS. Comparator interrupts should be disabled when
the V3 input is used for analog measurements.
Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB, IC, VC) are
sampled and the ADC counts obtained are stored in CE RAM where they can be accessed by the CE and, if necessary, by the
MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow signals, temperature
and V3.
VREF
IA
VA
IB
VB
IC
VC
VBIAS
∆Σ ADC
CONVERTER
VBIAS
(1.5V)
MUX
V3P3A
+
VREF
V3
TEMP
FIR
FILTER
MUX
MUX
CTRL
EQU
MUX_ALT
CHOP_EN
VREF_DIS
VREF
FIR_LEN
CK32
MUX_DIV
Figure 3: AFE Block Diagram
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Computation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.
The CE calculations and processes include:
•
Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied with the constant sample time).
•
Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between samples caused
by the multiplexing scheme).
•
90° phase shifter (for VAR calculations).
•
Pulse generation.
•
Monitoring of the input signal frequency (for frequency and phase information).
•
Monitoring of the input signal amplitude (for sag detection).
•
Scaling of the processed samples based on chip temperature (temperature compensation) and calibration
coefficients.
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word
is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code
pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the
multiplexer cycle ends (see System Timing Summary in the Functional Description Section).
The CE data RAM (CE DRAM) can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed,
depending on the frequency of CKMPU.
Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.
Address
Name
Zero
Reference
Description
0x00
IA
V3P3
Phase A current
0x01
VA
V3P3
Phase A voltage
0x02
IB
V3P3
Phase B current
0x03
VB
V3P3
Phase B voltage
0x04
IC
V3P3
Phase C current
0x05
VC
V3P3
Phase C voltage
0x06
TEMP
VBIAS
Temperature
0x07
V3
VBIAS
V3 monitor
Table 2: CE DRAM Locations for ADC Results
Meter Equations
The Compute Engine (CE) program for industrial meter configurations implements the equations in Table 3. The I/O RAM
register EQU specifies the equation to be used based on the number and arrangement of phases used for metering. In case of
single and two-phase metering, the unconnected inputs should be tied to V3P3A, the analog supply voltage. The EQU
selection enables the 71M6513 to calculate polyphase power measurement based on the type of service used. Table 3 also
states the sequence of the multiplexer in the AFE.
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EQU
Watt & VAR Formula
Inputs used from MUX sequence
Mux State:
Inputs used from alternate MUX
sequence
Mux State:
0
1
2
3
4
5
0
1
2
3
4
5
0
VA IA
(1 element, 2W 1ø)
IA
VA
IB
VB
IC
VC
TEMP
VA
V3
VC
IC
VC
1
VA(IA-IB)/2
(1 element, 3W 1ø)
IA
VA
IB
VB
IC
VC
TEMP
VA
IB
V3
VC
VC
2
VA IA + VB IB
(2 element, 3W 3 øDelta)
IA
VA
IB
VB
IC
VC
TEMP
VA
V3
VB
VC
VC
3
VA (IA - IB)/2 + VC IC
(2 element, 4W 3ø Delta)
IA
VA
IB
VB
IC
VC
TEMP
VA
IB
V3
IC
VC
4
VA(IA-IB)/2 + VB(IC-IB)/2
(2 element, 4W 3ø Wye)
IA
VA
IB
VB
IC
VC
TEMP
VA
IB
V3
IC
VC
5
VA IA + VB IB + VC IC
(3 element, 4W 3ø Wye)
IA
VA
IB
VB
IC
VC
TEMP
VA
V3
VB
IC
VC
Table 3: Standard Meter Equations (inputs shown gray are scanned but not used for calculation)
Pulse Generator
The CE contains two pulse generators which create low jitter pulses at a rate set by the CE DRAM registers APULSEW*WRATE
and APULSER*WRATE if EXT_PULSE (a CE input variable in CE DRAM) is 15. This mode puts the MPU in control of pulse
generation by placing values into the APULSEW and APULSER registers (“external pulse generation”).
If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X. In this mode, the CE
generates pulse based on its internal computation of WSUM_X and VARSUM_X, the signed sums of energy from all three
elements (“internal pulse generation”).
The DIO_PV and DIO_PW bits as described in the Digital I/O section can be programmed to route WPULSE and VARPULSE
to the output pins DIO6 and DIO7 respectively. DIO6 and DIO7 can be configured to generate interrupts, which can be useful
for pulse counting by the MPU (see On-Chip Resources, DIO Ports section).
Real-Time Monitor
The CE contains a Real Time Monitor (RTM), which can be programmed to monitor four selectable CE RAM locations at full
sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the
beginning of each CE code pass (see the Test Ports Section for details)
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the six samples taken during
one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS
(0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]
For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100
and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation
cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.
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1/2520.6Hz = 397µs
IB
2/32768Hz =
61.04µs
B
VB
A
IC
VC
IA
VA
C
13/32768Hz = 397µs
per mux cycle
Figure 4: Samples in Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle,
status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 5: Accumulation Interval
Figure 5 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples
of 397µs each (only one phase is shown) followed by the XFER_BUSY interrupt. The sampling in this example is applied to a
50Hz signal.
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when
SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6ms). Furthermore, sampling does not have to
start when the line voltage crosses the zero line.
Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be
sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
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φ=
t delay
T
⋅ 360 o = t delay ⋅ f ⋅ 360 o
Where f is the frequency of the input signal and tdelay is the sampling delay between voltage and current.
In traditional meter ICs, sampling is accomplished by using two A/D converters per phase (one for voltage and the other one
for current) controlled to sample simultaneously. Our Single-Converter Technology, however, exploits the 32-bit signal
processing capability of its CE to implement “constant delay” all-pass filters. These all-pass filters correct for the conversion
time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed A/D
converter.
The “constant delay” all-pass filters provide a broad-band delay β that is precisely matched to the difference in sample time
between the voltage and the current of a given phase. This digital filter does not affect the amplitude of the signal, but
provides a precisely controlled phase response. The delay compensation implemented in the CE aligns the voltage samples
with their corresponding current samples by routing the voltage samples through the all-pass filter, thus delaying the voltage
samples by β, resulting in the residual phase error β – Ф. The residual phase error is negligible, and is typically less than ±1.5
milli-degrees at 100Hz, thus it does not contribute to errors in the energy measurements.
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80515 MPU Core
80515 Overview
The 71M6513/6513H includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle.
Using a 5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and
implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0].
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are
available for the MPU as part of Teridian’s standard library. A standard ANSI “C” 80515-application programming interface
library is available to help reduce design cycle.
Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program
memory (flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, CE PRAM and I/O RAM, and
internal data memory (Internal RAM). Figure 6 shows the memory map (see also Table 54).
Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6513 IC. External data memory is only external to the 80515 MPU core.
0xFFFF
Flash memory
0x0000
Program memory
0xFFFF
--0x4000
0x3FFF
CE PRAM
0x3000
0x2FFF
--0x2100
0x20FF
I/O RAM
0x2000
0x1FFF
--0x1400
0x13FF
CE DRAM
0x1000
0x0FFF
--0x0800
0x07FF
XRAM
0x0000
External data memory
0xFF
SFRs, RAM,
reg. banks
0x00
Internal data memory
Figure 6: Memory Map
Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory
is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and
interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.
External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to
0xFFFF, only the memory ranges shown in Figure 6 contain physical memory. The 80515 writes into external data memory
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when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing
a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction).
Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low ordered
bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very
slow external RAM or external peripherals.
Table 4 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of
the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table,
performs the MOVX instructions with a stretch value equal to 1.
CKCON register
Stretch Value
Read signals width
Write signal width
memaddr
memrd
memaddr
memwr
0
1
1
2
1
1
1
2
2
3
1
1
0
2
3
3
4
2
0
1
1
3
4
4
5
3
1
0
0
4
5
5
6
4
1
0
1
5
6
6
7
5
1
1
0
6
7
7
8
6
1
1
1
7
8
8
9
7
CKCON.2
CKCON.1
CKCON.0
0
0
0
0
0
0
Table 4: Stretch Memory Cycle Width
There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external
data RAM.
In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits of
address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user paged access
(256 pages of 256 bytes each) to the full 64KB of external data RAM. In the second type of MOVX instruction (MOVX
A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient when accessing very large
data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and
two with paged access to the entire 64KB of external memory range.
Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is
used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data
pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB
of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.
The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently
selected DPTR for any activity.
The second data pointer may not be supported by certain compilers.
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Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data
memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special Function
Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing
accesses the upper 128 bytes of Internal RAM.
The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight
registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a
block of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible
through direct or indirect addressing. Table 5 shows the internal data memory map.
Address
0xFF
0x80
Direct addressing
Indirect addressing
Special Function Registers
(SFRs)
RAM
0x7F
Byte-addressable area
0x30
0x2F
Bit-addressable area
0x20
0x1F
Register banks R0…R7
0x00
Table 5: Internal Data Memory Map
Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 6.
Hex\Bin
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
Bit-addressable
X000
INTBITS
B
WDI
A
WDCON
PSW
Byte-addressable
X001
IRCON
IEN1
IP1
IEN0
P2
S0CON
P1
TCON
P0
IP0
DIR2
S0BUF
DIR1
TMOD
SP
X010
S0RELH
FLSHCTL
S0RELL
DIR0
IEN2
DPS
TL0
DPL
X011
X100
Bin/Hex
X101
X110
S1RELH
S1CON
TL1
DPH
X111
USR2
PGADR
S1BUF
ERASE
TH0
DPL1
S1RELL
EEDATA
EECTRL
TH1
DPH1
CKCON
WDTREL
PCON
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
Table 6: Special Function Registers Locations
Only a few addresses are occupied, the others are not implemented. SFRs specific to the 651X are shown in bold print. Any
read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers
at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable.
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Special Function Registers (Generic 80515 SFRs)
Table 7 shows the location of the SFRs and the value they assume at reset or power-up.
Name
Location
Reset value
Description
P0
SP
DPL
DPH
DPL1
DPH1
WDTREL
PCON
TCON
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0xFF
0x07
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Port 0
Stack Pointer
Data Pointer Low 0
Data Pointer High 0
Data Pointer Low 1
Data Pointer High 1
Watchdog Timer Reload register
UART Speed Control
Timer/Counter Control
TMOD
0x89
0x00
Timer Mode Control
TL0
0x8A
0x00
Timer 0, low byte
TL1
0x8B
0x00
Timer 1, high byte
TH0
0x8C
0x00
Timer 0, low byte
TH1
0x8D
0x00
Timer 1, high byte
CKCON
0x8E
0x01
Clock Control (Stretch=1)
P1
0x90
0xFF
Port 1
DPS
0x92
0x00
Data Pointer select Register
S0CON
0x98
0x00
Serial Port 0, Control Register
S0BUF
0x99
0x00
Serial Port 0, Data Buffer
IEN2
0x9A
0x00
Interrupt Enable Register 2
S1CON
0x9B
0x00
Serial Port 1, Control Register
S1BUF
0x9C
0x00
Serial Port 1, Data Buffer
S1RELL
0x9D
0x00
Serial Port 1, Reload Register, low byte
P2
0xA0
0x00
Port 2
IEN0
0xA8
0x00
Interrupt Enable Register 0
IP0
0xA9
0x00
Interrupt Priority Register 0
S0RELL
0xAA
0xD9
Serial Port 0, Reload Register, low byte
P3
0xB0
0xFF
Port 3
IEN1
0xB8
0x00
Interrupt Enable Register 1
IP1
0xB9
0x00
Interrupt Priority Register 1
S0RELH
0xBA
0x03
Serial Port 0, Reload Register, high byte
S1RELH
0xBB
0x03
Serial Port 1, Reload Register, high byte
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Name
USR2
Location
0xBF
Reset value
0x00
Description
User 2 Port, high address byte for MOVX@Ri
IRCON
0xC0
0x00
Interrupt Request Control Register
PSW
0xD0
0x00
Program Status Word
WDCON
0xD8
0x00
Baud Rate Control Register (only WDCON.7 bit used)
A
0xE0
0x00
Accumulator
B
0xF0
0x00
B Register
Table 7: Special Function Registers Reset Values
Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The
mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.
B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold
temporary data.
Program Status Word (PSW):
MSB
CV
LSB
AC
F0
RS1
RS
OV
-
Table 8: PSW Register Flags
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Bit
Symbol
Function
PSW.7
CV
Carry flag
PSW.6
AC
Auxiliary Carry flag for BCD operations
PSW.5
F0
General purpose Flag 0 available for user. Not to be confused with the F0 flag
in the CESTATUS register.
PSW.4
RS1
Register bank select control bits. The contents of RS1 and RS0 select the working
register bank:
RS1/RS0
Bank selected
Location
PSW.3
RS0
00
Bank 0
(0x00 – 0x07)
01
Bank 1
(0x08 – 0x0F)
10
Bank 2
(0x10 – 0x17)
11
Bank 3
(0x18 – 0x1F)
Overflow flag
PSW.2
OV
PSW.1
-
User defined flag
PSW.0
P
Parity flag, affected by hardware to indicate odd / even number of “one” bits in the
Accumulator, i.e. even parity.
Table 9: PSW bit functions
Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or
data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented
during the fetching operation code or when operating on data from program memory.
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Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be
observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 10) causes the corresponding pin to
be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction
registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section On-Chip Resources, DIO Ports for
details).
Register
SFR
Address
R/W
Description
P0
DIR0
0x80
0xA2
R/W
R/W
P1
DIR1
P2
DIR2
0x90
0x91
0xA0
0xA1
R/W
R/W
R/W
R/W
Register for port 0 read and write operations (pins DIO0…DIO7)
Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is
an output.
Register for port 1 read and write operations (pins DIO8…DIO15)
Data direction register for port 1.
Register for port 2 read and write operations (pins DIO16…DIO21)
Data direction register for port 2.
Table 10: Port Registers
All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P3’), an output driver, and an input
buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the
state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control.
Special Function Registers Specific to the 71M6513
Table 11 shows the location and description of the 71M6513-specific SFRs.
Register
Alternative
Name
SFR
Address
R/W
ERASE
FLSH_ERASE
0x94
W
PGADDR
FLSH_PGADR
0xB7
R/W
0x9E
0x9F
R/W
R/W
0xB2
R/W
Description
This register is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle (default =
0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write
to FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a
write to FLSH_MEEN @ SFR 0xB2 and the debug port must
be enabled.
Any other pattern written to FLSH_ERASE will have no effect.
EEDATA
EECTRL
Page: 22 of 104
Flash Page Erase Address register containing the flash memory
page address (page 0 thru 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase cycle.
I2C EEPROM interface data register
I2C EEPROM interface control register. If the MPU wishes to write a
byte of data to EEPROM, it places the data in EEDATA and then
writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates
the transmit sequence. See the section I2C Interface (EEPROM) for
a description of the command and status bits available for EECTRL.
Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation
(default).
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Register
Alternative
Name
SFR
Address
R/W
W
R/W
R
0xE8
WDI
R/W
R/W
W
INTBITS
INT0…INT6
0xF8
R
Description
1 – MOVX @DPTR,A moves A to Program Space (flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes
to this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
Only byte operations on the whole WDI register should be used
when writing. The byte must have all bits set except the bits that are
to be cleared.
The multi-purpose register WDI contains the following bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
This flag monitors the XFER_BUSY interrupt. It is set by hardware
and must be cleared by the interrupt handler
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by hardware and
must be cleared by the interrupt handler
Bit 7 (WD_RST): WD Timer Reset:
The WDT is reset when a 1 is written to this bit.
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have
any memory and are primarily intended for debug use
Table 11: Special Function Registers
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated
op-codes is contained in the 651X Software User’s Guide (SUG).
UART
The 71M6513 includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second
UART (UART1) is connected to the optical port, as described in the optical port description.
The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s
((with MPU clock = 1.2288MHz). The operation of each pin is as follows:
RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. The voltage applied
at RX must not exceed 3.6V.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6513 has several UART-related registers for the control and buffering of serial data.. A single SFR register serves as
both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1). When written by
the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the receive buffer. Writing data to the
transmit buffer starts the transmission by the associated UART. Received data are available by reading from the receive
buffer. Both UARTs can simultaneously transmit and receive data.
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WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are programmable for parity
enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps.
Table 12 shows how the baud rates are calculated. Table 13 shows the selectable UART operation modes.
Using Timer 1
Using Internal Baud Rate Generator
Serial Interface 0
2smod * fCKMPU/ (384 * (256-TH1))
2smod * fCKMPU/(64 * (210-S0REL))
Serial Interface 1
N/A
fCKMPU/(32 * (210-S1REL))
Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the
SMOD bit in the SFR PCON. TH1 is the high byte of timer 1.
Table 12: Baud Rate Generation
UART 0
UART 1
Mode 0
N/A
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Mode 1
Start bit, 8 data bits, stop bit,
variable baud rate (internal baud
rate generator or timer 1)
Start bit, 8 data bits, stop bit, variable baud rate
(internal baud rate generator)
Mode 2
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of
fCKMPU
N/A
Mode 3
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud
rate generator or timer 1)
N/A
Table 13: UART Modes
Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those
used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without
parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading
th
the 9 bit, using the control bits TB80 (S0CON.3) and TB81 (S1CON.3) in the S0CON and S1CON SFRs for transmit and RB81
(S1CON.2) for receive operations. SM20 (S0CON.5) and SM21 (S1CON.5) can be used as handshake signals for inter-processor
communication in multi-processor systems.
Serial Interface 0 Control Register (S0CON).
The function of the UART0 depends on the setting of the Serial Port Control Register S0CON.
MSB
SM0
LSB
SM1
SM20
REN0
TB80
RB80
TI0
Table 14: The S0CON Register
Page: 24 of 104
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Serial Interface 1 Control Register (S1CON).
The function of the serial port depends on the setting of the Serial Port Control Register S1CON.
MSB
LSB
SM
-
SM21
REN1
TB81
RB81
TI1
RI1
Table 15: The S1CON register
Bit
S0CON.7
S0CON.6
Symbol
SM0
SM1
Function
These two bits set the UART0 mode:
Mode
Description
SM0
0
N/A
0
SM1
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
1
S0CON.5
SM20
Enables the inter-processor communication feature.
S0CON.4
REN0
If set, enables serial reception. Cleared by software to disable reception.
S0CON.3
TB80
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
S0CON.2
RB80
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,
RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by
software
S0CON.1
TI0
Transmit interrupt flag, set by hardware after completion of a serial
transfer. Must be cleared by software.
S0CON.0
RI0
Receive interrupt flag, set by hardware after completion of a serial
reception. Must be cleared by software
Table 16: The S0CON Bit Functions
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Bit
Symbol
S1CON.7
SM
Function
Sets the baud rate for UART1
SM
Mode
Description
Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
S1CON.5
SM21
Enables the inter-processor communication feature.
S1CON.4
REN1
If set, enables serial reception. Cleared by software to disable reception.
S1CON.3
TB81
The 9 transmitted data bit in Mode A. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
S1CON.2
RB81
In Modes 2 and 3, it is the 9th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
S1CON.1
TI1
Transmit interrupt flag, set by hardware after completion of a serial
transfer. Must be cleared by software.
S1CON.0
RI1
Receive interrupt flag, set by hardware after completion of a serial
reception. Must be cleared by software
th
Table 17: The S1CON Bit Functions
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer
operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU
clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0
and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes 2 machine cycles
to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the
duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used
to select the appropriate mode.
Timer/Counter Mode Control register (TMOD):
MSB
GATE
LSB
C/T
M1
Timer 1
M0
GATE
C/T
M1
Timer 0
M0
Table 18: The TMOD Register
Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 21 and Table 22) start their associated timers when set.
Page: 26 of 104
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Bit
Symbol
Function
TMOD.7
TMOD.3
Gate
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,
respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a
counter is incremented every falling edge on t0 or t1 input pin
TMOD.6
TMOD.2
C/T
Selects Timer or Counter operation. When set to 1, a Counter operation is
performed. When cleared to 0, the corresponding register will function as a Timer.
TMOD.5
TMOD.1
M1
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
description.
TMOD.4
TMOD.0
M0
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
description.
Table 19: TMOD Register Bit Description
M1
M0
Mode
Function
0
0
Mode 0
13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1 are held at zero.
0
1
Mode 1
16-bit Counter/Timer.
1
0
Mode2
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,
while TL0 or TL1 is incremented every machine cycle. When TL(x)
overflows, a value from TH(x) is copied to TL(x).
1
1
Mode3
If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0
bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.
Table 20: Timers/Counters Mode Description
Note:
TL0 is affected by TR0 and gate control bits, and sets TF0 flag on overflow.
TH0 is affected by TR1 bit, and sets TF1 flag on overflow.
Timer/Counter Control Register (TCON)
MSB
TF1
LSB
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 21: The TCON Register
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Bit
Symbol
Function
TCON.7
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
TCON.6
TR1
Timer 1 Run control bit. If cleared, Timer 1 stops.
TCON.5
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is
processed.
TCON.4
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON.3
IE1
TCON.2
IT1
TCON.1
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin
int0 is observed. Cleared when an interrupt is processed.
TCON.0
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input
pin to cause interrupt.
Interrupt 1 edge flag is set by hardware when the falling edge on external pin
int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level on input
pin to cause an interrupt.
Table 22: The TCON Register Bit Functions
Table 23 specifies the combinations of operation modes allowed for timer 0 and timer 1:
Timer 1
Mode 0
Mode 1
Mode 2
Timer 0 - mode 0
YES
YES
YES
Timer 0 - mode 1
YES
YES
YES
Timer 0 - mode 2
Not allowed
Not allowed
YES
Table 23: Timer Modes
Timer/Counter Mode Control Register (PCON):
MSB
LSB
SMOD
Table 24: The PCON Register
The SMOD bit in the PCON register doubles the baud rate when set.
WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the
watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register
(WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the
internal reset signal becomes active.
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF,
an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state.
WDTS is cleared either by the reset signal or by changing the state of the WDT.
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Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from
becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction
sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock
cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is
reloaded with the content of the WDTREL register and WDT is automatically reset. Since the WDT requires exact timing,
firmware needs to be designed with special care in order to avoid unwanted WDT resets. Teridian strongly discourages the
use of the software WDT.
Special Function Registers for the WD Timer
Interrupt Enable 0 Register (IEN0):
MSB
LSB
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
Table 25: The IEN0 Register (see also Table 32)
Bit
Symbol
IEN0.6
WDT
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is
set to prevent an unintentional refresh of the watchdog timer. WDT is reset by
hardware 12 clock cycles after it has been set.
Table 26: The IEN0 Bit Functions (see also Table 32)
Note: The remaining bits in the IEN0 register are not used for watchdog control
Interrupt Enable 1 Register (IEN1):
MSB
LSB
EXEN2
SWDT
EX6
EX5
EX4
EX3
EX2
Table 27: The IEN1 Register (see also Tables 30/31)
Bit
Symbol
IEN1.6
SWDT
Function
Watchdog timer start/refresh flag.
Set to activate/refresh the watchdog timer. When directly set after setting WDT, a
watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock
cycles after it has been set.
Table 28: The IEN1 Bit Functions (see also Tables 30/31)
Note: The remaining bits in the IEN1 register are not used for watchdog control
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Interrupt Priority 0 Register (IP0):
MSB
LSB
--
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Table 29: The IP0 Register (see also Table 45)
Bit
Symbol
IP0.6
WDTS
Function
Watchdog timer status flag. Set when the watchdog timer was started. Can be
read by software.
Table 30: The IP0 bit Functions (see also Table 45)
Note: The remaining bits in the IP0 register are not used for watchdog control
Watchdog Timer Reload Register (WDTREL):
MSB
LSB
7
6
5
4
3
2
1
0
Table 31: The WDTREL Register
Bit
Symbol
Function
WDTREL.7
7
Prescaler select bit. When set, the watchdog is clocked through an additional
divide-by-16 prescaler
WDTREL.6
to
WDTREL.0
6-0
Seven bit reload value for the high-byte of the watchdog timer. This value is
loaded to the WDT when a refresh is triggered by a consecutive setting of bits
WDT and SWDT.
Table 32: The WDTREL Bit Functions
The WDTREL register can be loaded and read at any time.
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Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special
function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or
disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the
71M6513/6513H, for example the CE, DIO, RTC EEPROM interface, comparators.
Interrupt Overview: When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 50. Once
interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction, "RETI". When a RETI instruction is performed, the processor will return to the instruction that would
have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled
by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set.
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector
address, if the following conditions are met:
•
No interrupt of equal or higher priority is already in progress.
•
An instruction is currently being executed and is not completed.
•
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs. If the
MPU is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases, the
response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This
includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL.
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Special Function Registers for Interrupts:
Interrupt Enable 0 register (IE0)
MSB
LSB
EAL
WDT
ES0
ET1
EX1
ET0
EX0
Table 33: The IEN0 Register
Bit
Symbol
Function
IEN0.7
EAL
EAL=0 – disable all interrupts
IEN0.6
WDT
Not used for interrupt control
IEN0.5
-
IEN0.4
ES0
ES0=0 – disable serial channel 0 interrupt
IEN0.3
ET1
ET1=0 – disable timer 1 overflow interrupt
IEN0.2
EX1
EX1=0 – disable external interrupt 1
IEN0.1
ET0
ET0=0 – disable timer 0 overflow interrupt
IEN0.0
EX0
EX0=0 – disable external interrupt 0
Table 34: The IEN0 Bit Functions
Interrupt Enable 1 Register (IEN1)
MSB
LSB
SWDT
EX6
EX5
EX4
EX3
Table 35: The IEN1 Register
Bit
Symbol
Function
IEN1.7
-
IEN1.6
SWDT
IEN1.5
EX6
EX6=0 – disable external interrupt 6
IEN1.4
EX5
EX5=0 – disable external interrupt 5
IEN1.3
EX4
EX4=0 – disable external interrupt 4
IEN1.2
EX3
EX3=0 – disable external interrupt 3
IEN1.1
EX2
EX2=0 – disable external interrupt 2
IEN1.0
-
Not used for interrupt control
Table 36: The IEN1 Bit Functions
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Interrupt Enable 2 register (IE2)
MSB
LSB
-
-
-
-
-
-
-
ES1
Table 37: The IEN2 Register
Bit
Symbol
IEN2.0
ES1
Function
ES1=0 – disable serial channel 1 interrupt
Table 38: The IEN2 Bit Functions
Timer/Counter Control register (TCON)
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 39: The TCON Register
Bit
Symbol
Function
TCON.7
TF1
Timer 1 overflow flag
TCON.6
TR1
Not used for interrupt control
TCON.5
TF0
Timer 0 overflow flag
TCON.4
TR0
Not used for interrupt control
TCON.3
IE1
External interrupt 1 flag
TCON.2
IT1
External interrupt 1 type control bit
TCON.1
IE0
External interrupt 0 flag
TCON.0
IT0
External interrupt 0 type control bit
Table 40: The TCON Bit Functions
Interrupt Request register (IRCON)
MSB
LSB
EX6
IEX5
IEX4
IEX3
IEX2
Table 41: The IRCON Register
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Bit
Symbol
Function
IRCON.7
-
IRCON.6
-
IRCON.5
IEX6
External interrupt 6 edge flag
IRCON.4
IEX5
External interrupt 5 edge flag
IRCON.3
IEX4
External interrupt 4 edge flag
IRCON.2
IEX3
External interrupt 3 edge flag
IRCON.1
IEX2
External interrupt 2 edge flag
IRCON.0
Table 42: The IRCON Bit Functions
Note: Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine
is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called).
External Interrupts
The external interrupts are connected as shown in Table 43. The polarity of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to
achieve the edge polarity shown in Table 43.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6
enable and flag bits (see Table 44), and these interrupts must be cleared by the MPU software.
External
Interrupt
Connection
Polarity
Flag Reset
0
Digital I/O High Priority
see DIO_Rx
automatic
1
Digital I/O Low Priority
see DIO_Rx
automatic
2
Comparator 2 or 3
falling
automatic
3
CE_BUSY
falling
automatic
4
Comparator 2 or 3
rising
automatic
5
EEPROM busy
falling
automatic
6
XFER_BUSY OR RTC_1SEC
falling
manual
Table 43: External MPU Interrupts
Interrupt 6 is edge-sensitive. The RTC_1SEC interrupt from the RTC and the XFER_BUSY interrupt from the CE are combined using a logic OR function and the result is routed into interrupt 6. Therefore, both flags must be cleared at least once
during initialization, and both flags must always be cleared before exiting the interrupt service routine (ISR) for interrupt 6.
Note 1: If clearing of both flags is not performed, then no edge can occur to trigger interrupt 6 later resulting in the ISR for the
XFER_BUSY ceasing to run.
Note 2: Clearing both flags reliably requires some care. Either flag can be set by hardware while interrupt 6 code is running on
behalf of the other interrupt. In this situation, the unprocessed interrupt can create a lockout condition similar to the one in note
1. To prevent this lockout one must always process both interrupt flags in the same service routine.
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Note 3: After a reset from an in-circuit emulator, the IE_XFER flag may not be cleared because the CE may continue to run.
The flags for the RTC_1SEC and the XFER_BUSY interrupts are located in the WDI SFR (address 0xE8).
Enable Bit
Description
Flag Bit
Description
EX0
Enable external interrupt 0
IE0
External interrupt 0 flag
EX1
Enable external interrupt 1
IE1
External interrupt 1 flag
EX2
Enable external interrupt 2
IEX2
External interrupt 2 flag
EX3
Enable external interrupt 3
IEX3
External interrupt 3 flag
EX4
Enable external interrupt 4
IEX4
External interrupt 4 flag
EX5
Enable external interrupt 5
IEX5
External interrupt 5 flag
EX6
Enable external interrupt 6
IEX6
External interrupt 6 flag
EX_XFER
Enable XFER_BUSY interrupt
EX_RTC
Enable RTC_1SEC interrupt
IE_XFER
IE_RTC
XFER_BUSY interrupt flag
RTC_1SEC interrupt flag
Table 44: Control Bits for External Interrupts
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 45:
Group
0
External interrupt 0
Serial channel 1 interrupt
1
Timer 0 interrupt
-
External interrupt 2
2
External interrupt 1
-
External interrupt 3
3
Timer 1 interrupt
-
External interrupt 4
4
Serial channel 0 interrupt
-
External interrupt 5
5
-
-
External interrupt 6
Table 45: Priority Level Groups
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 49 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44),
and these interrupts must be cleared by the MPU software.
An overview of the interrupt structure is shown in Figure 7.
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Interrupt Priority 0 Register (IP0)
MSB
LSB
--
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Table 46: The IP0 Register:
Note: WDTS is not used for interrupt controls
Interrupt Priority 1 Register (IP1)
MSB
LSB
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
Table 47: The IP1 Register:
IP1.x
IP0.x
Priority Level
0
0
Level0 (lowest)
0
1
Level1
1
0
Level2
1
1
Level3 (highest)
Table 48: Priority Levels
External interrupt 0
Serial channel 1 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Polling sequence
Timer 0 interrupt
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Table 49: Interrupt Polling Sequence
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Interrupt Sources and Vectors
Table 50 shows the interrupts with their associated flags and vector addresses.
Interrupt Request Flag
Description
Interrupt Vector Address
IE0
External interrupt 0
0x0003
TF0
Timer 0 interrupt
0x000B
IE1
External interrupt 1
0x0013
TF1
Timer 1 interrupt
0x001B
RI0/TI0
Serial channel 0 interrupt
0x0023
RI1/TI1
Serial channel 1 interrupt
0x0083
IEX2
External interrupt 2
0x004B
IEX3
External interrupt 3
0x0053
IEX4
External interrupt 4
0x005B
IEX5
External interrupt 5
0x0063
IEX6
External interrupt 6
0x006B
Table 50: Interrupt Vectors
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DIO
External
Interrupt
Flags
Internal
Interrupt
Flags
Logic and
Polarity
Selection
Interrupt
Control
Re g i s t e r
Interrupt
Enable
IEN0.7
IEN0.0
Priority
Assignment
IE0
IEN2.0
RI1
UART1
(optical)
IP1.0/
IP0.0
Polling Se quen ce
Source
>=1
TI1
IEN0.1
TF0
Timer 0
IEN1.1
I2FR
Comparators
INT2
IP1.1/
IP0.1
IRCON.1
IEN0.2
DIO
IE1
I3FR
CE_BUSY
IEN1.2
INT3
IP1.2/
IP0.2
IRCON.2
IEN0.3
Timer 1
TF1
IEN1.3
Comparators
IRCON.3
INT4
IEN0.4
RI0
UART0
>=1
TI0
IEN1.4
EEPROM/
I2C
IP1.3/
IP0.3
INT5
IP1.4/
IP0.4
IRCON.4
IEN1.5
INT6
IRCON.5
XFER_BUSY
>=1
RTC_1S
Figure 7: Interrupt Structure
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On-Chip Resources
DIO Ports
The 71M6513/6513H includes up to 22 pins of general purpose digital I/O. 18 of these pins are dual function and can
alternatively be used as LCD drivers. Figure 8 shows a block diagram of the DIO section.
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction. The pins are configured and
controlled by the DIO and DIO_DIR registers (SFRs) and by the five bits of the I/O register LCD_NUM (0x2020[4:0]). See the
description for LCD_NUM in the I/O RAM Section for a table listing the available segment pins versus DIO pins, depending on
the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general
purpose pins to be LCD segment pins, starting at the higher pin numbers.
COM0..3
LCD DISPLAY
DRIVER
SEG6/SRDY
SEG0..2, SEG3/SCLK,
SEG4/SSDATA,
SEG5/SFR, SEG7..19
LCD_NUM
LCD_MODE
LCD_CLK
LCD_EN
DIGITAL I/O
DIO_EEX
PULSEV/W
DIO_IN
DIO_OUT
LCD_NUM
DIO_GP
SEG20..23
SEG24/DIO4 ..
SEG27/DIO7
SEG28/DIO8 ..
SEG31/DIO11
SEG32/DIO12 ..
SEG41/DIO21
DIO_0..3
Figure 8: DIO Ports Block Diagram
DIO
Pin number
Pin type
Data Register bit
0
18
0
1
2
3
4
5
6
19 20 21 60 61 62
DIO
Multi-use
1
2
3
4
5
6
DIO0=P0 (SFR 0x80)
---4
5
6
DIO_DIR0 (SFR 0xA2)
7
63
8
67
9
68
7
0
1
7
0
1
Y
Y
Y
Y
19 20 21 22
64 65 66
-Multi-use
1
2
3
4
5
-DIO2=P2 (SFR 0xA0)
1
2
3
4
5
-DIO_DIR2 (SFR 0xA1)
23
--
N
--
Direction Register
bit
Internal Resources
Configurable
-Y
Y
Y
DIO
Pin number
Pin type
16
34
17
16
18
17
Data Register bit
Direction Register
bit
Internal Resources
Configurable
0
0
N
N
Y
N
Y
N
Y
N
--
10
69
11 12 13 14
70 98 99 30
Multi-use
2
3
4
5
6
DIO1=P1 (SFR 0x90)
2
3
4
5
6
DIO_DIR1 (SFR 0x91)
Y
Y
N
N
N
15
31
7
7
N
---
Table 51: Data Registers, Direction Registers and Internal Resources for DIO Pin Groups
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Each pin declared as DIO can be configured independently as an input or output with the bits of the DIO_DIRn registers. Table
51 lists the direction registers and configurability associated with each group of DIO pins. Table 52 shows the configuration for
a DIO pin through its associated bit in its DIO_DIR register.
DIO_DIR bit
DIO Pin Function
0
1
input
output
Table 52: DIO_DIR Control Bit
Values read from and written into the DIO ports use the data registers P0, P1 and P2.
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when
configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 51 for DIO pins
available for this option). This way, DIO pins can be tracked even if they are configured as outputs. This feature is useful for
pulse counting. The control resources selectable for the DIO pins are listed in Table 53. If more than one input is connected to
the same resource, the resources are combined using a logical OR.
DIO_R
Value
Resource Selected for DIO Pin
0
NONE
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0 rising)
5
Low priority I/O interrupt (INT1 rising)
6
High priority I/O interrupt (INT0 falling)
7
Low priority I/O interrupt (INT1 falling)
Table 53: Selectable Controls using the DIO_DIR Bits
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6,
VARPULSE = DIO7) using the I/O RAM registers DIO_PW (0x2008[2]) and DIO_PV (0x2008[3]). In this case, DIO6 and DIO7
are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface by setting the I/O RAM register
DIO_EEX (0x2008[4]).
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Physical Memory
Data bus address space is allocated to on-chip memory as shown in Table 54.
Address
(hex)
Memory
Technology
Memory Type
0000-FFFF
Flash Memory
Non-volatile
0000-07FF
1000-13FF
Static RAM
Static RAM
Battery-buffered
Volatile
2000-20FF
Static RAM
Volatile
3000-3FFF
Static RAM
Volatile
Typical Usage
Program and non-volatile
data
MPU data RAM
CE data
Configuration RAM
(I/O RAM)
CE Program code
Wait States
(at 5MHz)
Memory Size
(bytes)
0
64KB
0
5
2KB
1KB
0
256
5
4KB
Table 54: MPU Data Memory Map
Flash Memory: The 71M6513 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU
program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations.
The I/O RAM bit register FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw,
this bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
1.
2.
Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
Write pattern 0xAA to FLSH_ERASE (SFR address 0x94)
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1.
2.
Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]
Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)
Writing to flash memory:
The MPU may write to the flash memory for non-volatile data storage or when implementing a boot-loader. The I/O RAM
register FLSH_PWE (flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL =1. After the
write operation, FLSH_PWE must be cleared.
The original state of a flash byte is 0xFF (all bits are 1). Overwriting programmed flash cells with a different value usually requires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a
page erase. After this, the page can be updated in RAM and then written back to the flash memory.
Writing to flash locations will affect the corresponding XRAM cells, i.e. 0x2000 to 0x20FF (I/O RAM), 0x0000 to
0x07FF (MPU RAM), plus CE DRAM and CE PRAM. It is critical to maintain the integrity of the cells 0x2000…0x2007
as a minimum (where important system settings are stored) during the flash-write operation. This can be achieved by
excluding the critical addresses from the write operation.
MPU RAM: The 71M6513 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256bytes of internal RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.
CE DRAM: The CE DRAM is the data memory of the CE. The MPU can read and write the CE DRAM as the primary means of
data communication between the two processors.
CE PRAM: The CE PRAM is the program memory of the CE. The CE PRAM has to be loaded with CE code before the CE
starts operating. CE PRAM cannot be accessed by the MPU when the CE is running.
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Oscillator
The oscillator drives a standard 32.768kHz watch crystal (see Figure 9). Crystals of this type are accurate and do not require a
high current oscillator circuit. The oscillator in the 71M6513 Power Meter IC has been designed specifically to handle watch
crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is
very low to maximize the lifetime of any battery backup device attached to the VBAT pin.
71M651X
XIN
crystal
XOUT
Figure 9: Oscillator Circuit
The oscillator should be placed as close as possible to the IC, and vias should be avoided.
An external resistor across the crystal must not be added.
Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. In the absence of the 3.3V supply, the RTC is powered by the external
battery (VBAT pin). The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes,
hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own
output register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the
RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the
same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU
clock speed, RTC reads require one wait state.
The RTC interrupt must be enabled using the I/O RAM register EX_RTC (address 0x2002[1]). RTC time is set by writing to the
I/O RAM registers RTC_SEC, RTC_MIN, through RTC_YR. Each byte written to RTC must be delayed at least 3 CK32 cycles
from any previous byte written to RTC.
Two time correction bits, the I/O RAM registers RTC_DEC_SEC (0x201C[1]) and RTC_INC_SEC (0x201C[0]) are provided to
adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second
at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can
integrate temperature and correct the RTC time as necessary as discussed in temperature compensation.
Comparators (V2, V3)
The 71M6513/6513H includes two programmable comparators that are connected to the V2 and V3 pins. The I/O RAM
register COMP_INT (0x2003[4:3]) allows the user to determine if comparators 2 and 3 will trigger an interrupt to the MPU. The
output of each comparator is available in the COMPSTAT register. VBIAS is used as the threshold, and built-in hysteresis
prevents each comparator from repeatedly responding to low-amplitude noise.
Comparators 2 and 3 can be used for early warning of power faults, or for monitoring of battery or other DC voltages. If they
are both selected to interrupt the MPU, their outputs will be XORed together. The voltage at V3 is also available to the ADC in
the AFE, but the comparator should not be used when V3 is used for analog measurements.
Comparator 1 is part of the power fault circuitry (see section V1 Pin) and cannot be programmed.
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LCD Drivers
The 71M6513 contains 24 dedicated LCD segment drivers and 18 multi-purpose pins which may be configured as additional
LCD segment drivers (see I/O RAM register LCD_NUM). The 71M6513/6513H is capable of driving between 96 to 168 pixels
of LCD display with 25% duty cycle. At seven segments per digit, the LCD can be designed for 13 to 24 digits for display.
Since each pixel is addressed individually, the LCD display can be a combination of alphanumeric digits and enunciator
symbols. The information to be displayed is written into the lower four bits of I/O RAM registers LCD_SEG0 through
LCD_SEG41. Bit 0 corresponds to the segment selected when COM0 pin is active while bit 1 is allocated to COM1.
The LCD driver circuitry is grouped into 4 common outputs (COM0 to COM3) and up to 42 segment outputs (see Table 55).
The typical LCD map is shown below.
SEG0
SEG1
SEG2
SEG3
…
SEG27
…
SEG41
COM0
P0
P4
P8
P12
...
P108
...
P164
COM1
P1
P5
P9
P13
…
P109
...
P165
COM2
P2
P6
P10
P14
...
P110
...
P166
COM3
P3
P7
P11
P15
...
P111
...
P167
Table 55: Liquid Crystal Display Segment Table (Typical)
Note: P0, P1, … Represent the pixel/segment numbers on the LCD.
A charge pump suitable for driving VLCD is included on-chip. This circuit creates 5V from the 3.3V supply. A contrast DAC is
provided that permits the LCD full-scale voltage to be adjusted between VLCD and 70% of VLCD. The LCD_NUM register
defines the number of dual purpose pins used for LCD segment interface.
LCD Voltage Boost Circuitry
A voltage boost circuit may be used to generate 5V from the 3.3V supply to support low-power 5V devices, such as LCDs.
Figure 10 shows a block diagram of the voltage boost circuitry including the voltage regulators for V2P5 and V2P5NV. When
activated using the I/O RAM register LCD_BSTEN (0x2020[7]), the boost circuitry provides an AC voltage at the VDRV output
pin (see the Applications section for details).
VOLTAGE
BOOST
VDRV
LCD_IBST
LCD_BSTEN
GNDD
V2P5NV
GNDD
V3P3D
VOLT
REG
V3P3D
VBAT
0.1V
GNDD
GNDD
V2P5
V2P5
VLCD
Figure 10: LCD Voltage Boost Circuitry
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UART (UART0) and Optical Port (UART1)
The 71M6513/6513H includes an interface to implement an IR or optical port. The pin OPT_TX is designed to directly drive an
external LED for transmitting data on an optical link (low-active). The pin OPT_RX, also low-active, is designed to sense the
input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated
UART port. OPT_TX can be tristated if it is desired to multiplex another I/O pin to the OPT_TX output. The control bit for the
OPT_TX output is the I/O RAM register OPT_TXDIS (0x2008[5]).
Hardware Reset Mechanisms
Several conditions will cause a hardware reset of the 71M6513/6513H:
•
•
•
•
•
Voltage at the RESETZ pin low
Voltage at the E_RST pin low
Voltage at the V1 pin below reset threshold (VBIAS)
The crystal frequency monitor detected a crystal malfunction
Hardware Watchdog timer
Reset Pin (RESETZ)
When the RESETZ pin is pulled low (or when V1 < VBIAS), all digital activity in the chip stops while analog circuits are still
active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared.
Hardware Watchdog Timer
In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware
watchdog timer (WDT) is included in the 71M6513/6513H. This timer will reset the MPU if it is not refreshed periodically, and
can be used to recover the MPU in situations where program control is lost.
The watchdog timer uses the RTC crystal oscillator as its time base and requires a reset under MPU program control at least
every 1.5 seconds. When the WDT overflow occurs, the MPU is momentarily reset as if RESETZ were pulled low for half of a
crystal oscillator cycle. Thus, after 4100 cycles of CK32 (32768Hz clock) , the MPU program will be launched from address 00.
An I/O RAM register status bit, WD_OVF (0x2002[2]), is set when WDT overflow occurs. This bit is powered by the VBAT
pin and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power up. After
reading this bit, MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESETZ pin.
The watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, WD_OVF is set and a
system reset will be performed when the crystal oscillator resumes.
There is no internal digital state that deactivates the WDT. For debug purposes, however, the WDT can be disabled by tying
the V1 pin to V3P3 (see Figure 11 and WD Disable Threshold [V1-V3P3A] in the Comparator Section of the Electrical
Specifications). Of course, this also deactivates the power fault detection implemented with V1. Since there is no way in firmware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the MPU might find itself in, it will be
reset to a known state upon watchdog timer overflow.
In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when
WAKE=0 and, during development, when a 0x14 command is received from the ICE port.
Crystal Frequency Monitor
The hardware watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, the I/O RAM
register WD_OVF is set and a system reset will be performed when the crystal oscillator resumes.
V1 Pin
The comparator at the V1 pin controls the state of the digital circuitry on the chip. When V1 < VBIAS (or when the RESETZ pin
is pulled low), all digital activity in the chip stops while analog circuits including the oscillator and RTC module are still active.
Additionally, when V1 < VBIAS, all I/O RAM bits are cleared. As long as V1 is greater than VBIAS, the internal 2.5V regulator
will continue to provide power to the digital section.
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V1
V3P3
V3P3-10mV
WDT disabled
V3P3 400mV
Normal
operation,
WDT
enabled
when
(V1 < VBIAS)
the battery is
enabled
VBIAS
Battery or
reset
mode
0V
Figure 11: Voltage Range for V1
Internal Clocks and Clock Dividers
All internal clocks are based on the watch crystal frequency (CK32 = 32,768Hz) applied to the XIN and XOUT pins. The PLL
multiplies this frequency by 150 to 4.9152MHz. This frequency is supplied to the ADC, the FIR filter (CKFIR), the clock test
output pin (CKTEST), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU
(CKMPU) and one for the CE (CKCE).
The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2 MPU_DIV Hz
where MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down
to 38.4kHz.
The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register
ECK_DIS (0x2005[5]) is asserted by the MPU.
I2C Interface (EEPROM)
A dedicated 2-pin serial interface implements an I2C driver that can be used to communicate with external EEPROM devices.
The interface can be multiplexed onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM register DIO_EEX
(0x2008[4]). The MPU communicates with the interface through two SFR registers: EEDATA (0x9E) and EECTRL (0x9F). If the
MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL.
The write to EECTRL initiates the transmit sequence. By observing the BUSY bit in EECTRL the MPU can determine when the
transmit operation is finished (i.e. when the BUSY bit transitions from 1 to 0). INT5 is also asserted when BUSY falls. The MPU
can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the ‘Receive’ command to EECTRL and waiting for BUSY to fall. Upon completion, the received data
will appear in EEDATA.
The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state until the next
transmission. The bits in EECTRL are shown in Table 56.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. However, controlling DIO4 and
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process
interrupts.
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2
Note: Clock stretching and multi-master operation are not supported for the I C interface.
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7
ERROR
R
0
Positive
1 when an illegal command is received.
6
BUSY
R
0
Positive
1 when serial data bus is busy.
5
RX_ACK
R
1
Negative
0 indicates that the EEPROM sent an ACK bit.
4
TX_ACK
R
1
Negative
0 indicates when an ACK bit has been sent to the EEPROM
CMD
3-0
CMD[3:0]
W
0
Positive,
see CMD
Table
Operation
0
No-op. Applying the no-op command will stop the I2C clock
(SCK, DIO4). Failure to issue the no-op command will keep
the SCK signal toggling.
2
Receive a byte from EEPROM and send ACK.
3
Transmit a byte to EEPROM.
5
Issue a ‘STOP’ sequence.
6
Receive the last byte from EEPROM and do not send ACK.
9
Issue a ‘START’ sequence.
Others
No Operation, set the ERROR bit.
Table 56: EECTRL Status Bits
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DATA SHEET
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Battery
The VBAT pin provides an input for an external battery that can be used to support the crystal oscillator, RTC, the WD_OVF bit
and XRAM in the absence of the main power supply. If the battery is not used, the VBAT pin should be connected to V3P3.
Internal Voltages (VBIAS, VBAT, V2P5)
The 71M6513 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages
can be tied together outside the chip. The internal supply voltage V2P5 is generated by a regulator from the 3.3V supplies.
The battery voltage, VBAT, is required when crystal oscillator, RTC and XRAM are required to keep operating while V3P3D is
removed (battery mode). VBAT, usually supplied by an external battery, powers crystal oscillator, RTC and XRAM (and the
WD_OVF bit).
VBIAS (1.5V) is generated internally and used for the comparators V1, V2 and V3.
Test Ports
TMUXOUT Pin: One out of 16 digital or 4 analog signals can be selected to be output on the TMUXOUT pin. The function of
the multiplexer is controlled with the I/O RAM register TMUX (0x2000[3:0]), as shown in Table 57.
Mode
Function
0
analog
DGND
1
analog
IBIAS
2
analog
PLL_2.5V
3
analog
VBIAS
4
digital
RTM (Real time output from CE)
5
digital
WDTR_EN (Comparator 1 Output AND V1LT3)
6
digital
V2_OK (Comparator 2 Output)
7
digital
V3_OK (Comparator 3 Output)
8
digital
RXD (from Optical interface)
9
digital
MUX_SYNC
A
digital
CK_10M
B
digital
CK_MPU
TMUX[3:0]
C
--
D
digital
RTCLK
reserved for production test
E
digital
CE_BUSY
F
digital
XFER_BUSY
Table 57: TMUX[3:0] Selections
Emulator Port: The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX provides control of the MPU through
an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ add trace capability to the
emulator. The emulator port is compatible with the ADM51 emulators manufactured by Signum Systems.
The signals of the emulator port have weak pull-ups. Adding 1kΩ pull-up resistors on the PCB is recommended.
Real-Time Monitor: The RTM output of the CE is available as one of the digital multiplexer options. RTM data is read from the
CE DRAM locations specified by I/O RAM registers RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC. The RTM can
be enabled and disabled with I/O RAM register RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked
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out in 35 cycles and contains a leading flag bit. Figure 13 in the System Timing Section illustrates the RTM output format. RTM
is low when not in use.
SSI Interface: A high-speed serial interface with handshake capability is available to send a contiguous block of CE data to an
external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycle of 32kHz before
each CE code pass begins. If the block of data is big enough that transmission has not completed when the code pass begins,
it will complete during the CE code pass with no timing impact to the CE or the serial data. In this case, care must be taken
that the transmitted data is not modified unexpectedly by the CE. The SSI interface is enabled by the SSI_EN bit and consists
of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit
processors. The operation of each pin is as follows:
SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls
whether SCLK runs continuously or is gated off when no SSI activity is occurring. If SCLK is gated, it will begin 3 cycles before
SFR rises and will persist 3 cycles after the last data bit is output.
The pins used for the SSI are multiplexed with the LCD segment outputs, as shown in Table 58. Thus, the LCD should be
disabled when the SSI is in use.
SSI Signal
LCD Segment
Output Pin
SCLK
SEG3
SSDATA
SEG4
SFR
SEG5
SRDY
SEG6
Table 58: SSI Pin Assignment
SRDY is an optional handshake input that indicates that the DSP or data-logging device is ready to receive data. SRDY must
be true (the polarity of SRDY is selectable with SSI_FPOL) to enable SFR to rise and initiate the transfer of the next field. It is
expected that SRDY changes state on the rising edges of SCLK. If SRDY is not true when the SSI port is ready to transmit the
next field, transmission will be delayed until it is. SRDY is ignored except at the beginning of a field transmission. If SRDY is
not enabled (by SSI_RDYEN), the SSI port will behave as if SRDY is always true.
SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the contents of a block of CE
RAM words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first.
The field size is set with the SSI_FSIZE register: 0 entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of
the SFR pulse can be inverted with SSI_FPOL (SSI_FPOL = 0 SRDY high-active). If SRDY does not delay it, the first SFR
pulse in a frame will rise on the third SCLK after MUX_SYNC (or the fourth SCLK if 10MHz). MUX_SYNC can be used to
synchronize the fields arriving at the data logger or DSP.
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FUNCTIONAL DESCRIPTION
Theory of Operation
The energy delivered by a power source into a load can be expressed as:
t
E = ∫ V (t ) I (t )dt
0
Assuming phase angles are constant, the following formulae apply:
P = Real Energy [Wh] = V * A * cos φ* t
Q = Reactive Energy [VARh] = V * A * sin φ * t
S = Apparent Energy [VAh] =
P2 + Q2
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change
constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the
71M6513/6513H functions by emulating the integral operation above, i.e. it processes current and voltage samples through an
ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic
range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for
the momentary energy. Summing up the momentary energy quantities over time will result in accumulated energy.
500
400
V [V], I [A], P [Ws]
300
200
100
0
-100
-200
Current [A]
-300
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
0
5
10
15
time [ms]
20
Figure 12: Voltage. Current, Momentary and Accumulated Energy
Figure 12 shows the shapes of V(t), I(t), the momentary energy and the total accumulated energy, resulting from 50 samples
of the voltage and current signals over a period of 20ms. The application of 240VAC and 100A results in an accumulation of
480Ws over the 20ms period, as indicated by the curve for Accumulated Energy.
The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion.
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System Timing Summary
Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV=0 (six mux states) and FIR_LEN = 0 (2 CK32 cycles). Since FIR filter conversions require
two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1 + 3 *
states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into
DRAM is shown in Figure 13.
Figure 13 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
ADC MUX Frame
ADC TIMING
MUX_DIV Conversions (MUX_DIV=6 is shown)
Settle
CK32
150
MUX_SYNC
MUX STATE
0
S
1
2
3
4
5
S
ADC EXECUTION
ADC0
CE TIMING
0
ADC1
600
300
ADC2
ADC3
900
1200
ADC4
ADC5
1500
1800
CE_EXECUTION
CK COUNT = CE_CYCLES + floor(CE_CYCLES + 2) / 5)
MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM and SSI TIMING
140
RTM
SSI
LAST SSI TRANSFER
BEGIN SSI TRANSFER
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respectively.
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CK32
MUX_SYNC
CKTEST
30
31
0
FLAG
1
30
31
0
FLAG
1
30
31
SIG
N
FLAG
1
LSB
0
SIG
N
31
LSB
30
SIG
N
LSB
FLAG
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
1
SIG
N
0
LSB
TMUXOUT/RTM
Figure 14: RTM Output Format
If SSI_CKGATE =1
If 16bit fields
If SSI_CKGATE =1
If 32bit fields
SFR (Output)
SRDY (Input)
SCLK (Output)
31
SSDATA (Output)
30
16
1
15
0
31
30
16
1
15
0
1
31
0
SSI_END
SSI_BEG+1
SSI_BEG
MUX_SYNC
Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0)
Next field is delayed while SRDY is low
SFR (Output)
SRDY (Input)
SCLK (Output)
SSDATA (Output)
31
30
29
18
17
16
16
16
16
15
14
13
12
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY)
SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single
field, as multiple 16-bit fields, or as multiple 32-bit fields. The SFR pulse is one SCLK clock cycle wide, changes state on the
rising edge of SCLK and precedes the first bit of each field.
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Data Flow
The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)
sequentially processes the samples from the voltage inputs on pins IA, VA, IB, VB, IC, and VC performing calculations to
2
2
measure active power (Wh), reactive power (VARh), A h, and V h for four-quadrant metering. These measurements are then
accessed by the MPU, processed further and output using the peripheral devices available to the MPU.
Pulses
IRQ
Samples
CE
Data
PreProcessor
MPU
PostProcessor
Processed
Metering
Data
I/O RAM (Configuration RAM)
Figure 17: MPU/CE Data Flow
CE/MPU Communication
Figure 18 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the
I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY,
which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the
output region of the CE RAM. This will occur whenever the CE has finished generating a sum by completing an accumulation
interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the
XFER_BUSY and CE_BUSY signals.
Figure 19 shows the sequence of events between CE and MPU upon reset or power-up. In a typical application, the sequence
of events is as follows:
1)
Upon power-up, the MPU initializes the hardware, including disabling the CE
2)
The MPU loads the code for the CE into the CE PRAM
3)
The MPU loads CE data into the CE DRAM.
4)
The MPU starts the CE by setting the CE_EN bit in the I/O RAM.
5)
The CE then repetitively executes its code, generating results and storing them in the CE DRAM
It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and
PRE_SAMPS is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting
accumulation interval is:
τ=
N ACC
2520
60 ⋅ 42
=
=
= 999.75ms
32768Hz 2520.62 Hz
fS
13
This means that accurate time measurements require the RTC.
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PULSES
W (DIO6)
WSUM
VARSUM
VAR (DIO7)
DISPLAY (memory-mapped
LCD segments)
APULSEW
SERIAL
(UART0/1)
APULSER
EXT_PULSE
DATA
ADC
MPU
EEPROM
(I2C)
SAMPLES
CE_BUSY
CE
Mux Ctrl.
DIO
XFER_BUSY
INTERRUPTS
I/O RAM (CONFIGURATION RAM)
Figure 18: MPU/CE Communication (Functional)
The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional
processing such as energy accumulation.
CE PRAM
FLASH
CE_EN
XFER Interrupt
COMPUTATION
ENGINE
CE DRAM
MPU
Figure 19: MPU/CE Communication (Processing Sequence)
Fault, Reset, Power-Up
Reset Mode: When the RESETZ pin is pulled low or when V1 < VBIAS, all digital activity in the chip stops while analog circuits
are still active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared. As long as V1, the
input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100
cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot
sequences from address 00. See the security section for more description of preboot and boot.
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Power-Up: After power-up, the 71M6513/6513H is in reset as long as V1 < VBIAS. As soon as V1 exceeds VBIAS, the reset
timer is started which takes the MPU out of reset after 4100 oscillator cycles (see Figure 20). The MPU then initiates its preboot phase lasting 32 cycles. The supply current will be low but not zero during power-up. It will increase, once V1 exceeds
VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under
firmware control, following the steps specified in Battery Operation and Power Save Modes.
V3P3
3.3V
V2P5
V1
1.5V
0V
POWER
DOWN
PWR
UP
PREBOOT
RESET TIMER
FIRMWARE HAS CONTROL OVER CHIP...
V1 > VBIAS
SUPPLY CURRENT
nominal
1ms
125ms
0mA
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up
Battery Operation
When V1 is lower than VBIAS, the external battery will power the following parts of the 71M6513/6513H:
•
•
RTC
Crystal oscillator circuitry
•
MPU XRAM
•
WD_OVF bit
Power Save Modes
In normal mode of operation, running on 3.3V supply, various resources of the 71M6513/6513H may be shut down by the
MPU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active.
Table 59 outlines these resources and their typical current consumption (based on initial condition MPU_DIV = 0).
Power Saving Measure
Disable the CE
Software Control
Typical
Savings
CE_EN = 0
0.16mA
ADC_DIS = 1
1.8mA
Disable clock test output CKTEST
CKOUTDIS = 1
0.6mA
Disable emulator clock
ECK_DIS = 1 *)
0.1mA
FLASH66Z =1
0.04mA
Disable the ADC
Set flash read pulse timing to 33 ns
Disable the LCD voltage boost circuitry
Disable RTM outputs
Increase the clock divider for the MPU
LCD_BSTEN = 0
0.9mA
RTM_EN = 0
0.01mA
MPU_DIV = X
0.4mA/MHz
*) This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus
preclude flash erase and programming operations.
Table 59: Power Saving Measures
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Temperature Compensation
Internal Compensation: The internal voltage reference is calibrated during device manufacture. Trim data is stored in on-chip
fuses.
For the 71M6513, the temperature coefficients TC1 and TC2 are given as constants that represent typical component
behavior.
For the 71M6513H, the temperature characteristics of the chip are measured during production and then stored in the fuse
registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be derived from the fuses by using the relations given in the
Electrical Specifications section. TC1 and TC2 can be further processed to generate the coefficients PPMC and PPMC2.
TRIMM[2:0], TRIMBGA and TRIMBGB are read by first writing either 4, 5 or 6 to TRIMSEL (0x20FD) and then reading the value
of TRIM (0x20FF).
When the EXT_TEMP register in CE DRAM (address 0x38) is set to 0, the CE automatically compensates for temperature
errors by controlling the GAIN_ADJ register (address 0x2E) based on the PPMC, PPMC2, and TEMP_X register values. In the
case of internal compensation, GAIN_ADJ is an output of the CE.
External Compensation: Rather than internally compensating for the temperature variation, the bandgap temperature is
provided to the embedded MPU, which then may digitally compensate the power outputs. This permits a system-wide
temperature correction over the entire system rather than local to the chip. The incorporated thermal coefficients may include
the current sensors, the voltage sensors, and other influences. Since the band gap is chopper stabilized via the CHOP_EN bits,
the most significant long-term drift mechanism in the voltage reference is removed.
When the EXT_TEMP register in CE DRAM is set to 15, the CE ignores the PPMC, PPMC2, and TEMP_X register values and
applies the gain supplied by the MPU in GAIN_ADJ. External compensation enables the MPU to control the CE gain based on
any variable, and when EXT_TEMP = 15, GAIN_ADJ is an input to the CE.
Chopping Circuitry
As explained in the hardware section, the bits of the I/O RAM register CHOP_EN[1:0] have to be toggled in between
multiplexer cycles to achieve the desired elimination of DC offset.
The amplifier within the reference is auto-zeroed by means of an internal signal that is controlled by the CHOP_EN bits. When
this signal is HIGH, the connection of the amplifier inputs is reversed. This preserves the overall polarity of the amplifier gain
but inverts the input offset. By alternately reversing the connection, the offset of the amplifier is averaged to zero. The two bits
of the CHOP_EN register have the function specified in Table 60.
CHOP_EN[1]
CHOP_EN[0]
Function
0
0
Toggle chop signal
0
1
Reference connection positive
1
0
Reference connection reversed
1
1
Toggle chop signal
Table 60: CHOP_EN Bits
For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the
reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 21. With an even number of
multiplexer cycles in each accumulation interval, the number of cycles with positive reference connection will equal the number
of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is
acceptable when only the primary signals (meter voltage, meter current) are of interest.
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Accumulation Interval m
MUX
cycle 2
MUX
cycle 1
MUX
cycle 3
Accumulation Interval m+2
Accumulation Interval m+1
MUX
cycle n
MUX
cycle 1
Reversed
Positive
MUX
cycle n
MUX
cycle 1
Reversed
Positive
Chop Polarity
Positive
Reversed
Positive
Reversed
Positive
Reversed
Positive
CE_BUSY interrupt
(falling edge)
XFER_BUSY interrupt
(falling edge)
Figure 21: Chop Polarity w/ Automatic Chopping
If temperature compensation or accurate reading of the die temperature is required, alternate multiplexer cycles have to be
inserted in between the regular cycles. This is done under MPU firmware control by asserting the MUX_ALT bit whenever
necessary. Since die temperature usually changes very slowly, alternate multiplexer cycles have to be inserted very
infrequently. Usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each
XFER_BUSY interrupt. This sequence is shown in Figure 22.
Accumulation Interval m
MUX
alt. MUX MUX
cycle 2 cycle 3
cycle
Accumulation Interval m+1
MUX alt. MUX
cycle n cycle
Accumulation Interval m+2
MUX alt. MUX
cycle n cycle
Chop Polarity
Positive
RePositive
versed
RePositive
versed
Re- Positive
versed
Reversed
Positive
Reversed
Positive
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
Figure 22: Sequence with Alternate Multiplexer Cycles
This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.
Consequently, DC offset will appear on the temperature measurement, which will decrease the accuracy of this measurement
and thus cause temperature reading and compensation to be less accurate.
The sequence shown in Figure 23 uses the CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.
CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each
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XFER_BUSY interrupt. After these first two cycles, CHOP_EN returns to 11 (automatic toggle). The value of CHOP_EN, when
set after the XFER_BUSY interrupt, is in force for the entire following multiplexer cycle.
When using this sequence, the alternate multiplexer cycle is toggled between positive and reversed connection resulting in
accurate temperature measurement.
An example for proper application of the CHOP_EN bits can be found in the Demo Code shipped with the 6513 Demo Kits.
Firmware implementations should closely follow this example.
Accumulation Interval m
alt. MUX MUX
cycle 2
cycle
MUX
cycle 3
Accumulation Interval m+1
Accumulation Interval m+2
MUX
cycle n
alt. MUX MUX
cycle 2
cycle
MUX
cycle 3
MUX
cycle n
alt. MUX MUX
cycle 2
cycle
MUX
cycle 3
MUX
cycle n
Positive
reversed
Positive
reversed
Positive Positive
reversed
Positive
Chop Polarity
rePositive Positive versed
reversed
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
CHOP_EN
01
11
(11)
(11)
(11)
10
11
(11)
(11)
(11)
01
11
(11)
(11)
(11)
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping
Internal/External Pulse Generation and Pulse Counting
The CE is the source for pulses. It can generate pulses directly based on the voltage and current inputs and the configured
pulse generation parameters. This is called “internal pulse generation”, and applies when the CE RAM register EXT_PULSE
(address 0x37) equals 0. Alternatively, the CE can be configured to generate pulses based on registers that are controlled by
the MPU (“external pulse generation”), i.e. when the register EXT_PULSE equals 15. In the case of external pulse generation,
the MPU writes values to the CE registers APULSEW (0x26) and APULSER (0x27).
The pulse rate, usually inversely expressed as “Kh” (and measured in Wh per pulse), is determined by the CE RAM registers
WRATE, PULSE_SLOW, PULSE_FAST, In_8, as well as by the sensor scaling VMAX and IMAX per the equation:
Kh =
VMAX ⋅ IMAX ⋅ 66.1782
[Wh / pulse]
In _ 8 ⋅ WRATE ⋅ N ACC ⋅ X
where
In_8 is the gain factor (1 or 8) controlled by the CE variable In_SHUNT,
X is the pulse gain factor controlled by the CE variables PULSE_SLOW and PULSE_FAST
NACC is the accumulation count (PRE_SAMPS * SUM_CYCLES)
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Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked.
This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a
32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to
perform a global erase of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM.
The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A readonly status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the
ICE can be enabled and is permitted to take control of the MPU.
SECURE (SFR 0xB2[6]), the security enable bit, is reset whenever the MPU is reset. Hardware associated with the bit permits
only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once
SECURE is set, the preboot code is protected and no external read of program code is possible.
Specifically, when SECURE is set:
•
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or
ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases CE program RAM whether
SECURE is set or not.
Writes to page zero, whether by MPU or ICE, are inhibited.
The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE
interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE
Interface description).
Additionally, by setting the I/O RAM register ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with
the emulator. See the cautionary note in the I/O RAM Register description!
Page: 58 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
FIRMWARE INTERFACE
I/O RAM MAP – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed.
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0
CE1
CE2
COMP0
CONFIG0
CONFIG1
VERSION
EQU[2:0]
2000
PRE_SAMPS[1:0]
2001
MUX_DIV[1:0]
2002
2003
2004 VREF_CAL
2005 RESERVED
2006
CE_EN
TMUX[3:0]
SUM_CYCLES[5:0]
CHOP_EN[1:0]
RTM_EN
WD_OVF
EX_RTC
EX_XFR
COMP_INT[1:0]
COMP_STAT[2:0]
RESERVED CKOUT_DIS
VREF_DIS
MPU_DIV
ECK_DIS
FIR_LEN
ADC_DIS
MUX_ALT
FLASH66Z
MUX_E
VERSION[7:0]
Digital I/O:
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
2008
2009
200A
200B
200C
200D
200E
RTC0
RTC1
RTC2
RTC3
RTC4
RTC5
RTC6
RTC7
2015
2016
2017
2018
2019
201A
201B
201C
LCDX
LCDY
LCDZ
LCD0
LCD1
LCD2
LCD3
…
LCD39
LCD40
LCD41
2020 LCD_BSTEN
2021
2022
2030
2031
2032
2033
…
2057
2058
2059
OPT_TXDIS
DIO_R1[2:0]
DIO_R3[2:0]
DIO_R5[2:0]
DIO_R7[2:0]
DIO_R9[2:0]
DIO_R11[2:0]
DIO_EEX
DIO_PW
DIO_PV
DIO_R0[2:0]
DIO_R2[2:0]
DIO_R4[2:0]
DIO_R6[2:0]
DIO_R8[2:0]
DIO_R10[2:0]
Real Time Clock:
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
RTC_DEC_SEC RTC_INC_SEC
LCD Display Interface:
LCD_EN
…
LCD_NUM[4:0]
LCD_MODE[2:0]
LCD_CLK[1:0]
LCD_FS[4:0]
LCD_SEG0[3:0]
LCD_SEG1[3:0]
LCD_SEG2[3:0]
LCD_SEG3[3:0]
…
LCD_SEG39[3:0]
LCD_SEG40[3:0]
LCD_SEG41[3:0]
© 2005-2011 Teridian Semiconductor Corporation
Page: 59 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSI_FPOL
SSI_RDYEN
SSI_RDYPOL
RTM Probes:
RTM0
RTM1
RTM2
RTM3
2060
2061
2062
2063
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
Synchronous Serial Interface:
SSI
2070
S S I _ B E G 2071
SSI_END 2072
SSI_EN
SSI_10M
SSI_CKGATE
SSI_FSIZE[1:0]
SSI_BEG[7:0]
SSI_END[7:0]
Fuse Selection Registers:
TRIMSEL
TRIM
20FD
20FF
TRIMSEL[7:0]
TRIM[7:0]
SFR MAP (SFRs Specific to Teridian 80515) – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers.
Name
SFR
Addr
P0
DIR0
P1
DIR1
P2
DIR2
80
A2
90
91
A0
A1
INTBITS
WDI
F8
E8
ERASE
FLSHCTL
PGADR
94
B2
B7
EEDATA
EECTRL
9E
9F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Digital I/O:
DIO_0[7:0]
DIO_DIR0[7:0]
DIO_1[7:0]
DIO_DIR1[7:0]
DIO_2[5:0]
DIO_DIR2[5:0]
(Port 0)
(Port 1)
(Port 2)
Interrupts and WD Timer:
INT6
INT5
INT4
INT3
WD_RST
INT2
INT1
IE_RTC
INT0
IE_XFER
FLSH_MEEN
FLSH_PWE
Flash:
FLSH_ERASE[7:0]
PREBOOT
SECURE
FLSH_PGADR[6:0]
Serial EEPROM:
Page: 60 of 104
EEDATA[7:0]
EECTRL[7:0]
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
I/O RAM (Configuration RAM) – Alphabetical Order
Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its parameters from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and
copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory
space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all
bits are cleared to zero unless otherwise stated. Generic SFR registers are not listed.
Name
Location
[Bit(s)]
Dir
Description
ADC_DIS
2005[3]
R/W
Disables ADC and removes bias current
CE_EN
2000[4]
R/W
CE enable.
CHOP_EN[1:0]
2002[5:4]
R/W
Chop enable for the reference band gap circuit.
00: enabled 01: disabled 10: disabled 11: enabled
RESERVED
2004[5]
R/W
Must be 0.
CKOUT_DIS
2004[4]
R/W
CKOUT Disable. When zero, CKTEST is an active output.
COMP_INT[1:0]
2003[4:3]
R/W
Two bits establishing whether a comparator state change should create
MPU interrupts. 1: interrupt, 0: no interrupt. If 11, the comparator outputs are
XOR’ed.
Bit0 = comp2, Bit1 = comp3
COMP_STAT[2:0]
2003[2:0]
R
DIO_R0[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
2009[2:0]
2009[6:4]
200A[2:0]
200A[6:4]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DIO_DIR0[7:0]
SFR A2
R/W
DIO_DIR1[7:0]
SFR 91
R/W
Programs the direction of DIO pins 15 through 8. 1 indicates output. Ignored
if the pin is not configured as I/O.
DIO_DIR2[5:0]
SFR
A1[5:0]
R/W
Programs the direction of DIO pins 21 through 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
Three bits containing comparator output status.
Bit0 = comp1, Bit1 = comp2, Bit2 = comp3
Connects dedicated I/O pins 0 to 11 to selectable internal resources. If more
than one input is connected to the same resource, the ‘Multiple’ column
below specifies how they are combined. See Software User’s Guide for
details).
DIO_GP
Resource
Multiple
0
NONE
-1
Reserved
OR
2
T0 (counter0 clock)
OR
3
T1 (counter1 clock)
OR
4
High priority I/O interrupt (int0 rising)
OR
5
Low priority I/O interrupt (int1 rising)
OR
6
High priority I/O interrupt (int0 falling)
OR
7
Low priority I/O interrupt (int1 falling)
OR
Programs the direction of DIO pins 7 through 0. 1 indicates output. Ignored if
the pin is not configured as I/O. See DIO_PV and DIO_PW for special option
for DIO6 and DIO7 outputs. See DIO_EEX for special option for DIO4 and
DIO5.
© 2005-2011 Teridian Semiconductor Corporation
Page: 61 of 104
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71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Name
Location
[Bit(s)]
Dir
Description
DIO_0[7:0]
DIO_1[7:0]
DIO_2[5:0]
SFR 80
SFR 90
SFR
A0[5:0]
R/W
R/W
R/W
Port 0
Port 1
Port 2
DIO_EEX
2008[4]
R/W
When set, converts DIO4 and DIO5 to interface with external EEPROM.
DIO4 becomes SCK and DIO5 becomes bi-directional SDA. LCD_NUM
must be less than 18.
DIO_PV
2008[2]
R/W
Causes VARPULSE to be output on DIO7, if DIO7 is configured as output.
LCD_NUM must be less than 15.
DIO_PW
2008[3]
R/W
Causes WPULSE to be output on DIO6, if DIO6 is configured as output.
LCD_NUM must be less than 16.
EEDATA[7:0]
SFR 9E
R/W
Serial EEPROM interface data
The value on the DIO pins. Pins configured
as LCD will read zero. When written,
changes data on pins configured as outputs. Pins configured as LCD or input will
ignore writes.
EECTRL[7:0]
SFR 9F
R/W
Serial EEPROM interface control
ECK_DIS
2005[5]
R/W
Emulator clock disable. When one, the emulator clock is disabled. This bit
is to be used with caution! Inadvertently setting this bit will
inhibit access to the part with the ICE interface and thus
preclude flash erase and programming operations. If ECK_DIS
is set, it should be done at least 1000ms after power-up to give emulators
and programming devices enough time to complete an erase operation.
EQU[2:0]
2000[7:5]
R/W
Specifies the power equation to the CE.
EX_XFR
EX_RTC
2002[0]
2002[1]
FIR_LEN
2005[4]
R/W
The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),
0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)
FLASH66Z
2005[1]
R/W
Should be set to 1 to minimize supply current.
FLSH_ERASE
SFR 94
W
FLSH_MEEN
SFR B2[1]
Page: 62 of 104
R/W
W
Interrupt enable bits. These bits enable the XFER_BUSY and the
RTC_1SEC interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the
Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in
order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be
enabled.
Any other pattern written to FLSH_ERASE will have no effect.
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
Name
Location
[Bit(s)]
Dir
Description
FLSH_PGADR
SFR
B7[7:1]
W
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be
erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
FLSH_PWE
SFR B2[0]
R/W
Program Write Enable
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this
bit are inhibited when interrupts are enabled.
IE_XFER
IE_RTC
SFR E8[0]
SFR E8[1]
R/W
Interrupt flags. These flags are part of the WDI SFR register and monitor the
XFER_BUSY interrupt and the RTC_1SEC interrupt. The flags are set by
hardware and must be cleared by the interrupt handler. See also WD_RST.
INTBITS
SFR
F8[6:0]
R
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
LCD_BSTEN
2020[7]
R/W
Enables the LCD voltage boost circuit.
LCD_CLK[1:0]
2021[1:0]
R/W
Sets the LCD clock frequency for COM/SEG pins (not the frame rate. Note:
fw = CKFIR/128
00: fw/29, 01: fw/28, 10: fw/27, 11: fw/26
LCD_EN
2021[5]
R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs.
LCD_FS[4:0]
2022[4:0]
R/W
Controls the LCD full scale voltage, VLC2:
VLC 2 = VLCD ⋅ (0.7 + 0.3
LCD_MODE[2:0]
2021[4:2]
R/W
LCD _ FS
)
31
The LCD bias mode.
000: 4 states, 1/3 bias
001: 3 states, 1/3 bias
010: 2 states, ½ bias
011: 3 states, ½ bias
100: static display
© 2005-2011 Teridian Semiconductor Corporation
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71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
Name
Location
[Bit(s)]
Dir
Description
LCD_NUM[4:0]
2020[4:0]
R/W
Number of dual-purpose LCD/DIO pins to be configured as LCD. This
number can be between 0 and 18. The first dual-purpose pin to be used as
LCD is SEG41/DIO21. If LCD_NUM = 2, SEG41 and SEG 40 will be
configured as LCD. The remaining SEG39 to SEG24 will be configured as
DIO19 to DIO4.
LCD_NUM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SEG
None
SEG41
SEG40-41
SEG39-41
SEG38-41
SEG37-41
SEG36-41
SEG35-41
SEG34-41
SEG33-41
SEG32-41
SEG31-41
SEG30-41
SEG29-41
SEG28-41
SEG27-41
SEG26-41
SEG25-41
SEG24-41
DIO
DIO4-21
DIO4-20
DIO4-19
DIO4-18
DIO4-17
DIO4-16
DIO4-15
DIO4-14
DIO4-13
DIO4-12
DIO4-11
DIO4-10
DIO4-9
DIO4-8
DIO4-7
DIO4-6
DIO4-5
DIO4
None
LCD_SEG0[3:0]
…
LCD_SEG41[3:0]
2030[3:0]
…
2059[3:0]
R/W
LCD Segment Data. Each word contains information for from 1 to 4 time
divisions of each segment. In each word, bit 0 corresponds to COM0, on up
to bit 3 for COM3.
MPU_DIV[2:0]
2004[2:0]
R/W
The MPU clock divider (from CKCE). These bits may be programmed by
the MPU without risk of losing control.
7
000 - CKCE, 001 - CKCE/2, …, 111 - CKCE/2
MPU_DIV is 000 on power-up.
MUX_ALT
2005[2]
R/W
The MPU asserts this bit when it wishes the MUX to perform ADC
conversions on an alternate set of inputs.
MUX_DIV[1:0]
2002[7:6]
R/W
The number of states in the input multiplexer.
00 - 6 states 01 - 4 states 10 - 3 states 11 - 2 states
MUX_E
2005[0]
R/W
MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC output.
OPT_TXDIS
2008[5]
R/W
Tristates the OPT_TX output.
PREBOOT
SFR B2[7]
Page: 64 of 104
R
Indicates that the preboot sequence is active.
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
Name
Location
[Bit(s)]
Dir
Description
PRE_SAMPS[1:0]
2001[7:6]
R/W
Together w/ SUM_CYCLES, this value determines the number of samples in
one sum cycle between XFER interrupts for the CE.
Number of samples = PRE_SAMPS*SUM_CYCLES.
00-42, 01-50, 10-84, 11-100
RTC_SEC[5:0]
RTC_MINI[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2015
2016
2017
2018
2019
201A
201B
R/W
The RTC interface. These are the ‘year’, ‘month’, ‘day’, ‘hour’, ‘minute’ and
‘second’ parameters for the RTC. The RTC is set by writing to these
registers. Year 00 is defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR
00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR
00 to 256
RTC_DEC_SEC
RTC_INC_SEC
201C[1]
201C[0]
W
RTC time correction bits. Only one bit may be pulsed at a time. When
pulsed, causes the RTC time value to be incremented (or decremented) by
an additional second the next time the RTC_SEC register is clocked. The
pulse width may be any value. If an additional correction is desired, the
MPU must wait 2 seconds before pulsing one of the bits again.
RTM_EN
2002[3]
R/W
Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2060
2061
2062
2063
R/W
Four RTM probes. Before each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM registers are ignored when
RTM_EN=0.
SECURE
SFR B2[6]
R/W
Enables security provisions that prevent external reading of flash memory
and CE program RAM. This bit is reset on chip reset and may only be set.
Attempts to write zero are ignored.
SSI_EN
2070[7]
R/W
Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take on the
new functions SCLK, SSDATA, SFR, and SRDY, respectively. When
SSI_EN is high and LCD_EN is low, these pins are converted to the SSI
function, regardless of LCDEN and LCD_NUM. For proper LCD operation,
SSI_EN must not be high when LCD_EN is high.
SSI_10M
2070[6]
R/W
SSI clock speed: 0: 5MHz, 1: 10MHz
SSI_CKGATE
2070[5]
R/W
SSI gated clock enable. When low, the SCLK is continuous. When high, the
clock is held low when data is not being transferred.
SSI_FSIZE[1:0]
2070[4:3]
R/W
SSI frame pulse format:
0: once at beginning of SSI sequence (whole block of data),
1: every 8 bits, 2: every 16 bits, 3: every 32 bits.
SSI_FPOL
2070[2]
R/W
SFR pulse polarity: 0: positive, 1: negative
SSI_RDYEN
2070[1]
R/W
SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SSI_RDYPOL
2070[0]
R/W
SRDY polarity: 0: positive, 1: negative
© 2005-2011 Teridian Semiconductor Corporation
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A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Name
Location
[Bit(s)]
SSI_BEG[7:0]
SSI_END[7:0]
2071[7:0]
2072[7:0]
SUM_CYCLES
[5:0]
2001[5:0]
TMUX[3:0]
2000[3:0]
R/W
Selects one of 16 inputs for TMUXOUT.
0 – DGND (analog)
1 – IBIAS (analog)
2 – PLL_2.5V (analog)
3 – VBIAS (analog)
4 – RTM (Real time output from CE)
5 – WDTR_EN (Comparator 1 Output AND V1LT3)
6 – V2_OK (Comparator 2 Output)
7 – V3_OK (Comparator 3 Output)
8 – RXD (from Optical interface)
9 – MUX_SYNC (from MUX_CTRL)
A – CK_10M
B – CK_MPU
C – reserved for production test
D – RTCLK
E – CE_BUSY
F – XFER_BUSY
RESERVED
2005[7]
R/W
Must be zero.
TRIMSEL
20FD
W
Selects the temperature trim fuse to be read with the TRIM register
(TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6)
TRIM
20FF
R
Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depending on the value
written to TRIMSEL. If TRIMBGB = 0 then the IC is a 6513 else the IC is a
6513H.
VERSION[7:0]
2006
R
The silicon revision number. This data sheet does not apply to revisions <
000 0100.
VREF_CAL
2004[7]
R/W
Brings VREF out to the VREF pin. This feature is disabled when
VREF_DIS=1.
VREF_DIS
2004[3]
R/W
Disables the internal voltage reference.
WD_RST
SFR E8[7]
WD_OVF
2002[2]
Page: 66 of 104
Dir
Description
R/W
The beginning and ending address of the transfer region of the CE data
memory. If the SSI is enabled, a block of words starting with SSI_BEG and
ending with SSI_END will be sent. SSI_END must be larger than SSI_BEG.
The maximum number of output words is limited by the number of SSI
clocks in a CE code pass—see FIR_LEN, MUX_DIV, and SSI_10M.
R/W
Together w/ PRE_SAMPS, this value determines (for the CE) the number of
samples in one sum cycle between XFER interrupts.
Number of samples = PRE_SAMPS*SUM_CYCLES.
W
Resets the WD timer. The WDT is reset when a 1 is written to this bit. Only
byte operations on the whole WDI register should be used.
R/W
The WD overflow status bit. This bit is set when the WD timer overflows. It
is powered by the VBAT pin and at boot-up will indicate if the part is
recovering from a WD overflow or a power fault. This bit should be cleared
by the MPU on boot-up. It is also automatically cleared when RESETZ is
low.
© 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
CE Program and Environment
CE Program
The CE program is supplied by Teridian as a data image that can be merged with the MPU operational code for meter
applications. Typically, the CE program covers most applications and does not need to be modified.
Formats
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement (-1 = 0xFFFFFFFF). ‘Calibration’
parameters are defined in flash memory (or external EEPROM) and must be copied to CE memory by the MPU before
enabling the CE. ‘Internal’ variables are used in internal CE calculations. ‘Input’ variables allow the MPU to control the
behavior of the CE code. ‘Output’ variables are outputs of the CE calculations. The corresponding MPU address for the most
significant byte is given by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_address for the least significant byte.
Constants
Constants used in the CE Data Memory tables are:
Sampling frequency: FS = 32768Hz/13 = 2520.62Hz.
F0 is the fundamental signal frequency, typically 50 or 60Hz.
IMAX is the external rms current corresponding to 250mV peak at the inputs IA, IB, IC.
VMAX is the external rms voltage corresponding to 250mV peak at the inputs VA, VB, VC.
NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES. This value resides in
SUM_PRE (CE address 36).
Accumulation count time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS.
In_8 is a gain constant of current channel n. Its value is 8 or 1 and is controlled by In_SHUNT.
X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW.
-9
Voltage LSB = VMAX * 7.879810 V.
The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as used by the CE) to
external, i.e. metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an
actual meter. The LSB values used in this document relate digital quantities at the CE or MPU interface to external meter input
quantities. For example, if a SAG threshold of 80V peak is desired at the meter input, the digital value that should be programmed into SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR.
The parameters EQU, CE_EN, PRE_SAMPS, and SUM_CYCLES are essential to the function of the CE and are stored in I/O
RAM (see I/O RAM section).
Environment
Before starting the CE using the CE_EN bit, the MPU has to establish the proper environment for the CE by implementing the
following steps:
•
Loading the image for the CE code into CE PRAM.
•
Loading the CE data into CE DRAM.
•
Establishing the equation to be applied in EQU.
•
Establishing the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.
•
Establishing the number of cycles per ADC mux cycle.
There must be thirteen 32768Hz cycles per ADC mux cycle (see System Timing Diagram, Figure 13). This means that the
product of the number of cycles per ADC conversion and the number of conversions per cycle must be 12 (allowing for one
settling cycle). The default configuration is FIR_LEN = 0 (two cycles per conversion) and MUX_DIV = 0 (6 conversions per mux
cycle).
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During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer
sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of CHOP must be altered
for each sample. It must also alternate for each alternate multiplexer reading.
The MPU must program CHOP_EN alternately between 01 and 10 on every CE_BUSY interrupt except for the first CE_BUSY
after an XFER_BUSY interrupt. Note that when XFER_BUSY occurs, it will always be at the same time as a CE_BUSY
interrupt.
Operating CE codes with environment parameters deviating from the values specified by Teridian will lead to
unpredictable results.
CE Calculations
The CE performs the precision computations necessary to accurately measure power. These computations include offset
cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag
detection, peak detection, and voltage phase measurement. All data computed by the CE is dependent on the selected meter
equation as given by EQU (in I/O RAM). As a function of EQU, the element components V0 through I2 take on different
meanings.
EQU
Watt & VAR Formula
(WSUM/VARSUM)
Element Input Mapping
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
W2SUM/
VAR2SUM
I0SQ
SUM
I1SQ
SUM
I2SQ
SUM
VA*IA
-
-
IA
-
-
-
(IA-IB)
IB
-
0
VA IA (1 element, 2W 1φ)
1
VA*(IA-IB)/2
(1 element, 3W 1φ)
2
VA*IA + VB*IB
(2 element, 3W 3φ Delta)
VA*IA
VB*IB
-
IA
IB
-
3
VA*(IA-IB)/2 + VC*IC
(2 element, 4W 3φ Delta)
VA*(IA-IB)/2
-
VC*IC
IA-IB
IB
IC
4
VA*(IA-IB)/2 + VB*(IC-IB)/2
(2 element, 4W 3φ Wye)
VA*(IA-IB)/2
VB*(IC-IB)/2
-
IA-IB
IC-IB
IC
5
VA*IA + VB*IB + VC*IC
(3 element, 4W 3φ Wye)
VA*IA
VB*IB
VC*IC
IA
IB
IC
VA*(IA-IB)/2
CE RAM Locations
The information given in the following tables apply to CE code Version CE13B09D.
Page: 68 of 104
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3-Phase Energy Meter IC
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DATA SHEET
SEPTEMBER 2011
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through 7, as listed below.
Address (HEX)
Name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
IA
VA
IB
VB
IC
VC
TEMP
0x07
V3
Description
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Phase C current
Phase C voltage
Temperature
V3 monitor/comparator
input
CE Status Word
Since the CE_BUSY interrupt occurs at 2520.6Hz, it is desirable to minimize the computation required in the interrupt handler
of the MPU. The CE status word can be read by the MPU at every CE_BUSY interrupt.
CE
Address
Name
0x51
CESTATUS
Description
See description of CE status word below
The CE Status Word is useful for generating early warnings to the MPU. It contains sag warnings for phase A, B, and C, as
well as F0, the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of
voltage and input AC signal frequency, which are useful for generating an early power fail warning to initiate necessary data
storage. CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt).
Note: The CE does not store sag alarms from one code pass to the next. CESTATUS is refreshed at every CE_BUSY
interrupt and remains valid for up to 100µs after the CE_BUSY interrupt occurs. Unsynchronized read operations of
CESTATUS will yield unreliable results.
The significance of the bits in CESTATUS is shown in the table below:
CESTATUS Bit
Name
Description
31-29
Not Used
28
F0
These unused bits will always be zero.
27
SAG_C
Normally zero. Becomes one when |VC| remains below SAG_THR for SAG_CNT
samples. Will not return to zero until |VC| rises above SAG_THR.
26
SAG_B
Normally zero. Becomes one when |VB| remains below SAG_THR for SAG_CNT
samples. Will not return to zero until |VB| rises above SAG_THR.
25
SAG_A
Normally zero. Becomes one when |VA| remains below SAG_THR for SAG_CNT
samples. Will not return to zero until |VA} rises above SAG_THR.
24-0
Not Used
F0 is a square wave at the exact fundamental input frequency.
These unused bits will always be zero.
For generating proper status information, the CE is initialized by the MPU using SAG_THR (default of 80V RMS at the meter
input if VMAX=600V) and SAG_CNT (default 80 samples). Using the default value for SAG_CNT, the peak-to-peak signal has to
be below SAG_THR value for 32 milliseconds to activate the SAG_X status bits.
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CE
Address
0x31
0x32
Name
Default
SAG_THR
SAG_CNT
Description
+23,930,000
(0x16D23AA)
Meter voltage inputs must be above this threshold to prevent sag alarms.
-9
LSB = VMAX * 7.879810 V.
For example, if a sag threshold of 80V RMS is desired,
2
SAG _ THR = VMAX ⋅807.8798
⋅10 −9
Number of consecutive voltage samples below SAG_THR before a sag alarm
is declared (80*397µs = 31.8ms).
80
CE Transfer Variables
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer
variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout
each accumulation interval. In this data sheet, the names of CE transfer variables always end with _X.
Fundamental Power Measurement Variables
The table below describes each transfer variable for fundamental power measurement. All variables are signed 32 bit integers.
Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the
integration time is 1 second. Additionally, the hardware will not permit output values to ‘fold back’ upon overflow.
CE
Address
Name
0x42
WSUM_X
0x43
W0SUM_X
0x44
W1SUM_X
0x45
W2SUM_X
0x46
VARSUM_X
0x47
VAR0SUM_X
0x48
VAR1SUM_X
0x49
VAR2SUM_X
Description
The signed sum: W0SUM_X+W1SUM_X+W2SUM_X
The sum of Watt samples from each wattmeter element.
LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh.
The signed sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X
The sum of VAR samples from each wattmeter element.
-13
LSB = 9.4045*10 VMAX IMAX / In_8 VARh.
WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase-C Wh or VARh values according to the
metering equation specified in the I/O RAM register EQU. WxSUM_X is the Wh value accumulated for phase ‘x’ in the last
accumulation interval and can be computed based on the specified LSB value.
For example, with VMAX = 600V and IMAX = 208A, LSB (for WxSUM_X ) is 0.1173 µWh.
Instantaneous Power Measurement Variables
The FREQSEL Register selects the input phase used for frequency measurement and for the MAIN_EDGE counter. The
frequency measurement is implemented using the frequency locked loop of the CE for the selected phase.
IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval.
INSQSUM_X can be used for computing the neutral current.
Page: 70 of 104
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71M6513/71M6513H
3-Phase Energy Meter IC
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DATA SHEET
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CE
Address
Name
Description
0x33
FREQSEL
Selected phase for the frequency monitor, the phase-to-phase voltage
measurements, and voltage zero crossings:
Phase A: 0 (default)
Phase B: 1
Phase C: 2
0x41
FREQ_X
Fundamental frequency. LSB
0x4A
I0SQSUM_X
0x4B
I1SQSUM_X
0x4C
I2SQSUM_X
≡
FS
≈ 0.587 ⋅ 10 −6 Hz
32
2
The sum of squared current samples from each element.
LSB = 9.4045*10-13 IMAX2 / In_82 A2h
The sum of squared current samples from the calculated neutral:
0x4D
INSQSUM_X
∑ (I
0
+ I1 + I 2 ) 2
-12
LSB = 1.2539*10
0x4E
V0SQSUM_X
0x4F
V1SQSUM_X
0x50
V2SQSUM_X
0x5A
V3SQSUM_X
.
IMAX2 / In_82 A2h
The sum of squared voltage samples from each element.
LSB= 9.4045*10-13 VMAX2 V2h
The sum of squared voltage samples from the V3 input. If CAL_V3 =
-13
2 2
-13
2 2
8192, then LSB = 9.4045*10 VMAX V h or 9.4045*10 IMAX I h
The RMS values can be computed by the MPU from the squared current and voltage samples as per the formulae:
IxRMS =
IxSQSUM ⋅ LSB ⋅ 3600 ⋅ FS
N ACC
VxRMS =
VxSQSUM ⋅ LSB ⋅ 3600 ⋅ FS
N ACC
Other Measurement Parameters
PH_AtoB_X and PH_AtoC_X contain phase angle information between the phase voltages, depending on the setting of
FREQ_SEL, as shown in the table below. The phase angle information can be used for phase sequencing and error detection.
If the voltage at the selected phase is missing, the meter accuracy will be reduced.
To maintain accuracy, FREQ_SEL must be set to a phase with an active voltage. For example, in a system where
phase A is lost (which can be detected using the SAG bits or by comparing the voltage VA with a lower limit),
FREQ_SEL must be set to an alternative phase to maintain accuracy.
MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X is the number of halfcycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQ_SEL register.
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CE
Address
Name
FREQU_SEL = 0
FREQU_SEL = 1
FREQU_SEL = 2
Phase lag from VA to VB.
Phase lag from VB to VC.
Phase lag from VC to VA.
PH_AtoB_X*360/NACC+2.4
PH_AtoB_X*360/NACC+2.4
PH_AtoB_X*360/NACC-4.8
Phase lag from VA to VC.
Phase lag from VB to VA.
Phase lag from VC to VB.
Angle in degrees
PH_AtoC_X*360/NACC+4.8
PH_AtoC_X *360/NACC-2.4
PH_AtoC_X *360/NACC-2.4
MAINEDGE_X
The number of zero
crossings of VA in the previous accumulation interval.
The number of zero
crossings of VB in the previous accumulation interval.
The number of zero
crossings of VC in the previous accumulation interval.
PH_AtoB_X
0x52
Angle in degrees
PH_AtoC_X
0x53
0x55
Description
Edge crossings are either direction and are debounced.
Temperature Measurement and Temperature Compensation
Input variables: TEMP_NOM is the reference value for temperature measurement, i.e. when this value is set with
TEMP_RAW_X at known temperature. The 71M6513/6513H measures temperature with reference to this value.
DEGSCALE is the slope or rate of temperature increase or decrease from the TEMP_NOM for TEMP_X measurement.
PPMC and PPMC2 are temperature compensation coefficients. Their values should reflect the characteristics of the band gap
voltage reference of the chip. PPMC and PPMC2 follow the square law characteristics to compensate for nonlinear temperature
behaviors, when the 71M6513/6513H is in internal temperature compensation mode.
EXT_TEMP allows the MPU to select between direct control of GAIN_ADJ or management of GAIN_ADJ by the CE, based on
TEMP_X and the temperature correction coefficients PPMC and PPMC2.
Page: 72 of 104
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DATA SHEET
SEPTEMBER 2011
CE
Address
Name
Default
0x11
TEMP_NOM
0
0x30
DEGSCALE
22721
Description
During calibration, the value of TEMP_RAW_X should be placed in
TEMP_NOM.
Scale factor for TEMP_X.
TEMP_X = -DEGSCALE*2-22*(TEMP_RAW_X-TEMP_NOM).
Should be 15 or 0. When 15, causes the CE to ignore internal temperature
compensation and permits the MPU to control GAIN_ADJ. When internal
temperature compensation is selected, GAIN_ADJ will be:
0x38
0x39
EXT_TEMP
PPMC
0
0
TEMP _ X ⋅ PPMC TEMP _ X 2 ⋅ PPMC 2
GAIN _ ADJ = 16384 + floor 1 +
+
214
2 23
Default is 0 (internal compensation).
Linear temperature compensation factor. Equals the linear temperature coefficient (PPM/°C) of VREF multiplied by 26.84, or TC1 (expressed in µV/°C,
1
see Electrical Specifications) multiplied by 22.46 . A positive value will cause
the meter to run faster when hot. The compensation factor affects both V and
I and will therefore have a double effect on products.
1
0x3A
PPMC2
0
CE scaling factor 22.46=221/(1.195*57)
Square-law temperature compensation factor. Equals the square-law temperature coefficient (PPM/°C2) of VREF multiplied by 1374, or TC2 (ex2
2
pressed in µV/°C , see Electrical Specifications) multiplied by 1150 .1. A positive value will cause the meter to run faster when hot. The compensation
factor affects both V and I and will therefore have a double effect on products.
2
29
8
CE scaling factor 1150=2 /(1.195*5 )
Output variables: TEMP_X is the temperature measurement from reference temperature of TEMP_NOM. TEMP_X is
computed using TEMP_RAW_X and DEGSCALE. This quantity is positive when the temperature is above the reference and is
negative for cold temperatures.
TEMP_RAW_X is the raw processed value from ADC output and is the fundamental quantity for temperature measurement.
TEMP_RAW_X is less than TEMP_NOM at higher temperatures. TEMP_RAW_X is more than TEMP_NOM for cooler
temperatures than reference temperature.
GAIN_ADJ is a scaling factor for power measurements based on temperature (when in internal temperature compensation
mode). In general, for higher temperatures it is lower than 16384 and higher than 16384 for lower temperatures. GAIN_ADJ is
mainly dependent on the PPMC, PPMC2 and TEMP_X register values. This parameter is automatically computed by the CE
and is used by the CE for temperature compensation.
CE
Address
Name
0x40
TEMP_X
0x54
TEMP_RAW_X
0x2E
GAIN_ADJ
Description
Deviation from Calibration temperature. LSB = 0.1 0C.
Filtered, unscaled reading from temperature sensor. This value should be
written to TEMP_NOM during meter calibration.
Scales all voltage and current inputs. 16384 provides unity gain. Default is
16384. If EXT_TMP = 0, GAIN_ADJ is updated by the CE.
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Pulse Generation
Input variables: The combination of the PULSE_SLOW and PULSE_FAST parameters control the speed of the pulse rate. The
default values of 1 and 1 will maintain the original pulse rate given by the Kh equation.
WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The lower WRATE it is the
slower is the pulse rate for measured power quantity. The metering constant Kh is derived from WRATE as the amount of
energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120V and 30A results in one
pulse per second. If the load is 240V at 150A, ten pulses per second will be generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE > 0. In this case, the pulse rate is determined by
APULSEW and APULSER. The MPU has to load the source for pulse generation in APULSEW and APULSER to generate pulses.
Irrespective of the EXT_PULSE, status the output pulse rate controlled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE > 0, the MPU is providing the source for pulse generation. If EXT_PULSE is negative, W0SUM_X
and VAR0SUM_X are the default pulse generation sources. In this case, creep cannot be controlled since it is an MPU function.
The maximum pulse rate is 3*FS = 7.56kHz.
PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. The
minimum pulse width possible is 66.16µs.
The maximum time jitter is 1/6 of the MUX cycle period (normally 67μs) and is independent of the number of pulses measured.
Thus, if the pulse generator is monitored for 1 second, the peak jitter is 67ppm. After 10 seconds, the peak jitter is 7ppm. The
average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output
at its maximum rate without exhibiting any roll-over characteristics. The actual pulse rate, using WSUM as an example, is:
RATE =
X ⋅ WRATE ⋅ WSUM ⋅ FS
Hz
2 46
Where FS = 2520.6Hz (sampling frequency), and X = pulse speed factor derived from CE variables PULSE_SLOW and
PULSE_FAST (see table below).
Page: 74 of 104
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CE
Address
0x28
Name
PULSE_SLOW
Default
1
Description
When PULSE_SLOW > 0, the pulse generator input is reduced 64x.
When PULSE_FAST > 0, the pulse generator input is increased 16x.
These two parameters control the pulse gain factor X (see table below).
Allowed values are either 1 or –1.
X
PULSE_SLOW
PULSE_FAST
2
-1
-1
6
-1
1
1.5 * 2 = 0.09375
-4
1
-1
1.5
1 (default)
1 (default)
1.5 * 2 = 6
0x29
PULSE_FAST
1
1.5 * 2 = 96
0x2D
WRATE
683
Kh = VMAX*IMAX *66.1782 / (In_8 *WRATE*NACC*X) Wh/pulse.
0x36
SUM_PRE
2520
PRE_SAMPS * SUM_CYCLES (NACC)
0x37
EXT_PULSE
15
Should be 15 or 0. When zero, causes the pulse generators to respond to
WSUM_X and VARSUM_X. Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
0x3C
PULSE_WIDTH
50
The maximum pulse width (low-going pulse) is:
(2 * PULSE_WIDTH + 1) * 66µs. 0 is a legitimate value.
0
Wh pulse generator input, to be updated by the MPU when using external pulse
generation (see DIO_PW bit). The output pulse rate is:
-32
-14
APULSEW * FS * 2 * WRATE * 2
This input is buffered and can be updated by the MPU during a computation
interval. The change will take effect at the beginning of the next interval.
0
VARh pulse generator input, to be updated by the MPU when using external
pulse generation (see DIO_PV bit). The output pulse rate is:
-32
-14
APULSER * FS*2 * WRATE * 2
This input is buffered and can be updated by the MPU during a computation
interval. The change will take effect at the beginning of the next interval.
0x26
0x27
APULSEW
APULSER
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CE Calibration Parameters
The table below lists the parameters that are typically entered to effect calibration of meter accuracy.
CE
Address
Name
Default
0x08
CAL_IA
16384
0x09
CAL_VA
16384
0x0A
CAL_IB
16384
0x0B
CAL_VB
16384
0x0C
CAL_IC
16384
0x0D
0x65
CAL_VC
CAL_V3
16384
8192
0x0E
PHADJ_A
0
0x0F
PHADJ_B
0
0x10
0x11
PHADJ_C
TEMP_NOM
Page: 76 of 104
Description
These constants control the gain of their respective channels. The nominal
14
value for each parameter is 2 = 16384. The gain of each channel is directly
proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow,
CAL should be increased by 1%.
Gain control for V3 channel, used for neutral current measurement.
These three constants control the CT phase compensation. No compensation
occurs when PHADJ_X = 0. As PHADJ_X is increased, more compensation
15
(lag) is introduced. Range: ±2 – 1. If it is desired to delay the current by the
angle Φ:
PHADJ _ X = 220
0.02229 ⋅ TANΦ
at 60Hz
0.1487 − 0.0131 ⋅ TANΦ
PHADJ _ X = 2 20
0.0155 ⋅ TANΦ
at 50Hz
0.1241 − 0.009695 ⋅ TANΦ
0
N/A
During calibration, the value of TEMP_RAW_X should be placed in
TEMP_NOM.
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
Other CE Parameters
The table below shows CE parameters used for suppression of noise due to scaling and truncation effects as well as scaling
factors.
CE
Address
Name
Default
0x2F
QUANT
0
This parameter is added to the Watt calculation to compensate for input noise
and truncation.
-9
LSB=(VMAX*IMAX / In_8) *1.04173*10 W
0x34
QUANT_VAR
0
This parameter is added to the VAR calculation to compensate for input noise
and truncation.
-9
LSB = (VMAX*IMAX/In_8) * 1.04173*10 W
0x35
This parameter is added to compensate for input noise and truncation in the
2
2
squaring calculations for I and V .
0
QUANT_I
Description
LSB=VMAX2*1.04173*10-9 V2
LSB= (IMAX2/In_82)*1.04173*10-9 A2
0x3B
KVAR
6448
0x64
QUANT_V3
0
Scale factor for the VAR calculation. The default value of KVAR should never
need to be changed.
Offset for low-current measurement on V3.
LSB = = 9.4045*10-13 IMAX2 A2h
TYPICAL PERFORMANCE DATA
Wh Accuracy at Room Temperature
0.2
0 Deg
60 Deg
0.15
-60 Deg
%Error
0.1
180 Deg
0.05
1
3
200
0.3
10
0
25 30
100
-0.05
-0.1
-0.15
-0.2
0.1
1
10
A
100
1000
Figure 24: Wh Accuracy, 0.3A - 200A/240V
VARh Accuracy at Room Temperature
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0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
90 Deg
150 Deg
% Error
3
270 Deg
10
25
1
30
0.3
100
0.1
1
10
200
100
A
1000
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance
Harmonic Performance
2
1
0
Error [%]
-1
-2
-3
50Hz Harmonic Data
60Hz Harmonic Data
-4
-5
-6
-7
-8
1
3
5
7
9
11
13
15
17
19
21
23
25
Harmonic
Test performed at current distortion amplitude of 40% and voltage distortion amplitude of 10% as per IEC 62053, part 22.
Figure 26: Meter Accuracy over Harmonics at 240V, 30A
Page: 78 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
APPLICATION INFORMATION
Connection of Sensors (CT, Resistive Shunt, Rogowski Coil)
Figures 27 through 30 show how resistive dividers, current transformers, restive shunts, and Rogowski coils are connected to
the voltage and current inputs of the 71M6513.
The analog input pins of the 71M6511 are designed for sensors with low source impedance. RC filters with resistance
values higher than those implemented in the Teridian Demo Boards should be avoided.
VA = Vin * Rout/(Rout + Rin)
VA
Vin
Rin
Rout
Figure 27: Resistive Voltage Divider (left), Current Transformer (right)
Vout = dIin /dt
R
Vout
Iin
1/N
Vout = dIin /dt
IA
R
Vout
VC
V3P3
Figure 28: Resistive Shunt (left), Rogowski Coil (right)
Distinction between 71M6513 and 71M6513H Parts
71M6513H parts go through a process of trimming and characterization during production that make them suitable to highaccuracy applications.
The first process applied to the 71M6513H is the trimming of the reference voltage, which is guaranteed to have accuracy over
temperature of better that ±10PPM/°C.
The second process applied to the 71M6513H is the characterization of the reference voltage over temperature. The
coefficients for the reference voltage are stored in so-called trim fuses (I/O RAM registers TRIMBGA, TRIMBGB, TRIMM[2:0].
The MPU program can read these trim fuses and calculate the correction coefficients PPM1 and PPM2 per the formulae given
in the Performance Specifications section (VREF, VBIAS). See the Temperature Compensation section for details.
The fuse TRIMBGB is non-zero for the 71M6513H part and zero for the 71M6513 part.
Trim fuse information is not available for non-H parts. Thus, the standard settings are to be applied. These settings are:
•
PPMC = TC1 * 22.46 = –149
•
PPMC2 = TC2 * 1150.1 = –392
© 2005-2011 Teridian Semiconductor Corporation
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71M6513/71M6513H
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DATA SHEET
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Temperature Compensation and Mains Frequency Stabilization for the RTC
The accuracy of the RTC depends on the stability of the external crystal. Crystals vary in terms of initial accuracy as well as in
terms of behavior over temperature. The flexibility provided by the MPU allows for compensation of the RTC using the substrate temperature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL,
Y_CALC, and Y_CAL_C2 have to be calculated. Provided the IC substrate temperatures tracks the crystal temperature, the
coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count, using the
RTC_DEC_SEC or RTC_INC_SEC registers in I/O RAM.
It is not recommended to measure crystal frequency directly due to the error introduced by the measurement probes. A
practical method to measure the crystal frequency (when installed on the PCB with the 71M6513) is to have a DIO pin toggle
every second, based on the RTC interrupt, with all other interrupts disabled. When this signal is measured with a precision
timer, the crystal frequency can be obtained from the measured time period t (in µs):
f = 32768
10 6 µs
t
Example: Let us assume a crystal characterized by the measurements shown in Table 61. The values show that even at
nominal temperature (the temperature at which the chip was calibrated for energy), the deviation from the ideal crystal
frequency is 11.6 PPM, resulting in about one second inaccuracy per day, i.e. more than some standards allow.
Deviation from
Nominal
Temperature [°C]
Measured
Frequency [Hz]
Deviation from
Nominal
Frequency [PPM]
+50
32767.98
-0.61
+25
32768.28
8.545
0
32768.38
11.597
-25
32768.08
2.441
-50
32767.58
-12.817
Table 61: Frequency over Temperature
As Figure 29 shows, even a constant compensation would not bring much improvement, since the temperature characteristics
of the crystal are a mix of constant, linear, and quadratic effects (in commercially available crystals, the constant and quadratic
effects are dominant).
32768.5
32768.4
32768.3
32768.2
32768.1
32768
32767.9
32767.8
32767.7
32767.6
32767.5
-50
-25
0
25
50
Figure 29: Crystal Frequency over Temperature
The temperature characteristics of the crystal are obtained from the curve in Figure 29 by curve-fitting the PPM deviations. A
fairly close curve fit is achieved with the coefficients a = 10.89, b = 0.122, and c = –0.00714 (see Figure 30).
Page: 80 of 104
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3-Phase Energy Meter IC
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DATA SHEET
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When applying the inverted coefficients, a curve (see Figure 30) will result that effectively neutralizes the original crystal
characteristics. The frequencies were calculated using the fit coefficients as follows:
a
b
c
f = f nom ⋅ 1 + 6 + T 6 + T 2 6
10
10
10
32768.5
32768.4
32768.3
32768.2
32768.1
32768
32767.9
32767.8
crystal
32767.7
curve fit
32767.6
inverse curve
32767.5
-50
-25
0
25
50
Figure 30: Crystal Compensation
The MPU Demo Code supplied with the Teridian Demo Kits has a direct interface for these coefficients and it directly controls
the RTC_DEC_SEC or RTC_INC_SEC registers. The Demo Code uses the coefficients in the following form:
CORRECTION ( ppm) =
Y _ CAL
Y _ CALC
Y _ CALC 2
+T ⋅
+T2 ⋅
10
100
1000
Note that the coefficients are scaled by 10, 100, and 1000 to provide more resolution. For our example case, the coefficients
would then become (after rounding, since the Demo Code accepts only integers):
Y_CAL = 109, Y_CALC = 12, Y_CALC2 = 7
Alternatively, the mains frequency may be used to stabilize or check the function of the RTC. For this purpose, the CE
provides a count of the zero crossings detected for the selected line voltage in the MAIN_EDGE_X address. This count is
equivalent to twice the line frequency, and can be used to synchronize and/or correct the RTC.
External Temperature Compensation
In a production electricity meter, the 71M6513 or 71M6513H is not the only component contributing to temperature dependency. In fact, a whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors)
will exhibit slight or pronounced temperature effects. Since the output of the on-chip temperature sensor is accessible to the
MPU, temperature-compensation mechanisms with great flexibility, i.e. beyond the capabilities implemented in the CE, are
possible.
Temperature Measurement
Temperature measurement can be implemented with the following steps:
1)
At a known temperature TN, read the TEMP_RAW register of the CE and write the value into TEMP_NOM.
2)
Read the TEMP_X register at the known temperature. The obtained value should be 40 (i.e. T > 62°C) or for which
T-22 < -40 (i.e. T < -18°C), the data sheet states ±40 PPM/°C. For temperatures between -18°C and +62°C, the error should
be considered constant at ±1,600 PPM, or ±0.16%.
Similar considerations apply to the high-accuracy part 71M6513H (see Table 63), where the error around the calibration
temperature should be considered constant at ±600 PPM, or ±0.06%.
Table 62: VREF Definition for the Regular Accuracy Parts 71M6513
Parameter
Typ
Min
VREF(T) deviation from VNOM(T)
VREF (T ) − VNOM (T )
10 6
max( T − 22 ,40)
VNOM (T )
-40
+40
PPM/ºC
Table 63: VREF Definition for the High-Accuracy Parts 71M6513H
Parameter
Min
VREF(T) deviation from VNOM(T)
VREF (T ) − VNOM (T )
10 6
max( T − 22 ,40)
VNOM (T )
-10
Typ
+10
PPM/ºC
Figure 31 and Figure 32 show this concept graphically. The “box” from -18°C to +62°C reflects the fact that it is impractical
to measure the temperature coefficient of high-quality references at small temperature excursions. For example, at +25°C,
the expected error would be ±3°C * 40 PPM/°C, or just 0.012% for the regular-accuracy parts.
The maximum deviation of ±2520 PPM (or 0.252%) for the regular-accuracy parts is reached at the temperature
extremes. If the reference voltage is used to measure both voltage and current, the identical errors of ±0.252% add up to
a maximum Wh registration error of ±0.504%.
The maximum deviation of ±630 PPM (or 0.063%) for the 71M6513H is reached at the temperature extremes. If the
reference voltage is used to measure both voltage and current, the identical errors of ±0.063% add up to a maximum Wh
registration error of ±0.126%.
Page: 82 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
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DATA SHEET
SEPTEMBER 2011
Error Band (PPM) over Temperature (°C)
2800
2400
2000
1600
1200
800
400
0
-400
-800
-1200
-1600
-2000
-2400
-2800
±40 PPM/°C
±40 PPM/°C
-40
-20
0
20
40
60
80
Figure 31: Error Band for VREF over Temperature (Regular-Accuracy Parts)
Error Band (PPM) over Temperature (°C)
1000
+10 PPM/°C
800
600
400
200
0
-200
-400
-600
-10 PPM/°C
-800
-1000
-40
-20
0
20
40
60
80
Figure 32: Error Band for VREF over Temperature (High-Accuracy Parts)
Crystal Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these
crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is
very low to maximize the lifetime of any battery backup device attached to VBAT.
Board layouts with minimum capacitance from XIN to XOUT will require less battery current. Good layouts will have XIN and
XOUT shielded from each other.
© 2005-2011 Teridian Semiconductor Corporation
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For best rejection of electromagnetic interference, connect the crystal body and the ground terminals of the two
crystal capacitors to GNDD through a ferrite bead. No external resistor should be connected across the crystal,
since the oscillator is self-biasing.
Connecting LCDs
The 71M6513 has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 33 shows the basic
connection for a LCD.
71M6513
LCD
segments
commons
Figure 33: Connecting LCDs
Figure 34 shows how 5V LCDs can be operated even when a 5V supply is not available. Setting the I/O RAM register
LCD_BSTEN to 1 starts the on-chip boost circuitry that will output an AC frequency on the VDRV pin. Using a small coupling
capacitor, two general-purpose diodes and a reservoir capacitor, a 5VDC voltage is generated which can be fed back into the
VLCD pin of the 71M6513. The LCD drivers are enabled with the I/O register LCD_ON; I/O register LCD_FS is used to adjust
contrast, and LCD_MODE selects the operation mode (LCD type).
Page: 84 of 104
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3-Phase Energy Meter IC
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DATA SHEET
SEPTEMBER 2011
V3P3
71M6513
LCD_BSTEN
VDRV
V3P3
5VDC
5V LCD
VLCD
Contrast
LCD_FS
ON/OFF
LCD_EN
segments
LCD type LCD_MODE
commons
Figure 34: LCD Boost Circuit
Connecting I2C EEPROMs
I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 35.
Pull-up resistors of roughly 3kΩ to V3P3 should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM
must be set to 1 in order to convert the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.
71M6513
V3P3
3kΩ
3kΩ
EEPROM
DIO4
SCL
DIO5
SDA
Figure 35: EEPROM Connection
Connecting 5V Devices
In general, all pins of the 71M6513 are compatible with external 5V devices. The exceptions are the power supply pins and the
RX pin of the UART (see section Electrical Specifications).
© 2005-2011 Teridian Semiconductor Corporation
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V3P3
71M651X
R1 = 100kΩ
RX
VIN
Figure 36: Interfacing RX to a 0-5V Signal
Figure 36 shows how a 5V signal from an external device can be safely interfaced to the RX pin.
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3-Phase Energy Meter IC
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DATA SHEET
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Optical Interface
The pins OPT_TX and OPT_RX can be used for a regular serial interface, e.g. by connecting a RS_232 transceiver, or they
can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a FLAG interface.
Figure 37 shows the basic connections. The OPT_TX pin becomes active when the I/O RAM register OPT_TXDIS is set to 0.
V3P3SYS
R1
71M6513
OPT_RX
100pF 100kΩ
Phototransistor
V3P3SYS
R2
LED
OPT_TX
Figure 37: Connection for Optical Components
Connecting V1 and Reset Pins
A voltage divider should be used to establish that V1 is in a safe range when the meter is in mission mode (V1 must be lower
than 2.9V in all cases in order to keep the hardware watchdog timer enabled). For proper debugging or loading code into the
71M6513 mounted on a PCB, it is necessary to have a provision like the header shown above R1 in Figure 38. A shorting
jumper on this header pulls V1 up to V3P3 disabling the hardware watchdog timer.
R3
R1
Vin
10kΩ
R2
V1
Figure 38: Voltage Divider for V1
Even though a functional meter will not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping.
When a circuit is used in an EMI environment, the RESETZ pin should be supported by the external components shown in
Figure 39. R1 should be in the range of 200Ω, R2 should be around 10Ω. The capacitor C1 should be 1nF. R1 and C1 should
be mounted as close as possible to the IC. In cases where the trace from the pushbutton switch to the RESTZ pin poses a
problem, R2 can be removed.
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71M6513
V3P3
V3P3
10Ω
200Ω
R1
RESETZ
R2
C1
1nF
Pushbutton
DGND
Figure 39: External Components for RESETZ
Connecting the V3 Pin
The following should be noted when connecting the V3 pin:
1)
If the V3 pin is unused it should be left floating or terminated to the VREF pin.
2)
If the V3 pin is used as a comparator input the digital input voltage applied to V3 should be limited to VBIAS ±0.9V.
3)
If the V3 pin is used either as an auxiliary analog input, and temperature measurements are made and evaluated
using the alternate multiplexer cycle, the V3 input voltage range must be restricted to VBIAS ±0.9 V (i.e. 0.6 V to 2.4
V). Otherwise, the TEMP or V3 measurement could be inaccurate. This precaution is particularly important for
customers who are using the TEMP samples for temperature compensation, especially with the 71M6513H devices.
Connecting a Battery
Many meter manufacturers assemble the meter PCB with the 71M6513 IC and the other electronic components first and then
join the meter PCB with the meter enclosure, sensors and other main components separately at a later production step.
Typically, programming, final test (ATE), and calibration are performed after this second step.
The following production sequence is strongly recommended:
1)
2)
During PCB assembly, when adding/inserting the battery, the board supply voltage (V3P3A, V3P3D) should be active
(i.e. at 3.3 VDC), which can be achieved by briefly connecting the battery to V3P3A/V3P3D through a jumper wire.
After the battery is inserted with the board power active, the jumper wire should be removed.
The battery should then remain connected through factory test (ATE), time on the shelf and shipment.
In cases where it is not feasible to power V3P3A/V3P3D while inserting the battery, it is recommended to isolate the battery in
its holder using a removable piece of Kapton tape or other isolating material. This isolation should then be removed once the
meter is fully powered during the calibration and test process.
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71M6513/71M6513H
3-Phase Energy Meter IC
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Flash Programming
Operational or test code can be programmed into the flash memory using either an in-circuit emulator or the Flash Download
Board Module (FDBM) available from Teridian. The flash programming procedure uses the E_RTS, E_RXTX, and E_TCLK
pins.
MPU Firmware Library
All application-specific MPU functions mentioned above under “Application Information” are available from Teridian as a
standard ANSI C library and as ANSI “C” source code. The code is available as part of the Demonstration Kit for the 71M6513
and 71M6513H ICs. The Demonstration Kits come with the 71M6513 or 71M6513H IC preprogrammed with demo firmware
mounted on a functional sample meter PCB (Demo Board). The Demo Boards allow for quick and efficient evaluation of the IC
without having to write firmware or having to supply an in-circuit emulator (ICE).
A reference guide for firmware development on the 71M6513 and 71M6513H is available as a separate document (Software
User’s Guide, “SUG”). The User’s Manuals supplied with the Demo Kits contain MPU address maps for the demo code as well
as other useful information, such as sample calibration procedures.
© 2005-2011 Teridian Semiconductor Corporation
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A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
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SPECIFICATIONS
Electrical Specifications
ABSOLUTE MAXIMUM RATINGS
Supplies and Ground Pins:
−0.5V to 4.6V
0V to 0.5V
-0.5V to 7V
-0.5V to 4.6V
-0.5V to +0.5V
V3P3D, V3P3A
| V3P3D - V3P3A |
VLCD
VBAT
GNDD
Analog Output Pins:
-1mA to 1mA,
-0.5 to V3P3A+0.5V
-1mA to 1mA,
-0.5V to 3.0V
VREF, VBIAS
V2P5
Analog Input Pins:
IA, VA, IB, VB, IC, VC, V2, V3
XIN, XOUT
RX
-0.5V to V3P3A+0.5V
-0.5V to 3.0V
-0.5V to 3.6V
-1mA to 1mA
-0.5 to V3P3A+0.5V
OPT_RX
Digital Input Pins:
DIO0-21, E_RXTX, E_RST, E_ISYNC/BRKRQ
-0.5 to 6V
TEST, RESETZ
-0.5 to V3P3D+0.5V
All Other Pins:
Input pins
-5mA to 5mA
-0.5V to V3P3D+0.5V
Output pins
-30mA to 30mA
-0.5 to V3P3D+0.5V
Temperature:
Operating junction temperature (peak, 100ms)
Operating junction temperature (continuous)
Storage temperature
Solder temperature – 10 second duration
140 °C
125 °C
−45 °C to 165 °C
250 °C
ESD Stress:
Pins IA, VA, IB, VB, IC, VC, RX, TX, E_RST, E_TCLK, E_RXTX, E_TBUS[n]
All other pins
4kV
2kV
Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA.
Page: 90 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITION
MIN
TYP
3.3V Supply Voltage
†
(V3P3A, V3P3D)
Normal Operation
3.0
3.3
Battery Backup
VLCD
VBAT
Operating Temperature
†
UNIT
3.6
V
0
3.45
V
2.9
5.5
V
No Battery
Battery Backup
MAX
Externally Connect to V3P3D
2.0
3.8
V
-40
85
ºC
V3P3A and V3P3D should be shorted together on the circuit board. GNDA and GNDD should also be shorted on the circuit board.
LOGIC LEVELS
PARAMETER
CONDITION
TYP
MAX
UNIT
Digital high-level input voltage, VIH
2
V3P3D
V
Digital low-level input voltage, VIL
−0.3
0.8
V
ILOAD = 1mA
V3P3D
–0.4
V3P3D
V
ILOAD = 15mA
V3P3D1
0.6
ILOAD = 1mA
0
Digital high-level output voltage VOH
Digital low-level output voltage VOL
V
0.4
V
1
0.8
V
10
10
100
100
μA
μA
-1
1
μA
10
-1
100
1
μA
μA
ILOAD = 15mA
Input pull-up current, IIL
VIN=0V
RESETZ
.......................................
Other digital inputs
VIN=V3P3D
Input pull down current, IIH
TEST
Other digital inputs
1
MIN
Guaranteed by design; not production tested.
© 2005-2011 Teridian Semiconductor Corporation
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71M6513/71M6513H
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DATA SHEET
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SUPPLY CURRENT
PARAMETER
V3P3A + V3P3D + VLCD current
V3P3A current
V3P3D current
VLCD current
VBAT current
V3P3D current
V3P3A + V3P3D current
1
CONDITION
Normal Operation,
V3P3A=V3P3D=VLCD=3.3V
CKMPU=614kHz
VBAT=3.6V
No flash memory write
MIN
TYP
6.4
9.5
mA
4.3
mA
2.5
4.8
mA
0.2
0.4
mA
300
nA
-300
2.9
3.6
5.1
Power save/sleep mode
V3P3A=V3P3D=VLCD=3.3V,
CE, ADC, E_TCLK, VREF disabled
CKMPU=153.5kHz
CKMPU=38.4kHz
6
4.9
Normal Operation as above,
except write Flash at maximum
rate.
VBAT current,
VBAT=3.6V
Battery backup,
≤25°C
V3P3A=V3P3D=VLCD=0V
fOSC = 32kHz
85°C
UNIT
3.7
Normal Operation,
V3P3A=V3P3D=VLCD=3.3V
VBAT=3.6V, no flash memory
write
CKMPU=1,228kHz
CKMPU=2,456kHz
CKMPU=4,912kHz
V3P3D current, Write Flash
MAX
mA
mA
mA
7
7
mA
mA
mA
2
4
μA
41
121
μA
TYP
MAX
UNIT
440
mV
+3
mV/V
Guaranteed by design; not production tested.
2.5V VOLTAGE REGULATOR
Unless otherwise specified, load = 5mA
PARAMETER
Voltage overhead V3P3-V2P5
PSSR ∆V2P5/∆V3P3
Page: 92 of 104
CONDITION
Reduce V3P3 until V2P5
drops 200mV
RESETZ=1, iload=0
MIN
-3
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
VREF, VBIAS
Unless otherwise specified, VREF_DIS=0
PARAMETER
VREF output voltage, VNOM(25)
VREF chop step
VREF output impedance
A
VNOM definition
CONDITION
Ta = 22ºC
MIN
1.193
TYP
1.195
VREF_CAL =1,
ILOAD = 10µA, -10µA
VNOM(T) = VREF(22) + (T–22)TC1 + (T–22)2TC2
-- If TRIMBGA and TRIMBGB available (6513H) --
VREF temperature coefficients
TC1 (linear)
TC2 (quadratic)
TRIMBGA, TRIMBGB, TRIMM[2:0]: See
TRIMSEL, TRIM registers
MAX
1.197
40
UNIT
V
mV
2.5
kΩ
V
x(33-0.28y) + 0.33y + 7.9
x(0.02-0.0002y) – 0.46
where x = 0.1TRIMBGB - 0.14(TRIMM[2:0]+0.5),
µV/°C
2
µV/°C
TEMP _ NOM
− 500TRIM _ BGA − 370000
2
y=
900
VREF(T) deviation from VNOM(T)
10 6
VREF (T ) − VNOM (T )
-10
max(| T − 22 |,40)
VNOM
-- If TRIMBGA and TRIMBGB not available (6513) -VREF temperature coefficients
TC1 (linear)
TC2 (quadratic)
VREF(T) deviation from VNOM(T)
7.0
-0.341
VREF (T ) − VNOM (T )
10 6
VNOM
max(| T − 22 |,40)
Ta = -40ºC to +85ºC
VREF aging
Ta = 25ºC
1
-40
Ta = 25ºC
(-1%)
Ta = -40ºC to 85ºC
(-2%)1
VBIAS output impedance
ILOAD = 1mA, -1mA
A
This relationship describes the nominal behavior of VREF at different temperatures.
VBIAS output voltage
1
10
µV/ºC
µV/°C2
+401
ppm/ºC
(+1%)
(+2%)1
500
ppm/
year
V
V
Ω
±25
1.5
1.51
240
ppm/ºC
Guaranteed by design; not production tested.
CRYSTAL OSCILLATOR
Crystal is disconnected. Test load is series 200pF, 100kΩ connected between DGND and XOUT.
PARAMETER
CONDITION
MIN
TYP
MAX
4
Maximum Output Power to Crystal
Crystal connected
1
1
Xin to Xout Capacitance
3
Capacitance to DGND1
Xin
5
Xout
5
Watchdog RTC_OK threshold
25
© 2005-2011 Teridian Semiconductor Corporation
UNIT
μW
pF
pF
pF
kHz
Page: 93 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
ADC CONVERTER, VDD REFERENCED
FIR_LEN=0, VREF_DIS=0, VDDREFZ=0
PARAMETER
Recommended Input Range
(Vin-V3P3A)
Voltage to Current Crosstalk:
CONDITION
MAX
250
UNIT
mV
peak
Vin = 200mV peak, 65Hz,
on VA, VB, or VC
IC
Vin=65Hz,
64kpts FFT, BlackmanHarris window
Vin=65Hz
1
10
μV/V
90
dB
dB
kΩ
1
-10
-75
-90
40
Vin=65Hz
FIR_LEN=0
1.7
Ω/°C
355
nV/LSB
LSB
+884736
Vin=200mV peak, 65Hz
V3P3A=3.0V, 3.6V
10 6 ∆Nout PK 357 nV / VIN
100 ∆V 3P3 A / 3.3
1
TYP
-250
10 6 *Vcrosstalk
cos(∠Vin − ∠Vcrosstalk ) Vcrosstalk = largest
Vin
measurement on IA, IB, or
THD (First 10 harmonics)
250mV- peak
20mV- peak
Input Impedance
Temperature coefficient of Input
Impedance
LSB size
Digital Full Scale
ADC Gain Error vs
%Power Supply Variation
MIN
Input Offset (Vin-V3P3A)
Guaranteed by design; not production tested.
-10
50
ppm/%
10
mV
OPTICAL INTERFACE
PARAMETER
OPT_TX VOH (V3P3D-OPT_TX)
OPT_TX VOL
OPT_RX Vin Threshold
(VinRISING+VinFALLING)/2
OPT_RX Vin Hysteresis
(VinRISING-VinFALLING)
OPT_RX input impedance
CONDITION
ISOURCE=1mA
ISINK=20mA
MIN
TYP
MAX
0.4
0.7
UNIT
V
V
200
250
300
mV
30
mV
5
|Vin|≤300mV
MΩ
1
TEMPERATURE SENSOR
PARAMETER
2
Nominal Sensitivity (Sn)
Nominal Offset (Nn) 2
Temperature Error
CONDITION
TA=25ºC, TA=75ºC
Nominal relationship:
N(T)= Sn*T+Nn
MIN
TA = -40ºC to +85ºC
-31
TYP
-900
40000
0
MAX
UNIT
LSB/ºC
LSB
1
ERR = (T − 25) −
( N (T ) − N (25))
Sn
1
31
ºC
Guaranteed by design; not production tested.
This parameter defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with
other specs that use this nominal relationship as a reference.
2
Page: 94 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
LCD BOOST
PARAMETER
VDRV Frequency
VDRV Sink Current
VDRV Source Current
VLCD Target Voltage
CONDITION
Vol=1.5V
Voh=1.5V
MIN
TYP
OSC/2
1.2
1.2
4.5
VLCD=5.0V,
LCD_FS=1F,
LCD_MODE=0,1,2,3
LCD_BSTEN=1
VLCD Input Current
MAX
2.75
2.6
5.5
UNIT
Hz
mA
mA
V
450
μA
MAX
0
0.2
UNIT
V
V
+10
+10
%
%
+15
+10
30
%
%
kΩ
LCD DRIVERS
Applies to all COM and SEG pins. Unless otherwise stated, VLCD=5.0V, LCD_FS=1F
PARAMETER
CONDITION
MIN
With respect to VLCD
-0.2
VLC0 Max Voltage (LCD_FS =1F)
With respect to VLCD*0.7
-0.2
VLC0 Min Voltage (LCD_FS =00)
VLC1 Voltage,
1/3 bias
With respect to 2*VLCD/3
-10
½ bias
With respect to VLCD/2
-10
VLC0 Voltage,
1/3 bias
With respect to VLCD/3
-15
½ bias
With respect to VLCD/2
-10
Output Impedance
∆ILOAD=10µA
TYP
RTC
PARAMETER
Range for date
CONDITION
MIN
2000
TYP
-
MAX
2255
UNIT
year
CONDITION
MIN
5
TYP
MAX
UNIT
µs
µs
RESETZ
PARAMETER
Reset pulse width
Reset pulse fall time
1
11
Guaranteed by design; not production tested.
© 2005-2011 Teridian Semiconductor Corporation
Page: 95 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
COMPARATORS
PARAMETER
Offset Voltage
V1-VBIAS
V2-VBIAS
V3-VBIAS
Hysteresis Current
V1
V2
V3
Response Time
V1
V2
V3
WD Disable Threshold (V1-V3P3A)
CONDITION
Vin = VBIAS - 100mV
MIN
TYP
MAX
UNIT
-20
-20
-20
15
15
15
mV
mV
mV
0.8
0.8
0.8
1.2
1.2
1.2
μA
μA
μA
2
0.5
0.5
-400
15
50
50
-10
μs
μs
μs
mV
MAX
UNIT
Cycles
Cycles
Cycles
Years
Years
2
Cycles
+100mV overdrive
RAM AND FLASH MEMORY
PARAMETER
CE RAM wait states
Flash write cycles
Flash data retention
Flash data retention
Flash byte writes between page or mass
erase operations
CONDITION
CKMPU = 4.9MHz
CKMPU = 1.25MHz
-40°C to +85°C
25°C
85°C
MIN
5
2
20,000
100
10
TYP
FLASH MEMORY TIMING
PARAMETER
Write Time per Byte
Page Erase (512 bytes)
Mass Erase
CONDITION
MIN
TYP
MAX
42
20
200
UNIT
µs
ms
ms
MIN
TYP
MAX
UNIT
EEPROM INTERFACE
PARAMETER
Write Clock frequency
Page: 96 of 104
CONDITION
CKMPU=4.9MHz, Using
interrupts
CKMPU=4.9MHz, “bitbanging” DIO4/5
© 2005-2011 Teridian Semiconductor Corporation
78
kHz
150
kHz
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
Recommended External Components
NAME
FROM
TO
C1
V3P3A
AGND
C2
V3P3D
XTAL
FUNCTION
VALUE
UNIT
Bypass capacitor for 3.3V supply
≥0.1±20%
µF
DGND
Bypass capacitor for 3.3V supply
≥0.1±20%
µF
XIN
XOUT
32.768kHz crystal. Electrically similar to ECS
ECX-3TA series
32.768
kHz
CXS
XIN
AGND
22±10%
pF
CXL
XOUT
AGND
Load capacitor for crystal (depends on crystal
specs and board parasitics).
22±10%
pF
CV1
V1
AGND
Bypass capacitor for V1
≥0.1±20%
µF
CBIAS
VBIAS
AGND
Bypass capacitor for VBIAS
≥1000±20%
pF
CBST 1
VDRV
external
33±20%
nF
CBST 2
VLCD
DGND
Boost bypass capacitor
≥0.22±20%
µF
C2P5
V2P5
DGND
Bypass capacitor for V2P5
≥0.1±20%
µF
RTST
TEST
DGND
Resistor for TEST
10kΩ±10%
µF
Boost charging capacitor
© 2005-2011 Teridian Semiconductor Corporation
Page: 97 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
Packaging Information
100-Pin LQFP PACKAGE OUTLINE (Bottom View)
15.7(0.618)
16.3(0.641)
1
15.7(0.618)
16.3(0.641)
Top View
13.8(0.543)
14.2(0.559)
0.05(0.002)
0.15(0.006)
1.40(0.055)
1.60(0.063)
0.60(0.024) TYP.
0.18(0.007)
0.27(0.011)
0.50(0.0197)TYP.
Side View
Notes: Controlling dimensions are in mm.
Page: 98 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
76
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TERIDIAN
71M6513-IGT/71M6513H-IGT
GNDD
RESETZ
V2P5
VBAT
RX
SEG31/DIO11
SEG30/DIO10
SEG29/DIO9
SEG28/DIO8
SEG41/DIO21
SEG40/DIO20
SEG39/DIO19
SEG27/DIO7
SEG26/DIO6
SEG25/DIO5
SEG24/DIO4
SEG23
SEG22
SEG21
SEG20
NC
SEG19
SEG18
SEG17
SEG16
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
26
27
28
29
30
31
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG0
SEG1
SEG2
E_ISYNC/BRKRQ
SEG34/DIO14
SEG35/DIO15
NC
NC
SEG36/DIO16
SEG6/SRDY
NC
SEG7/MUX_SYNC
SEG8
SEG9
GNDD
SEG10
NC
NC
NC
SEG11
SEG12
NC
SEG13
SEG14
SEG15
GNDD
E_RXTX
OPT_TX
TMUXOUT
TX
SEG3/SCLK
VDRV
CKTEST
V3P3D
SEG4/SSDATA
SEG5/SFR
E_TBUS[3]
E_TBUS[2]
E_TBUS[1]
E_TBUS[0]
SEG37/DIO17
SEG38/DIO18
DIO_0
DIO_1
DIO_2
DIO_3
COM0
COM1
COM2
COM3
100
99
98
97
96
95
94
E_TCLK
SEG33/DIO13
SEG32/DIO12
E_RST
VLCD
NC
XOUT
TEST
XIN
GNDA
NC
OPT_RX
V1
V2
V3
VREF
IA
IB
IC
VBIAS
VA
VB
VC
V3P3A
GNDA
Pinout (Top View)
© 2005-2011 Teridian Semiconductor Corporation
Page: 99 of 104
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Pin Descriptions
Power/Ground Pins
Name
Pin #
GNDA
76,91
Type
Description
P
Analog ground: This pin should be connected directly to the analog ground plane.
1, 40, 75
P
Digital ground: This pin should be connected directly to the digital ground plane.
77
P
Analog power supply: A 3.3V analog power supply should be connected to this pin.
9
P
Digital power supply: A 3.3V digital power supply should be connected to this pin.
VBAT
72
P
Battery backup power supply. A battery or super-capacitor is to be connected between
VBAT and GNDD. If no battery is used, connect VBAT to V3P3D.
V2P5
73
O
Output of the 2.5V regulator. A 0.1µF capacitor to GNDA should be connected to this pin.
VLCD
96
32,33,36,
42,43,44,
47,55,90,95
P
LCD power supply.
--
No Connect
GNDD
V3P3A
V3P3D
NC
Analog Pins
Name
IA
IB
IC
VA
VB
VC
Pin #
84
83
82
80
79
78
Type
Circuit
I
6
I
6
V1
V2
V3
88
87
86
I
7
VBIAS
81
O
9
VREF
85
I/O
9
XIN,
XOUT
92
94
I
8
VDRV
7
O
4
Description
Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the output of a current transformer. Unused
pins must be connected to V3P3A.
Line Voltage Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the output of a resistor divider. Unused pins
must be connected to V3P3A.
Comparator Inputs - voltage inputs to the internal comparator: The voltages applied
to these pins are compared to VBIAS. If the voltage is above VBIAS, the corresponding comparator output will be high (1). The outputs are maintained in the
COMP_STAT register. A typical application is to sense the voltage on the DC supply
using an external resistor divider to scale the power supply voltage to a level that
triggers the comparator at the desired voltage drop.
V1: This pin is part of the reset circuitry. It also controls the hardware watchdog
timer. A 0.1µF capacitor to GNDA should be connected to this pin.
V2: Comparator input. If unused, this pin must be connected to V3P3A or
ground.
V3: Comparator input, also available to the ADC during alternative multiplexer
cycles. If not used for measuring or sensing purposes, the V3 pin should either
be left unconnected or be connected to the VREF pin. See precautions on page
88.
Reference voltage used by the power fault detection circuit. A 1,000pF capacitor to
GND should be connected to this pin.
Voltage Reference for the ADC. A 0.1µF capacitor to GNDA should be connected to
this pin.
Crystal Inputs: A 32kHz style crystal should be connected across these pins.
Typically, a 22-27pF capacitor is also connected from each pin to GNDA. See crystal
manufacturer datasheet for details.
Voltage boost output.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output
The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.
Page: 100 of 104
© 2005-2011 Teridian Semiconductor Corporation
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
Digital Pins
Name
DIO_3,
DIO_2,
DIO_1,
DIO_0
COM3,
COM2,
COM1,
COM0
SEG0…SEG2,
SEG8…SEG23
SEG24/DIO4…
…….
SEG41/DIO21
Pin #
21
20
19
18
25
24
23
22
Type
Circuit
I/O
3, 4
O
5
LCD Common Outputs: These 4 pins provide the select signals for the
LCD display.
See
pinout
O
5
Dedicated LCD Segment Output.
See
pinout
I/O
3, 4, 5
SEG7/MUX_SYNC
37
O
4, 5
SEG6/SRDY
35
I/O
2, 5
SEG5/SFR
SEG4/SDATA
SEG3/SCLK
11
10
6
O
O
O
4, 5
4, 5
4, 5
RESETZ
74
I
1
RX
71
I
3
TX
5
O
4
OPT_RX
89
I
7
OPT_TX
3
O
4
CKTEST
TMUXOUT
8
4
O
O
4
4
2
12
13
14
15
29
100
97
93
I/O
1, 4
O
4
I/O
O
I/O
I
1, 4
4
1, 4
7
E_RXTX
E_TBUS[3]
E_TBUS[2]
E_TBUS[1]
E_TBUS[0]
E_ISYNC/BRKRQ
E_TCLK
E_RST
TEST
Description
Digital input/output pins 0 through 3. If unused, these DIO pins must be
configured as outputs or terminated to V3P3 or ground.
Multi-use pins, configurable as either LCD SEG driver or DIO (DIO4 =
SCK, DIO5 = SDA when configured as EEPROM I/F, WPULSE = DIO6,
VARPULSE = DIO7 when configured as pulse outputs). If unused, these
pins must be configured as outputs or terminated to V3P3/ground.
Multi-use-pin LCD Segment Output/ MUX_SYNC is output for Synchronous serial interface
Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous serial
interface. If unused, this pin must be terminated to ground.
Multi-use-pin, LCD Segment Output/ SFR output for SSI.
Multi-use-pin, LCD Segment Output/ SDATA output for SSI.
Multi-use-pin, LCD Segment Output/ SCLK output for SSI.
This pin is used to reset the chip into a known state. For normal operation,
this pin is set to 1. To reset the chip, this pin is driven to 0. This pin has an
internal 30μA (nominal) current source pull-up but no Schmitt-trigger
circuitry. The minimum width of the pulse is 5μs. A 0.1µF capacitor to
GNDA should be connected to this pin. Since the chip resets itself at
power-up, no other external reset circuitry is required.
UART input. The voltage applied at this input must be below 3.6V. If unused, the RX pin must be terminated to V3P3 or ground.
UART output.
Optical Receive Input: This pin receives a signal from an external photodetector used in an IR serial interface. If unused, the OPT_RX pin must
be terminated to V3P3 or ground.
Optical LED Transmit Output: This pin is designed to directly drive an LED
for transmitting data in an IR serial interface. Can be tristated with
OPT_TXDIS to be multiplexed with other DIO pins.
Clock PLL output. Can be enabled and disabled by CKOUT_EN.
Digital output test multiplexer. Controlled by TMUX[3:0].
Emulator serial data.
Emulator trace bus. These pins have internal pull-up resistors.
Emulator handshake. This pin has an internal pull-up resistor.
Emulator clock. This pin has an internal pull-up resistor.
Emulator reset. This pin has an internal pull-up resistor.
For Teridian internal use. Must be connected to GNDD via a 10kΩ resistor.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output
The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.
© 2005-2011 Teridian Semiconductor Corporation
Page: 101 of 104
71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
I/O Equivalent Circuits:
V3P3D
V3P3D
V3P3A
110K
Digital
Input
Pin
CMOS
Input
LCD SEG
Output
Pin
LCD
Driver
from
internal
reference
VREF
Pin
GNDD
GNDD
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
GNDA
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
VREF Equivalent Circuit
Type 9:
VREF
V3P3D
V3P3A
V3P3D
Digital
Input
Pin
CMOS
Input
110K
GNDD
Analog
Input
Pin
from
internal
reference
To
MUX
V2P5
Pin
GNDD
GNDD
GNDA
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
V2P5 Equivalent Circuit
Type 10:
V2P5
Analog Input Equivalent Circuit
Type 6:
ADC Input
V3P3D
V3P3A
Digital
Input
Pin
CMOS
Input
Comparator
Input
Pin
To
Comparator
VLCD
Pin
LCD
Drivers
GNDD
GNDA
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
GNDD
VLCD Equivalent Circuit
Type 11:
VLCD Power
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
V3P3D
V3P3D
V3P3D
Digital
Output
Pin
CMOS
Output
Oscillator
Pin
To
Oscillator
Power
Down
Circuits
VBAT
Pin
GNDD
GNDD
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
Page: 102 of 104
GNDD
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
© 2005-2011 Teridian Semiconductor Corporation
GNDD
VBAT Equivalent Circuit
Type 12:
VBAT Power
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
ORDERING INFORMATION
ORDERING
NUMBER
PACKAGE
MARKING
71M6513-IGT/F
71M6513-IGT
71M6513
100-pin lead-free LQFP, 0.5% accuracy, T&R
71M6513-IGTR/F
71M6513-IGT
71M6513H
100-pin lead-free LQFP, 0.1% accuracy
71M6513H-IGT/F
71M6513H-IGT
71M6513H-IGTR/F
71M6513H-IGT
PART DESCRIPTION
71M6513
100-pin lead-free LQFP, 0.5% accuracy
71M6513H
100-pin lead-free LQFP, 0.1% accuracy, T&R
Revision History
Revision
Date
Description
2.0
2.1
11/23/2005
11/30/2005
2.2
4/17/2006
2.3
3/14/2007
Initial release
Updated Electrical Specification (TC1/TC2, fuse descriptions)
Improved MPU register (SFR) description. Added information in Electrical
Specifications (ADC resolution 355nV/LSB with FIR_LEN=0, formula for
temperature coefficients, 38 kHz MPU clock, VREF aging information, current
consumption in low-power mode, removed note on ADC count [3.589,461 * 600 *
7.8E-9 = 169V]). Improved CE description (added X to pulse rate formula,
TEMP_NOM default value, APULSER and APULSEW update by MPU, relation
between ADC cycles and MUX_DIV. Added notes and clarifications on flash
write operations. Added information in Applications section on connection of V3,
crystal frequency variations and frequency measurement. Improved figures 4 and
5. Added caution notes for timing required for SW WDT and for conditions
blocking interrupt processing. Added note in pin descriptions on connection of V3.
Added I/O Equivalent Circuits and interrupt structure diagram. Added note in CE
Section stating that CE STATUS word must be read right after the CE_BUSY
interrupt. Deleted FLSH_TMR from list of pins in Logic Levels. Updated Table 51
(DIO pins) and Figure 11. Changed capacitor value for XIN/XOUT in Pin
Descriptions and in Recommended External Components. Added items in
Electrical Specification (temperature range for maximum write cycles, flash
retention time for +85°C, maximum number of writes in between flash erase
operations). Added note in Pin Descriptions on external reset circuitry. Added
cautionary notes for ECK_DIS and SECURE bits. Added requirements for termination
in pin tables for DIO_0-DIO_3, DIO/SEG, RX, OPT_RX pins. Added explanation
of SRDY polarity.
© 2005-2011 Teridian Semiconductor Corporation
Page: 103 of 104
A Maxim Integrated Products Brand
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Revision History (Continued)
Revision
Date
2.4
8/17/2007
2.5
8/12/2008
2.6
12/10
Description
Removed all references to ROM versions. Removed reference to 3rd UART in
“Hardware Overview” using bit-bang technique. Added note stating that “bitbanging” of DIO4/5 is discouraged. Added “A 1,000pF capacitor to GND should
be connected to this pin” for VBIAS in Analog Pin Descriptions. Added precaution
regarding I/O RAM locations affected by flash write under “Flash Memory”. Added
remark in “MPU/CE Communication” on inaccuracy of accumulation interval as
compared to RTC. Modified CE Interface description. Changed in Electrical Specifications: TC1 to +7.0 (VREF section), recommended capacitor values for
XIN/XOUT and crystal type. Corrected diagram for Rogowski coil (Figure 30).
Fixed Table 56.
Updated package information from IEL (exposed pad LQFP) to IGT/F package
type (title page, package drawing, and ordering information). Updated Teridian
street address information. Updated explanation for V3SQSUM register in CE
Interface Description.
Added revision history table to replace separate revision notes.
Changed information on Wh accuracy on title page. Added section on delay
compensation in CE Description. Corrected UART description in MPU section.
Added cautionary note in CE Program and Environment section stating that
operating CE code with environmental settings other than those specified in the
data sheet will lead to unpredictable results. Deleted graphs showing typical
performance over temperature. Added crystal oscillator information in Application
Information section. Added note in Applications section stating that high source
impedance sensor circuits should be avoided.
Clarified “guaranteed by design” and “tested in production” information in
Electrical Specifications section.
Changed font for all SFR and I/O RAM register variables to Times New Roman
Italic.
Corrected various typos.
3
Page: 104 of 104
9/11
Added the following:
- Changed “50ppm/°C” to “40ppm/°C” (page 1).
- Explanation of scaling factors applied to PPMC and PPMC2 (page 73).
- Explanation of error bands for temperature compensation (page 82).
- Precautionary notes regarding the voltage range of the V3 pin (page 88).
- Precautionary notes for connecting a battery (page 88).
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