71M6543F/71M6543G
Energy Meter ICs
GENERAL DESCRIPTION
FEATURES
The 71M6543F/71M6543G are 4th-generation polyphase metering
systems-on-chips (SoCs) with a 5MHz 8051-compatible MPU core,
low-power real-time clock (RTC) with digital temperature
compensation, flash memory, and LCD driver. Our Single
Converter Technology® with a 22-bit delta-sigma ADC, seven
analog inputs, digital metrology temperature compensation,
precision voltage reference, and a 32-bit computation engine (CE)
supports a wide range of metering applications with very few
external components.
• 0.1% Typical Accuracy Over 2000:1 Current
Range
• Exceeds IEC 62053/ANSI C12.20 Standards
• Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
• Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
• High-Speed Wh/VARh Pulse Outputs with
Programmable Width
• 64KB Flash, 5KB RAM (71M6543F)
• 128KB Flash, 5KB RAM (71M6543G)
• Up to Four Pulse Outputs with Pulse Count
• Four-Quadrant Metering, Phase Sequencing
• Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
• Independent 32-Bit Compute Engine
• 46-64Hz Line Frequency Range with the Same
Calibration
• Phase Compensation (±7°)
• Three Battery-Backup Modes:
Brownout Mode
LCD Mode
Sleep Mode
• Wake-Up on Pin Events and Wake-on-Timer
• 1µA in Sleep Mode
• Flash Security
• In-System Program Update
• 8-Bit MPU (80515), Up to 5MIPS
• Full-Speed MPU Clock in Brownout Mode
• LCD Driver:
6 Common Segment Drivers
Up to 56 Selectable Pins
• Up to 51 Multifunction DIO Pins
• Hardware Watchdog Timer (WDT)
• I2C/MICROWIRE® EEPROM Interface
• SPI Interface with Flash Program Capability
• Two UARTs for IR and AMR
• IR LED Driver with Modulation
• Industrial Temperature Range
• 100-Pin Lead-Free LQFP Package
The 71M6543F/71M6543G support optional interfaces to the
71M6xx3 series of isolated sensors that offer BOM cost reduction,
immunity to magnetic tamper, and enhanced reliability. The ICs
feature ultra-low-power operation in active and battery modes, 5KB
shared RAM, and 64KB (71M6543F) or 128KB (71M6543G) of
flash memory, which can be programmed with code and/or data
during meter operation.
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
C
Shunt Current Sensors
LOAD
NEUTRAL
B
A
POWER SUPPLY
Resistor Dividers
71M6xx3
71M6xx3
71M6xx3
NEUTRAL
Pulse Transformers
Note: This system is referenced to Neutral
3x 71M6xx3
MUX and ADC
IADC0
IADC1 }IN*
VADC10 (VC)
IADC6
IADC7 }IC
VADC9 (VB)
IADC4
IADC5 }IB
VADC8 (VA)
IADC2
IADC3 }IA
AMR
IR
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
71M6543F/
71M6543G
TEMPERATURE
SENSOR
VREF
RAM
COMPUTE
ENGINE
RX
MODUL- RX
ATOR
TX
FLASH
MEMORY
POWER FAULT
COMPARATOR
HOST
SPI INTERFACE
*IN = Neutral Current
MPU
RTC
TIMERS
ICE
BATTERY
VBAT
VBAT_RTC
SERIAL PORTS
TX
WAKE-UP
REGULATOR
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
XOUT
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
9/17/2010
Single Converter Technology is a registered trademark of Maxim Integrated
Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-5375; Rev 2; 10/13
71M6543F/71M6543G Data Sheet
Table of Contents
1
2
3
2
Introduction ....................................................................................................................................... 10
Hardware Description ....................................................................................................................... 11
2.1 Hardware Overview ................................................................................................................... 11
2.2 Analog Front-End (AFE) ............................................................................................................ 12
2.2.1 Signal Input Pins ............................................................................................................ 13
2.2.2 Input Multiplexer............................................................................................................. 14
2.2.3 Delay Compensation ..................................................................................................... 19
2.2.4 ADC Pre-Amplifier ......................................................................................................... 20
2.2.5 A/D Converter (ADC) ..................................................................................................... 20
2.2.6 FIR Filter ........................................................................................................................ 20
2.2.7 Voltage References ....................................................................................................... 20
2.2.8 71M6xx3 Isolated Sensor Interface ............................................................................... 22
2.3 Digital Computation Engine (CE) ............................................................................................... 25
2.3.1 CE Program Memory ..................................................................................................... 25
2.3.2 CE Data Memory ........................................................................................................... 25
2.3.3 CE Communication with the MPU ................................................................................. 25
2.3.4 Meter Equations ............................................................................................................. 26
2.3.5 Real-Time Monitor (RTM) .............................................................................................. 26
2.3.6 Pulse Generators ........................................................................................................... 26
2.3.7 CE Functional Overview ................................................................................................ 28
2.4 80515 MPU Core ....................................................................................................................... 30
2.4.1 Memory Organization and Addressing .......................................................................... 30
2.4.2 Special Function Registers (SFRs)................................................................................ 32
2.4.3 Generic 80515 Special Function Registers ................................................................... 33
2.4.4 Instruction Set ................................................................................................................ 35
2.4.5 UARTs ........................................................................................................................... 35
2.4.6 Timers and Counters ..................................................................................................... 38
2.4.7 WD Timer (Software Watchdog Timer) ......................................................................... 39
2.4.8 Interrupts ........................................................................................................................ 39
2.5 On-Chip Resources ................................................................................................................... 46
2.5.1 Physical Memory............................................................................................................ 46
2.5.2 Oscillator ........................................................................................................................ 48
2.5.3 PLL and Internal Clocks................................................................................................. 49
2.5.4 Real-Time Clock (RTC) ................................................................................................. 49
2.5.5 71M6543 Temperature Sensor ...................................................................................... 53
2.5.6 71M6xx3 Temperature Sensor ...................................................................................... 56
2.5.7 71M6543 Battery Monitor .............................................................................................. 56
2.5.8 71M6xx3 VCC Monitor ................................................................................................... 56
2.5.9 UART and Optical Interface ........................................................................................... 56
2.5.10 Digital I/O and LCD Segment Drivers ............................................................................ 57
2.5.11 EEPROM Interface ........................................................................................................ 65
2.5.12 SPI Slave Port................................................................................................................ 67
2.5.13 Hardware Watchdog Timer ............................................................................................ 71
2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins) ............................................................. 72
Functional Description ..................................................................................................................... 74
3.1 Theory of Operation ................................................................................................................... 74
3.2 Battery Modes ............................................................................................................................ 74
3.2.1 BRN Mode ..................................................................................................................... 77
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71M6543F/71M6543G Data Sheet
4
5
v2
3.2.2 LCD Mode ...................................................................................................................... 77
3.2.3 SLP Mode ...................................................................................................................... 78
3.3 Fault and Reset Behavior .......................................................................................................... 79
3.3.1 Events at Power-Down .................................................................................................. 79
3.3.2 IC Behavior at Low Battery Voltage ............................................................................... 80
3.3.3 Reset Sequence ............................................................................................................ 80
3.3.4 Watchdog Timer (WDT) Reset ...................................................................................... 80
3.4 Wake-Up Behavior ..................................................................................................................... 81
3.4.1 Wake on Hardware Events ............................................................................................ 81
3.4.2 Wake on Timer............................................................................................................... 83
3.5 Data Flow and MPU/CE Communication ................................................................................... 83
Application Information .................................................................................................................... 85
4.1 Connecting 5 V Devices............................................................................................................. 85
4.2 Directly Connected Sensors ...................................................................................................... 85
4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts ............................................... 86
4.4 System Using Current Transformers ......................................................................................... 87
4.5 Metrology Temperature Compensation ..................................................................................... 88
4.5.1 Temperature Compensation .......................................................................................... 88
4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G ....................................... 88
4.5.3 Temperature Coefficients for the 71M6xx3 ................................................................... 89
4.5.4 Temperature Compensation for VREF and Shunt Sensors .......................................... 89
4.5.5 Temperature Compensation of VREF and Current Transformers................................. 90
2
4.6 Connecting I C EEPROMs ........................................................................................................ 92
4.7 Connecting Three-Wire EEPROMs ........................................................................................... 92
4.8 UART0 (TX/RX) ......................................................................................................................... 92
4.9 Optical Interface (UART1).......................................................................................................... 93
4.10 Connecting the Reset Pin .......................................................................................................... 93
4.11 Connecting the Emulator Port Pins ............................................................................................ 94
4.12 Flash Programming.................................................................................................................... 94
4.12.1 Flash Programming via the ICE Port ............................................................................. 94
4.12.2 Flash Programming via the SPI Port ............................................................................. 94
4.13 MPU Demonstration Code ......................................................................................................... 94
4.14 Crystal Oscillator ........................................................................................................................ 95
4.15 Meter Calibration ........................................................................................................................ 95
Firmware Interface ............................................................................................................................ 96
5.1 I/O RAM Map –Functional Order ............................................................................................... 96
5.2 I/O RAM Map – Alphabetical Order ......................................................................................... 102
5.3 CE Interface Description .......................................................................................................... 116
5.3.1 CE Program ................................................................................................................. 116
5.3.2 CE Data Format ........................................................................................................... 116
5.3.3 Constants ..................................................................................................................... 116
5.3.4 Environment ................................................................................................................. 117
5.3.5 CE Calculations ........................................................................................................... 117
5.3.6 CE Front-End Data (Raw Data) ................................................................................... 118
5.3.7 CE Status and Control ................................................................................................. 119
5.3.8 CE Transfer Variables ................................................................................................. 121
5.3.9 Pulse Generation ......................................................................................................... 123
5.3.10 CE Calibration Parameters .......................................................................................... 127
5.3.11 CE Flow Diagrams ....................................................................................................... 128
3
71M6543F/71M6543G Data Sheet
6
71M6543 Specifications.................................................................................................................. 130
6.1 Absolute Maximum Ratings ..................................................................................................... 130
6.2 Recommended External Components ..................................................................................... 131
6.3 Recommended Operating Conditions ...................................................................................... 131
6.4 Performance Specifications ..................................................................................................... 132
6.4.1 Input Logic Levels ........................................................................................................ 132
6.4.2 Output Logic Levels ..................................................................................................... 132
6.4.3 Battery Monitor............................................................................................................. 133
6.4.4 Temperature Monitor ................................................................................................... 134
6.4.5 Supply Current ............................................................................................................. 135
6.4.6 V3P3D Switch .............................................................................................................. 136
6.4.7 Internal Power Fault Comparators ............................................................................... 136
6.4.8 2.5 V Voltage Regulator – System Power ................................................................... 136
6.4.9 2.5 V Voltage Regulator – Battery Power .................................................................... 137
6.4.10 Crystal Oscillator .......................................................................................................... 137
6.4.11 Phase-Locked Loop (PLL) ........................................................................................... 137
6.4.12 LCD Drivers ................................................................................................................. 137
6.4.13 VLCD Generator .......................................................................................................... 138
6.4.14 71M6543 VREF ........................................................................................................... 140
6.4.15 ADC Converter............................................................................................................. 141
6.4.16 Pre-Amplifier for IADC0-IADC1 ................................................................................... 142
6.5 Timing Specifications ............................................................................................................... 143
6.5.1 Flash Memory .............................................................................................................. 143
6.5.2 SPI Slave ..................................................................................................................... 143
6.5.3 EEPROM Interface ...................................................................................................... 143
6.5.4 RESET Pin ................................................................................................................... 144
6.5.5 Real-Time Clock (RTC) ............................................................................................... 144
6.6 100-Pin LQFP Package Outline Drawing ................................................................................ 145
6.7 71M6543 Pinout ....................................................................................................................... 146
6.8 71M6543 Pin Descriptions ....................................................................................................... 147
6.8.1 71M6543 Power and Ground Pins .............................................................................. 147
6.8.2 71M6543 Analog Pins .................................................................................................. 148
6.8.3 71M6543 Digital Pins ................................................................................................... 149
6.8.4 I/O Equivalent Circuits ................................................................................................. 151
7
Ordering Information ...................................................................................................................... 152
7.1 71M6543 Ordering Guide ........................................................................................................ 152
8
Related Information ..................................................................................................................... 152
9
Contact Information ..................................................................................................................... 152
Appendix A: Acronyms .......................................................................................................................... 153
Appendix B: Revision History................................................................................................................ 154
4
v2
71M6543F/71M6543G Data Sheet
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 9
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ......................................................... 12
Figure 3. AFE Block Diagram (Four CTs) ................................................................................................... 13
Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) ..................................................................... 17
Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) ..................................................................... 17
Figure 6: General Topology of a Chopped Amplifier .................................................................................. 21
Figure 7: CROSS Signal with CHOP_E = 00 ............................................................................................... 21
Figure 8: RTM Timing ................................................................................................................................. 26
Figure 9. Pulse Generator FIFO Timing...................................................................................................... 28
Figure 10: Samples from Multiplexer Cycle (Frame) .................................................................................. 29
Figure 11: Accumulation Interval ................................................................................................................ 29
Figure 12: Interrupt Structure ...................................................................................................................... 45
Figure 13: Automatic Temperature Compensation ..................................................................................... 52
Figure 14: Optical Interface ......................................................................................................................... 57
Figure 15: Optical Interface (UART1) ......................................................................................................... 57
Figure 16: Connecting an External Load to DIO Pins ................................................................................. 59
Figure 17: LCD Waveforms......................................................................................................................... 64
Figure 18: 3-wire Interface. Write Command, HiZ=0. ................................................................................ 66
Figure 19: 3-wire Interface. Write Command, HiZ=1 ................................................................................. 67
Figure 20: 3-wire Interface. Read Command. ............................................................................................ 67
Figure 21: 3-Wire Interface. Write Command when CNT=0 ...................................................................... 67
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................... 67
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations ................................................ 69
Figure 24: Voltage, Current, Momentary and Accumulated Energy ........................................................... 74
Figure 25: Operation Modes State Diagram ............................................................................................... 75
Figure 26: MPU/CE Data Flow .................................................................................................................... 84
Figure 27: Resistive Voltage Divider (Voltage Sensing) ............................................................................. 85
Figure 28. CT with Single-Ended Input Connection (Current Sensing) ...................................................... 85
Figure 29: CT with Differential Input Connection (Current Sensing) .......................................................... 85
Figure 30: Differential Resistive Shunt Connections (Current Sensing) ..................................................... 85
Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor .............................................. 86
Figure 32. System Using Current Transformers ......................................................................................... 87
2
Figure 33: I C EEPROM Connection .......................................................................................................... 92
Figure 34: Connections for UART0 ............................................................................................................. 92
Figure 35: Connection for Optical Components .......................................................................................... 93
Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ........ 94
Figure 37: External Components for the Emulator Interface ...................................................................... 94
Figure 38: CE Data Flow: Multiplexer and ADC........................................................................................ 128
Figure 39: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase ......................... 128
Figure 40: CE Data Flow: Squaring and Summation Stages .................................................................... 129
Figure 41: 100-pin LQFP Package Outline ............................................................................................... 145
Figure 42: Pinout for the LQFP-100 Package ........................................................................................... 146
Figure 43: I/O Equivalent Circuits ............................................................................................................. 151
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5
71M6543F/71M6543G Data Sheet
Tables
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ............................................................ 15
Table 2. Required CE Code and Settings for CT Sensors ......................................................................... 16
Table 3: Multiplexer and ADC Configuration Bits........................................................................................ 19
Table 4. RCMD[4:0] Bits ............................................................................................................................. 23
Table 5: Remote Interface Read Commands ............................................................................................. 23
Table 6: I/O RAM Control Bits for Isolated Sensor ..................................................................................... 24
Table 7: Inputs Selected in Multiplexer Cycles ........................................................................................... 26
Table 8: CKMPU Clock Frequencies .......................................................................................................... 30
Table 9: Memory Map ................................................................................................................................. 31
Table 10: Internal Data Memory Map ......................................................................................................... 32
Table 11: Special Function Register Map ................................................................................................... 32
Table 12: Generic 80515 SFRs - Location and Reset Values .................................................................... 33
Table 13: PSW Bit Functions (SFR 0xD0) ................................................................................................... 34
Table 14: Port Registers (SEGDIO0-15) ..................................................................................................... 35
Table 15: Stretch Memory Cycle Width ...................................................................................................... 35
Table 16: Baud Rate Generation ................................................................................................................ 36
Table 17: UART Modes ............................................................................................................................... 36
Table 18: The S0CON (UART0) Register (SFR 0x98) ................................................................................. 37
Table 19: The S1CON (UART1) Register (SFR 0x9B) ................................................................................ 37
Table 20: PCON Register Bit Description (SFR 0x87) ................................................................................. 38
Table 21: Timers/Counters Mode Description ............................................................................................ 38
Table 22: Allowed Timer/Counter Mode Combinations .............................................................................. 38
Table 23: TMOD Register Bit Description (SFR 0x89) ................................................................................ 39
Table 24: The TCON Register Bit Functions (SFR 0x88) ............................................................................ 39
Table 25: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 40
Table 26: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 40
Table 27: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 41
Table 28: TCON Bit Functions (SFR 0x88) ................................................................................................. 41
Table 29: The T2CON Bit Functions (SFR 0xC8) ........................................................................................ 41
Table 30: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 41
Table 31: External MPU Interrupts .............................................................................................................. 42
Table 32: Interrupt Enable and Flag Bits .................................................................................................... 42
Table 33: Interrupt Priority Level Groups .................................................................................................... 43
Table 34: Interrupt Priority Levels ............................................................................................................... 43
Table 35: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 43
Table 36: Interrupt Polling Sequence .......................................................................................................... 44
Table 37: Interrupt Vectors.......................................................................................................................... 44
Table 38: Flash Memory Access ................................................................................................................. 46
Table 39: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G ....................................... 47
Table 40: Flash Security ............................................................................................................................. 48
Table 41: Clock System Summary.............................................................................................................. 49
Table 42: RTC Control Registers ................................................................................................................ 50
Table 43: I/O RAM Registers for RTC Temperature Compensation .......................................................... 52
Table 44: I/O RAM Registers for RTC Interrupts ........................................................................................ 53
Table 45: I/O RAM Registers for Temperature and Battery Measurement ................................................ 55
Table 46: Selectable Resources using the DIO_Rn[2:0] Bits ..................................................................... 58
Table 47: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15 ......................... 60
Table 48: Data/Direction Registers for SEGDIO16 to SEGDIO31.............................................................. 60
6
v2
71M6543F/71M6543G Data Sheet
Table 49: Data/Direction Registers for SEGDIO32 to SEGDIO45.............................................................. 60
Table 50: Data/Direction Registers for SEGDIO51 to SEGDIO55.............................................................. 61
Table 51: LCD_VMODE Configurations ...................................................................................................... 61
Table 52: LCD Configurations ..................................................................................................................... 63
Table 53: LCD Data Registers for SEGDIO46 to SEGDIO55..................................................................... 64
Table 54: EECTRL Bits for 2-pin Interface ................................................................................................... 65
Table 55: EECTRL Bits for the 3-wire Interface ........................................................................................... 66
Table 56: SPI Transaction Fields ................................................................................................................ 68
Table 57: SPI Command Sequences .......................................................................................................... 69
Table 58: SPI Registers .............................................................................................................................. 69
Table 59: TMUX[4:0] Selections ................................................................................................................. 72
Table 60: TMUX2[4:0] Selections ............................................................................................................... 73
Table 61: Available Circuit Functions .......................................................................................................... 76
Table 62: VSTAT[2:0] (SFR 0xF9[2:0]) ........................................................................................................ 79
Table 63: Wake Enable and Flag Bits ......................................................................................................... 81
Table 64: Wake Bits .................................................................................................................................... 82
Table 65: Clear Events for WAKE flags ...................................................................................................... 83
Table 66: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1) ........................................ 90
Table 67: GAIN_ADJx Compensation Channels (Figure 3, Figure 32, Table 2) ........................................ 91
Table 68: I/O RAM Map – Functional Order, Basic Configuration .............................................................. 96
Table 69: I/O RAM Map – Functional Order ............................................................................................... 98
Table 70: I/O RAM Map – Alphabetical Order .......................................................................................... 102
Table 71: CE EQU[2:0] Equations and Element Input Mapping ............................................................... 117
Table 72: CE Raw Data Access Locations ............................................................................................... 118
Table 73: CESTATUS Register ................................................................................................................... 119
Table 74: CESTATUS Bit Definitions .......................................................................................................... 119
Table 75: CECONFIG Register .................................................................................................................. 119
Table 76: CECONFIG Bit Definitions (CE RAM 0x20) ............................................................................... 120
Table 77: Sag Threshold, Phase Measurement, and Gain Adjust Control ............................................... 121
Table 78: CE Transfer Variables (with Shunts)......................................................................................... 121
Table 79: CE Transfer Variables (with CTs) ............................................................................................. 122
Table 80: CE Energy Measurement Variables (with Shunts) ................................................................... 122
Table 81: CE Energy Measurement Variables (with CTs) ........................................................................ 122
Table 82: Other Transfer Variables ........................................................................................................... 123
Table 83: CE Pulse Generation Parameters............................................................................................. 125
Table 84: CE Parameters for Noise Suppression and Code Version ....................................................... 126
Table 85: CE Calibration Parameters ....................................................................................................... 127
Table 86: Absolute Maximum Ratings ...................................................................................................... 130
Table 87: Recommended External Components ...................................................................................... 131
Table 88: Recommended Operating Conditions ....................................................................................... 131
Table 89: Input Logic Levels ..................................................................................................................... 132
Table 90: Output Logic Levels .................................................................................................................. 132
Table 91: Battery Monitor Performance Specifications (TEMP_BAT = 1) ................................................. 133
Table 92: Temperature Monitor ................................................................................................................ 134
Table 93: Supply Current Performance Specifications ............................................................................. 135
Table 94: V3P3D Switch Performance Specifications .............................................................................. 136
Table 95: Internal Power Fault Comparators Performance Specifications ............................................... 136
Table 96: 2.5 V Voltage Regulator Performance Specifications ............................................................... 136
Table 97: Low-Power Voltage Regulator Performance Specifications ..................................................... 137
Table 98: Crystal Oscillator Performance Specifications .......................................................................... 137
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7
71M6543F/71M6543G Data Sheet
Table 99: PLL Performance Specifications ............................................................................................... 137
Table 100: LCD Drivers Performance Specifications ............................................................................... 137
Table 101: VLCD Generator Specifications .............................................................................................. 138
Table 102: 71M6543 VREF Performance Specifications ......................................................................... 140
Table 103: ADC Converter Performance Specifications ........................................................................... 141
Table 104: Pre-Amplifier Performance Specifications .............................................................................. 142
Table 105: Flash Memory Timing Specifications ...................................................................................... 143
Table 106. SPI Slave Timing Specifications ............................................................................................. 143
Table 107: EEPROM Interface Timing ...................................................................................................... 143
Table 108: RESET Pin Timing .................................................................................................................. 144
Table 109: RTC Range for Date ............................................................................................................... 144
Table 110: 71M6543 Power and Ground Pins .......................................................................................... 147
Table 111: 71M6543 Analog Pins ............................................................................................................. 148
Table 112: 71M6543 Digital Pins .............................................................................................................. 149
Table 113. 71M6543 Ordering Guide ....................................................................................................... 152
8
v2
71M6543F/71M6543G Data Sheet
VREF
IADC0
IADC1
IADC2
IADC3
IADC4
IADC5
IADC6
IADC7
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
V3P3A
GNDA GNDD
VLCD V3P3SYS
∆Σ_
AD CONVERTER
VBIAS
MUX
and
PREAMP
VBIAS
V3P3A
VLCD
Voltage
Boost
FIR
-
V3P3D
+
VREF
VREF
MUX
MUX CTRL
VBAT
CROSS
Voltage
Regulator
CK32
XIN
XOUT
MCK
PLL
RTCLK (32KHz)
Oscillator
CK32
32KHz
32 KHz
DIV
ADC
4.9 MHZ
CKADC
4.9 MHz
22
CK_4X
CLOCK GEN
2.5V to logic
MUX
CKMPU_2x
WPULSE
STRT
LCD_GEN
VLC2
VLC1
VLC0
MEMORY SHARE
MPU RAM
(5 KB)
CE
MUX_SYNC
VARPULSE
CKCE
< 4.9MHz
TEST
VDD
CKFIR
32-bit Compute
Engine
TEST
MODE
LCD DRIVER
RTM
CEDATA
32 0x000...0x2FF
CE CONTROL
COM0..5
6
IP
S
0x0000...0x13FF
SEG Pins
8
PROG
0x000...0x3FF
MPU
(80515)
UART0
2
M
A
R
O
I/
EEPROM
INTERFACE
CKMPU
< 4.9MHz
RX
WPULSE
VARPULSE
Y
S
U
B
R
E
F
X
Y
S
U
B
_
E
C
PB
OPT_TX/
SEGDIO51/
WPULSE/
VPULSE
OPTICAL
INTERFACE
RTCLK
SDCK
SDOUT
Non-Volatile
CONFIGURATION
RAM
SDIN
CONFIGURATION
RAM
(I/O RAM)
DATA
0x0000...0xFFFF
8
PROGRAM
0x0000...0xFFFF
VBIAS
CKMPU_2x
MEMORY
SHARE
8
17
CONFIGURATION
PARAMETERS
EMULATOR
PORT
RTM
3
VSTAT
RESET
TEMP
SENSOR
0x00000
…
FLASH 128KB
0X1FFFF
WAKE
FAULTZ
BAT
TEST
0x2000...0x20FF
8
MPU_RSTZ
POWER FAULT
DETECTION
VBAT_RTC
RTC
TX
OPT_RX/
SEGDIO55
SEGDIO Pins
DIGITAL I/O
16
TEST MUX TEST MUX
2
E_RXTX
E_TCLK
E_RST(Open Drain)
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
ICE_E
9/20/2010
Figure 1: IC Functional Block Diagram
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9
71M6543F/71M6543G Data Sheet
1
Introduction
This data sheet covers the 71M6543F (64KB) and 71M6543G (128KB) 4th-generation polyphase energy
measurement system-on-chips (SoCs). The term “71M6543” is used when discussing a device feature or
behavior that is applicable to all four part numbers. The specific part numbers are used when discussing
those features that apply only to specific part numbers. This data sheet also covers details about the
companion 71M6xx3 isolated current sensor device.
This document covers the use of the 71M6543 in conjunction with the 71M6xx3 isolated current sensor.
The 71M6543 and 71M6xx3 ICs make it possible to use one non-isolated and three additional isolated
shunt current sensors to create polyphase energy meters using inexpensive shunt resistors, while
achieving unprecedented performance with this type of sensor technology. The 71M6543 SoCs also
support Current Transformers (CT).
To facilitate document navigation, hyperlinks are often used to reference figures, tables and section
headings that are located in other parts of the document. All hyperlinks in this document are highlighted in
blue. Hyperlinks are used extensively to increase the level of detail and clarity provided within each
section by referencing other relevant parts of the document. To further facilitate document navigation, this
document is published as a PDF document with bookmarks enabled.
The reader is also encouraged to obtain and review the documents listed in 8 Related Information on
page 152 of this document.
10
v2
71M6543F/71M6543G Data Sheet
2
Hardware Description
2.1
Hardware Overview
The 71M6543 single-chip energy meter integrates all primary functional blocks required to implement a
solid-state electricity meter. Included on the chip are:
•
•
•
•
•
•
•
•
•
•
•
•
•
An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC
An independent 32-bit digital computation engine (CE) to implement DSP functions
An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515)
A precision voltage reference (VREF)
A temperature sensor for digital temperature compensation of:
- Metrology (MPU)
- Automatic RTC in all power states
- MPU assisted RTC compensation
LCD Driver
RAM and Flash memory
A real time clock (RTC)
A variety of I/O pins
A power failure interrupt
A zero-crossing interrupt
Selectable current sensor interfaces for locally-connected sensors as well as isolated sensors (i.e.,
using the 71M6xx3 companion IC with a shunt resistor sensor)
Resistive Shunt and Current Transformers are supported
In order to implement a polyphase meter with or without neutral current sensing, one resistive shunt
current sensor may be connected directly (non-isolated) to the 71M6543 device, while up to three
additional current shunts are isolated using a companion 71M6xx3 isolated sensor IC. An inexpensive,
small size pulse transformer is used to electrically isolate the 71M6xx3 remote sensor from the 71M6543.
The 71M6543 performs digital communications bi-directionally with the 71M6xx3 and also provides power
to the 71M6xx3 through the isolating pulse transformer. Isolated (remote) shunt current sensors are
connected to the differential input of the 71M6xx3. The 71M6543 may also be used with Current
Transformers; in this case the 71M6xx3 isolated sensors are not required. Included on the 71M6xx3
companion isolator chip are:
•
•
•
•
•
•
•
Digital isolation communications interface
An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC
A precision voltage reference (VREF)
A temperature sensor (for current-sensing digital temperature compensation)
A fully differential shunt resistor sensor input
A pre-amplifier to optimize shunt current sensor performance
Isolated power circuitry obtains dc power from pulses sent by the 71M6543
In a typical application, the 32-bit compute engine (CE) of the 71M6543 sequentially processes the
samples from the voltage inputs on analog input pins and performs calculations to measure active energy
2
2
(Wh) and reactive energy (VARh), as well as A h, and V h for four-quadrant metering. These measurements
are then accessed by the MPU, processed further and output using the peripheral devices available to the
MPU.
In addition to advanced measurement functions, the real time clock (RTC) function allows the 71M6543 to
record time of use (TOU) metering information for multi-rate applications and to time-stamp tamper or other
events. An automatic RTC temperature compensation circuit operates in all power states including when the
MPU is halted, and continues to compensate using back-up battery power during power outages.
Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments. The
integrated charge pump and temperature sensor can be used by the MPU to enhance 3.3 V LCD
performance at cold temperatures. The on-chip charge pump may also drive 5 V LCDs. Flexible mapping of
LCD display segments facilitates the integration of existing custom LCDs. Design trade-off between the
v2
11
71M6543F/71M6543G Data Sheet
number of LCD segments and DIO pins can be implemented in software to accommodate various
requirements.
In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temperature effects on metrology and RTC accuracy (i.e., to meet the requirements of ANSI and IEC
standards). Temperature-dependent external components such as the crystal oscillator, current
transformers (CTs), Current Shunts and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy
over the industrial temperature range.
One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense
configuration and can also function as a standard UART. The optical output can be modulated at 38 kHz.
This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC
is shown in Figure 1.
2.2
Analog Front-End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. The 71M6543 AFE may also be
augmented by isolated 71M6xx3 sensors in order to support low-cost current shunt sensors. Figure 2,
and Figure 3 show the two most common configurations; other configurations are possible. Sensors that
are connected directly to the 71M6543 (i.e., IADC0-IADC1, VADC8, VADC9 and VADC10) are
multiplexed into the single second-order sigma-delta ADC input for sampling in the 71M6543. The
71M6543 ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and
processed by the CE.
Shunt current sensors that are isolated by using a 71M6xx3 device, are sampled by a second-order
sigma delta ADC in the 71M6xx3 and the signal samples are transferred over the digital isolation interface
through the low-cost isolation pulse transformer.
Figure 2 shows the 71M6543 using shunt current sensors and the 71M6xx3 isolated sensor devices.
Figure 2 supports neutral current measurement with a local shunt connected to the IADC0-IADC1 input
plus three remote (isolated) shunt sensors. As seen in Figure 2, when a remote isolated shunt sensor is
connected via the 71M6xx3, the samples associated with this current channel are not routed to the
multiplexer, and are instead transferred digitally to the 71M6543 via the isolation interface and are directly
stored in CE RAM. The MUX_SELn[3:0] I/O RAM control fields allow the MPU to configure the AFE for the
desired multiplexer sampling sequence. Refer to Table 1 and Table 2 for the appropriate CE code and the
corresponding AFE settings.
See Figure 31 for the meter wiring configuration corresponding to Figure 2.
VREF
IN*
IADC0
Local
Shunt
MUX
VREF
IADC1
∆Σ ADC
CONVERTER
VREF
FIR
VADC
VADC8 (VA)
22
VADC9 (VB)
VADC10 (VC)
IA
INP
Remote
Shunt
71M6xx3
SP
IADC2
SN
IADC3
22
INN
CE RAM
IB
INP
Remote
Shunt
71M6xx3
SP
IADC4
SN
IADC5
SP
IADC6
SN
IADC7
INN
Digital
Isolation
Interface
22
IC
INP
Remote
Shunt
71M6xx3
22
INN
*IN = Neutral Current
71M6543
9/17/2010
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes)
12
v2
71M6543F/71M6543G Data Sheet
The 71M6543 AFE can also be directly interfaced to Current Transformers (CTs), as seen in Figure 3. In
this case, all voltage and current channels are multiplexed into a single second-order sigma-delta ADC in
the 71M6543 and the 71M6xx3 remote isolated sensors are not used. The fourth CT and the
measurement of Neutral current via the IADC0-IADC1 current channel are optional.
See Figure 32 for the meter wiring configuration corresponding to Figure 3.
VREF
IA
IADC2
MUX
CT
∆Σ ADC
CONVERTER
VREF
IADC3
VREF
FIR
VADC
IB
22
CE RAM
IADC4
CT
IADC5
IC
IADC6
CT
IADC7
IN*
IADC0
CT
IADC1
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
*IN = Neutral Current
71M6543
9/17/2010
Figure 3. AFE Block Diagram (Four CTs)
2.2.1
Signal Input Pins
The 71M6543 features eleven ADC input pins.
IADC0 through IADC7 are intended for use as current sensor inputs. These eight current sensor inputs can
be configured as four single-ended inputs, or can be paired to form four differential inputs. For best
performance, it is recommended to configure the current sensor inputs as differential inputs (i.e., IADC0IADC1, IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7). The first differential input (IADC0-IADC1)
features a pre-amplifier with a selectable gain of 1 or 8, and is intended for direct connection to a shunt
resistor sensor, and can also be used with a Current Transformer (CT). The three remaining differential
pairs (i.e., IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7) may be used with CTs, or may be enabled to
interface to a remote 71M6xx3 isolated current sensor providing isolation for a shunt resistor sensor using a
low cost pulse transformer.
The remaining three inputs VADC8 (VA), VADC9 (VB) and VADC10 (VC) are single-ended, and are
intended for sensing each of the phase voltages in a polyphase meter application. These three single-ended
inputs are referenced to the V3P3A pin.
All ADC input pins measure voltage. In the case of shunt current sensors, currents are sensed as a voltage
drop in the shunt resistor sensor. In the case of Current Transformers (CT), the current is measured as a
voltage across a burden resistor that is connected to the secondary of the CT. Meanwhile, line voltages are
sensed through resistive voltage dividers. The VADC8 (VA), VADC9 (VB) and VADC10 (VC) pins are
single-ended and their common return is the V3P3A pin. See Figure 27, Figure 28, Figure 29 and Figure
30 for detailed connections for each type of sensor. Also refer to the 71M6543 Demonstration Board
schematic and bill of materials for typical component values used in these and other circuits.
v2
13
71M6543F/71M6543G Data Sheet
Pins IADC0-IADC1 can be programmed individually to be differential or single-ended as determined by
the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IADC0-IADC1 are
configured as a differential input to work with a resistive shunt or CT directly interfaced to the IADC0IADC1 differential input with the appropriate external signal conditioning components.
The performance of the IADC0-IADC1 pins can be enhanced by enabling a pre-amplifier with a fixed gain
of 8, using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IADC0-IADC1 become
the inputs to the 8x pre-amplifier, and the output of this amplifier is supplied to the multiplexer. The 8x
amplification is useful when current sensors with low sensitivity, such as shunt resistors, are used. With
PRE_E set, the IADC0-IADC1 input signal amplitude is restricted to 31.25 mV peak. When PRE_E = 0
(Gain = 1), the IADC0-IADC1 input signal is restricted to 250 mV peak.
For the 71M6543 application utilizing shunt resistor sensors (Figure 2), the IADC0-IADC1 pins are
configured for differential mode to interface to a local shunt by setting the DIFF0_E control bit. Meanwhile,
the IADC2-IADC3 , IADC4-IADC5 and IADC6-IADC7 pins are re-configured as digital remote sensor
interface designed to communicate with a 71M6xx3 isolated sensor by setting the RMTx_E control bits (I/O
RAM 0x2709[5:3]). The 71M6xx3 communicates with the 71M6543 using a bi-directional digital data stream
through an isolating pulse transformer. The 71M6543 also supplies power to the 71M6xx3 through the
isolating transformer. This type of interface is further described at the end of this chapter. See 2.2.8
71M6xx3 Isolated Sensor Interface.
For use with Current Transformers (CTs), as shown in Figure 3, the RMTx_E control bits are reset, so that
IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 are configured as local analog inputs. The IADC0-IADC1
pins cannot be configured as a remote sensor interface.
2.2.2
Input Multiplexer
When operating with locally connected sensors, the input multiplexer sequentially applies the input signals
from the analog input pins to the input of the ADC (see Figure 3), according to the sampling sequence
determined by the eleven MUXn_SEL[3:0] control fields. One complete sampling sequence is called a
multiplexer frame. The multiplexer of the 71M6543 can select up to eleven input signals when the current
sensor inputs are configured for single-ended mode. When the current sensor inputs are configured in
differential mode (recommended for best performance), the number of input signals is seven (i.e., IADC0IADC1, IADC2-IADC3, IADC4-IADC5, IADC6-IADC7, VADC8, VADC9 and VADC10) per multiplexer frame.
The number of slots in the multiplexer frame is controlled by the I/O RAM control field MUX_DIV[3:0] (I/O
RAM 0x2100[7:4]) (see Figure 4). The multiplexer always starts at state 0 and proceeds until the number
of sensor channels determined by the MUX_DIV[3:0] field setting have been converted.
The 71M6543 requires a unique CE code that is written for the specific meter configuration. Moreover,
each CE code requires specific AFE and MUX settings in order to function properly. Table 1 provides
the CE code and settings corresponding to the 1-Local / 3-Remote sensor configuration shown in
Figure 2. Table 2 provides the CE code and settings corresponding to the CT configuration shown in
Figure 3.
14
v2
71M6543F/71M6543G Data Sheet
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes
I/O RAM
I/O RAM
I/O RAM Setting
Comments
Mnemonic
Location
FIR_LEN[1:0]
210C[2:1]
1
288 cycles
ADC_DIV
2200[5]
0
Fast
PLL_FAST
2200[4]
1
19.66 MHz
MUX_DIV[3:0]
2100[7:4]
6
See note 1
MUX0_SEL[3:0]
Slot 0 is IADC0-IADC1
2105[3:0]
0
(IN)
MUX1_SEL[3:0]
2105[7:4]
1
Unused (See note 2)
MUX2_SEL[3:0]
2104[3:0]
1
Unused (See note 2)
MUX3_SEL[3:0]
Slot 3 is VADC8
2104[7:4]
8
(VA)
MUX4_SEL[3:0]
Slot 4 is VADC9
2103[3:0]
9
(VB)
MUX5_SEL[3:0]
Slot 5 is VADC10
2103[7:4]
A
(VC)
MUX6_SEL[3:0]
2102[3:0]
0
MUX7_SEL[3:0]
2102[7:4]
0
MUX8_SEL[3:0]
2101[3:0]
0
Slots not enabled
MUX9_SEL[3:0]
2101[7:4]
0
MUX10_SEL[3:0]
2100[3:0]
0
RMT2_E
2709[3]
1
Enable Remote IADC2-IADC3
(IA)
RMT4_E
2709[4]
1
Enable Remote IADC4-IADC5
(IB)
RMT6_E
2709[5]
1
Enable Remote IADC6-IADC7
(IC)
DIFF0_E
210C[4]
1
Differential IADC0-IADC1
(IN)
DIFF2_E
210C[5]
0
See note 3
DIFF4_E
210C[6]
0
See note 3
DIFF6_E
210C[7]
0
See note 3
PRE_E
2704[5]
1
IADC0-IADC1 Gain = 8
EQU[2:0]
2106[7:5]
5
IA*VA + IB*VB + IC*VC
ce43b016603 (use with 71M6603)
CE Codes
ce43b016103 (use with 71M6103)
(See note 4)
ce43b016113 (use with 71M6113)
ce43b016203 (use with 71M6203)
Equation(s)
5
Current Sensor Type
1 Local Shunt and 3 Remote Shunts
Applicable Figures
Figure 2, Figure 4 and Figure 31
Notes:
1. MUX_DIV[3:0] must be set to 0 while writing the other RAM locations in this table.
2. Each unused slot must be assigned to a valid (0 to A), but unused ADC handle.
3. This channel is remote (71M6xx3), hence DIFFx_E is irrelevant.
4. Must use the CE code that corresponds to the specific 71M6xx3 device used.
Maxim updates the CE code periodically. Contact your local Maxim representative to obtain
the latest CE code and the associated settings.
v2
15
71M6543F/71M6543G Data Sheet
Table 2. Required CE Code and Settings for CT Sensors
I/O RAM
I/O RAM
I/O RAM Setting
Comments
Mnemonic
Location
(Hex)
FIR_LEN[1:0]
210C[2:1]
1
288 cycles
ADC_DIV
2200[5]
0
Fast
PLL_FAST
2200[4]
1
19.66 MHz
MUX_DIV[3:0]
2100[7:4]
7
See note 1
MUX0_SEL[3:0]
Slot 0 is IADC2-IADC3
2105[3:0]
2
(IA)
MUX1_SEL[3:0]
Slot 1 is VADC8
2105[7:4]
8
(VA)
MUX2_SEL[3:0]
Slot 2 is IADC4-IADC5
2104[3:0]
4
(IB)
MUX3_SEL[3:0]
Slot 3 is VADC9
2104[7:4]
9
(VB)
MUX4_SEL[3:0]
Slot 4 is IADC6-IADC7
2103[3:0]
6
(IC)
MUX5_SEL[3:0]
Slot 5 is VADC10
2103[7:4]
A
(VC)
MUX6_SEL[3:0]
2102[3:0]
0
Slot 6 is IADC0-IADC1
(IN – See note 2)
MUX7_SEL[3:0]
2102[7:4]
0
MUX8_SEL[3:0]
2101[3:0]
0
Slots not enabled
MUX9_SEL[3:0]
2101[7:4]
0
MUX10_SEL[3:0]
2100[3:0]
0
RMT2_E
2709[3]
0
Local Sensor IADC2-IADC3
RMT4_E
2709[4]
0
Local Sensor IADC4-IADC5
RMT6_E
2709[5]
0
Local Sensor IADC6-IADC7
DIFF0_E
210C[4]
1
Differential IADC0-IADC1
DIFF2_E
210C[5]
1
Differential IADC2-IADC3
DIFF4_E
210C[6]
1
Differential IADC4-IADC5
DIFF6_E
210C[7]
1
Differential IADC6-IADC7
PRE_E
2704[5]
0
IADC0-IADC1 Gain = 1
EQU[2:0]
2106[7:5]
5
IA*VA + IB*VB + IC*VC
CE Code
ce43a02
Equation(s)
5
Current Sensor Type
4 Current Transformers (CTs)
Applicable Figures
Figure 3, Figure 4 and Figure 32
Notes:
1. MUX_DIV[3:0] must be set to 0 while writing the other RAM locations in this table.
2. IN is the optional Neutral Current.
Maxim updates the CE code periodically. Contact your local Maxim representative to obtain the
latest CE code and the associated settings.
16
v2
71M6543F/71M6543G Data Sheet
Using settings for the I/O RAM Mnemonics listed in Table 1 and Table 2 that do not match
those required by the corresponding CE code being used may result in undesirable side
effects and must not be selected by the MPU. Consult your local Maxim representative to
obtain the correct CE code and AFE / MUX settings corresponding to the application.
For a polyphase configuration with neutral current sensing using shunt resistor current sensors and the
71M6xx3 isolated sensors, as shown in Figure 2, the IADC0-IADC1 input must be configured as a
differential input, to be connected to a local shunt (see Figure 30 for the shunt connection details). The
local shunt connected to the IADC0-IADC1 input is used to sense the Neutral current. The voltage
sensors (VADC8, VADC9 and VADC10) are also directly connected to the 71M6543 (see Figure 27 for
the connection details) and are also routed though the multiplexer, as seen in Figure 2. Meanwhile, the
IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current inputs are configured as remote sensor digital
interfaces and the corresponding samples are not routed through the multiplexer. For this configuration,
the multiplexer sequence is as shown in Figure 4.
For a polyphase configuration with optional neutral current sensing using Current Transformer (CTs)
sensors, as shown in Figure 3, all four current sensor inputs must be configured as a differential inputs, to
be connected to their corresponding CTs (see Figure 29 for the differential CT connection details). The
IADC0-IADC1 current sensor input is optionally used to sense the Neutral current for anti-tampering
purposes. The voltage sensors (VADC8, VADC9 and VADC10) are directly connected to the 71M6543
(see Figure 27 for the voltage sensor connection details). No 71M6xx3 isolated sensors are used in this
configuration and all sensors are routed though the multiplexer, as seen in Figure 3. For this
configuration, the multiplexer sequence is as shown in Figure 5.
The multiplexer sequence shown in Figure 4 corresponds to the configuration shown in Figure 2. The
frame duration is 13 CK32 cycles (where CK32 = 32,768 Hz), therefore, the resulting sample rate is
32,768 Hz / 13 = 2,520.6 Hz. Note that Figure 4 only shows the currents that pass through the 71M6543
multiplexer, and does not show the currents that are copied directly into CE RAM from the remote
sensors (see Figure 2), which are sampled during the second half of the multiplexer frame. The two
unused conversion slots shown are necessary to produce the desired 2,520.6 Hz sample rate.
Multiplexer Frame
MUX_DIV[3:0] = 6 Conversions
Settle
CK32
MUX STATE
S
0
1
IN
Unused
2
Unused
3
VA
4
5
VB
VC
S
CROSS
MUX_SYNC
Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6)
The multiplexer sequence shown in Figure 5 corresponds to the CT configuration shown in Figure 3.
Since in this case all current sensors are locally connected to the 71M6543, all currents are routed
through the multiplexer, as seen in Figure 3. For this multiplexer sequence, the frame duration is 15 CK32
cycles (where CK32 = 32,768 Hz), therefore, the resulting sample rate is 32,768 Hz / 15 = 2,184.5 Hz.
Multiplexer Frame
MUX_DIV[3:0] = 7 Conversions
Settle
CK32
MUX STATE
S
0
IA
1
VA
2
IB
3
VB
4
IC
5
VC
6
IN
S
CROSS
MUX_SYNC
Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7)
v2
17
71M6543F/71M6543G Data Sheet
Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS
signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally,
MUX_CTRL launches each pass of the CE through its code. MUX_CTRL is clocked by CK32, the 32768 Hz
clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:
•
•
•
•
CHOP_E[1:0] (I/O RAM 0x2106[3:2])
MUX_DIV[3:0] (I/O RAM 0x2100[7:4])
FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
ADC_DIV (I/O RAM 0x2200[5])
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the
rising edge of CK32, the 32-kHz clock.
It is required that MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) be set to zero while changing the ADC
configuration to minimize system transients. After all configuration bits are set, MUX_DIV[3:0]
should be set to the required value.
The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Duration = (3-2*PLL_FAST)*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in CK32 cycles is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]
The duration of a multiplexer frame in CK_FIR cycles is:
MUX frame duration (CK_FIR cycles) =
[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)
The ADC conversion sequence is programmable through the MUXn_SEL control fields (I/O RAM 0x2100
to 0x2105). As stated above, there are up to eleven ADC time slots in the 71M6543, as set by
MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXn_SEL[3:0] = x, ‘n’ refers to the multiplexer
frame time slot number and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10,
or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the 71M6543 devices. For
example, if MUX0_SEL[3:0] = 0, then IADC0, corresponding to the sample from the IADC0-IADC1 input
(configured as a differential input), is positioned in the multiplexer frame during time slot 0. See Table 1 and
Table 2 for the appropriate MUXn_SEL[3:0] settings and other settings applicable to a particular meter
configuration and CE code.
Note that when the remote sensor interface is enabled, the samples corresponding to the remote
sensor currents do not pass through the 71M6543 multiplexer. The sampling of the remote current
sensors occurs in the second half of the multiplexer frame. The VA, VB and VC voltages are assigned
the last three slots in the frame. With this slot assignment for VA, VB and VC, the sampling of the
corresponding remote sensor currents bears a precise timing relationship to their corresponding phase
voltages, and delay compensation is accurately performed (see 2.2.3 Delay Compensation on page 19).
Also when using remote sensors, it is necessary to introduce unused slots to realize the number of
slots specified by the MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) field setting (see Figure 4 and Figure 5). The
MUXn_SEL[3:0] control fields for these unused (“dummy”) slots must be written with a valid ADC handle
(i.e., 0 to 10 decimal) that is not otherwise being used. In this manner, the unused ADC handle, is used
as a “dummy” place holder in the multiplexer frame, and the correct duration multiplexer frame
sequence is generated and also the desired sample rate. The resulting sample data stored in the CE
RAM location corresponding to the “dummy” ADC handle is ignored by the CE code. Meanwhile, the
digital isolation interface takes care of automatically storing the samples for the remote current sensors
in the appropriate CE RAM locations.
18
v2
71M6543F/71M6543G Data Sheet
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],
MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.
Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6543.
Table 3 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All
listed registers are 0 after reset and wake from battery modes, and are readable and writable.
Table 3: Multiplexer and ADC Configuration Bits
Name
Location
Description
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
ADC_DIV
MUX_DIV[3:0]
PLL_FAST
FIR_LEN[1:0]
DIFF0_E
DIFF2_E
DIFF4_E
DIFF6_E
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:0]
2101[3:0]
2101[7:0]
2100[3:0]
2200[5]
2100[7:4]
2200[4]
210C[2:1]
210C[4]
210C[5]
210C[6]
210C[7]
Selects the ADC input converted during time slot 0.
Selects the ADC input converted during time slot 1.
Selects the ADC input converted during time slot 2.
Selects the ADC input converted during time slot 3.
Selects the ADC input converted during time slot 4.
Selects the ADC input converted during time slot 5.
Selects the ADC input converted during time slot 6.
Selects the ADC input converted during time slot 7.
Selects the ADC input converted during time slot 8.
Selects the ADC input converted during time slot 9.
Selects the ADC input converted during time slot 10.
Controls the rate of the ADC and FIR clocks.
The number of ADC time slots in each multiplexer frame (maximum = 11).
Controls the speed of the PLL and MCK.
Determines the number of ADC cycles in the ADC decimation FIR filter.
Enables the differential configuration for analog input pins IADC0-IADC1 .
Enables the differential configuration for analog input pins IADC2-IADC3 .
Enables the differential configuration for analog input pins IADC4-IADC5 .
Enables the differential configuration for analog input pins IADC6-IADC7 .
Enables the remote sensor interface transforming pins IADC2-IADC3 into a digital
RMT2_E
2709[3]
interface for communications with a 71M6xx3 sensor.
Enables the remote sensor interface transforming pins IADC4-IADC5 into a digital
RMT4_E
2709[4]
interface for communications with a 71M6xx3 sensor.
Enables the remote sensor interface transforming pins IADC6-IADC7 into a digital
RMT6_E
2709[5]
interface for communications with a 71M6xx3 sensor.
PRE_E
2704[5]
Enables the 8x pre-amplifier.
Refer to Table 70 starting on page 102 for more complete details about these I/O RAM locations.
2.2.3
Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
φ=
t delay
T
⋅ 360 o = t delay ⋅ f ⋅ 360 o
Where f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and
voltage.
Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the
other one for current) controlled to sample simultaneously. Maxim’s Single Converter Technology,
however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” all-pass
filters. The all-pass filter corrects for the conversion time difference between the voltage and the
corresponding current samples that are obtained with a single multiplexed A/D converter.
o
The “constant delay” all-pass filter provides a broad-band delay 360 - θ, which is precisely matched to
the difference in sample time between the voltage and the current of a given phase. This digital filter does
not affect the amplitude of the signal, but provides a precisely controlled phase response.
v2
19
71M6543F/71M6543G Data Sheet
The recommended ADC multiplexer sequence samples the current first, immediately followed by
sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to
the current. The delay compensation implemented in the CE aligns the voltage samples with their
corresponding current samples by first delaying the current samples by one full sample interval (i.e.,
o
360 ), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by
o
360 - θ, resulting in the residual phase error between the current and its corresponding voltage of θ – Ф.
The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does
not contribute to errors in the energy measurements.
When using remote sensors, the CE performs the same delay compensation described above to align
each voltage sample with its corresponding current sample. Even though the remote current samples do
not pass through the 71M6543 multiplexer, their timing relationship to their corresponding voltages is
fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as
shown in Table 1. Note that these slot assignments result in VA, VB and VC occupying multiplexer slots
3, 4 and 5, respectively (see Figure 4).
2.2.4
ADC Pre-Amplifier
The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the
IADC0-IADC1 sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When
disabled, the supply current of the pre-amplifier is >2
8+S
-256
Look Up
RAM
63
-64
63
-64
255
6+S
ADDR
Q
Σ
7+S
19
4*RTC_P+RTC_Q
19
0x40000
Figure 13: Automatic Temperature Compensation
The 128 NV RAM locations are organized in 2’s complement format. As mentioned above, the
STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM addresses are
equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See 2.5.5 71M6543 Temperature Sensor on
page 53 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
52
v2
71M6543F/71M6543G Data Sheet
For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties
with respect to temperature, which is typically done once during initialization. Since the lookup table is
not directly addressable, the MPU uses the following procedure to load the NV RAM table:
1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
3. Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888).
4. Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM
5. Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM).
6. Repeat steps 3 through 5 until all data has been written to NV RAM.
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process
of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] (I/O RAM 0x2887[6:0]) auto-increments every time LKP_RD or
LKP_WR is pulsed. It is also possible to perform random access of the NV RAM by writing a 0 to the
LKPAUTOI bit and loading the desired address into LKPADDR[6:0].
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage area as ordinary battery-backed NV storage space using the procedure described
above to read and write NV RAM data. In this case, the OSC_COMP bit (I/O RAM 0x28A0[5]) is
reset to disable the automatic oscillator temperature compensation feature.
2.5.4.5 RTC Interrupts
The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC
and RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the
minutes and hours registers both equal their respective target counts as defined in Table 44. The alarm
clock interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See Table 32
in the interrupt section for the enable bits and flags for these interrupts.
The minute and hour target registers are listed in Table 44.
Table 44: I/O RAM Registers for RTC Interrupts
Name
Location
Rst
Wk
RTC_TMIN[5:0]
289E[5:0]
0
0
RTC_THR[4:0]
289F[4:0]
0
0
2.5.5
Dir
Description
R/W The target minutes register. See below.
The target hours register. The RTC_T interrupt occurs
R/W when RTC_MIN[5:0] becomes equal to RTC_TMIN[5:0]
and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
71M6543 Temperature Sensor
The 71M6543 includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system for the compensation of current, voltage and energy
measurement and the RTC. See 4.5 Metrology Temperature Compensation on page 88. Also see 2.5.4.4
RTC Temperature Compensation on page 52.
Unlike earlier generation Maxim SoCs, the 71M6543 does not use the ADC to read the temperature
sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor can be used to compensate for the frequency variation
of the crystal, even in SLP mode while the MPU is halted. See 2.5.4.4 RTC Temperature Compensation
on page 52.
In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the
TEMP_START (I/O RAM 0x28B4[6]) control bit. In SLP and LCD modes, it is awakened at a regular rate
set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The result of the temperature measurement is read from the two I/O RAM locations STEMP[10:3] (I/O
RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must be
v2
53
71M6543F/71M6543G Data Sheet
read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in Table 45). The resulting
11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal).
The equations below are used to calculate the sensed temperature. The first equation applies when the
71M6543F and 71M6543G are in MSN mode and TEMP_PWR = 1. The second equation applies when the
71M6543F and 71M6543G are in BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must
both be set to the same value, so that the battery that supplies the temperature sensor is also the battery
that is measured and reported in BSENSE. Thus, the second equation requires reading STEMP and
BSENSE. In the second equation, BSENSE (the sensed battery voltage) is used to obtain a more accurate
temperature reading when the IC is in BRN mode. The coefficients provided in the various STEMP
equations below are typical.
For the 71M6543F and 71M6543G in MSN Mode (with TEMP_PWR = 1):
Temp (°C ) = 0.325 ⋅ STEMP + 22
For the 71M6543F and 71M6543G in BRN Mode, (with TEMP_PWR=TEMP_BSEL):
Temp (oC ) = 0.325 ⋅ STEMP + 0.00218 ⋅ BSENSE 2 − 0.609 ⋅ BSENSE + 64.4
Table 45 shows the I/O RAM registers used for temperature and battery measurement.
54
v2
71M6543F/71M6543G Data Sheet
If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature measurement
may not finish. In this case, firmware may complete the measurement by selecting V3P3D
(TEMP_PWR = 1).
Table 45: I/O RAM Registers for Temperature and Battery Measurement
Name
Location
Rst
Wk
Dir
28A0[3]
0
0
R
28A0[2:0]
0
–
R/W
TEMP_BAT
28A0[4]
0
–
TEMP_START
28B4[6]
0
–
TEMP_PWR
28A0[6]
0
–
TEMP_BSEL
28A0[7]
0
–
0
–
TBYTE_BUSY
TEMP_PER[2:0]
TEMP_TEST[1:0] 2500[1:0]
Description
Indicates that hardware is still writing the 0x28A0
byte. Additional writes to this byte are locked out
while it is one. Write duration could be as long as 6 ms.
Sets the period between temperature measurements.
Automatic measurements can be enabled in any
mode (MSN, BRN, LCD, or SLP).
TEMP_PER
0
1-6
7
Causes VBAT to be measured whenever a
temperature measurement is performed.
TEMP_PER[2:0] must be zero in order for TEMP_START
to function. If TEMP_PER[2:0] = 0, then setting
TEMP_START starts a temperature measurement.
R/W
Ignored in SLP and LCD modes. Hardware clears
TEMP_START when the temperature measurement is
complete.
Selects the power source for the temperature sensor:
1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in
R/W
SLP and LCD modes, where the temperature sensor is
always powered by VBAT_RTC.
Selects which battery is monitored by the
R/W
temperature sensor: 1 = VBAT, 0 = VBAT_RTC
Test bits for the temperature monitor VCO.
TEMP_TEST must be 00 in regular operation. Any
other value causes the VCO to run continuously with
the control voltage described below.
R/W TEMP_TEST Function
R/W
00
01
1X
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
BSENSE[7:0]
2885[7:0]
–
–
2704[3]
0
0
BCURR
v2
Time
Manual updates (see TEMP_START)
2 ^ (3+TEMP_PER) (seconds)
Continuous
Normal operation
Reserved for factory test
Reserved for factory test
R
R
The result of the temperature measurement.
The STEMP[10:0] value may be obtained in C with a
single 16-bit read and divide by 32 operation as
follows:
volatile int16_t xdata STEMP _at_0x2881;
fa = (float)(STEMP/32);
R The result of the battery measurement.
Connects a 100 µA load to the battery selected by
R/W
TEMP_BSEL.
55
71M6543F/71M6543G Data Sheet
2.5.6
71M6xx3 Temperature Sensor
The 71M6xx3 includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of the current measurement
performed by the71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the
71M6xx3 STEMP[10:0] reading. Also, see 4.5 Metrology Temperature Compensation on page 88.
See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read the
STEMP[10:0] information from the 71M6xx3.
2.5.7
71M6543 Battery Monitor
The 71M6543 temperature measurement circuit can also monitor the batteries at the VBAT and
VBAT_RTC pins. The battery to be tested (i.e., VBAT or VBAT_RTC pin) is selected by TEMP_BSEL (I/O
RAM 0x28A0[7]).
When TEMP_BAT (I/O RAM 0x28A0[4]) is set, a battery measurement is performed as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885). The following equations are used to calculate the voltage measured on the VBAT pin (or
VBAT_RTC pin) from the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts.
A slightly different equation is used for MSN mode and BRN mode, as follows.
In MSN mode, TEMP_PWR = 1 use:
VBAT (orVBAT _ RTC ) = 3.3V + ( BSENSE − 142) ⋅ 0.0246V + STEMP ⋅ 0.000297V
In BRN mode, TEMP_PWR = TEMP_BSEL use:
VBAT (orVBAT _ RTC ) = 3.291V + ( BSENSE − 142) ⋅ 0.0255V + STEMP ⋅ 0.000328V
In MSN mode, a 100 µA de-passivation load can be applied to the selected battery (i.e., selected by the
TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by
taking a battery measurement with and without BCURR. Regardless of the BCURR bit setting, the battery
load is never applied in BRN, LCD, and SLP modes.
2.5.8
71M6xx3 VCC Monitor
The 71M6xx3 monitors its VCC pin voltage. The voltage of the VCC pin can be obtained by the 71M6543
by issuing a read command to the 71M6xx3. The 71M6543 must request both the VSENSE[7:0] and
STEMP[10:0] values from the 71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate the
71M6xx3 VCC pin voltage from the VSENSE[7:0] and STEMP[10:0] values read from the 71M6xx3.
See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read
VSENSE[7:0] and STEMP[10:0] from the 71M6xx3 remote sensors.
2.5.9
UART and Optical Interface
The 71M6543 provides two asynchronous interfaces, UART0 and UART1. Both can be used to connect
to AMR modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash
memory.
Referring to Figure 14, UART1 includes an interface to implement an IR/optical port. The pin OPT_TX is
designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has
the same threshold as the RX pin, but can also be used to sense the input from an external photo detector
used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port
(UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV (I/O RAM 0x2456[0])
and OPT_RXINV (I/O RAM 0x2457[1]), respectively. Additionally, the OPT_TX output may be modulated at
38 kHz. Modulation is available in MSN and BRN modes (see Table 61). The OPT_TXMOD bit (I/O RAM
0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]) ,
which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means that OPT_TX is
low for 6.25% of the period.
56
v2
71M6543F/71M6543G Data Sheet
When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is
via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The
OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse
modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured
as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).
VARPULSE
from
OPT_TX UART
3
2
WPULSE
0
DIO2
A
MOD
B
1
EN DUTY
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
OPT_TXINV
A
B
B
OPT_TX
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
V3P3
Internal
1/38kHz
Figure 14: Optical Interface
Bit Banged Optical UART (Third UART)
As shown in Figure 15, the 71M6543 can also be configured to drive the optical UART with a DIO signal
in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port is
driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used when
the two dedicated UARTs must be connected to high speed clients and a slower optical UART is
permissible.
Internal
SEG55
DIO55
UART1_RX
1
1
0
0
OPT_RXDIS
UART1_TX
0
DIO5
1
0
OPT_TXMOD
OPT_FDC
OPT_TXINV
EN
3
WPULSE
2
DIO51
B
0
MOD
A
SEG51
VARPULSE
DUTY
SEGDIO55/
OPT_RX
LCD_MAP[55]
V3P3
SEGDIO51/
OPT_TX
1
0
LCD_MAP[51]
1
OPT_TXE[1:0]
SEG5
2
1
0
1
SEGDIO5/TX2
LCD_MAP[5]
OPT_BB
OPT_TXMOD=1,
OPT_FDC=2 (25%)
OPT_TXMOD=0
A
B
1/38kHz
Figure 15: Optical Interface (UART1)
2.5.10 Digital I/O and LCD Segment Drivers
2.5.10.1 General Information
The 71M6543 combines most DIO pins with LCD segment drivers. Each SEG/DIO pin can be configured
as a DIO pin or as a segment driver pin (SEG).
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
v2
57
71M6543F/71M6543G Data Sheet
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
PORT_E.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in Table 47.
Example: SEGDIO12 (pin 32 in Table 47) is configured as a DIO output pin with a value of 1 (high) by
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured
as an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5
of LCD_SEG12.
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in Figure 12.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 47 lists the
internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0]. If
more than one input is connected to the same resource, the resources are combined using a logical OR.
Table 46: Selectable Resources using the DIO_Rn[2:0] Bits
Resource Selected for SEGDIOn or PB Pin
Value in DIO_Rn[2:0]
0
None
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0)
5
Low priority I/O interrupt (INT1)
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See Table 48.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in Figure 16, right), not source it from V3P3D (as shown in Figure 16, left). This is due
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch on page 136.
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pullup or pulldown resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
58
v2
71M6543F/71M6543G Data Sheet
MISSION
LCD/SLEEP
BROWNOUT
V3P3SYS
MISSION
LCD/SLEEP
BROWNOUT
VBAT
V3P3D
HIGH
HIGH-Z
LOW
DIO
VBAT
V3P3D
HIGH
HIGH-Z
LOW
GNDD
Not recommended
V3P3SYS
DIO
GNDD
Recommended
Figure 16: Connecting an External Load to DIO Pins
2.5.10.2 Combined DIO and SEG Pins
A total of 51 combined DIO/LCD pins are available. These pins can be categorized as follows:
39 combined DIO/LCD segment pins:
o SEGDIO4…SEGDIO25 (22 pins)
o SEGDIO28…SEGDIO35 (8 pins)
o SEGDIO40…SEGDIO45 (6 pins)
o SEGDIO52…SEGDIO54 (3 pins)
12 combined DIO/LCD segment pins shared with other functions:
o SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
o SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
o SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
o SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
o SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
Additionally, 5 LCD segment (SEG) pins are available. These pins can be categorized as follows:
o 3 SEG pins combined with the ICE interface (SEG48/E_RXTX, SEG49/E_TCLK,
SEG50/E_RST)
o 2 SEG pins combined with the test multiplexer outputs (SEG46/TMUX2OUT,
SEG47/TMUXOUT)
Thus, a total of 51 DIO pins are available with minimum LCD configuration, and a total of 56 LCD pins are
available with minimum DIO configuration.
v2
59
71M6543F/71M6543G Data Sheet
Table 47: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15
SEGDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin #
45
44
43
42
41
39
38
37
36
35
34
33
32
31
30
29
0
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see Table 46)
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_MAP[15:8] (I/O RAM 0x240A)
10
11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
P0 (SFR80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
7
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 48, and the configuration for pins
SEGDIO32 to SEGDIO45 is shown in Table 49. The configuration for pins SEGDIO51 to SEGDIO55 is
shown in Table 50.
Table 48: Data/Direction Registers for SEGDIO16 to SEGDIO31
SEGDIO
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin #
28
27
25
24
23
22
21
20
19
18
17
16
11
10
9
8
Configuration:
0 = DIO, 1 = LCD
0
16
SEG Data Register
16
DIO Data Register
16
Direction Register:
0 = input, 1 = output
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[23:16] (I/O RAM 0x2409)
LCD_MAP[31:24] (I/O RAM 0x2408)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
Table 49: Data/Direction Registers for SEGDIO32 to SEGDIO45
SEGDIO
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Pin #
7
6
5
4
3
2
1
100
99
98
97
96
95
94
0
1
5
32
33
32
33
32
33
2
3
4
5
6
7
0
1
2
3
4
LCD_MAP[39:32]
LCD_MAP[45:40]
(I/O RAM 0x2407)
(I/O RAM 0x2406[5:0])
34 35 36
37 38
39 40 41 42 43 44
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
34 35 36
37 38
39 40 41 42 43 44
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
34 35 36
37 38
39 40 41 42 43 44
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
60
45
45
45
v2
71M6543F/71M6543G Data Sheet
Table 50: Data/Direction Registers for SEGDIO51 to SEGDIO55
SEGDIO
51
52
53
54
55
Pin #
53
52
51
47
46
3
4
5
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
–
–
–
6
7
–
–
–
LCD_MAP[55:48]
(I/O RAM 0x2405)
51
52 53 54 55
–
–
–
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
51
52 53 54 55
–
–
–
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
51
52 53 54 55
–
–
–
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
2.5.10.3 LCD Drivers
The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers.
The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols.
A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the
V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a
maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from
a trimmed low-power reference.
The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM
0x2401[7:6]). It is decoded into LCD_EXT, LDAC_E, and LCD_BSTE. Table 51 details the
LCD_VMODE[1:0] configurations.
Table 51: LCD_VMODE Configurations
LCD_VMODE[1:0] LCD_EXT LDAC_E LCD_BSTE Description
11
1
0
0
External VLCD connected to the VLCD pin.
LCD boost is enabled. Maximum VLCD voltage is
2*V3P3L-1.
10
0
1
1
VLCD = max(2*V3P3L-1, 2.65(1+LCD_DAC[4:0]/31)
LCD boost is disabled. The maximum VLCD
voltage is V3P3L.
01
0
1
0
VLCD = max(V3P3L, 2.65(1+LCD_DAC[4:0]/31)
VLCD=V3P3L, the LCD DAC and LCD boost are disabled. In LCD mode, this setting causes the lowest
00
0
0
0
battery current.
Notes:
1. LCD_EXT, LDAC_E and LCD_BSTE are 71M6543 internal signals which are decoded from
the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded signals,
when asserted, has the effect indicated in the description column above, and as summarized
below.
LCD_EXT : When set, the VLCD pin expects an external supply voltage
LDAC_E : When set, LCD DAC is enabled
LCD_BSTE : When set, the LCD boost circuit is enabled
2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS pin,
depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC, the
71M6543 switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise V3P3L
is sourced from the V3P3SYS pin while in MSN mode.
v2
61
71M6543F/71M6543G Data Sheet
When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0])
value to ensure that the LCD manufacturer’s recommended operating voltage specification is not
exceeded.
The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current
dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated
directly from VBAT.
The LCD DAC uses a low-power reference and, within the constraints of VBAT and the voltage doubler,
generates a VLCD voltage of 2.65 VDC + 2.65 * LCD_DAC[4:0]/31. Two fuse bytes increase the accuracy
of the LCD_DAC. LCDADJ12 and LCDADJ0 indicate the actual VLCD output voltage when the DAC is
programmed to 12 and 0 respectively.
The LCD_BAT (I/O RAM 0x2402[7]) bit causes the LCD system to use the battery voltage in all power
modes. This may be useful when an external supply is available for the LCD system. The advantage of
connecting the external supply to VBAT, rather than VLCD is that the LCD DAC is still active.
If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has
no effect.
The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with
six back planes, the 6-way multiplexing reduces the number of SEG pins required to drive a display and
therefore enhances the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field
(I/O RAM 0x2400[6:4]) settings (Table 52) for the different LCD multiplexing choices. If 5-state multiplexing
is selected, SEGDIO27 is converted to COM4. If 6-state multiplexing is selected, SEGDIO26 is converted
to COM5. These conversions override the SEG/DIO mapping of SEGDIO26 and SEGDIO27. Additionally,
independent of LCD_MODE[2:0], if LCD_ALLCOM = 1 (I/O RAM 0x2400[3]), then SEGDIO26 and
SEGDIO27 become COM4 and COM5 if their LCD_MAP[ ] bits are set.
The LCD_ON (I/O RAM 0x240C[0]) and LCD_BLANK (I/O RAM 0x240C[1]) bits are an easy way to either
blank the LCD display or turn it fully on. Neither bit affects the contents of the LCD data stored in the
LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data to zero.
LCD_RST affects only pins that are configured as LCD.
A small amount of power can be saved by programming the LCD frequency to the lowest value that
provides satisfactory LCD visibility over the required temperature range.
Table 52 shows all I/O RAM registers that control the operation of the LCD interface.
62
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71M6543F/71M6543G Data Sheet
Table 52: LCD Configurations
Name
Location
Rst
Wk
Dir
LCD_ALLCOM
2400[3]
0
–
R/W
LCD_BAT
2402[7]
0
–
R/W
LCD_E
2400[7]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
R/W
R/W
LCD_RST
240C[2]
0
–
R/W
LCD_DAC[4:0]
240D[4:0]
0
–
R/W
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
LCD_MODE[2:0] 2400[6:4]
0
–
Description
Configures all 6 SEG/COM pins as COM. Has no effect
on pins whose LCD_MAP bit is zero.
Connects the LCD power supply to VBAT in all modes.
Enables the LCD display. When disabled, VLC2,
VLC1, and VLC0 are ground as are the COM and SEG
outputs if their LCD_MAP bit is 1.
LCD_ON = 1 turns on all LCD segments without
affecting the LCD data. Similarly, LCD_BLANK = 1
turns off all LCD segments without affecting the LCD
data. If both bits are set, all LCD segments are turned
on.
Clear all bits of LCD data. These bits affect SEGDIO
pins that are configured as LCD drivers.
This register controls the LCD contrast DAC which
adjusts the VLCD voltage and has an output range of
2.65 VDC to 5.3 VDC. The VLCD voltage is
VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 85.5 mV. The maximum
DAC output voltage is limited by V3P3SYS, VBAT, and
whether LCD_BSTE is set.
Sets the LCD clock frequency (1/T). See definition of T
in Figure 17.
Note: fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
The LCD bias and multiplex mode.
Output
LCD_MODE
000
4 states, 1/3 bias
001
3 states, 1/3 bias
R/W
010
2 states, ½ bias
011
3 states, ½ bias
100
Static display
101
5 states, 1/3 bias
110
6 states, 1/3 bias
This register specifies how VLCD is generated.
LCD_VMODE
11
LCD_VMODE[1:0] 2401[7:6]
00
00
R/W
10
01
00
Description
External VLCD
LCD boost and LCD DAC
enabled
LCD DAC enabled
No boost and no DAC.
VLCD = VBAT or V3P3SYS
The LCD can be driven in static, ½ bias, and 1/3 bias modes. Figure 17 defines the COM waveforms.
Note that COM pins that are not required in a specific mode maintain a segment off state rather than
GND, VCC, or high impedance.
The segment drivers SEGDIO22 and SEGDIO23 can be configured to blink at either 0.5 Hz or 1 Hz.
The blink rate is controlled by LCD_Y (I/O RAM 0x2400[2]). There can be up to six pixels/segments
connected to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0])
and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0]) identify which pixels, if any, are to blink.
LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] are non-volatile.
v2
63
71M6543F/71M6543G Data Sheet
The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]).
The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN
and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered
down. This setting can be used to reduce current in LCD mode.
STATIC (LCD_MODE=100)
1/2 BIAS, 2 STATES (LCD_MODE = 010 )
0
1
COM0
COM0
1/2 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
COM1
(1/2)
COM1
COM2
(1/2)
COM2
(1/2)
COM2
COM3
(1/2)
COM3
(1/2)
COM3
(1/2)
COM4
(1/2)
COM4
(1/2)
COM4
(1/2)
COM5
(1/2)
COM5
(1/2)
COM5
(1/2)
COM1
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
T
1/3 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
1/3 BIAS, 4 STATES (LCD_MODE = 000 )
3
0
1
2
COM0
1/3 BIAS, 6 STATES (LCD_MODE = 110 )
3
4
5
0
1
2
COM0
COM1
COM1
COM1
COM2
COM2
COM2
(2/3)
(1/3)
COM3
COM3
COM4
COM4
COM4
COM5
COM5
COM5
COM3
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
Figure 17: LCD Waveforms
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 53).
Table 53: LCD Data Registers for SEGDIO46 to SEGDIO55
SEGDIO
46
47
48
49
50
51
52
53
54
55
Pin #
93
92
58
57
56
53
52
51
47
46
LCD_SEGDIO55[5:0]
(I/O RAM 0x2447[5:0])
LCD_SEGDIO54[5:0]
(I/O RAM 0x2446[5:0])
LCD_SEGDIO53[5:0]
(I/O RAM 0x2445[5:0])
LCD_SEGDIO52[5:0]
(I/O RAM 0x2444[5:0])
LCD_SEGDIO51[5:0]
(I/O RAM 0x2443[5:0])
See 2.5.10.2
LCD_SEGDIO50[5:0]
(I/O RAM 0x2442[5:0])
LCD_SEGDIO49[5:0]
(I/O RAM 0x2441[5:0])
LCD_SEGDIO48[5:0]
(I/O RAM 0x2440[5:0]
LCD_SEGDIO47[5:0]
(I/O RAM 0x243F[5:0])
SEG Data
Register
Always LCD pins
LCD_SEGDIO46[5:0]
(I/O RAM 0x243E[5:0]
Configuration:
The LCD_MAP[47:46] (I/O RAM 0x2406[7:6]) bits are used to determine whether SEG46 and SEG47 are
SEG pins or their alternate function (see pins 93 and 92 in Figure 42). If the LCD_MAP[47:46] bits are 1,
then the pins are configured as SEG pins. If the LCD_MAP[47:46] bits are 0, then the pins are configured
as their alternate functions (TMUX2OUT and TMUXOUT, respectively).
64
v2
71M6543F/71M6543G Data Sheet
For example, if LCD_MAP[46] = 1, then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if
LCD_MAP[46]=0, then pin 93 is configured as TMUX2OUT.
The SEG pins with alternate ICE interface function (see pins 56-58 in Figure 42) are forced to their
alternate ICE interface function (i.e., E_RXTX, E_TCLK and E_RST) if the ICE_E pin (pin 59) is driven
high, and in this case, the bits LCD_MAP[50:48] (I/O RAM 0x2405[2:0]) bits are “don’t care” bits. If the
ICE_E pin is driven low, then LCD_MAP[50:48] bits must written with 1 in order to configure these pins as
SEG pins. If the ICE_E pin is low and LCD_MAP[50:48] are written with 0, then these pins are tied to an
internal pullup.
2.5.11 EEPROM Interface
The 71M6543 provides hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM
interface. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication.
2.5.11.1 Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is
multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA) pins and is selected by setting
DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with the interface through the SFR
registers EEDATA and EECTRL. If the MPU wishes to write a byte of data to the EEPROM, it places the
data in EEDATA and then writes the Transmit code to EECTRL. This initiates the transmit operation which
is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the
RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin
interface is selected are shown in Table 54.
Table 54: EECTRL Bits for 2-pin Interface
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7
6
5
ERROR
BUSY
RX_ACK
R
R
R
0
0
1
Positive
Positive
Positive
4
TX_ACK
R
1
Positive
1 when an illegal command is received.
1 when serial data bus is busy.
1 indicates that the EEPROM sent an ACK bit.
1 indicates when an ACK bit has been sent to the
EEPROM.
CMD[3:0]
0000
0010
3:0
CMD[3:0]
W
0000
Positive
0011
0101
0110
1001
Others
Operation
2
No-op command. Stops the I C clock
(SDCK). If not issued, SDCK keeps
toggling.
Receive a byte from the EEPROM and
send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The
direction of the DIO line can be changed from input to output and an output value can be written
with a single write operation, thus avoiding collisions (see Table 14 Port Registers (SEGDIO0-15)).
Therefore, no resistor is required in series SDATA to protect against collisions.
v2
65
71M6543F/71M6543G Data Sheet
2.5.11.2 Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin
A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are
shown in Table 55. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
or read from the EEPROM, depending on the values of the EECTRL bits.
2.5.11.3 Three-Wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins
If DIO_EEX[1:0] = 11, the 71M6543 three-wire interface is the same as above, except DI and DO are
separate pins. In this case, SEGDIO3 becomes DO and SEGDIO8 becomes DI. The timing diagrams
are the same as for DIO_EEX[1:0] = 10 except that all output data appears on DO and all input data is
expected on DI. In this mode, DI is ignored while data is being received on DO. This mode is compatible
with SPI modes 0,0 and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on
the rising edge of the clock.
Table 55: EECTRL Bits for the 3-wire Interface
Control
Bit
Name
Read/
Write
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until
a rising edge is seen on the data line. This bit can be used during the
WFR
7
W
last byte of a Write command to cause the INT5 interrupt to occur when
the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
BUSY
6
R
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately
HiZ
5
W
after the last SDCK rising edge.
RD
Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.
4
W
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD = 1, CNT bits of data are read MSB first, and right
CNT[3:0]
justified into the low order bits of EEDATA. If RD = 0, CNT bits are sent
3:0
W
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
The timing diagrams in Figure 18 through Figure 22 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 18 through Figure 22
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
drives SDATA, but transitions to HiZ (high impedance) when CS falls. The firmware should then
immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a
low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
SDATA (output)
SDATA output Z
D7
D6
D5
D4
D3
D2
(LoZ)
BUSY (bit)
Figure 18: 3-wire Interface. Write Command, HiZ=0.
66
v2
71M6543F/71M6543G Data Sheet
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
(HiZ)
BUSY (bit)
Figure 19: 3-wire Interface. Write Command, HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
SDATA (input)
D7
D5
D6
SDATA output Z
D4
D3
D2
D1
D0
(HiZ)
BUSY (bit)
Figure 20: 3-wire Interface. Read Command.
EECTRL Byte Written
INT5 not issued
CNT Cycles (0 shown)
Write -- No HiZ
EECTRL Byte Written
Write -- HiZ
INT5 not issued
CNT Cycles (0 shown)
SCLK (output)
SCLK (output)
SDATA (output)
SDATA (output)
D7
SDATA output Z
SDATA output Z
(LoZ)
(HiZ)
BUSY (bit)
BUSY (bit)
Figure 21: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
SDATA (out/in)
D7
D6
D5
(From 6520)
SDATA output Z
(LoZ)
D4
D3
D2
BUSY
READY
(From EEPROM)
(HiZ)
BUSY (bit)
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
2.5.12 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface
to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed
with the combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39 (pins 3, 2, 1 and 100).
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
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67
71M6543F/71M6543G Data Sheet
1) An external host reads data from CE locations to obtain metering information. This can be used in
applications where the 71M6543 function as a smart front-end with preprocessing capability. Since the
addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not
SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
the external host can initiate and control processes in the 71M6543 MPU. Writing to a CE or MPU
location normally generates an interrupt, a function that can be used to signal to the MPU that the
byte that had just been written by the external host must be read and processed. Data can also be
inserted by the external host without generating an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the
71M6543 as an analog front-end (AFE).
4) Flash programming by the external host (SPI Flash Mode).
SPI Transactions
A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state.
During this state, SPI_DO is held in high impedance state and all transitions on SPI_CLK and SPI_DI are
ignored. When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As
shown in Table 56, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status
byte, followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some
transactions may consist of a command only.
When SPI_CSZ rises, SPI command bytes that are not of the form x0000000 cause the SPI_CMD (SFR
0xFD) register to be updated and then cause an interrupt to be issued to the MPU. The exception is if the
transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued.
SPI_CMD is not cleared when SPI_CSZ is high.
The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8
clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI
access to DRAM is always possible.
Table 56: SPI Transaction Fields
Field
Name
Required
Address
Yes, except
single byte
transaction
Size
Description
(bytes)
2
Command
Yes
1
Status
Yes, if transaction
includes DATA
1
Data
Yes, if transaction
includes DATA
1 or
more
16-bit address. The address field is not required if the transaction
is a simple SPI command.
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit. Unless
the transaction is multi-byte and SPI_CMD is exactly 0x80 or
0x00, the SPI_CMD register is updated and an SPI interrupt is
issued. Otherwise, the SPI_CMD register is unchanged and the
interrupt is not issued.
8-bit status field, indicating the status of the previous transaction.
This byte is also available in the MPU memory map as
SPI_STAT (I/O RAM 0x2708). See Table 58 for the contents.
The read or write data. Address is auto incremented for each
new byte.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
•
•
68
71M6543 not ready
Transaction not ending on a byte boundary.
v2
71M6543F/71M6543G Data Sheet
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte
transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use
the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value,
single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 23, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
SERIAL READ
16 bit Address
Status Byte
8 bit CMD
DATA[ADDR]
DATA[ADDR+1]
Extended Read . . .
(From Host) SPI_CSZ
0
15
16
A0
C7
23
24
31
32
ST0
D7
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
A15
A14
A1
C6
C5
C0
HI Z
(From 6543) SPI_DO
SERIAL WRITE
x
ST7
16 bit Address
ST6
ST5
D6
DATA[ADDR]
Status Byte
8 bit CMD
D1
D6
D1
D0
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Write . . .
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
x
A15
A14
A1
C6
C5
HI Z
(From 6543) SPI_DO
D7
C0
ST7
ST6
ST5
D6
D1
D6
D1
D0
x
ST0
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations
Table 57: SPI Command Sequences
Command Sequence
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
ADDR 0xxx xxxx STATUS
Byte0 ... ByteN
Description
Read data starting at ADDR. ADDR is auto-incremented until SPI_CSZ
is raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command
byte is 1000 0000. In this case, no MPU interrupt is generated and
SPI_CMD is not updated.
Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
Table 58: SPI Registers
Name
Location
Rst
Wk
Dir
Description
2701[7]
SFR FD[7:0]
0
–
0
–
R/W
R
SPI_E
270C[4]
1
1
R/W
IE_SPI
SFR F8[7]
0
0
R/W
SPI interrupt enable bit.
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SEGDIO36 – SEGDIO39.
SPI interrupt flag. Set by hardware, cleared by writing a 0.
EX_SPI
SPI_CMD
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69
71M6543F/71M6543G Data Sheet
Name
SPI_SAFE
SPI_STAT
Location
Rst
Wk
Dir
270C[3]
0
0
R/W
2708[7:0]
0
0
R
Description
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
SPI_STAT contains the status results from the previous
SPI transaction
Bit 7 - 71M6543 ready error: the 71M6543 was not
ready to read or write as directed by the previous
command.
Bit 6 - Read data parity: This bit is the parity of all bytes
read from the 71M6543 in the previous command. Does
not include the SPI_STAT byte.
Bit 5 - Write data parity: This bit is the overall parity of
the bytes written to the 71M6543 in the previous
command. It includes CMD and ADDR bytes.
Bit 4:2 - Bottom 3 bits of the byte count. Does not
include ADDR and CMD bytes. One, two, and three
byte instructions return 111.
Bit 1 - SPI FLASH mode: This bit is zero when the
TEST pin is zero.
Bit 0 - SPI FLASH mode ready: Used in SPI FLASH
mode. Indicates that the flash is ready to receive
another write instruction.
SPI Flash Mode (SFM)
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6543 supports a special flash mode (SFM) which facilitates initial programming of the flash memory.
When the 71M6543 is in this mode, the SPI can erase, read, and write the flash memory. Other memory
elements such as XRAM and IO RAM are not accessible in this mode. In order to protect the flash
contents, several operations are required before the SFM mode is successfully invoked.
In SFM mode, the 71M6543 supports n byte reads and dual-byte writes to flash memory. See the SPI
Transaction description on Page 68 for the format of read and write commands. Since the flash write
operation is always based on a two-byte word, the initial address must always be even. Data is written to
the 16-bit flash memory bus after the odd word is written.
When the 71M6543G is operating SFM, SPI single-byte transactions are used to write to FL_BANK[1:0]
(SFR 0xB6[1:0]). During an SPI single-byte transaction, SPI_CMD[1:0] will over-write the contents of
FL_BANK[1:0] (SFR 0xB6[1:0]). This will allow for access of the entire 128 KB flash memory while
operating in SFM.
In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI
Transaction section above is not available in SFM mode. The 71M6543 must be reset by the WD timer or
by the RESET pin in order to exit SFM mode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
•
•
•
•
•
70
ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent
Flash corruption.
The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC).
PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]).
SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
FLSH_UNLOCK[3:0] = 0010 (I/O RAM 0x2702[7:4]).
v2
71M6543F/71M6543G Data Sheet
The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for
disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is:
•
First, write to SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM mode.
o 0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM.
o 0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes
will not be blocked and it is up to the user to guarantee that only previously unwritten
locations are written. This mode is not accessible when SPI secure mode is set.
o SFM is not invoked if any other pattern is written to the SFMM register.
•
Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This write invokes SFM provided that the
previous write operation to SFMM met the requirements. Writing any other pattern to this register
does not invoke SFM. Additionally, any write operations to this register automatically reset the
previously written SFMM register values to zero.
SFM Details
The following occurs upon entering SFM.
•
•
•
•
•
The CE is disabled.
The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the
VBAT pin).
The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
Mass erase is invoked if specified in the SFMM (I/O RAM 0x2080) register (see Invoking SFM, above).
The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles.
All SPI read and write operations now refer to Flash instead of XRAM space.
The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transactions that write two bytes to an even
address. The write transactions must contain a command byte of 0x00 which is the form that does not
create an MPU interrupt. Auto incrementing is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be 0x80 in SFM read transactions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is shown in the
SPI Transactions description on Page 68.SPI Transactions
2.5.13 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6543. It uses the
RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET pin
were pulled high, except that the I/O RAM bits are in the same state as after a wake-up from SLP or LCD
modes (see the I/O RAM description in 5.2 for a list of I/O RAM bit states after RESET and wake-up).
Four thousand, one hundred CK32 cycles (or 125 ms) after the WDT overflow, the MPU is launched from
program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake-Up Behavior). The
WDT is disabled when the ICE_E pin is pulled high.
For details, see 3.3.4 Watchdog Timer (WDT) Reset.
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71
71M6543F/71M6543G Data Sheet
2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or analog signals listed in Table 60 can be selected to be output on the TMUXOUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX[4:0] (I/O RAM 0x2502[4:0], as
shown in Table 59.
One of the digital or analog signals listed in Table 60 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
shown in.
The TMUX and TMUX2 I/O RAM locations are non-volatile and their contents are preserved by
battery power and across resets.
The TMUXOUT and TMUX2OUT pins may be used for diagnosis purposes or in production test. The
RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides
even higher precision.
Table 59: TMUX[4:0] Selections
Signal Name
Description
1
RTCLK
9
WD_RST
A
CKMPU
D
V3AOK bit
E
V3OK bit
1B
MUX_SYNC
32.768 kHz clock waveform
Indicates when the MPU has reset the watchdog timer. Can be
monitored to determine spare time in the watchdog timer.
MPU clock – see Table 8
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M6543 monitors the V3P3A pin voltage only.
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654 monitors the V3P3A pin voltage only.
Internal multiplexer frame SYNC signal. See Figure 4 and Figure
5.
1C
1D
1F
CE_BUSY interrupt
CE_XFER interrupt
RTM output from CE
TMUX[5:0]
See 2.3.3 on page 25 and Figure 12 on page 45
See 2.3.5 on page 26
Note:
All TMUX[5:0] values which are not shown are reserved.
72
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71M6543F/71M6543G Data Sheet
Table 60: TMUX2[4:0] Selections
Signal Name
Description
0
WD_OVF
1
PULSE_1S
2
PULSE_4S
3
A
RTCLK
SPARE[1] bit – I/O RAM
0x2704[1]
SPARE[2] bit – I/O RAM
0x2704[2]
WAKE
B
MUX_SYNC
C
E
12
13
14
15
16
17
18
1F
MCK
GNDD
INT0 – DIG I/O
INT1 – DIG I/O
INT2 – CE_PULSE
INT3 – CE_BUSY
INT4 - VSTAT
INT5 – EEPROM/SPI
INT6 – XFER, RTC
RTM_CK (flash)
Indicates when the watchdog timer has expired (overflowed).
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 1 second
interval. Multiple cycles should be averaged together to filter out
jitter.
Four second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 4 second
interval. Multiple cycles should be averaged together to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 second pulse.
32.768 kHz clock waveform
Copies the value of the bit stored in 0x2704[1]. For general
purpose use.
Copies the value of the bit stored in 0x2704[2]. For general
purpose use.
Indicates when a WAKE event has occurred.
Internal multiplexer frame SYNC signal. See Figure 4 and Figure
5.
See 2.5.3 on page 49.
Digital GND. Use this signal to make the TMUX2OUT pin static.
TMUX2[4:0]
8
9
Interrupt 0. See 2.4.8 on page 39. Also see Figure 12 on page 45.
See 2.3.5 on page 26.
Note:
All TMUX2[4:0] values which are not shown are reserved.
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73
71M6543F/71M6543G Data Sheet
3
Functional Description
3.1
Theory of Operation
The energy delivered by a power source into a load can be expressed as:
t
E = ∫ V (t ) I (t )dt
0
Assuming phase angles are constant, the following formulae apply:
P = Real Energy [Wh] = V * A * cos φ* t
S = Apparent Energy [VAh] =
Q = Reactive Energy [VARh] = V * A * sin φ * t
P2 + Q2
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic
content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern
solid-state electricity meter IC such as the 71M6543 functions by emulating the integral operation
above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as
the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest,
the current and voltage samples, multiplied with the time period of sampling yields an accurate quantity
for the momentary energy. Summing-up the momentary energy quantities over time results in
accumulated energy.
500
400
300
200
100
0
0
5
10
15
20
-100
-200
-300
Current [A]
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
Figure 24: Voltage, Current, Momentary and Accumulated Energy
Figure 24 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from
50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and
100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the
accumulated power curve. The described sampling method works reliably, even in the presence of dynamic
phase shift and harmonic distortion.
3.2
Battery Modes
Shortly after system power (V3P3SYS) is applied, the 71M6543 is in mission mode (MSN mode). MSN
mode means that the part is operating with system power and that the internal PLL is stable. This mode
is the normal operating mode where the part is capable of measuring energy.
74
v2
71M6543F/71M6543G Data Sheet
When system power is not available, the 71M6543 is in one of three battery modes:
•
•
•
BRN mode (brownout mode)
LCD mode (LCD-only mode)
SLP mode (sleep mode).
An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are
typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 2.8 VDC, the
comparator resets an internal power status bit called V3OK . As soon as system power is removed and
V3OK = 0, the 71M6543 is forced to BRN mode. The MPU continues to execute code when the system
transitions from MSN to BRN mode or from BRN to MSN mode. A soft reset should be executed when
returning from BRN to MSN mode in order to re-initialize the I/O RAM. Depending on the MPU code, the
MPU can choose to stay in BRN mode, or transition to LCD or to SLP mode (via the I/O RAM bits
LCD_ONLY, I/O RAM 0x28B2[6] and SLEEP, I/O RAM 0x28B2[7]). BRN mode is similar to MSN mode except
that resources powered by system power, such as the ADC and the CE, are not available (see Table 61),
and that the supply current is drawn from the VBAT pin. In BRN mode, the PLL continues to function at
the same frequency as in MSN mode. The MPU can configure BRN mode as it desires. For instance, it
may choose to minimize battery power by reducing the PLL or MPU clock speed (see 3.2.1 BRN Mode,
for the recommended settings to realize minimum power consumption in BRN mode).
When system power is restored, the 71M6543 automatically transitions from any of the battery modes
(BRN, LCD, SLP) back to MSN mode.
Figure 25 shows a state diagram of the various operating modes, with the possible transitions between modes.
When the part wakes-up under battery power, the part automatically enters BRN mode (see 3.4 Wake-Up
Behavior). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU.
MSN
RESET
V3P3SYS
falls
VSTAT=00X
V3P3SYS
rises
System Power
Battery Power
VSTAT=001
V3P3SYS
rises
LCD_ONLY
BRN
V3P3SYS
rises
RESET &
VBAT
sufficient
Wake Flags
SLEEP or
VBAT
insufficient
Wake
event
LCD
Wake
event
VBAT
insufficient
VBAT
insufficient
RESET &
VBAT
insufficient
SLP
Figure 25: Operation Modes State Diagram
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75
71M6543F/71M6543G Data Sheet
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
Wake-up timer timeout.
Pushbutton (PB) is activated.
A rising edge on SEGDIO4, or a high logic level on SEGDIO52 or SEGDIO55.
Activity on the RX or OPT_RX pins.
•
•
•
•
The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4
Wake-Up Behavior for details.
Table 61 shows the circuit functions available in each operating mode.
Table 61: Available Circuit Functions
Circuit Function
CE (Computation Engine)
FIR
ADC, VREF
PLL
Battery Measurement
Temperature sensor
Max MPU clock rate
System Power
MSN (Mission Mode)
PLL_FAST=1 PLL_FAST=0
Yes
Yes
Yes
Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Battery Power
BRN (Brownout Mode)
LCD
PLL_FAST=1 PLL_FAST=0
--1
--Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
---Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SLEEP
---Boost2
-Yes
-----Yes
--
--
MPU_DIV clk. divider
--ICE
--DIO Pins
--Watchdog Timer
--LCD
Yes
-LCD Boost
Yes
EEPROM Interface (2-wire)
--EEPROM Interface (3-wire)
--UART (full speed)
--Optical TX modulation
--Flash Read
--Flash Page Erase
--Flash Write
--RAM Read and Write
--Wakeup Timer
Yes
Yes
OSC and RTC
Yes
Yes
DRAM data preservation
--NV RAM data preservation
Yes
Yes
Notes:
1. “--“ indicates that the corresponding circuit is not active
2. “Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6])). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.
76
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71M6543F/71M6543G Data Sheet
3.2.1
BRN Mode
In BRN mode, most non-metering digital functions are active (as shown in Table 61) including ICE, UART,
EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN
mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU
frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power.
From BRN mode, the MPU can choose to enter LCD or SLP modes. When system power is restored
while the 71M6543 is in BRN mode, the part automatically transitions to MSN mode.
The recommended minimum power configuration for BRN mode is as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RCE0 = 0x00 (I/O RAM 0x2709[7:0]) - remote sensors disabled
LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT
LCD_VMODE[1:0] = 0 (I/O RAM 0x2401[7:6]) - 5V LCD boost disabled
CE6 = 0x00 (I/O RAM 0x2106) - CE, RTM and CHOP are disabled
MUX_DIV[3:0] = 0(I/O RAM 0x2100[7:4]) - the ADC multiplexer is disabled
ADC_E = 0 (I/O RAM 0x2704[4]) - ADC disabled
VREF_CAL = 0 (I/O RAM 0x2704[7]) – Vref not driven out
VREF_DIS = 1 (I/O RAM 0x2704[6]) - Vref disabled
PRE_E = 0 (I/O RAM 0x2704[5] - pre-amp disabled
BCURR = 0 (I/O RAM 0x2704[3]) - battery 100µA current load OFF
TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) – TMUXOUT output set to a dc value
TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set to a dc value
CKGN = 0x24 (I/O RAM 0x2200) - PLL set slow, and MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum
TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - temp measurement set to automatic every 512 s
TEMP_BSEL = 1 (I/O RAM 0x28A0[7]) - temperature sensor monitors VBAT
PCON |= 1 (SFR 0x87) - at the end of the main BRN loop, halt the MPU and wait for an interrupt
The baud rate registers are adjusted as needed
All unused interrupts are disabled
3.2.2
LCD Mode
LCD mode may be commanded by the MPU at any time by setting the LCD_ONLY control bit (I/O RAM
0x28B2[6]). However, it is recommended that the LCD_ONLY control bit be set by the MPU only after the
71M6543 has entered BRN mode. For example, if the 71M6543 is in MSN mode when LCD_ONLY is set,
the duration of LCD mode is very brief and the 71M6543 immediately 'wakes'.
In LCD mode, V3P3D is disabled, and the VBAT pin supplies the LCD current. Before asserting
LCD_ONLY mode, it is recommended that the MPU minimize PLL current by reducing the output
frequency of the PLL to 6.29 MHz (i.e., write PLL_FAST = 0, I/O RAM 0x2200[4]). The LCD boost system
requires a clock from the PLL for its operation. Thus, if the LCD boost system is enabled (i.e.,
LCD_VMODE[1:0] = 10, I/O RAM 0x2401[7:6]), then the PLL is automatically kept active during LCD
mode, otherwise the PLL is de-activated.
In LCD mode, the data contained in the LCD_SEG registers is displayed using the segment driver pins.
Up to two LCD segments connected to the pins SEGDIO22 and SEGDIO23 can be made to blink without
the involvement of the MPU, which is disabled in LCD mode. To minimize battery power consumption,
only segments that are used should be enabled.
After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x0000, the
XRAM is in an undefined state, and configuration I/O RAM bits are reset (see Table 70 for I/O RAM state
upon wake). The data stored in non-volatile I/O RAM locations is preserved in LCD mode (the shaded
locations in Table 70 are non-volatile).
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71M6543F/71M6543G Data Sheet
3.2.3
SLP Mode
The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the
SLEEP bit (I/O RAM 0x28B2[7]). The purpose of the SLP mode is to consume the least power while still
maintaining the RTC, temperature compensation of the RTC, and the non-volatile portions of the I/O RAM.
In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from VBAT and V3P3SYS.
The non-volatile memory domain and the basic functions, such as temperature sensor, oscillator, and
RTC, are powered by the VBAT_RTC input. In this mode, the I/O configuration bits, LCD configuration
bits, and NV RAM values are preserved and RTC and oscillator continue to run. This mode can be exited
only by system power-up or one of the wake methods described in 3.4 Wake-Up Behavior.
If the SLEEP bit is asserted when V3P3SYS pin power is present (i.e., while in MSN mode), the 71M6543
enters SLP mode, resetting the internal WAKE signal, at which point the 71M6543 begins the standard
wake from sleep procedures as described in 3.4 Wake-Up Behavior.
After the transition from SLP mode to MSN or BRN mode the PC is at 0x0000, the XRAM is in an
undefined state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in
5.2). The non-volatile sections of the I/O RAM are preserved unless RESET goes high.
78
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71M6543F/71M6543G Data Sheet
3.3
Fault and Reset Behavior
3.3.1
Events at Power-Down
Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and
also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be
tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A
pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage. The following
discussion assumes that the V3P3A and V3P3SYS pins are tied together at the PCB level.
During a power failure, as V3P3A falls, two thresholds are detected:
The first threshold, at 3.0 VDC (VSTAT[2:0] = 001, SFR 0xF9[2:0]), warns the MPU that the analog
modules are no longer accurate. Other than warning the MPU, the hardware takes no action when
this threshold is crossed. This comparison produces an internal bit named V3OKA.
The second threshold, at 2.8 VDC, causes the 71M6543 to switch to battery power. This switching
happens while the FLASH and RAM systems are still able to read and write. This comparison
produces an internal bit named V3OK.
•
•
The power quality is reflected by the VSTAT[2:0] register in I/O RAM space, as shown in Table 62. The
VSTAT[2:0] register is located at SFR address F9 and occupies bits 2:0. The VSTAT[2:0] field can only be
read.
In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal
VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the 71M6543
always switches from battery to system power.
Table 62: VSTAT[2:0] (SFR 0xF9[2:0])
VSTAT[2:0]
000
001
010
011
101
Description
System Power OK. V3P3A > 3.0 VDC. Analog modules are functional and accurate.
System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Analog modules not accurate.
Switch over to battery power is imminent.
The IC is on battery power and VDD is OK. VDD > 2.25 VDC. The IC has full digital
functionality.
The IC is on battery power and 2.25 VDC > VDD > 2.0 VDC. Flash write operations are
inhibited.
The IC is on battery power and VDD < 2.0, which means that the MPU is nearly out of
voltage. A reset occurs in 4 cycles of the crystal clock CK32.
The response to a system power fault is almost entirely controlled by firmware. During a power failure,
system power slowly falls. This fall in power is monitored by internal comparators that cause the
hardware to automatically switch over to taking power from the VBAT input. An interrupt notifies the MPU
that the part is now battery powered. At this point, it is the MPU’s responsibility to reduce power by
slowing the clock rate, disabling the PLL, etc.
Precision analog components such as the bandgap reference, the bandgap buffer, and the ADC are
powered only by the V3P3A pin and become inaccurate and ultimately unavailable as the V3P3A pin
voltage continues to drop (i.e., circuits powered by the V3P3A pin are not backed by the VBAT pin).
When the V3P3A pin falls below 2.8 VDC, the ADC clocks are halted and the amplifiers are unbiased.
Meanwhile, control bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O RAM
storage is powered from the VDD pin (2.5 VDC). The VDD pin is supplied with power through an internal
2.5 VDC regulator that is connected to the V3P3D pin. In turn, the V3P3D pin is switched to receive
power from the VBAT pin when the V3P3SYS pin drops below 3.0 VDC. Note that the V3P3SYS and
V3P3A pins are typically tied together at the PCB level.
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79
71M6543F/71M6543G Data Sheet
3.3.2
IC Behavior at Low Battery Voltage
When system power is not present, the 71M6543 relies on the VBAT pin for power. If the VBAT voltage is
not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage
can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode. Two cases
can be distinguished, depending on MPU code:
•
•
Case 1: System power is not present, and the part is waking from SLP or LCD mode. In this case,
the hardware checks the value of VDD to determine if processor operation is possible. If it is not
possible, the part configures itself for BRN operation, and holds the processor in reset (WAKE=0). In
this mode, VBAT powers the 1.0 VDC reference for the LCD system, the VDD regulator, the PLL, and
the fault comparator. The part remains in this waiting mode until VDD becomes high due to system
power being applied or the VBAT battery being replaced or recharged.
Case 2: The part is operating under VBAT power and VSTAT[2:0] (SFR 0xF9[2:0]) becomes 101,
indicating that VDD falls below 2.0 VDC. In this case, the firmware has two choices:
1) One choice is to assert the SLEEP bit (I/O RAM 0x28B2[7]) immediately. This assertion preserves
the remaining charge in VBAT. Of course, if the battery voltage is not increased, the 71M6543
enters Case 1 as soon as it tries to wake up.
2) The alternative choice is to enter the waiting mode described in Case 1 immediately. Specifically,
if the firmware does not assert the SLEEP bit, the hardware resets the processor four CE32 clock
cycles (i.e. 122 µs) after VSTAT[2:0] becomes 101 and, as described in Case 1, it begins waiting
for VDD to become greater than 2.0 VDC. The MPU wakes up when system power returns, or
when VDD becomes greater than 2.0 VDC.
In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2])
can be read to determine that the processor is recovering from a bad VBAT condition. The WF_BADVDD
flag remains set until the next time WAKE falls. This flag is independent of the other WF flags.
In all cases, low VBAT voltage does not corrupt RTC operation, the state of NV memory, or the state of
non-volatile memory. These circuits depend on the VBAT_RTC pin for power.
3.3.3
Reset Sequence
When the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator
and RTC. Additionally, all I/O RAM bits are forced to their RST state. A reliable reset does not occur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC are not reset unless the TEST pin
is pulled high while RESET is high.
The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a
significantly shorter reset timer is used.
Once initiated, the reset sequence waits until the reset timer times out. The time out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from
address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences.
If system power is not present, the reset timer duration is two CE32 cycles, at which time the MPU begins
executing in BRN mode, starting at address 0x0000.
A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event causes
the MPU and other registers in the MPU core to be reset but does not reset the remainder of the
71M6543. It does not trigger the reset sequence. This type of reset is intended to reset the MPU
program, but not to make other changes to the chip’s state.
3.3.4
Watchdog Timer (WDT) Reset
The watchdog timer (WDT) is described in 2.5.13.
A status bit, WF_OVF (I/O RAM 0x28B0[4]), is set when a WDT overflow occurs. Similar to the other wake
flags, this bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is
initializing after a WD overflow event or after a power-up. The WF_OVF bit is cleared by the RESET pin.
There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT
can be disabled by raising the ICE_E pin to 3.3 VDC.
80
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71M6543F/71M6543G Data Sheet
In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP mode, and
when ICE_E=1.
3.4
Wake-Up Behavior
As described above, the part always wakes up in MSN mode when system power is restored. As stated
in 3.2 Battery Modes, transitions from both LCD and SLP mode to BRN mode can be initiated by a wakeup timer timeout, when the pushbutton (PB) input is activated, a rising edge on SEGDIO4, or a high logic
level on SEGDIO52 or SEGDIO55, or by activity on the RX or OPT_RX pins.
3.4.1
Wake on Hardware Events
The following pin signal events wake the 71M6543 from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin, or a high level on
the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 63 for de-bounce details on each pin and
for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52, and SEGDIO55 pins must
be configured as DIO inputs and their wake enable (EW_x bits) must be set. In SLP and LCD modes, the
MPU is held in reset and cannot poll pins or react to interrupts. When one of the hardware wake events
occurs, the internal WAKE signal rises and within three CK32 cycles the MPU begins to execute. The
MPU can determine which one of the pins awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4,
WF_DIO52, or WF_DIO55 flags (see Table 63).
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so it may be pulled high by a push button depression.
Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial
transition. Table 63 shows which pins are equipped with de-bounce circuitry.
Pins that do not have de-bounce circuits must still be high for at least 2 µs to be recognized.
The wake enable and flag bits are shown in Table 63. The wake flag bits are set by hardware when the
MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the part
is already awake. Table 65 lists the events that clear the WF flags.
In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in Table 63, each of these
mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wakeup is caused by
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicates that
system power is stable.
Table 63: Wake Enable and Flag Bits
Wake Enable
Wake Flag
Description
Location
Name
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake on Timer.
EW_PB
28B3[3]
WF_PB
28B1[3]
Yes
Wake on PB.*
EW_RX
28B3[4]
WF_RX
28B1[4]
2 µs
Wake on either edge of RX.
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2 µs
Wake on SEGDIO4.
EW_DIO52
28B3[1]
WF_DIO52
28B1[1]
Yes
Wake on SEGDIO52.*
EW_DIO55
v2
Location
De-bounce
Name
WF_DIO55
28B1[0]
Yes
Always Enabled
Always Enabled
WF_RST
WF_RSTBIT
28B0[6]
28B0[5]
2 µs
No
Always Enabled
WF_ERST
28B0[3]
2 µs
28B3[0]
OPT_RXDIS = 1: Wake on DIO55 with
64 ms de-bounce.*
OPT_RXDIS = 0: Wake on either edge
of OPT_RX with 2 µs de-bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Wake after RESET.
Wake after RESET bit.
Wake after E_RST.
(ICE must be enabled)
81
71M6543F/71M6543G Data Sheet
Wake Enable
Name
Location
Always Enabled
Wake Flag
Name
Location
WF_OVF
28B0[4]
De-bounce
Description
No
Wake after WD reset.
Wake after cold start - the first
WF_CSTART
Always Enabled
28B0[7]
No
application of power.
Wake after insufficient VBAT
WF_BADVDD
Always Enabled
28B0[2]
No
voltage.
*This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This pin is highlevel sensitive.
Table 64: Wake Bits
Name
Location
RST
WK
Dir
EW_DIOR
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
WAKE_ARM
28B2[5]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
WF_DIO4
28B1[2]
0
–
R
WF_DIO52
28B1[1]
0
–
R
WF_DIO55
28B1[0]
0
–
R
WF_TMR
WF_PB
WF_RX
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
0
0
0
*
*
*
*
*
–
–
–
R
R
R
82
–
R
Description
Connects SEGDIO4 to the WAKE logic and permits
SEGDIO4 rising to wake the part. This bit has no effect
unless SEGDIO4 is configured as a digital input.
Connects DIO52 to the WAKE logic and permits DIO52
high level to wake the part. This bit has no effect unless
DIO52 is configured as a digital input.
Connects DIO55 to the WAKE logic and permits DIO55
high level to wake the part. This bit has no effect unless
DIO55 is configured as a digital input.
Arms the WAKE timer and loads it with the value in
WAKE_TMR (I/O RAM 0x2880) register. When SLP or
LCD mode is asserted by the MPU, the WAKE timer
becomes active.
Connects the PB pin to the WAKE logic and permits PB
high level to wake the part. PB is always configured as
an input.
Connects the RX pin to the WAKE logic and permits
RX rising to wake the part. See 3.4.1 for de-bounce
issues.
SEGDIO4 flag bit. If SEGDIO4 is configured to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO4 is not configured for wakeup.
SEGDIO52 flag bit. If SEGDIO52 is configured to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not configured
for wakeup.
SEGDIO55 flag bit. If SEGDIO55 is configured to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not configured
for wakeup.
Indicates that the Wake timer caused the part to wake up.
Indicates that the PB pin caused the part to wake.
Indicates that RX pin caused the part to wake.
Indicates that the RST pin, E_RST pin, RESET bit (I/O
RAM 0x2200[3]), the cold start detector, or low voltage
on the VBAT pin caused the part to reset.
*See Table 65 for details.
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71M6543F/71M6543G Data Sheet
Table 65: Clear Events for WAKE flags
Flag
Wake on:
Clear Events
WF_TMR
Timer expiration
WF_PB
PB pin high level
WAKE falls
WF_RX
Either edge RX pin
WAKE falls
WF_DIO4
SEGDIO4 rising edge
WAKE falls
WF_DIO52
SEGDIO52 high level
If OPT_RXDIS = 1 (I/O RAM 0x2457[2]),
wake on SEGDIO55 high
If OPT_RXDIS = 0
wake on either edge of OPT_RX
WAKE falls
RESET pin driven high
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_OVF, WF_BADVDD
RESET bit is set (I/O RAM 0x2200[3])
WAKE falls, WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
WF_DIO55
WF_RST
WF_RSTBIT
WF_ERST
WF_OVF
WF_CSTART
E_RST pin driven high and the ICE
interface must be enabled by driving the
ICE_E pin high.
Watchdog (WD) reset
Cold-start (i.e., after the application of
first power)
WAKE falls
WAKE falls
WAKE falls, WF_CSTART, WF_RST,
WF_OVF, WF_RSTBIT
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
WAKE falls, WF_RSTBIT, WF_OVF,
WF_BADVDD, WF_RST
Note:
“WAKE falls” implies that the internal WAKE signal has been reset, which happens automatically upon
entry into LCD mode or SLEEP mode (i.e., when the MPU sets the LCD_ONLY bit (I/O RAM 0x28B2[6]) or
the SLEEP (I/O RAM 0x28B2[7]) bit). When the internal WAKE signal resets, all wake flags are reset. Since
the various wake flags are automatically reset when WAKE falls, it is not necessary for the MPU to reset
these flags before entering LCD mode or SLEEP mode. Also, other wake events can cause the wake flag
to reset, as indicated above (e.g., the WF_RST flag can also be reset by any of the following flags setting:
WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD)
3.4.2
Wake on Timer
If the part is in SLP or LCD mode, it can be awakened by the Wake Timer. Until this timer times out, the
MPU is in reset due to the internal WAKE signal being low. When the Wake Timer times out, WAKE rises
and within three CK32 cycles, the MPU begins to execute. The MPU can determine that the timer woke it
by checking the WF_TMR (I/O RAM 0x28B1[2]) wake flag.
The Wake Timer begins timing when the part enters LCD or SLP mode. Its duration is controlled by the
WAKE_TMR[7:0] register (I/O RAM 0x2880). The timer duration is WAKE_TMR[7:0] +1 seconds.
The Wake Timer is armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2[5]). It must be armed at least
three RTC cycles before either SLP or LCD modes are initiated. Setting WAKE_ARM presets the timer
with the value in WAKE_TMR and readies the timer to start when the MPU writes to the SLEEP (I/O RAM
0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. The timer is neither reset nor disarmed when the
MPU wakes-up. Thus, once armed and set, the MPU continues to be awakened WAKE_TMR[7:0]
seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds
its value and does not have to be re-written each time the MPU enters SLP or LCD mode. Also, since
WAKE_TMR[7:0] is non-volatile, it also holds its value through resets and power failures).
3.5
Data Flow and MPU/CE Communication
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 26. In a typical application,
the 32-bit CE sequentially processes the samples from the ADC inputs, performing calculations to measure
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83
71M6543F/71M6543G Data Sheet
2
2
active power (Wh), reactive power (VARh), A h, and V h for four-quadrant metering. These measurements
are then accessed by the MPU, processed further and output using the peripheral devices available to the
MPU.
Both the CE and multiplexer are controlled by the MPU via shared registers in the I/O RAM and in RAM.
The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts:
•
•
•
•
CE_BUSY
XFER_BUSY
WPULSE, VPULSE (pulses for active and reactive energy)
XPULSE, YPULSE (auxiliary pulses)
These interrupts are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY
indicates that the CE is actively processing data. This signal occurs once every multiplexer cycle (typically
396 µs), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80).
XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This update occurs
whenever the CE has finished generating a sum by completing an accumulation interval determined by
SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 2108[7:0], (typically every 1000 ms). Interrupts to the MPU occur
on the falling edges of the XFER_BUSY and CE_BUSY signals.
WPULSE and VPULSE are typically used to signal energy accumulation of real (Wh) and reactive (VARh)
energy. Tying WPULSE and VPULSE into the MPU interrupt system can support pulse counting.
XPULSE and YPULSE can be used to signal events such as sags and zero crossings of the mains voltage
to the MPU. Tying these outputs into the MPU interrupt system relieves the MPU from having to read the
CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing
events.
Refer to 5.3 CE Interface Description on page 116 for additional information on setting up the device
using the MPU firmware.
Pulses
XPULSE
YPULSE
Interrupts
VPULSE
WPULSE
CE_BUSY
XFER_BUSY
CE
Samples
Processed
Metering
Data
CESTATUS
CECONFIG
MUX
Control
MPU
Control
Control
XRAM
I/O RAM (Configuration RAM)
Figure 26: MPU/CE Data Flow
84
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71M6543F/71M6543G Data Sheet
4
Application Information
4.1
Connecting 5 V Devices
All digital input pins of the 71M6543 are compatible with external 5 V devices. I/O pins configured as
inputs do not require current-limiting resistors when they are connected to external 5 V devices.
4.2
Directly Connected Sensors
Figure 27 through Figure 30 show voltage-sensing resistive dividers, current-sensing current transformers
(CTs) and current-sensing resistive shunts and how they are connected to the voltage and current inputs
of the 71M6543. All input signals to the 71M6543 sensor inputs are voltage signals providing a scaled
representation of either a sensed voltage or current.
The analog input pins of the 71M6543 are designed for sensors with low source impedance.
RC filters with resistance values higher than those implemented in the Demo Boards must not
be used. Refer to the Demo Board schematics for complete sensor input circuits and
corresponding component values.
VADCn
(n = 8, 9 or 10)
VIN
ROUT
V3P3A
Figure 27: Resistive Voltage Divider (Voltage Sensing)
IIN
IOUT
IADCn
(n = 0,1,...7)
CT
RBURDEN
VOUT
Noise Filter
V3P3A
1:N
Figure 28. CT with Single-Ended Input Connection (Current Sensing)
IIN
IOUT
IADCn
(n = 0, 2, 4 or 6)
V3P3A
CT
RBURDEN
VOUT
IADCn+1
Bias Network and Noise Filter
1:N
Figure 29: CT with Differential Input Connection (Current Sensing)
IIN
IADCn
(n = 2, 4 or 6)
V3P3A
RSHUNT
VOUT
IADCn+1
Bias Network and Noise Filter
Figure 30: Differential Resistive Shunt Connections (Current Sensing)
v2
85
71M6543F/71M6543G Data Sheet
4.3
Systems Using 71M6xx3 Isolated Sensors and Current Shunts
Figure 31 shows a typical connection for current shunt sensors; using the 71M6xx3 (polyphase) isolated
sensors. Note that one shunt current sensor is connected without isolation, which is the neutral current
sensor in this example (connected to pins IADC0-IADC1). Each 71M6xx3 device is electrically isolated
by a low-cost pulse transformer. The 71M6543 current sensor inputs must be configured for remote
sensor communications, as described in 2.2.8 71M6xx3 Isolated Sensor Interface (page 22). Flexible
remapping using the I/O RAM registers MUXn_SEL[3:0] allows the sequence of analog input pins to be
different from the standard configuration (a corresponding CE code must be used). See Figure 2 for the
AFE configuration corresponding to Figure 31.
C
Shunt Current Sensors
LOAD
NEUTRAL
B
A
POWER SUPPLY
Resistor Dividers
71M6xx3
71M6xx3
71M6xx3
NEUTRAL
Pulse Transformers
Note: This system is referenced to Neutral
3x 71M6xx3
MUX and ADC
IADC0
IADC1 }IN*
VADC10 (VC)
IADC6
IADC7 }IC
VADC9 (VB)
IADC4
IADC5 }IB
VADC8 (VA)
IADC2
IADC3 }IA
AMR
IR
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
71M6543F/
71M6543G
RAM
SERIAL PORTS
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
FLASH
MEMORY
POWER FAULT
COMPARATOR
HOST
SPI INTERFACE
*IN = Neutral Current
MPU
RTC
TIMERS
ICE
BATTERY
VBAT
VBAT_RTC
TEMPERATURE
SENSOR
VREF
TX
WAKE-UP
REGULATOR
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
XOUT
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
9/17/2010
Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor
86
v2
71M6543F/71M6543G Data Sheet
4.4
System Using Current Transformers
Figure 32 shows a polyphase system using four current transformers to support optional Neutral current
sensing for anti-tamper purposes. The Neutral current sensing CT can be omitted if Neutral current
sensing is not required. The system is referenced to Neutral (i.e., the Neutral rail is tied to V3P3A and
V3P3SYS).
Current Transformers
A
LOAD
NEUTRAL
B
C
Note: This system is referenced to Neutral
POWER SUPPLY
NEUTRAL
Resistor Dividers
MUX and ADC
IADC2
}IA
IADC3
VADC8 (VA)
IADC4 }IB
IADC5
VADC9 (VB)
IADC6
}IC
IADC7
VADC10 (VC)
IADC0
}IN*
IADC1
AMR
IR
PWR MODE
CONTROL
71M6543F/
71M6543G
TEMPERATURE
SENSOR
RAM
SERIAL PORTS
COMPUTE
ENGINE
TX
RX
MODUL- RX
ATOR TX
SPI INTERFACE
WAKE-UP
REGULATOR
FLASH
MEMORY
MPU
RTC
TIMERS
ICE
*IN = Optional Neutral Current
BATTERY
VBAT
VBAT_RTC
VREF
POWER FAULT
COMPARATOR
HOST
V3P3A V3P3SYS GNDA GNDD
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
XOUT
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
9/17/2010
Figure 32. System Using Current Transformers
v2
87
71M6543F/71M6543G Data Sheet
4.5
Metrology Temperature Compensation
4.5.1
Temperature Compensation
Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2])
control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage
references (VREF), is automatically removed by the chopper circuit. Both the 71M6543 and the 71M6xx3
feature chopper circuits for their respective VREF voltage reference.
Since the variation in the bandgap reference voltage (VREF) is the major contributor to measurement
error across temperatures, Maxim implements a two-step procedure to trim and characterize the VREF
voltage reference during the device manufacturing process.
The first step in the process is applied to all parts (71M6543F, 71M6543G). In this first step, the reference
voltage (VREF) is trimmed to a target value of 1.195V. During this trimming process, the TRIMT[7:0] (I/O
RAM 0x2309) value is stored in non-volatile fuses. TRIMT[7:0] is trimmed to a value that results in
minimum VREF variation with temperature.
For the 71M6543F and 71M6543G devices, the TRIMT[7:0] value can be read by the MPU during
initialization in order to calculate parabolic temperature compensation coefficients suitable for each
individual 71M6543F and 71M6543G device. The resulting temperature coefficient for VREF in the
71M6543F and 71M6543G is ±40 ppm/°C.
Considering the factory calibration temperature of VREF to be +22°C and the industrial temperature
range (-40°C to +85°C), the VREF error at the temperature extremes for the 71M6543F and 71M6543G
devices can be calculated as:
(85o C − 22 o C ) ⋅ 40 ppm / oC = +2520 ppm = +0.252%
and
(−40 o C − 22 o C ) ⋅ 40 ppm / oC = −2480 ppm = −0.248%
The above calculation implies that both the voltage and the current measurements are individually
subject to a theoretical maximum error of approximately ±0.25%. When the voltage sample and current
sample are multiplied together to obtain the energy per sample, the voltage error and current error
combine resulting in approximately ±0.5% maximum energy measurement error. However, this
theoretical ±0.5% error considers only the voltage reference (VREF) as an error source. In practice,
other error sources exist in the system. The principal remaining error sources are the current sensors
(shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage divider
used to measure the voltage. The 71M6543F and 71M6543G devices should be used in Class 1%
designs, to allow margin for the other error sources in the system.
The preceding discussion in this section also applies to the 71M6603 (0.5%), 71M6113 (0.5%) and
71M6203 (0.1%) remote sensors. Refer to the 71M6xxx Data Sheet for details.
4.5.2
Temperature Coefficients for the 71M6543F and 71M6543G
The equations provided below for calculating TC1 and TC2 apply to the 71M6543F and 71M6543G. In order
to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2 equations
provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting tracking of
the reference voltage (VREF) is within ±40 ppm/°C.
TC1( µV / °C ) = 275 − 4.95 ⋅ TRIMT
TC 2( µV / °C 2 ) = −0.557 − 0.00028 ⋅ TRIMT
PPMC = 22.4632 ⋅ TC1
PPMC 2 = 1150.116 ⋅ TC 2
See 4.5.4 and 4.5.5 below for further temperature compensation details.
88
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71M6543F/71M6543G Data Sheet
4.5.3
Temperature Coefficients for the 71M6xx3
Refer to the 71M6xxx Data sheet for the equations that are applicable to each 71M6xx3 part number and
the corresponding temperature coefficients.
4.5.4
Temperature Compensation for VREF and Shunt Sensors
This section discusses metrology temperature compensation for the meter designs where current shunt
sensors are used in conjunction with the 71M6xx3 remote isolated sensors, as shown in Figure 31.
Sensors that are directly connected to the 71M6543 are affected by the voltage variation in the 71M6543
VREF due to temperature. On the other hand, shunt sensors that are connected to 71M6xx3 remote
sensor are affected by the VREF in the 71M6xx3. The VREF in both the 71M6543 and 71M6xx3 can be
compensated digitally using a second-order polynomial function of temperature. The 71M6543 and
71M6xx3 feature temperature sensors for the purposes of temperature compensating their corresponding
VREF. The compensation computations must be implemented in MPU firmware.
Referring to Figure 31, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are always
directly connected to the 71M6543. Thus, the precision of the voltage sensors is primarily affected by
VREF in the 71M6543. The temperature coefficient of the resistors used to implement the voltage dividers
for the voltage sensors (see Figure 27) determine the behavior of the voltage division ratio with respect to
temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire
voltage divider using resistors belonging to the same technology family, in order to minimize the temperature
dependency of the voltage division ratio. The resistors must also have suitable voltage ratings.
The 71M6543 also may have one local current shunt sensor that is connected directly to it via the IADC0IADC1 input pins, and therefore this local current sensor is also affected by the VREF in the 71M6543.
The shunt current sensor resistance has a temperature dependency, which also may require
compensation, depending on the required accuracy class.
The IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current sensors are isolated by the 71M6xx3 and
depend on the VREF of the 71M6xx3, plus the variation of the corresponding remote shunt current sensor
with temperature.
The MPU has the responsibility of computing the necessary sample gain compensation values required for
each sensor channel based on the sensed temperature. Maxim provides demonstration code that
implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are
stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The
demonstration code thus provides a suitable implementation of temperature compensation, but other
methods are possible in MPU firmware by utilizing the on-chip temperature sensors while storing the
sample gain adjustment results in the CE RAM GAIN_ADJx storage locations for use by the CE. The
demonstration code maintains five separate sets of PPMC and PPMC2 coefficients and computes five
separate GAIN_ADJx values based on the sensed temperature using the equation below:
10 ⋅ TEMP _ X ⋅ PPMC 100 ⋅ TEMP _ X 2 ⋅ PPMC 2
GAIN _ ADJx = 16385 +
+
214
2 23
The GAIN_ADJx values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply)
14
the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 2 )corresponds to
unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify
the samples.
In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in
o
multiples of 0.1 °C. The 10x and 100x factors seen in the above equation are due to 0.1 C scaling of
o
TEMP_X. For example, if the calibration (reference) temperature is 22 C and the measured temperature
o
o
o
is 27 C, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 C deviation from 22 C.
In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor
reading using the equation provided below and is scaled in 0.1°C units. See 2.5.5 71M6543 Temperature
Sensor on page 53 for the equation to calculate temperature in degrees °C from the STEMP[10:0] value.
Table 66 shows the five GAIN_ADJx equation output storage locations and the voltage or current sensor
channels for which they compensate for the 1 Local / 3 Remote configuration shown in Figure 31.
v2
89
71M6543F/71M6543G Data Sheet
Table 66: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1)
Gain Adjustment Output
CE RAM Address
GAIN_ADJ0
0x40
GAIN_ADJ1
0x41
GAIN_ADJ2
0x42
GAIN_ADJ3
0x43
GAIN_ADJ4
0x44
Sensor Channel(s)
(pin names)
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
IADC0-IADC1
IADC2-IADC3
IADC4-IADC5
IADC6-IADC7
Compensation For:
VREF in 71M6543 and Voltage Divider
Resistors
VREF in 71M6543 and Shunt
(Neutral Current)
VREF in 71M6xx3 and Shunt
(Phase A)
VREF in 71M6xx3 and Shunt
(Phase B)
VREF in 71M6xx3 and Shunt
(Phase C)
In the demonstration code, the shape of the temperature compensation second-order parabolic curve is
st
nd
determined by the values stored in the PPMC (1 order coefficient) and PPMC2 (2 order coefficient),
which are typically setup by the MPU at initialization time from values that are stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of the shunt current sensor
(if required) and the corresponding VREF voltage reference (summed together).
The shunt sensor requires a second order polynomial compensation which is determined by the PPMC
and PPMC2 coefficients for the corresponding current measurement channel. The corresponding VREF
voltage reference also requires the PPMC and PPMC2 coefficients to match the second order
temperature behavior of the voltage reference. The PPMC and PPMC2 values associated with the shunt
and with the corresponding VREF are summed together to obtain the compensation coefficients for a
st
nd
given current-sensing channel (i.e., the 1 order PPMC coefficients are summed together, and the 2
order PPMC2 coefficients are summed together).
In the 71M6543F and 71M6543G, the required VREF compensation coefficients PPMC and PPMC2 are
calculated from readable on-chip non-volatile fuses (see 4.5.2 Temperature Coefficients for the
71M6543F). These coefficients are designed to achieve ±40 ppm/°C for VREF in the 71M6543F and
71M6543G. PPMC and PPMC2 coefficients are similarly calculated for the 71M6xx3 remote sensor
(see 4.5.3 Temperature Coefficients for the 71M6xx3).
For the current channels, to determine the PPMC and PPMC2 coefficients for the shunt current
sensors, the designer must either know the average temperature curve of the shunt from its
manufacturer’s data sheet or obtain these coefficients by laboratory characterization of the shunt used
in the design.
4.5.5
Temperature Compensation of VREF and Current Transformers
This section discusses metrology temperature compensation for meter designs where Current
Transformer (CT) sensors are used, as shown in Figure 32.
Sensors that are directly connected to the 71M6543 are affected by the voltage variation in the 71M6543
VREF due to temperature. The VREF in the 71M6543 can be compensated digitally using a secondorder polynomial function of temperature. The 71M6543 features a temperature sensor for the purposes
of temperature compensating its VREF. The compensation computations must be implemented in MPU
firmware and written to the corresponding GAIN_ADJx CE RAM location.
Referring to Figure 32, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are directly
connected to the 71M6543. Thus, the precision of the voltage sensors is primarily affected by VREF in the
71M6543. The temperature coefficient of the resistors used to implement the voltage dividers for the voltage
sensors (see Figure 27) determine the behavior of the voltage division ratio with respect to temperature. It is
recommended to use resistors with low temperature coefficients, while forming the entire voltage divider
using resistors belonging to the same technology family, in order to minimize the temperature dependency of
the voltage division ratio. The resistors must also have suitable voltage ratings.
The Current Transformers are directly connected to the 71M6543 and are therefore primarily affected by the
VREF temperature dependency in the 71M6543. For best performance, it is recommended to use the
90
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71M6543F/71M6543G Data Sheet
differential signal conditioning circuit, as shown in Figure 29, to connect the CTs to the 71M6543. Current
transformers may also require temperature compensation. The copper wire winding in the CT has dc
resistance with a temperature coefficient, which makes the voltage delivered to the burden resistor
temperature dependent, and the burden resistor also has a temperature coefficient. Thus, each CT sensor
channel needs to compensate for the 71M6543 VREF, and optionally for the temperature dependency of the
CT and its burden resistor depending on the required accuracy class.
The MPU has the responsibility of computing the necessary sample gain compensation values required for
each sensor channel based on the sensed temperature. Maxim provides demonstration code that
implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are
stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The
demonstration code thus provides a suitable implementation of temperature compensation, but other
methods are possible in MPU firmware by utilizing the on-chip temperature sensor while storing the sample
gain adjustment results in the CE RAM GAIN_ADJn storage locations. The demonstration code maintains
five separate sets of PPMC and PPMC2 coefficients and computes five separate GAIN_ADJn values
based on the sensed temperature using the equation below:
GAIN _ ADJx = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC 100 ⋅ TEMP _ X 2 ⋅ PPMC 2
+
214
2 23
The GAIN_ADJn values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply)
14
the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 2 )corresponds to
unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify
the samples.
In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in
o
multiples of 0.1 °C. The 10x and 100x factors seen in the above equation are due to 0.1 C scaling of
TEMP_X. For example, if the calibration (reference) temperature is 22 °C and the measured temperature
is 27 °C, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 °C deviation from 22 °C.
In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor
reading using the equation provided below and is scaled in 0.1°C units. See 2.5.5 71M6543 Temperature
Sensor on page 53 for the equation to calculate temperature in °C from the STEMP[10:0] reading.
Table 67 shows the five GAIN_ADJx equation output storage locations and the voltage or current
measurements for which they compensate.
Table 67: GAIN_ADJx Compensation Channels (Figure 3, Figure 32, Table 2)
Gain Adjustment Output
CE RAM Address
GAIN_ADJ0
0x40
GAIN_ADJ1
0x41
GAIN_ADJ2
0x42
GAIN_ADJ3
0x43
GAIN_ADJ4
0x44
Sensor Channel(s)
(pin names)
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
IADC0-IADC1
Compensation For:
VREF in 71M6543 and Voltage Divider
Resistors
VREF in 71M6543, CT and Burden
Resistor (Neutral Current)
IADC2-IADC3
VREF in 71M6543, CT and Burden
Resistor (Phase A)
IADC4-IADC5
VREF in 71M6543, CT and Burden
Resistor (Phase B)
IADC6-IADC7
VREF in 71M6543, CT and Burden
Resistor (Phase C)
In the demonstration code, the shape of the temperature compensation second-order parabolic curve is
st
nd
determined by the values stored in the PPMC (1 order coefficient) and PPMC2 (2 order coefficient),
which are typically setup by the MPU at initialization time from values that are stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected VREF temperature variation and optionally the
v2
91
71M6543F/71M6543G Data Sheet
corresponding sensor circuit (i.e., the CT and burden resistor for current channels or the resistor divider
network for the voltage channels).
In the 71M6543F and 71M6543G, the required VREF compensation coefficients PPMC and PPMC2 are
calculated from readable on-chip non-volatile fuses (see 4.5.2Temperature Coefficients for the
71M6543F). These coefficients are designed to achieve ±40 ppm/°C for VREF.
4.6
2
Connecting I2C EEPROMs
2
I C EEPROMs or other I C compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as shown in Figure 33.
Pullup resistors of roughly 10 kΩ to V3P3D (to ensure operation in BRN mode) should be used for both
SDCK and SDATA signals. The DIO_EEX (I/O RAM 0x2456[7:6]) field must be set to 01 in order to convert
2
the DIO pins SEGDIO2 and SEGDIO3 to I C pins SCL and SDATA.
10 kΩ
V3P3D
10 kΩ
EEPROM
DIO2
SDCK
DIO3
SDATA
71M6543
2
Figure 33: I C EEPROM Connection
4.7
Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as described in 2.5.11 EEPROM Interface on page 65.
4.8
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF
ceramic capacitor, as shown in Figure 34.
71M6543
RX
100 pF 10 k Ω
TX
RX
TX
Figure 34: Connections for UART0
92
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71M6543F/71M6543G Data Sheet
4.9
Optical Interface (UART1)
The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232
transceiver for example), or they can be used to directly operate optical components (for example, an
infrared diode and phototransistor implementing a FLAG interface). Figure 35 shows the basic connections
for UART1. The OPT_TX pin becomes active when the control field OPT_TXE (I/O RAM 0x2456[3:2]) is
set to 01.
The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV
(I/O RAM 0x2456[0]) and OPT_RXINV (I/O RAM 0x2457[1]), respectively.
The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not
available in BRN mode. The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The duty cycle is
controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]), which can select 50%, 25%, 12.5%, and 6.25% duty
cycle. A 6.25% duty cycle means OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital
signal thresholds. It may need an analog filter when receiving modulated optical signals.
With modulation, an optical emitter can be operated at higher current than nominal, enabling it to
increase the distance along the optical path.
If operation in BRN mode is desired, the external components should be connected to V3P3D. However,
it is recommended to limit the current to a few mA.
V3P3SYS
R1
71M6543
OPT_RX
100 pF
10 kΩ
Phototransistor
V3P3SYS
OPT_TX
R2
LED
Figure 35: Connection for Optical Components
4.10
Connecting the Reset Pin
Even though a functional meter does not necessarily need a reset switch, it is useful to have a reset
pushbutton for prototyping as shown in Figure 36, left side. The RESET signal may be sourced from
V3P3SYS (functional in MSN mode only), V3P3D (MSN and BRN modes), or VBAT (all modes, if a battery is
present), or from a combination of these sources, depending on the application.
For a production meter, the RESET pin should be protected by the by the external components
shown in Figure 36, right side. R1 should be in the range of 100Ω and mounted as closely as possible
to the IC.
Since the 71M6543 generates its own power-on reset, a reset button or circuitry, as shown in Figure 36, is
only required for test units and prototypes.
v2
93
71M6543F/71M6543G Data Sheet
VBAT/
V3P3D
71M6543
71M6543
V3P3D
R2
1k Ω
Reset
Switch
RESET
10k Ω
R1
0.1µF
GNDD
Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)
4.11
Connecting the Emulator Port Pins
Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection
from EMI as illustrated in Figure 37. Production boards should have the ICE_E pin connected to ground.
LCD Segments
(optional)
V3P3D
71M6543
ICE_E
62 Ω
E_RST
62 Ω
E_RXT
E_TCLK
62 Ω
22 pF 22 pF 22 pF
Figure 37: External Components for the Emulator Interface
4.12
Flash Programming
4.12.1 Flash Programming via the ICE Port
Operational or test code can be programmed into the flash memory using either an in-circuit emulator or
the Flash Programmer Module (TFP-2) available from Maxim. The flash programming procedure uses the
E_RST, E_RXTX, and E_TCLK pins.
4.12.2 Flash Programming via the SPI Port
It is possible to erase, read and program the flash memory of the 71M6543 via the SPI port. See 2.5.12
for a detailed description.
4.13
MPU Demonstration Code
All application-specific MPU functions mentioned in 4 Application Information are featured in the
demonstration C source code supplied by Maxim. The code is available as part of the Demonstration Kit
for the 71M6543. The Demonstration Kits come with the 71M6543 preprogrammed with demonstration
firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick and
efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator
(ICE).
94
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71M6543F/71M6543G Data Sheet
4.14
Crystal Oscillator
The oscillator of the 71M6543 drives a standard 32.768 kHz watch crystal. The oscillator has been
designed specifically to handle these crystals and is compatible with their high impedance and limited
power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any
battery backup device attached to the VBAT_RTC pin.
Board layouts with minimum capacitance from XIN to XOUT require less battery current. Good layouts
have XIN and XOUT shielded from each other and also keep the XIN and XOUT traces short and away
from LCD and digital signals.
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.
4.15
Meter Calibration
Once the 71M6543 energy meter device has been installed in a meter system, it must be calibrated. A
complete calibration includes the following:
•
•
•
Establishment of the reference temperature for factory calibration (e.g., typically 22 °C).
Calibration of the metrology section, i.e., calibration for errors of the current sensors, voltage
dividers and signal conditioning components as well as of the internal reference voltage (VREF) at
the reference temperature (e.g., typically 22 °C).
Calibration of the oscillator frequency using the RTCA_ADJ register (I/O RAM 0x2504).
The metrology section can be calibrated using the gain and phase adjustment factors accessible to the
CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning,
especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced
by the current sensors or by the effects of reactive power supplies.
Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or
current and voltage can be implemented. It is also possible to implement segment-wise calibration
(depending on current range).
The 71M6543 supports common industry standard calibration techniques, such as single-point
(energy-only), multi-point (energy, Vrms, Irms), and auto-calibration.
Maxim provides a calibration spreadsheet file to facilitate the calibration process. Contact your Maxim
representative to obtain a copy of the latest calibration spreadsheet file for the 71M6543.
v2
95
71M6543F/71M6543G Data Sheet
5
Firmware Interface
5.1
I/O RAM Map –Functional Order
In Table 68 and Table 69, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT pin.
The I/O RAM locations listed in Table 68 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 68 are an alternative sequential address to the addresses
from Table 69 which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM
0x2106[7:5].
Table 68: I/O RAM Map – Functional Order, Basic Configuration
96
Name
Addr
CE6
CE5
CE4
2000
2001
2002
CE3
2003
CE2
CE1
CE0
RCE0
RTMUX
FOVRD
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
LCD0
LCD1
2004
2005
2006
2007
2008
2009
200A
200B
200C
200D
200E
200F
2010
2011
2012
Bit 7
U
Bit 6
EQU[2:0]
U
Bit 5
Bit 4
U
Bit 3
Bit 2
CHOP_E[1:0]
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
Bit 1
RTM_E
Bit 0
CE_E
CE_LCTN[6/5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
DIFF0_E
RFLY_DIS
RMT4_E
RMT2_E
U
U
U
DIFF6_E
DIFF4_E
DIFF2_E
CHOPR[1:0]
RMT6_E
U
TMUXR4[2:0]
U
U
R
MUX_DIV[3:0]
MUX9_SEL
MUX7_SEL
MUX5_SEL
MUX3_SEL
MUX1_SEL
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT
LCD_E
LCD_MODE[2:0]
LCD_VMODE[1:0]
FIR_LEN[1:0]
PLS_INV
TMUXR6[2:0]
TMUXR2[2:0]
U
U
U
MUX10_SEL
MUX8_SEL
MUX6_SEL
MUX4_SEL
MUX2_SEL
MUX0_SEL
TBYTE_BUSY
TEMP_PER[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD_BLNKMAP23[5:0]
v2
71M6543F/71M6543G Data Sheet
Name
Addr
Bit 7
LCD_BAT
Bit 6
R
Bit 5
Bit 4
Bit 3
Bit 2
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
U
DIO_R11[2:0]
U
DIO_R9[2:0]
U
DIO_R7[2:0]
U
DIO_R5[2:0]
U
DIO_R3[2:0]
U
U
U
OPT_TXE[1:0]
OPT_FDC[1:0]
U
OPT_RXDIS
U
U
U
U
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_VPULSE
EW_RX
EW_PB
EW_DIO4
SFMM[7:0]*
SFMS[7:0]*
LCD2
2013
LCD_MAP6 2014
LCD_MAP5 2015
LCD_MAP4 2016
LCD_MAP3 2017
LCD_MAP2 2018
LCD_MAP1 2019
LCD_MAP0 201A
U
U
DIO_R5
201B
U
DIO_R4
201C
U
DIO_R3
201D
U
DIO_R2
201E
U
DIO_R1
201F
U
DIO_R0
2020
DIO_EEX[1:0]
DIO0
2021
DIO_PW
DIO_PV
DIO1
2022
DIO_PX
DIO_PY
DIO2
2023
EX_EEX
EX_XPULSE
INT1_E
2024
EX_SPI
EX_WPULSE
INT2_E
2025
WAKE_E
2026
SFMM
2080
SFMS
2081
Notes:
*SFMM and SFMS are accessible only through the SPI slave port. See 2.5.1.1 Flash Memory for details.
v2
Bit 1
Bit 0
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
EX_RTC1S
OPT_TXINV
OPT_BB
U
EX_XFER
EW_DIO52
EW_DIO55
97
71M6543F/71M6543G Data Sheet
Table 69 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile
bits have a darker gray background.
Table 69: I/O RAM Map – Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CE and ADC
MUX_DIV[3:0]
MUX10_SEL[3:0]
MUX5
2100
MUX9_SEL[3:0]
MUX8_SEL[3:0]
MUX4
2101
MUX7_SEL[3:0]
MUX6_SEL[3:0]
MUX3
2102
MUX5_SEL[3:0]
MUX4_SEL[3:0]
MUX2
2103
MUX3_SEL[3:0]
MUX2_SEL[3:0]
MUX1
2104
MUX1_SEL[3:0]
MUX0_SEL[3:0]
MUX0
2105
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE6
2106
U
SUM_SAMPS[12:8]
CE5
2107
SUM_SAMPS[7:0]
CE4
2108
U
CE_LCTN[6:0] (71M6543G), CE_LCTN[5:0] (71M6543F)
CE3
2109
PLS_MAXWIDTH[7:0]
CE2
210A
PLS_INTERVAL[7:0]
CE1
210B
DIFF6_E
DIFF4_E
DIFF2_E
DIFF0_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
CE0
210C
U
U
U
U
U
U
RTM0[9:8]
RTM0
210D
RTM0[7:0]
RTM0
210E
RTM1[7:0]
RTM1
210F
RTM2[7:0]
RTM2
2110
RTM3[7:0]
RTM3
2111
CLOCK GENERATION
U
U
ADC_DIV
PLL_FAST
RESET
MPU_DIV[2:0]
CKGN
2200
VREF TRIM FUSES
TRIMT[7:0]
TRIMT
2309
LCD/DIO
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD0
2400
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD1
2401
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD2
2402
LCD_MAP[55:48]
LCD_MAP6 2405
LCD_MAP[47:40]
LCD_MAP5 2406
LCD_MAP[39:32]
LCD_MAP4 2407
LCD_MAP[31:24]
LCD_MAP3 2408
98
v2
71M6543F/71M6543G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
LCD_MAP2
LCD_MAP1
LCD_MAP0
LCD4
LCD_DAC
SEGDIO0
…
SEGDIO15
SEGDIO16
…
SEGDIO45
SEGDIO46
…
SEGDIO50
SEGDIO51
…
SEGDIO55
2409
240A
240B
240C
240D
2410
…
241F
2420
…
243D
243E
…
2442
2443
…
2447
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
DIO_R5
2450
DIO_R4
2451
DIO_R3
2452
DIO_R2
2453
DIO_R1
2454
DIO_R0
2455
DIO0
2456
DIO1
2457
DIO2
2458
NV BITS
SPARENV 2500
FOVRD
2501
TMUX
2502
TMUX2
2503
RTC1
2504
71M6xx3 Interface
v2
U
R
U
U
U
U
U
DIO_EEX[1:0]
DIO_PW
DIO_PV
DIO_PX
DIO_PY
U
U
U
U
U
U
U
U
U
Bit 4
Bit 3
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
LCD_RST
LCD_DAC[4:0]
LCD_SEG0[5:0]
…
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
…
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
…
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
…
LCD_SEGDIO55[5:0]
R
R
DIO_R11[2:0]
DIO_R9[2:0]
DIO_R7[2:0]
DIO_R5[2:0]
DIO_R3[2:0]
U
U
OPT_FDC[1:0]
U
U
U
R
U
Bit 2
U
U
U
U
U
U
U
U
OPT_TXE[1:0]
U
OPT_RXDIS
U
U
Bit 1
Bit 0
LCD_BLANK
LCD_ON
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
OPT_TXINV
OPT_BB
U
U
U
R
U
U
TMUX[5:0]
TMUX2[4:0]
RTCA_ADJ[6:0]
99
71M6543F/71M6543G Data Sheet
Name
Addr
REMOTE2 2602
REMOTE1 2603
RBITS
INT1_E
2700
INT2_E
2701
SECURE
2702
Analog0
2704
VERSION 2706
INTBITS
2707
FLAG0 SFR E8
FLAG1 SFR F8
STAT
SFR F9
REMOTE0 SFR FC
SPI1
SFR FD
SPI0
2708
RCE0
2709
RTMUX
270A
DIO3
270C
NV RAM and RTC
2800NVRAMxx
287F
WAKE
2880
STEMP1
2881
STEMP0
2882
BSENSE
2885
LKPADDR 2887
LKPDATA 2888
LKPCTRL 2889
RTC0
2890
RTC2
2892
RTC3
2893
RTC4
2894
RTC5
2895
100
Bit 7
EX_EEX
EX_SPI
VREF_CAL
U
IE_EEX
IE_SPI
U
U
Bit 6
Bit 4
Bit 3
RMT_RD[15:8]
RMT_RD[7:0]
EX_XPULSE
EX_YPULSE
EX_WPULSE EX_VPULSE
FLSH_UNLOCK[3:0]
VREF_DIS
PRE_E
INT6
IE_XPULSE
IE_WPULSE
U
PERR_RD
CHOPR[1:0]
U
U
Bit 5
U
INT5
IE_YPULSE
IE_VPULSE
U
PERR_WR
RMT6_E
TMUXR4[2:0]
PORT_E
EX_RTCT
U
U
U
R
ADC_E
BCURR
VERSION[7:0]
INT4
INT3
IE_RTCT
U
U
U
PLL_OK
U
Bit 2
Bit 1
Bit 0
EX_RTC1M
U
FLSH_RDE
EX_RTC1S
U
FLSH_WRE
SPARE[2:0]
EX_XFER
U
R
INT2
IE_RTC1M
U
INT1
IE_RTC1S
U
VSTAT[2:0]
INT0
IE_XFER
PB_STATE
RCMD[4:0]
SPI_CMD[7:0]
SPI_STAT[7:0]
RMT4_E
RMT2_E
U
SPI_E
SPI_SAFE
U
TMUXR6[2:0]
TMUXR2[2:0]
U
U
U
U
LKP_RD
U
LKP_WR
U
NVRAM[0] – NVRAM[7F] – Direct Access
STEMP[2:0]
LKPAUTOI
U
RTC_WR
U
RTC_RD
U
U
U
U
U
U
U
U
U
WAKE_TMR[7:0]
STEMP[10:3]
U
U
U
BSENSE[7:0]
LKPADDR[6:0]
LKPDAT[7:0]
U
U
U
RTC_FAIL
U
U
RTC_SBSC[7:0]
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
v2
71M6543F/71M6543G Data Sheet
Name
Addr
Bit 7
U
U
U
RTC6
2896
RTC7
2897
RTC8
2898
RTC9
2899
U
RTC10
289B
RTC11
289C
RTC12
289D
U
RTC13
289E
U
RTC14
289F
TEMP_BSEL
TEMP
28A0
WF1
28B0 WF_CSTART
U
WF2
28B1
SLEEP
MISC
28B2
U
WAKE_E
28B3
WD_RST
WDRST
28B4
MPU PORTS
PORT3 SFR B0
PORT2 SFR A0
PORT1 SFR 90
PORT0 SFR 80
FLASH
ERASE SFR 94
FLSHCTL SFR B2 PREBOOT
U
FL_BANK SFR B6
PGADR SFR B7
2
IC
EEDATA SFR 9E
EECTRL SFR 9F
v2
Bit 6
U
U
U
Bit 5
U
U
U
Bit 4
U
Bit 3
U
Bit 2
Bit 1
RTC_DAY[2:0]
Bit 0
RTC_DATE[4:0]
RTC_MO[3:0]
U
RTC_YR[7:0]
U
U
U
U
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
U
U
TEMP_PWR
WF_RST
U
LCD_ONLY
U
TEMP_START
U
OSC_COMP
WF_RSTBIT
WF_TMR
WAKE_ARM
U
U
TEMP_BAT
WF_OVF
WF_RX
U
EW_RX
U
RTC_Q[1:0]
RTC_TMIN[5:0]
RTC_THR[4:0]
TBYTE_BUSY
TEMP_PER[2:0]
WF_ERST
WF_BADVDD
U
U
WF_PB
WF_DIO4
WF_DIO52
WF_DIO55
U
U
U
U
EW_PB
EW_DIO4
EW_DIO52
EW_DIO55
U
U
U
U
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
SECURE
U
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
FLSH_ERASE[7:0]
U
U
FLSH_PEND
U
U
U
FLSH_PGADR[5:0]
FLSH_PSTWR
U
FLSH_MEEN FLSH_PWE
FL_BANK[1:0]
U
U
EEDATA[7:0]
EECTRL[7:0]
101
71M6543F/71M6543G Data Sheet
5.2
I/O RAM Map – Alphabetical Order
Table 70 lists I/O RAM bits and registers in alphabetical order.
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
Table 70: I/O RAM Map – Alphabetical Order
Name
ADC_E
Location Rst Wk Dir
2704[4]
0
0
R/W
ADC_DIV
2200[5]
0
0
R/W
BCURR
2704[3]
0
0
R/W
2885[7:0]
–
–
R
2106[0]
0
0
R/W
BSENSE[7:0]
CE_E
CE_LCTN[6:0]
2109[6:0]
31 31 R/W
CHIP_ID[15:8]
CHIP_ID[7:0]
2300[7:0]
2301[7:0]
0
0
0
0
R
R
CHOP_E[1:0]
2106[3:2]
0
0
R/W
102
Description
Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The resulting ADC and FIR clock is as shown below.
PLL_FAST = 0
PLL_FAST = 1
MCK
6.291456 MHz
19.660800 MHz
ADC_DIV = 0
1.572864 MHz
4.9152 MHz
ADC_DIV = 1
0.786432 MHz
2.4576 MHz
Connects a 100 µA load to the battery selected by TEMP_BSEL.
The result of the battery measurement.
See 2.5.7 71M6543 Battery Monitor on page 56.
CE enable.
CE program location. The starting address for the CE program is 1024*CE_LCTN.
(CE_LCTN[6:0], 2109[6:0] for 71M6543G)
(CE_LCTN[5:0], 2109[5:0] for 71M6543F)
These bytes contain the chip identification as shown below.
CHIP_ID[15:8] CHIP_ID[7:0]
71M6543F
0x04
0x10
71M6543G
0x05
0x10
Chop enable for the reference bandgap circuit. The value of CHOP changes on the
rising edge of the internal MUXSYNC signal according to the value in CHOP_E[1:0]:
1
00 = toggle 01 = positive 10 = reversed 11 = toggle
1
except at the mux sync edge at the end of an accumulation interval.
v2
71M6543F/71M6543G Data Sheet
Name
CHOPR[1:0]
DIFF0_E
DIFF2_E
DIFF4_E
DIFF6_E
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
v2
Location Rst Wk Dir
2709[7:6]
00 00 R/W
210C[4]
210C[5]
210C[6]
210C[7]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
0
0
0
0
0
0
0
0
0
0
0
–
R/W
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
SFR B0[7:4]
SFR A0[7:4]
F
SFR 90[7:4]
SFR 80[7:4]
F
R/W
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
SFR B0[3:0]
SFR A0[3:0]
F
SFR 90[3:0]
SFR 80[3:0]
F
R/W
Description
The CHOP settings for the remote sensor.
00 = Auto chop. Change every MUX frame.
01 = Positive
10 = Negative
11 = Auto chop (same as 00)
Enables IADC0-IADC1 differential configuration.
Enables IADC2-IADC3 differential configuration.
Enables IADC4-IADC5 differential configuration.
Enables IADC6-IADC7 differential configuration.
Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources. If more
than one input is connected to the same resource, the MULTIPLE column below specifies
how they are combined.
MULTIPLE
DIO_Rx Resource
0
NONE
–
1
Reserved
OR
2
T0 (Timer0 clock or gate)
OR
3
T1 (Timer1 clock or gate)
OR
4
IO interrupt (int0)
OR
5
IO interrupt (int1)
OR
Programs the direction of the first 16 DIO pins. 1 indicates output. Ignored if the pin is
not configured as I/O. See DIO_PV and DIO_PW for special option for DIO0 and DIO1
outputs. See DIO_EEX[1:0] for special option for SEGDIO2 and SEGDIO3. Note that
the direction of DIO pins above 15 is set by SEGDIOx[1]. See PORT_E to avoid powerup spikes.
The value on the first 16 DIO pins. Pins configured as LCD read zero. When written,
changes data on pins configured as outputs. Pins configured as LCD or input ignore
writes. Note that the data for DIO pins above 15 is set by SEGDIOx[0].
103
71M6543F/71M6543G Data Sheet
Name
Location Rst Wk Dir
DIO_EEX[1:0]
2456[7:6]
0
–
R/W
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
2457[6]
2457[7]
2458[7]
2458[6]
SFR 9E
0
0
0
0
0
–
–
–
–
0
R/W
R/W
R/W
R/W
R/W
EECTRL[7:0]
SFR 9F
0
0
R/W
Description
When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM.
SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if
LCD_MAP[2] and LCD_MAP[3] are cleared.
DIO_EEX[1:0]
00
01
10
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
3-Wire EEPROM interface with separate DO (SEGDIO3) and DI
11
(SEGDIO8) pins.
Causes VPULSE to be output on SEGDIO1, if LCD_MAP[1]=0.
Causes WPULSE to be output on SEGDIO0, if LCD_MAP[0]=0.
Causes XPULSE to be output on SEGDIO6 , if LCD_MAP[6]=0.
Causes YPULSE to be output on SEGDIO7 , if LCD_MAP[7]=0.
Serial EEPROM interface data.
Serial EEPROM interface control.
Status
Name
Bit
ERROR
7
BUSY
6
5
RX_ACK
Read/
Write
R
R
R
Reset
Polarity Description
State
0
Positive 1 when an illegal command is received.
0
Positive 1 when serial data bus is busy.
1 indicates that the EEPROM sent an
1
Positive
ACK bit.
Specifies the power equation.
EQU[2:0]
3
EQU[2:0]
2106[7:5]
0
0
R/W
4
5*
Description
2 element, 4W,
3φ Delta
2 element, 4W,
3φ Wye
3 element, 4W,
3φ Wye
Element
0
Element
1
Element
2
Recommended
MUX Sequence
VA(IA-IB)/2
0
VC IC
IA VA IB IC VC
VA(IA-IB)/2
VB(IC-IB)/2
0
IA VA IB VB IC
VA IA
VB IB
VC IC
IA VA IB VB IC VC
Note:
*The available CE codes implements only equation 5. Contact your local Maxim representative to obtain
CE code for equation 3 and 4.
104
v2
71M6543F/71M6543G Data Sheet
Name
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0
0
R/W
EW_DIO4
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
210C[2:1]
0
0
R/W
FIR_LEN[1:0]
v2
Location Rst Wk Dir
Description
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The
bits are set by hardware and cannot be set by writing a 1. The bits are reset by writing
0. Note that if one of these interrupts is to enabled, its corresponding 8051 EX enable
bit must also be set. See 2.4.8 Interrupts, for details.
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake the part.
This bit has no effect unless DIO4 is configured as a digital input.
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to wake the part.
This bit has no effect unless SEGDIO52 is configured as a digital input.
Connects SEGDIO55 to the WAKE logic and permits the SEGDIO55 rising edge to
awaken the part. This bit has no effect unless SEGDIO55 is configured as a digital
input.
Connects PB to the WAKE logic and permits a high level on PB to awaken the part. PB
is always configured as an input.
Connects RX to the WAKE logic and permits the RX rising edge to awaken the part.
See the WAKE description in 3.4 Wake on Timer for de-bounce issues.
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0]
ADC Cycles
00
141
01
288
10
384
PLL_FAST = 0:
FIR_LEN[1:0]
ADC Cycles
00
135
01
276
10
Not Allowed
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to
Table 81 on page 122 and Table 103 on page 141 for details.
105
71M6543F/71M6543G Data Sheet
Name
Location Rst Wk Dir
FL_BANK[1:0]
SFR B6[1:0] 01 01 R/W
FLSH_ERASE[7:0]
SFR 94[7:0] 0
0
W
FLSH_MEEN
SFR B2[1]
0
0
W
FLSH_PEND
SFR B2[3]
0
0
R
SFR B7[7:2] 0
0
W
0
R/W
FLSH_PGADR[5:0]
FLSH_PSTWR
106
SFR B2[2]
0
Description
Flash Bank Selection (71M6543G only)
The program memory of the 71M6543G consists of a fixed lower bank of 32 KB,
addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at
0x8000 to 0xFFFF. The I/O RAM register FL_BANK is used to switch one of four
memory banks of 32 KB each into the address range from 0x8000 to 0xFFFF. Note that
when FL_BANK = 0, the upper bank is the same as the lower bank.
Address Range for Lower Bank
Address Range for Upper Bank
FL_BANK[1:0]
(0x0000-0x7FFF)
(0x8000-0xFFFF)
00
0x0000-0x7FFF
0x0000-0x7FFF
01
0x0000-0x7FFF
0x8000-0xFFFF
10
0x0000-0x7FFF
0x10000-0x17FFF
11
0x0000-0x7FFF
0x18000-0x1FFFF
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page
Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the
appropriate Erase cycle. (default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] (SFR 0xB7).
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN (SFR 0xB2) and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE has no effect.
Mass Erase Enable
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Indicates that a posted flash write is pending. If another flash write is attempted, it is
ignored.
Flash Page Erase Address
Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle.
(default = 0x00).
Must be re-written for each new Page Erase cycle.
Enables posted flash writes. When 1, and if CE_E = 1, flash write requests are stored in
a one element deep FIFO and are executed when CE_BUSY falls. FLSH_PEND can be
read to determine the status of the FIFO. If FLSH_PSTWR = 0 or if CE_E = 0, flash writes
are immediate.
v2
71M6543F/71M6543G Data Sheet
Name
v2
Location Rst Wk Dir
FLSH_PWE
SFR B2[0]
0
0
R/W
FLSH_RDE
2702[2]
–
–
R
FLSH_UNLOCK[3:0]
2702[7:4]
0
0
R/W
FLSH_WRE
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
2702[1]
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[3]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[6]
SFR F8[5]
–
–
R
0
0
R/W
INTBITS
2707[6:0]
–
–
R
LCD_ALLCOM
LCD_BAT
LCD_BLNKMAP23[5:0]
0
0
–
–
R/W
R/W
LCD_BLNKMAP22[5:0]
2400[3]
2402[7]
2401[5:0]
2402[5:0]
0
–
R/W
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
Description
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this bit are
inhibited when interrupts are enabled.
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = (!SECURE)
Must be a 2 to enable any flash modification. See the description of Flash security for
more details.
Indicates that the flash may be written through ICE or SPI slave ports.
Interrupt flags for external interrupts 2 and 6. These flags monitor the source of the int6
and int2 interrupts (external interrupts to the MPU core). These flags are set by
hardware and must be cleared by the software interrupt handler. The IEX2 (SFR
0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are automatically cleared by the MPU
core when it vectors to the interrupt handler. IEX2 and IEX6 must be cleared by writing
zero to their corresponding bit positions in SFR 0xC0, while writing ones to the other bit
positions that are not being cleared.
Interrupt inputs. The MPU may read these bits to see the input to external interrupts
INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended
for debug use.
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP bit is zero.
Connects the LCD power supply to VBAT in all modes.
Identifies which segments connected to SEG23 and SEG22 should blink. 1 means
blink. The most significant bit corresponds to COM5, the least significant, to COM0.
Sets the LCD clock frequency. Note: fXTAL = 32768 Hz
LCD_CLK[1:0] LCD Clock Frequency
9
00
fXTAL/2
8
01
fXTAL/2
7
10
fXTAL/2
6
11
fXTAL/2
107
71M6543F/71M6543G Data Sheet
Name
LCD_DAC[4:0]
LCD_E
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
Location Rst Wk Dir
240D[4:0]
0
–
R/W
2400[7]
0
–
R/W
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
The LCD contrast DAC. This DAC controls the VLCD voltage and has an output range of
2.65 V to 5.3 V. The VLCD voltage is
VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 85.5 mV. The maximum DAC output voltage is limited by
V3P3SYS, VBAT, and whether LCD_BSTE = 1.
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are
the COM and SEG outputs if their LCD_MAP bit is 1.
Enables LCD segment driver mode of combined SEGDIO pins. Pins that cannot be
configured as outputs (SEG48 through SEG50) become inputs with internal pull ups
when their LCD_MAP bit is zero. Also, note that SEG48 through SEG50 are multiplexed
with the in-circuit emulator signals. When the ICE_E pin is high, the ICE interface is
enabled, and SEG48 through SEG50 become E_RXTX, E_TCLK and E_RST,
respectively.
Selects the LCD bias and multiplex mode.
LCD_MODE[2:0]
LCD_MODE
000
001
010
011
100
101
110
Output
4 states, 1/3 bias
3 states, 1/3 bias
2 states, 1/2 bias
3 states, 1/2 bias
Static display
5 states, 1/3 bias
6 states, 1/3 bias
2400[6:4]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
R/W
R/W
LCD_ONLY
28B2[6]
0
0
W
LCD_RST
240C[2]
0
–
R/W
2410[5:0] to
0
241F[5:0]
–
R/W
SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR space.
2420[5:0] to
0
243D[5:0]
–
R/W
SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO, bit 1 is
direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored.
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
108
Turns on or off all LCD segments without changing LCD data. If both bits are set, the
LCD display is turned on.
Puts the 71M6543 to sleep, but with LCD display still active. Ignored if system power is
present. It awakens when the Wake Timer times out, when certain DIO pins are raised,
or when system power returns (see 3.2 Battery Modes).
Clear all bits of LCD data. These bits affect SEGDIO pins that are configured as LCD
drivers. This bit does not auto clear.
v2
71M6543F/71M6543G Data Sheet
Name
LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0]
Location Rst Wk Dir
Description
243E[5:0]
0
to 2442[5:0]
–
R/W
SEG data for SEG46 through SEG50. These pins cannot be configured as DIO.
2443[5:0] to
0
2447[5:0]
–
R/W
SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO, bit 1 is
direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored.
Specifies how VLCD is generated. See 2.5.10.3 for the definition of V3P3L.
LCD_VMODE[1:0]
LCD_Y
00 00 R/W
2400[2]
0
–
R/W
2887[6:0]
0
0
R/W
2887[7]
0
0
R/W
2888[7:0]
0
0
R/W
2889[1]
2889[0]
0
0
0
0
R/W
R/W
MPU_DIV[2:0]
2200[2:0]
0
0
R/W
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:4]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
v2
2401[7:6]
LCD_VMODE
11
10
01
00
Description
External VLCD
LCD boost and LCD DAC enabled
LCD DAC enabled
No boost and no DAC. VLCD=V3P3L.
LCD Blink Frequency (ignored if blink is disabled).
1 = 1 Hz, 0 = 0.5 Hz
The address for reading and writing the RTC lookup RAM.
Auto-increment flag. When set, LKPADDR[6:0] auto increments every time LKP_RD or
LKP_WR is pulsed. The incremented address can be read at LKPADDR.
The data for reading and writing the RTC lookup RAM.
Strobe bits for the RTC lookup RAM read and write. When set, the LKPADDR[6:0] and
LKPDAT registers is used in a read or write operation. When a strobe is set, it stays set
until the operation completes, at which time the strobe is cleared and LKPADDR[6:0] is
incremented if LKPAUTOI is set.
MPU clock rate is:
-(2+MPU_DIV[2:0])
MPU Rate = MCK Rate * 2
.
The maximum value for MPU_DIV[2:0] is 4. Based on the default values of the PLL_FAST
bit and MPU_DIV[2:0], the power-up MPU rate is 6.29 MHz / 4 = 1.5725 MHz. The
minimum MPU clock rate is 38.4 kHz when PLL_FAST = 1.
Selects which ADC input is to be converted during time slot 0.
Selects which ADC input is to be converted during time slot 1.
Selects which ADC input is to be converted during time slot 2.
Selects which ADC input is to be converted during time slot 3.
Selects which ADC input is to be converted during time slot 4.
Selects which ADC input is to be converted during time slot 5.
Selects which ADC input is to be converted during time slot 6.
Selects which ADC input is to be converted during time slot 7.
109
71M6543F/71M6543G Data Sheet
Name
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
Location Rst Wk Dir
Description
2101[3:0]
2101[7:4]
2100[3:0]
0
0
0
0
0
0
R/W
R/W
R/W
MUX_DIV[3:0]
2100[7:4]
0
0
R/W
2457[0]
0
–
R/W
2457[5:4]
0
–
R/W
Selects which ADC input is to be converted during time slot 8.
Selects which ADC input is to be converted during time slot 9.
Selects which ADC input is to be converted during time slot 10.
MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The maximum
number of time slots is 11.
Configures the input of the optical port to be a DIO pin to allow it to be
bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to 2.5.9 UART
and Optical Interface =under the “Bit Banged Optical UART (Third UART)” subheading on page 56.
Selects OPT_TX modulation duty cycle
OPT_FDC Function
00
50% Low
01
25% Low
10
12.5% Low
11
6.25% Low
OPT_BB
OPT_FDC[1:0]
OPT_RXDIS
2457[2]
0
–
R/W
OPT_RXINV
2457[1]
0
–
R/W
00 –
R/W
OPT_TXE [1,0]
2456[3:2]
OPT_TXINV
2456[0]
0
–
R/W
OPT_TXMOD
2456[1]
0
–
R/W
OSC_COMP
28A0[5]
0
–
R/W
SFR F8[0]
SFR FC[6]
SFR FC[5]
0
0
R
0
0
R/W
PB_STATE
PERR_RD
PERR_WR
110
OPT_RX can be configured as an input to the optical UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55
Inverts result from OPT_RX comparator when 1. Affects only the UART input. Has no
effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
If LCD_MAP[51] = 0:
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VPULSE
If LCD_MAP[51] = 1:
xx = SEG51
Invert OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inversion
caused by OPT_TXINV.
Enables the automatic update of RTC_P[16:0] and RTC_Q [1:0]every time the temperature
is measured.
The de-bounced state of the PB pin.
The 71M6543 sets these bits to indicate that a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are cleared by the MPU.
v2
71M6543F/71M6543G Data Sheet
Name
PLL_OK
PLL_FAST
Description
SFR F9[4]
0
0
R
2200[4]
0
0
R/W
Indicates that the clock generation PLL is settled.
Controls the speed of the PLL and MCK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if
PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is
(2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] in units of CK_FIR
clock cycles. If PLS_INTERVAL[7:0] = 0 or PLS_MAXWIDTH[7:0] = 255, no pulse
width checking is performed and the output pulses have 50% duty cycle. See 2.3.6.2
VPULSE and WPULSE.
PLS_INTERVAL[7:0] determines the interval time between pulses. The time between
output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If
PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE
issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0] = Floor ( Mux frame duration in CK_FIR cycles / CE pulse updates per Mux
PLS_MAXWIDTH[7:0]
210A[7:0] FF FF R/W
PLS_INTERVAL[7:0]
210B[7:0]
0
0
R/W
PLS_INV
210C[0]
0
0
R/W
PORT_E
270C[5]
0
0
R/W
2704[5]
SFRB2[7]
0
–
0
–
R/W
R
SFR FC[4:0] 0
0
R/W
PRE_E
PREBOOT
RCMD[4:0]
v2
Location Rst Wk Dir
RESET
2200[3]
0
0
W
RFLY_DIS
210C[3]
0
0
R/W
frame / 4 )
For example, since the 71M6543 CE code is written to generate 6 pulses in one integration
interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0) and that the frame
duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0] should be written with
Floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the
integration interval and the last pulse is issued just prior to the end of the interval. See
2.3.6.2 VPULSE and WPULSE.
Inverts the polarity of WPULSE, VARPULSE, XPULSE, and YPULSE. Normally, these
pulses are active low. When inverted, they become active high.
Enables outputs from the SEGDIO0-SEGDIO15 pins. PORT_E = 0 blocks the momentary
output pulse that occurs when SEGDIO0-SEGDIO15 are reset on power-up.
Enables the 8x pre-amplifier.
Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD, the 71M6543 issues a command to
the appropriate remote sensor. When the command is complete, the 71M6543 clears
RCMD.
When set, writes a one to WF_RSTBIT and then causes a reset.
Controls how the 71M6543 drives the power pulse for the 71M6xxx. When set, the
power pulse is driven high and low. When cleared, it is driven high followed by an open
circuit fly-back interval.
111
71M6543F/71M6543G Data Sheet
Name
RMT2_E
RMT4_E
RMT6_E
RMT_RD[15:8]
RMT_RD[7:0]
RTCA_ADJ[6:0]
RTC_FAIL
Location Rst Wk Dir
2709[3]
2709[4]
2709[5]
2602[7:0]
2603[7:0]
2504[6:0]
0
0
R/W
0
0
R
40 –
R/W
2890[4]
0
0
R
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
R/W
RTC_Q[1:0]
289D[1:0]
0
0
R/W
2890[6]
0
0
R/W
RTC_SBSC[7:0]
RTC_TMIN[5:0]
2892[7:0]
289E[5:0]
–
0
–
–
R
R/W
RTC_THR[4:0]
289F[4:0]
0
–
R/W
2890[7]
0
0
R/W
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W
2106[1]
0
0
R/W
RTC_RD
RTC_WR
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
RTM_E
112
Description
Enables the remote interface.
Response from remote read request.
Register for analog RTC frequency adjustment.
Indicates that a count error has occurred in the RTC and that the time is not trustworthy.
This bit can be cleared by writing a 0.
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is
read, it returns the status of the shadow register:
0 = up to date, 1 = frozen.
Time remaining since the last 1 second boundary. LSB=1/128 second.
The target minutes register. See RTC_THR below.
The target hours register. The RTC_T interrupt occurs when RTC_MIN [5:0] becomes
equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
Freezes the RTC shadow register so it is suitable for MPU writes. When RTC_WR is
cleared, the contents of the shadow register are written to the RTC counter on the next
RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is set. It
continues to return one until the RTC counter actually updates.
The RTC interface. These are the year, month, day, hour, minute and second parameters
for the RTC. The RTC is set by writing to these registers. Year 00 and all others divisible
by 4 are defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR 00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR
00 to 99
Each write operation to one of these registers must be preceded by a write to 0x2890.
Real Time Monitor enable. When 0, the RTM output is low.
v2
71M6543F/71M6543G Data Sheet
Name
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
Location Rst Wk Dir
Description
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0
0
0
0
0
0
R/W
Four RTM probes. Before each CE code pass, the values of these registers are serially
output on the RTM pin. The RTM registers are ignored when RTM_E = 0. Note that
RTM0 is 10 bits wide. The others assume the upper two bits are 00.
SECURE
SFR B2[6]
0
0
R/W
28B2[7]
0
0
W
SFR FD[7:0] –
–
R
SLEEP
SPI_CMD
SPI_E
270C[4]
1
1
R/W
SPI_SAFE
270C[3]
0
0
R/W
SPI_STAT
2708[7:0]
0
0
R
Inhibits erasure of page 0 and flash memory addresses above the beginning of CE code
as defined by CE_LCTN[6/5:0]. Also inhibits the reading of flash memory by external
devices (SPI or ICE port).
Puts the 71M6543 to sleep. Ignored if system power is present. The 71M6543 wakes
when the Wake timer times out, when push button is pushed, or when system power
returns.
SPI command. 8-bit command from the bus master.
SPI port enable. Enables the SPI interface on pins SEGDIO36 – SEGDIO39. Requires
that LCD_MAP[36-39] = 0.
Limits SPI writes to SPI_CMD and a 16 byte region in DRAM. No other writes are
permitted.
SPI_STAT contains the status results from the previous SPI transaction
Bit 7 - 71M6543 ready error: the 71M6543 was not ready to read or write as directed by
the previous command.
Bit 6 - Read data parity: This bit is the parity of all bytes read from the 71M6543 in the
previous command. Does not include the SPI_STAT byte.
Bit 5 - Write data parity: This bit is the overall parity of the bytes written to the 71M6543
in the previous command. It includes CMD and ADDR bytes.
Bit 4:2 - Bottom 3 bits of the byte count. Does not include ADDR and CMD bytes.
One, two, and three byte instructions return 111.
Bit 1 - SPI FLASH mode: This bit is zero when the TEST pin is zero.
Bit 0 - SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the flash is ready to
receive another write instruction.
STEMP[10:3]
STEMP[2:0]
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
TBYTE_BUSY
TEMP_22[10:8]
TEMP_22[7:0]
v2
2881[7:0]
2882[7:5]
2107[4:0]
2108[7:0]
–
–
–
–
R
R
0
0
R/W
28A0[3]
0
0
R
230A[2:0]
230B[7:0]
0
–
R
The result of the temperature measurement.
The number of multiplexer cycles (frames) per XFER_BUSY interrupt. Maximum value is
8191 cycles.
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are
locked out while it is one. Write duration could be as long as 6 ms.
Storage location for STEMP[10:0] at 22C. STEMP[10:0] is an 11 bit word.
113
71M6543F/71M6543G Data Sheet
Name
TEMP_BAT
TEMP_BSEL
Location Rst Wk Dir
28A0[4]
0
–
R/W
28A0[7]
0
–
R/W
Description
Causes VBAT to be measured whenever a temperature measurement is performed.
Selects which battery is monitored by the temperature sensor:
1 = VBAT, 0 = VBAT_RTC
Sets the period between temperature measurements. Automatic measurements can be
enabled in any mode (MSN, BRN, LCD, or SLP). TEMP_PER = 0 disables automatic
temperature updates, in which case TEMP_START may be used by the MPU to initiate a
one-shot temperature measurement.
TEMP_PER[2:0]
28A0[2:0]
0
–
R/W
TEMP_PER
0
1-6
7
TEMP_PWR
28A0[6]
0
–
R/W
TEMP_START
28B4[6]
0
0
R/W
TMUX[5:0]
TMUX2[4:0]
TMUXR2[2:0]
TMUXR4[2:0]
TMUXR6[2:0]
2502[5:0] – – R/W
2503[4:0] – – R/W
270A[2:0]
270A[6:4] 000 000 R/W
2709[2:0]
Time (seconds)
No temperature updates
2 (3 + TEMP _ PER )
Continuous updates
Selects the power source for the temp sensor:
1 = V3P3D, 0 = VBAT_RTC.
This bit is ignored in SLP and LCD modes, where the temp sensor is always powered
by VBAT_RTC.
When TEMP_PER = 0 automatic temperature measurements are disabled, and
TEMP_START may be set by the MPU to initiate a one-shot temperature
measurement. TEMP_START is ignored in SLP and LCD modes. Hardware clears
TEMP_START when the temperature measurement is complete.
Selects one of 32 signals for TMUXOUT. See 2.5.14 for details.
Selects one of 32 signals for TMUX2OUT. See 2.5.14 for details.
The TMUX setting for the remote isolated sensors (71M6xx3).
The silicon version index. This word may be read by firmware to determine the silicon
version.
VERSION[7:0]
VERSION[7:0]
2706[7:0]
–
–
R
VREF_CAL
2704[7]
0
0
R/W
VREF_DIS
2704[6]
0
1
R/W
114
0001 0001
0001 0011
0001 0011
0010 0010
71M6543F
Silicon Version
A01
A03
B01
B02
71M6543G
Silicon Version
A01
N/A
N/A
N/A
Brings the ADC reference voltage out to the VREF pin. This feature is disabled when
VREF_DIS=1.
Disables the internal ADC voltage reference.
v2
71M6543F/71M6543G Data Sheet
Name
Location Rst Wk Dir
Description
This word describes the source of power and the status of the VDD.
VSTAT[2:0]
000
001
VSTAT[2:0]
SFR F9[2:0]
–
–
R
010
011
101
v2
Description
System Power OK. V3P3A>3.0v. Analog modules are functional and
accurate. [V3AOK,V3OK]=11
System Power Low. 2.8v2.0. Flash writes are inhibited. If the
TRIMVDD[5] fuse is blown, PLL_FAST is cleared.
[V3AOK,V3OK]=00, [VDDOK,VDDgt2]=01
Battery power and VDD 1 into V_ANG_CNT
(V_ANG_CNT indicates how many accumulation periods to sum PH_AtoB_X and PH_AtoC_X
over. The MPU then has to divide by that number. For standard CE codes that support shunts
with remotes, V_ANG_CNT is at CE address 0x53. For standard CE codes that support shunts
with CT, V_ANG_CNT is at CE address 0x55. For other than standard CE codes, please contact
Maxim for information).
5.3.9
Pulse Generation
Table 83 describes the CE pulse generation parameters.
The combination of the CECONFIG PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1])
bits controls the speed of the pulse rate. The default values of 0 and 0 maintain the original pulse rate
given by the Kh equation.
WRATE (CE RAM 0x21) controls the number of pulses that are generated per measured Wh and VARh
quantities. The lower WRATE is the slower the pulse rate for measured energy quantity. The metering
constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh =
v2
123
71M6543F/71M6543G Data Sheet
1Wh/pulse, a power applied to the meter of 120 V and 30 A results in one pulse per second. If the load is
240 V at 150 A, ten pulses per second are generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case,
the pulse rate is determined by APULSEW and APULSER (CE RAM 0x45 and 0x49). The MPU has to load
the source for pulse generation in APULSEW and APULSER to generate pulses. Irrespective of the
EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE = 1, the MPU is providing the source for pulse generation. If EXT_PULSE is 0,
W0SUM_X and VAR0SUM_X are the default pulse generation sources. In this case, creep cannot be
controlled since it is an MPU function.
The maximum pulse rate is 3*FS = 7.5 kHz.
See 2.3.6.2 VPULSE and WPULSE (page 27) for details on how to adjust the timing of the output pulses.
The maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 µs) and is independent of the
number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is
67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted
to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without
exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is:
RATE =
WRATE ⋅ WSUM ⋅ FS ⋅ X
Hz ,
2 46
where FS = sampling frequency (2184.53 Hz), X = Pulse speed factor derived from the CE variables
PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1]).
124
v2
71M6543F/71M6543G Data Sheet
Table 83: CE Pulse Generation Parameters
CE
Address
Name
Default
0x21
WRATE
227
0x22
KVAR
6444
0x23
SUM_PRE
2184
0x45
APULSEW
0
0x46
WPULSE_CTR
0
0x47
WPULSE_ FRAC
0
0x48
0x49
0x4A
WSUM_ ACCUM
APULSER
VPULSE_CTR
0
0
0
0x4B
VPULSE_ FRAC
0
0x4C
VSUM_ACCUM
0
Description
Kh = VMAX*IMAX*K / (WRATE*NACC*X) Wh/pulse
where:
K = 76.3594 when used with local sensors (CT or shunt)
K = 54.5793 when used with 71M6xx3 remote sensors
Scale factor for VAR measurement.
Number of samples per accumulation interval, as specified in
SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 0x2108[7:0] (NACC).
Wh pulse (WPULSE) generator input to be updated by the MPU
when using external pulse generation. The output pulse rate is:
-32
-14
APULSEW * FS * 2 * WRATE * X * 2 .
This input is buffered and can be updated by the MPU during a
conversion interval. The change takes effect at the beginning of
the next interval.
Counter for WPULSE output.
Unsigned numerator, containing a fraction of a pulse. The value
in this register always counts up towards the next pulse.
Roll-over accumulator for WPULSE.
VARh (VPULSE) pulse generator input.
Counter for VPULSE output.
Unsigned numerator, containing a fraction of a pulse. The value
in this register always counts up towards the next pulse.
Roll-over accumulator for VPULSE.
Other CE Parameters
Table 84 shows the QUANT CE parameters used for suppression of noise due to scaling and truncation
effects. The equations for calculating the LSB weight of each QUANT parameter are provided at the
bottom of Table 84.
v2
125
71M6543F/71M6543G Data Sheet
Table 84: CE Parameters for Noise Suppression and Code Version
CE
Address
Name
Default
0x26
0x27
0x28
0x2A
0x2B
0x2C
0x2E
0x2F
0x30
QUANT_IA
QUANT_WA
QUANT_VARA
QUANT_IB
QUANT_WB
QUANT_VARB
QUANT_IC
QUANT_WC
QUANT_VARC
0
0
0
0
0
0
0
0
0
Description
Compensation factors for truncation and noise in current, real
energy and reactive energy for phase A.
Compensation factors for truncation and noise in current, real
energy and reactive energy for phase B.
Compensation factors for truncation and noise in current, real
energy and reactive energy for phase C.
Compensation factors for truncation and noise in current for
phase D.
LSB weights for use with the 71M6xx3 isolated sensors:
0x31
QUANT_ID
0
QUANT _ Ix _ LSB = 5.20864 ⋅ 10 −10 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 8.59147 ⋅ 10 −10 ⋅ VMAX ⋅ IMAX (Watts )
QUANT _ VARx _ LSB = 8.59147 ⋅ 10 −10 ⋅ VMAX ⋅ IMAX (Vars )
LSB weights for use with Current Transformers (CTs):
QUANT _ Ix _ LSB = 5.08656 ⋅ 10 −13 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Watts )
QUANT _ VARx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Vars )
126
v2
71M6543F/71M6543G Data Sheet
5.3.10 CE Calibration Parameters
Table 85 lists the parameters that are typically entered to effect calibration of meter accuracy.
Table 85: CE Calibration Parameters
CE
Address
Name
Default
Description
0x10
0x11
0x13
0x14
0x16
0x17
0x19
CAL_IA
CAL_VA
CAL_IB
CAL_VB
CAL_IC
CAL_VC
CAL_ID
16384
16384
16384
16384
16384
16384
16384
These constants control the gain of their respective channels. The
14
nominal value for each parameter is 2 = 16384. The gain of each
channel is directly proportional to its CAL parameter. Thus, if the
gain of a channel is 1% low, CAL should be increased by 1%.
0x12
PHADJ_A
0
0x15
PHADJ_B
0
0x18
PHADJ_C
0
0x12
DLYADJ_A
0
These constants control the CT phase compensation. No
compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
15
more compensation (lag) is introduced. The range is ± 2 – 1. If it
is desired to delay the current by the angle Φ, the equations are:
0.029615TANΦ
at 60Hz
PHADJ _ X = 2 20
0.1714 − 0.0168 ⋅ TANΦ
PHADJ _ X = 2 20
0.0206 ⋅ TANΦ
at 50Hz
0.1430 − 0.01226 ⋅ TANΦ
The shunt delay compensation is obtained using the equation
provided below:
2πf
2πf
+ 2ab cos
a 2 cos 2
2π
fs
fs
DLYADJ _ X = ∆ deg rees (1 + 0.1∆ deg rees )214
360
2πf
c sin
fs
+ b
where:
a = 2A
0x15
DLYADJ_B
0
b = A2 + 1
2𝜋𝑓
�+2
𝑓𝑠
f is the mains frequency
fs is the sampling frequency
𝑐 = 2𝐴2 + 4𝐴𝑐𝑜𝑠 �
0x18
DLYADJ_C
0
The table below provides the value of A for each channel:
Value of A
Channel
(decimal)
D YADJ_A
13840
DLYADJ_B
11693
DLYADJ_C
9359
Note:
The current sensor inputs are not assigned to the A, B and C phases in a fixed manner. The
assignments of phases A, B and C depends on how the IADC0-1, IADC2-3, IADC4-5, IADC6-7 current
sensing inputs are connected in the meter design. The CE code must be aware of these connections.
See Figure 31 and Figure 32 for typical meter configurations. VADC8, VADC9 and VADC10 are
assigned to voltage phases VA, VB and VC in a fixed manner, respectively.
The CE addresses listed in this table are assigned to phases A, B and C as indicated by their names.
v2
127
71M6543F/71M6543G Data Sheet
5.3.11 CE Flow Diagrams
Figure 38 through Figure 40 show the data flow through the CE in simplified form. Functions not shown
include delay compensation, sample interpolation, scaling and the processing of meter equations.
multiplexer
IA
VA
IB
VB
IC
VC
VREF
∆∑
mod
de-multiplexer
IA_RAW
VA_RAW
IB_RAW
VB_RAW
IC_RAW
VC_RAW
ID_RAW
Decimator
ID
FS= 2184 Hz
FS= 2184 Hz
Figure 38: CE Data Flow: Multiplexer and ADC
Figure 39: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase
128
v2
71M6543F/71M6543G Data Sheet
SUM
WA
WB
WC
VARA
VARB
VARC
WASUM_X
WBSUM_X
WCSUM_X
VARASUM_X
VARBSUM_X
VARCSUM_X
Σ
Σ
I2
V2
IASQ
IBSQ
ICSQ
VASQ
VBSQ
VCSQ
IDSQ
F0
SUM
Σ
Σ
v
SQUARE
IA
IB
IC
VA
VB
VC
ID
MPU
SUM_SAMPS = 2184
IASQSUM_X
IBSQSUM_X
ICSQSUM_X
VASQSUM_X
VBSQSUM_X
VCSQSUM_X
IDSQSUM_X
F0
Figure 40: CE Data Flow: Squaring and Summation Stages
v2
129
71M6543F/71M6543G Data Sheet
6
71M6543 Specifications
This section provides the electrical specifications for the 71M6543. Please refer to the 71M6xxx Data
Sheet for the 71M6xx3 electrical specifications, pin-out and package mechanical data.
6.1
Absolute Maximum Ratings
Table 86 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings only and functional operation at
these or any other conditions beyond those indicated under recommended operating conditions (See 6.3)
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. All voltages are with respect to GNDA.
Table 86: Absolute Maximum Ratings
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A
VBAT, VBAT_RTC
GNDD
Analog Output Pins
VREF
VDD
V3P3D
VLCD
Analog Input Pins
IADC0, IADC1, IADC2, IADC3, IADC4, IADC5, IADC6, IADC7,
VADC8, VADC9 and VADC10
XIN, XOUT
−0.5 V to +4.6 V
-0.5 V to +4.6 V
-0.1 V to +0.1 V
-10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
-10 mA to +10 mA,
-0.5 to +3.0 V
-10 mA to +10 mA,
-0.5 V to 4.6 V
-10 mA to +10 mA,
-0.5 V to +6 V
-10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
-10 mA to +10 mA
-0.5 V to +3.0 V
SEG and SEGDIO Pins
Configured as SEG or COM drivers
Configured as Digital Inputs
Configured as Digital Outputs
-1 mA to +1 mA,
-0.5 V to VLCD+0.5 V
-10 mA to +10 mA,
-0.5 V to +6 V
-10 mA to +10 mA,
-0.5 V to V3P3D+0.5 V
Digital Pins
Inputs (PB, RESET, RX, ICE_E, TEST)
Outputs (TX)
Temperature
Operating junction temperature (peak, 100ms)
Operating junction temperature (continuous)
Storage temperature
Soldering temperature – 10 second duration
130
-10 mA to +10 mA,
-0.5 to 6 V
-10 mA to +10 mA,
-0.5 V to V3P3D+0.5 V
140 °C
125 °C
−45 °C to +165 °C
250 °C
v2
71M6543F/71M6543G Data Sheet
6.2
Recommended External Components
Table 87: Recommended External Components
Name
From
To
C1
V3P3A
GNDA
C2
V3P3D
GNDD
Function
Value
Unit
Bypass capacitor for 3.3 V supply
≥0.1 ±20%
µF
Bypass capacitor for 3.3 V output
0.1 ±20%
µF
CSYS
V3P3SYS
GNDD
Bypass capacitor for V3P3SYS
≥1.0 ±30%
µF
CVDD
VDD
GNDD
Bypass capacitor for VDD
0.1 ±20%
µF
CVLCD
VLCD
GNDD
Bypass capacitor for VLCD pin
≥0.1 ±20%
µF
XTAL
XIN
XOUT
32.768
kHz
CXS
XIN
GNDA
15 ±10%
pF
CXL
XOUT
GNDA
10 ±10%
pF
6.3
32.768 kHz crystal – electrically
equivalent to ECS .327-12.5-17X or
Vishay XT26T, load capacitance 12.5 pF
Load capacitor values for crystal depend
on crystal specifications and board
parasitics. Nominal values are based on
4 pF board capacitance and include an
allowance for chip capacitance.
Recommended Operating Conditions
Unless otherwise specified, all parameters listed under 6.4 Performance Specifications and 6.5 Timing
Specifications are valid over the Recommended Operating Conditions provided in Table 88 below.
Table 88: Recommended Operating Conditions
Parameter
Condition
V3P3SYS and V3P3A Supply Voltage for precision
metering operation (MSN mode). Voltages at
VBAT and VBAT_RTC need not be present.
VBAT=0 V to 3.8 V
VBAT_RTC =0 V to
3.8 V
V3P3SYS < 2.8 V
and
Max(VBAT_RTC,
V3P3SYS) > 2.0 V
VBAT Voltage (BRN mode). V3P3SYS is below
the 2.8 V comparator threshold. Either V3P3SYS
or VBAT_RTC must be high enough to power the
RTC module.
VBAT_RTC Voltage. VBAT_RTC is not needed to
support the RTC and non-volatile memory unless
V3P3SYS