73M1822/73M1922 MicroDAA
Silicon DAA with Serial Interface
DATA SHEET
Simplifying System Integration™
DS_1x22_001
April 2010
DESCRIPTION
APPLICATIONS
The 73M1822 MicroDAA is the world’s first
single-package silicon Data Access Arrangement
(DAA) for data/fax modem and voice applications.
It provides a serial Modem Analog Front End
(MAFE) interface to popular DSP/host processors to
implement a globally compliant low-cost soft modem
solution.
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The 73M1822 MicroDAA is available as a
two-chip configuration (the 73M1922) that consists
of a 73M1902 Host-Side Device and a 73M1912
Line-Side Device. The MicroDAA integrates all
codec and DAA functions necessary to achieve
reliable PSTN connection worldwide.
FEATURES
The MicroDAA uses a small pulse transformer,
which can achieve more than 6 kV isolation. Power
may be supplied along with data through this barrier
interface to achieve superior performance in weak
loop current conditions. Inherently immune to RFI
and other forms of common mode interference, the
patented MicroDAA technology achieves global DAA
compliance with unparalleled flexibility, reliability,
and cost structure and requires less than 2 square
inches of a single sided PCB.
The MicroDAA supports Caller ID Type I and II, ring
detection, tip/ring polarity reversal detection, hook
switch control, pulse dialing, regulation of loop
current (DC mask), configurable line impedance
matching, line in use and parallel pickup detection.
The MicroDAA integrates billing tone filters, external
clock reference, audio monitor output, and requires
only a small number of low cost and commonly
available external components.
The MicroDAA incorporates a configurable sample
rate circuit to support soft modem and
DSP-based implementations of all speeds up to
V.92 (56 Kbps). Sampling rates from 7.2 kHz to
16 kHz can be easily supported.
Rev. 1.6
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V.92 modems
Satellite Set Top Boxes
Fax/Multifunction Peripherals (MFP)
Point of Sale Terminals
Voicemail Systems
Industrial and medical telemetry
Meets FCC, ETSI ES 203 021-2, JATE, NET4
and other PTT standards
Configurable PSTN termination
Up to 8 mA minimum line current operation
0 dBm Transmit/Receive full scale
THD –80 dB
16-bit codec up to 16 kHz sample rate
Up to 56 Kbps (V.92) performance
Configurable sample rates (7.2 – 16 kHz)
Reference clock range of 9-40 MHz
Crystal frequency range of 9-27 MHz
MAFE I/F with Master, Slave and Daisy
Chaining
Billing tone reject filter
Polarity reversal detection on-chip
GPIO for user-configurable I/O port
Call Progress Monitor
3.3 V Operation
Industrial temperature range (-40° to +85° C)
6 kV isolation (73M1922)
4-5 kV isolation (73M1822)
8x8 mm 42-pin QFN (73M1822)
20-pin TSSOP or 5x5 mm 32-pin QFN
(73M1922)
RoHS compliant (6/6) lead-free package
© 2010 Teridian Semiconductor Corporation
1
73M1822/73M1922 Data Sheet
DS_1x22_001
Table of Contents
1
2
3
4
5
6
7
8
2
Introduction ...................................................................................................................................... 6
Pinout ................................................................................................................................................ 8
2.1
73M1902 20-Pin TSSOP Pinout ............................................................................................... 8
2.2
73M1912 20-Pin TSSOP Pinout ............................................................................................. 10
2.3
73M1902 32-Pin QFN Pinout ................................................................................................. 11
2.4
73M1912 32-Pin QFN Pinout ................................................................................................. 13
2.5
73M1822 Pinout..................................................................................................................... 15
2.6
Exposed Bottom Pad on 73M1x66B QFN Packages .............................................................. 16
Electrical Characteristics and Specifications................................................................................ 17
3.1
Isolation Barrier Characteristics.............................................................................................. 17
3.2
Electrical Specifications ......................................................................................................... 17
3.2.1 Absolute Maximum Ratings .......................................................................................... 17
3.2.2 Recommended Operating Conditions ........................................................................... 17
3.2.3 DC Characteristics........................................................................................................ 18
3.3
Serial Interface Timing Specification ...................................................................................... 19
3.4
Analog Specifications............................................................................................................. 19
3.4.1 DC Specifications ......................................................................................................... 19
3.4.2 Call Progress Monitor ................................................................................................... 20
3.5
73M1x22 Line-Side Electrical Specifications (73M1912)......................................................... 22
3.6
Reference and Regulation ..................................................................................................... 22
3.7
AC Signal Levels ................................................................................................................... 22
3.8
DC Transfer Characteristics ................................................................................................... 23
3.9
Transmit Path ........................................................................................................................ 24
3.10 Receive Path ......................................................................................................................... 25
3.11 Transmit Hybrid Cancellation ................................................................................................. 26
3.12 Receive Notch Filter............................................................................................................... 26
3.13 Detectors ............................................................................................................................... 27
3.13.1 Over-Voltage Detector................................................................................................. 27
3.13.2 Over-Current Detector ................................................................................................. 27
3.13.3 Under-Voltage Detector............................................................................................... 27
3.13.4 Over-Load Detector..................................................................................................... 27
Applications Information ................................................................................................................ 28
4.1
Example Schematic of the 73M1922 and 73M1822 ................................................................ 28
4.2
Bill of Materials ...................................................................................................................... 30
4.3
Over-Voltage and EMI Protection ........................................................................................... 31
4.4
Isolation Barrier Pulse Transformer ........................................................................................ 32
Control and Status Registers ......................................................................................................... 33
5.1
Line-Side Device Register Polling .......................................................................................... 36
Hardware Control Functions .......................................................................................................... 37
6.1
Device Revision ..................................................................................................................... 37
6.2
Interrupt Control..................................................................................................................... 37
6.3
Power Management ............................................................................................................... 38
6.4
Device Clock Management .................................................................................................... 38
6.5
GPIO Registers...................................................................................................................... 39
6.6
Call Progress Monitor ............................................................................................................ 40
Clock and Sample Rate Management ............................................................................................ 41
7.1
Clock Generation with HIC (73M1902) ................................................................................... 41
7.2
Crystal Oscillator.................................................................................................................... 41
7.3
PLL Prescaler ........................................................................................................................ 42
7.4
PLL Circuit ............................................................................................................................. 42
7.5
PLL System Timing Control.................................................................................................... 45
MAFE Serial Interface ..................................................................................................................... 46
8.1
Data and Control Frame Formats ........................................................................................... 46
8.2
Data and Control Frame Timing ............................................................................................. 47
8.3
Serial Clock Operation ........................................................................................................... 48
Rev 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
8.4
MicroDAA IN Master/Slave Configuration ............................................................................... 49
8.5
73M1x22 Reset ..................................................................................................................... 49
8.6
73M1x22 in Daisy Chain Configuration................................................................................... 50
8.7
MAFE Configuration Registers ............................................................................................... 51
8.8
Slave Registers...................................................................................................................... 51
9
Signal Processing........................................................................................................................... 52
9.1
Transmit Path Signal Processing ........................................................................................... 52
9.1.1 General Description ...................................................................................................... 52
9.1.2 Total Transmit Path Response...................................................................................... 52
9.1.3 73M1x22 Transmit Spectrum ........................................................................................ 53
9.2
Receive Path Signal Processing ............................................................................................ 53
9.2.1 General Description ...................................................................................................... 53
9.2.2 Total Receive Path Response....................................................................................... 54
9.3
Signal Control Functions ........................................................................................................ 55
9.3.1 Transmit and Receive Level Control ............................................................................. 55
10 Barrier Information ......................................................................................................................... 57
10.1 Isolation Barrier...................................................................................................................... 57
10.2 Barrier Powered Options ........................................................................................................ 57
10.2.1 Barrier Powered Operation .......................................................................................... 57
10.2.2 Line Powered Operations ............................................................................................ 57
10.3 Synchronization of the Barrier ................................................................................................ 57
10.4 Auxiliary A/D Converter .......................................................................................................... 58
10.5 Auto-Poll................................................................................................................................ 58
10.6 Barrier Control Functions ....................................................................................................... 59
10.7 Line-Side Device Operating Modes ........................................................................................ 60
10.8 Fail-Safe Operation of the Line-Side Device ........................................................................... 60
11 Configurable Direct Access Arrangement (DAA) .......................................................................... 61
11.1 Pulse Dialing.......................................................................................................................... 61
11.2 DC Termination...................................................................................................................... 61
11.2.1 Current Limit Detection................................................................................................ 63
11.3 AC Termination ...................................................................................................................... 63
11.4 Billing Tone Rejection ............................................................................................................ 64
11.5 Trans-Hybrid Cancellation ...................................................................................................... 65
11.6 Direct Access Arrangement Control Functions ....................................................................... 65
11.7 International Register Settings Table for DC and AC Terminations ......................................... 69
12 Line Sensing and Status ................................................................................................................ 70
12.1 Auxiliary A/D Converter .......................................................................................................... 70
12.2 Ring Detection ....................................................................................................................... 70
12.3 Line In Use Detection (LIU) .................................................................................................... 70
12.4 Parallel Pick Up (PPU) ........................................................................................................... 70
12.5 Polarity Reversal Detection .................................................................................................... 70
12.6 Off-hook Detection of Caller ID Type II ................................................................................... 70
12.7 Voltage and Current Detection ............................................................................................... 71
12.8 Under Voltage Detection (UVD) ............................................................................................. 71
12.9 Over Voltage Detection (OVD) ............................................................................................... 71
12.10 AC Signal Over Load Detection.............................................................................................. 71
12.11 Over Current Detection (OID)................................................................................................. 71
12.12 Line Status Functions Control Functions ................................................................................ 72
13 Loopback and Testing Modes ........................................................................................................ 75
14 Performance ................................................................................................................................... 77
14.1 DC VI Characteristics ............................................................................................................. 77
14.2 Receive ................................................................................................................................. 78
15 Package Layout .............................................................................................................................. 79
16 Ordering Information ...................................................................................................................... 81
17 Contact Information........................................................................................................................ 81
Revision History ..................................................................................................................................... 82
Rev. 1.6
3
73M1822/73M1922 Data Sheet
DS_1x22_001
Figures
Figure 1: Simple 73M1x22 Reference Block Diagram.................................................................................. 6
Figure 2: 73M1902 20-Pin TSSOP Pinout ................................................................................................... 8
Figure 3: 73M1912 20-Pin TSSOP Pinout ................................................................................................. 10
Figure 4: 73M1902 32-Pin QFN Pinout ..................................................................................................... 11
Figure 5: 73M1912 32-Pin QFN Pinout ..................................................................................................... 13
Figure 6: 73M1822 42-Pin Pinout.............................................................................................................. 15
Figure 7: MAFE Timing Diagram ............................................................................................................... 19
Figure 8: Call Progress Monitor Frequency Response............................................................................... 20
Figure 9: Demo Board Circuit Connecting AOUT to a Speaker .................................................................. 20
Figure 10: Recommended Circuit for the 73M1922 ................................................................................... 28
Figure 11: Recommended Circuit for the 73M1822 ................................................................................... 29
Figure 12: Suggested Over-voltage Protection and EMI Suppression Circuit ............................................. 31
Figure 13: Clock Generation Block Diagram (assumes 8 kHz sample rate) ............................................... 41
Figure 14: Crystal Oscillator with Configurable Load Current..................................................................... 41
Figure 15: Prescaler Block Diagram .......................................................................................................... 42
Figure 16: PLL Block Diagram .................................................................................................................. 42
Figure 17: Serial Port Timing Diagram ...................................................................................................... 46
Figure 18: Data and Control Frames Timing Diagram................................................................................ 47
Figure 19: Control Frame Position versus SPOS....................................................................................... 48
Figure 20: SCLK and FS with SCKM = 0................................................................................................... 48
Figure 21: Example Connections for Master and Slave Operation ............................................................. 49
Figure 22: Master/Slave Serial Timing Diagram ........................................................................................ 49
Figure 23: Daisy Chaining a Master and Two Slaves ................................................................................ 50
Figure 24: Timing Diagram with One Master and Two Slaves .................................................................... 50
Figure 25: Transmit Path Overall Frequency Response to Fs (8 kHz)........................................................ 52
Figure 26: Pass-Band Response of the Transmit Path .............................................................................. 52
Figure 27: Transmit Spectrum to 32 kHz ................................................................................................... 53
Figure 28: Overall Frequency Response of the Receive Path .................................................................... 54
Figure 29: Pass-band Response of the Overall Receive Path.................................................................... 54
Figure 30: Line-Side Device AC and DC Circuits....................................................................................... 60
Figure 31: DC-IV Characteristics............................................................................................................... 61
Figure 32: Tip-Ring Voltage versus Current Using Different DCIV Settings................................................ 62
Figure 33: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings ............................ 63
Figure 34: Magnitude Response of IPMF, ACZ=01 (ETSI ES 203 021-2) .................................................. 64
Figure 35: Magnitude Response of Billing Tone Notch Filter ..................................................................... 64
Figure 36: Loopback Modes Highlighted ................................................................................................... 75
Figure 37: Off-Hook Tip and Ring DC Characteristics................................................................................ 77
Figure 38: ES 203 021-2 DC Mask with Current Limit Enabled .................................................................. 77
Figure 39: Australian Hold State Characteristics ....................................................................................... 78
Figure 40: Return Loss ............................................................................................................................. 78
Figure 41: 20-Pin TSSOP Package Dimensions........................................................................................ 79
Figure 42: 32-Pin QFN Package Dimensions ............................................................................................ 79
Figure 43: 42-Pin QFN Package Dimensions ............................................................................................ 80
4
Rev. 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
Tables
Table 1: 73M1902 20-Pin TSSOP Pin Definitions ........................................................................................ 8
Table 2: 73M1912 20-Pin TSSOP Pin Definitions ...................................................................................... 10
Table 3: 73M1902 32-Pin QFN Pin Definitions .......................................................................................... 11
Table 4: 73M1912 32-Pin QFN Pin Definitions .......................................................................................... 13
Table 5: 73M1822 Pin Definitions ............................................................................................................. 15
Table 6: Isolation Barrier Characteristics at 8 kHz Sample Rate ................................................................ 17
Table 7: Absolute Maximum Device Ratings ............................................................................................. 17
Table 8: Recommended Operating Conditions .......................................................................................... 17
Table 9: DC Characteristics ...................................................................................................................... 18
Table 10: Serial Data Port Timing at 8 kHz Sample Rate........................................................................... 19
Table 11: Reference Voltage Specifications .............................................................................................. 19
Table 12: Component Values for the Speaker Driver ................................................................................. 20
Table 13: Call Progress Monitor Specification ........................................................................................... 21
Table 14: Line-Side Absolute Maximum Ratings ....................................................................................... 22
Table 15: VBG Specifications ................................................................................................................... 22
Table 16: Maximum Transmit Levels ......................................................................................................... 22
Table 17: Maximum DC Transmit Levels ................................................................................................... 23
Table 18: Transmit Path............................................................................................................................ 24
Table 19: Receive Path ............................................................................................................................ 25
Table 20: Transmit Hybrid Cancellation Characteristics ............................................................................. 26
Table 21: Receive Notch Filter .................................................................................................................. 26
Table 22: Over-Voltage Detector............................................................................................................... 27
Table 23: Over-Current Detector ............................................................................................................... 27
Table 24: Under-Voltage Detector ............................................................................................................. 27
Table 25: Over-Load Detector ................................................................................................................... 27
Table 26: Reference Bill of Materials for 73M1822/73M1922..................................................................... 30
Table 27: Reference Bill of Materials for Figure 12 .................................................................................... 31
Table 28: Compatible Pulse Transformer Sources .................................................................................... 32
Table 29: Transformer Characteristics ...................................................................................................... 32
Table 30: Control and Status Register Map ............................................................................................... 33
Table 31: Alphabetical Bit Map ................................................................................................................. 34
Table 32: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................. 43
Table 33: Clock Generation Register Settings for Fxtal = 24.576 MHz....................................................... 43
Table 34: Clock Generation Register Settings for Fxtal = 9.216 MHz......................................................... 43
Table 35: Clock Generation Register Settings for Fxtal = 24.000 MHz....................................................... 44
Table 36: Clock Generation Register Settings for Fxtal = 25.35 MHz......................................................... 44
Table 37: PLL System Timing Controls ..................................................................................................... 45
Table 38: Behavior of SCLK under SCKM................................................................................................. 48
Table 39: Signal Control Functions ........................................................................................................... 55
Table 40: Transmit Gain Control ............................................................................................................... 55
Table 41: Receive Gain Control ................................................................................................................ 56
Table 42: Barrier Control Functions........................................................................................................... 59
Table 43: Trans-Hybrid Cancellation ......................................................................................................... 65
Table 44: DAA Control Functions .............................................................................................................. 65
Table 45: Recommended Register Settings for International Compatibility ................................................ 69
Table 46: Line Sensing Control Functions ................................................................................................. 72
Table 47: Loopback Modes....................................................................................................................... 75
Table 48: Loopback Controls .................................................................................................................... 76
Table 49: Order Numbers and Packaging Marks ....................................................................................... 81
Rev. 1.6
5
73M1822/73M1922 Data Sheet
DS_1x22_001
1 Introduction
The 73M1922 MicroDAA is a two-device chip set that consists of a 73M1902 Host-Side Device and a
73M1912 Line-Side Device that can be used in any voice-band PSTN telephone interface application
requiring a CODEC. The 73M1822 is a single-package MicroDAA with the same interfaces. Each connects
directly between a host processor and the telephone network with a low-cost pulse transformer to provide
the required high-voltage isolation. A few low-cost components complete the interface to the network. The
pulse transformer transmits encoded digital data rather than analog signals as with other transformer
designs. Data is transmitted and received without the usual degradation from common mode noise and
magnetic coupling typical of other capacitive and voice-band transformer techniques. The data stream
passed between the Host-Side and Line-Side Devices includes the media stream data, control, status and
clocking information.
The data sheet describes both the 73M1922 and 73M1822, which will be collectively referred to as the
73M1x22 in this document.
The Host-Side Device uses a serial data port for transferring transmit and receive data, status and control
information to a host. This interface is compatible with most DSP and high-performance processor
synchronous serial CODEC interfaces.
All media stream data and control information between the Host-Side Device and Line-Side Device of the
73M1822 and 73M1922 are transferred across the pulse transformer. Clocking information used by the
Line-Side Device is embedded in the bit stream received from the Host-Side Device and reconstructed by
the Line-Side Device of the 73M1822 or 73M1922.
On start up, the Host-Side Device provides power to the Line-Side Device through the transformer. After
going off-hook, the Line-Side Device is capable of being powered from the PSTN network. The only
physical connections between the devices are the primary side of the pulse transformer that is connected to
the Host-Side Device and the secondary side to the Line-Side Device.
Figure 1 shows a reference block diagram of the 73M1922 connected by a pulse transformer and example
external line interface circuitry shown for clarification.
Host-Side Device
Line-Side Device
73M1902
73M1912
CTL
STA
Ring
Buffer
Aux A/D
STA
Tip
SCP
PRP
TxData
RxData
MAFE
Interface
Transmit
Interpolation
Filter (TIF) TxD Modem
Side
Barrier
Interface
Receive
Decimation RxD (MSBI)
Filter (RDF)
Line
Side
Barrier
Interface
(LSBI)
PRM
Digital
Sigma
Delta
Modulator
(DSDM)
SinC3
Filter
TBS
RBS
Transmit
Analog
Front End
(TxAFE)
Receive
Analog
Front End
(RxAFE)
SCM
TxA
Off-Chip
Line
Interface
Circuit
On-Chip
Line
Interface
Circuit
RxA
Ring
Figure 1: Simple 73M1x22 Reference Block Diagram
The Host-Side Device (73M1902) consists of:
1.
2.
3.
4.
6
Modem Analog Front End (MAFE) Interface Block
Transmit Interpolation Filter (TIF)
Receive Decimation Filter (RDF)
Modem-Side Barrier Interface Circuit (MSBI)
Rev. 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
The Line-Side Device (73M1912 / 73M1822) consists of:
1.
2.
3.
4.
5.
6.
Digital Sigma Delta Modulator (DSDM)
Transmit Analog Front End (TxAFE)
Receive Analog Front End (RxAFE) including Sigma Delta Modulator (ASDM)
Sinc^3 Filter (Sinc3)
On-chip Line Interface Circuit (ONLIC)
Line-Side Barrier Interface Circuit (LSBI)
The transmit data (TxData) is interpolated up within TIF (Transmit Interpolation Filter) from the sampling
frequency (Fs) to twice the sampling frequency resulting in TxD.
Control information (CTL) is time-division multiplexed with TxD, serialized within MSBI, and sent across the
barrier to 73M1912 LIC (Line Interface Circuitry). This is then received and processed within LSBI and
separated into TxD and CTL. TxD is digitally sigma-delta modulated to form a serialized Transmit Bit
Stream (TBS). The TBS is D/A converted for final transmission to the line. CTL is used to control various
features of the Line-Side Device.
On the receive side, the received analog signal from the line is sigma-delta modulated to form a serialized
Receive Bit Stream (RBS). RBS is decimated down to twice the sampling frequency as RxD and
time-division multiplexed with status Information (STA) from the Auxiliary A/D regarding line condition in
LSBI block and transmitted to the Host-Side Device. The MSBI processes this data and separates it into
RxD and STA. Rxd is further decimated to down to Fs and sent to the host through the MAFE interface.
STA is sent to the host through the MAFE interface using a different time slot.
Rev. 1.6
7
73M1822/73M1922 Data Sheet
DS_1x22_001
2 Pinout
The 73M1922 consists of two devices, the 73M1902 and the 73M1912, which are available as 20-pin
TSSOP packages and as 32-pin QFN package sets.
2.1
73M1902 20-Pin TSSOP Pinout
Figure 2 shows the 73M1902 20-pin TSSOP pinout.
FSD
1
20
SDOUT
FS
2
19
SDIN
VND
3
18
VND
VPD/VPPLL
4
17
SCLK
OSCIN/MCLK
5
16
INT/RGDT
OSCOUT
6
15
VPT/VPD
VNPLL/VNA
7
14
PRP
8
13
PRM
TYPE
9
12
M/S
VPA/VPM
10
11
VNMVNT
AOUT
73M1902
Figure 2: 73M1902 20-Pin TSSOP Pinout
Table 1 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 1: 73M1902 20-Pin TSSOP Pin Definitions
Pin
Number
Pin
Name
1
FSD
2
3
4
FS
VND
VPD/VPPLL
5
OSCIN/MCLK
6
7
8
OSCOUT
VNA/VNPLL
AOUT
O
GND
O
9
TYPE
I
10
11
12
13
VPA/VPM
VNM/VNT
8
M/S
PRM
Type
O
O
GND
PWR
I
PWR
GND
I
I/O
Description
Frame synchronization (FS) delayed
Frame synchronization
Negative digital ground
Positive digital/PLL supply
Crystal oscillator circuit input pin.
Input from an external clock source. Crystal frequency range
is 9 MHz – 27 MHz.
Crystal oscillator output pin. (N.C. with external oscillator)
Negative analog/PLL ground
Call progress audio output
Type of frame sync. 0 = late (mode0), 1 = early (mode1).
Weak-pulled high – default = early.
Positive analog supply
Negative barrier interface supply / negative transformer supply
Master/slave control, reset at a transition.
Pulse transformer primary minus
Rev. 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
14
15
PRP
VPD
16
INT/RGDT
O
17
SCLK
O
18
19
20
VND
GND
Rev. 1.6
SDIN
SDOUT
I/O
PWR
I
O
Pulse transformer primary plus
Positive digital supply, positive transformer supply
Ring detection indicator or other Interrupts
Open drain
Serial interface clock. With continuous SCLK selected,
Frequency = 256∗Fs (=1.8432MHz for Fs=7.2kHz, 2.048MHz
for Fs=8kHz)
Negative digital ground
Serial data input (or output from the controller to 73M1902)
Serial data output (or input to the controller from 73M1902)
9
73M1822/73M1922 Data Sheet
2.2
DS_1x22_001
73M1912 20-Pin TSSOP Pinout
Figure 3 shows the 73M1912 20-pin TSSOP pinout.
DCI
1
20
DCG
RGN
2
19
DCS
RGP
3
18
DCD
OFH
4
17
TXM
VND/VNX
5
16
RXM
SCP
6
15
RXP
MID
7
14
VPD/VPS
VPX
8
13
VNX/VNS
SRE
9
12
ACS
SRB
10
11
VBG
73M1912
Figure 3: 73M1912 20-Pin TSSOP Pinout
Table 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 2: 73M1912 20-Pin TSSOP Pin Definitions
Pin
Number
Pin Name
Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DCI
RGN
RGP
OFH
VND/VNX
SCP
MID
VPX
SRE
SRB
VBG
ACS
VNX/VNS
VPD/VPS
I
I
I
O
GND
I/O
I/O
PWR
I
O
O
I
GND
PWR
DC loop input
Ring detect negative voltage input
Ring detect positive voltage input
Off-hook control
Digital/analog negative supply voltage
Positive side of the secondary pulse transformer winding
Charge pump midpoint
Supply from the barrier, connect to VPD
Voltage regulator sense
Voltage regulator drive
VBG bypass, connect to 0.1 μF capacitor to VNS
AC current sense
Digital/analog negative supply voltage
Digital/analog positive supply voltage
15
16
17
18
19
20
RXP
RXM
TXM
DCD
DCS
DCG
10
I
I
O
O
I
O
Receive plus – signal input
Receive minus – signal input
Transmit minus – signal output
DC loop drive
DC loop current sense
DC loop drive
Rev. 1.6
DS_1x22_001
2.3
73M1822/73M1922 Data Sheet
73M1902 32-Pin QFN Pinout
GPIO6
GPIO7
VND
FS
FSD
VPD
SDOUT
SDIN
32
31
30
29
28
27
26
25
Figure 4 shows the 73M1902 32-pin QFN pinout.
VND
1
24
VND
GPIO5
2
23
SCLK
GPIO4
3
22
INT/RGDT
VPD/VPPLL
4
21
LEV
OSCIN/MCLK
5
20
VPT/VPD
OSCOUT
6
19
RST
VNPLL
7
18
PRP
VNA
8
17
PRM
10
11
12
13
14
15
16
AOUT
TOUT
TYPE
VPA/VPM
SCLKM
VNM/VNT
M/S
VBG
9
73M1902
Figure 4: 73M1902 32-Pin QFN Pinout
Table 3 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 3: 73M1902 32-Pin QFN Pin Definitions
Pin
Number
1
2
3
4
Pin Name
Type
Description
VND
GPIO5
GPIO4
VPD/VPPLL
GND
I/O
I/O
PWR
Negative digital ground
Configurable digital input/output pins
Configurable digital input/output pins
Positive digital/PLL supply
Crystal oscillator circuit input pin.
Input from an external clock source.
Crystal frequency range supported is 9 MHz – 27 MHz.
Crystal oscillator output pin. (N.C. with external oscillator)
Negative analog/PLL ground
Negative analog/PLL ground
Band gap voltage reference monitor
Call progress audio output
Digital test output
Type of frame sync. 0 = late (mode0), 1 = early (mode1).
Weak-pulled high – default = early.
Positive analog supply
5
OSCIN/MCLK
6
7
OSCOUT
VNA/VNPLL
O
GND
8
9
10
11
VNA/VNPLL
VBG
AOUT
TOUT
GND
O
O
O
12
TYPE
13
VPA/VPM
Rev. 1.6
I
I
PWR
11
73M1822/73M1922 Data Sheet
DS_1x22_001
Pin
Number
Pin Name
14
SCKM
15
VNM/VNT
16
17
18
M/S
PRM
PRP
I/O
I/O
19
20
21
RST
VPD
LEV
I
PWR
O
22
INT/RGDT
O
23
SCLK
O
24
25
26
27
28
29
30
31
32
VND
SDIN
SDOUT
VPD
12
FSD
FS
VND
GPIO7
GPIO6
Type
I
GND
I
GND
I
O
PWR
O
O
GND
I/O
I/O
Description
Controls the SCLK behavior after FS. Weak-pulled high –
default = continuous SCLK
Negative barrier interface/transformer supply
Master/slave control, reset at a transition
Pulse transformer primary minus
Pulse transformer primary plus
Factory test mode – leave open
Positive digital supply, positive transformer supply
Test output (CMOS level)
Ring detection indicator or other Interrupts.
Open drain
Serial interface clock. With continuous SCLK selected,
Frequency = 256∗Fs (=1.8432MHz for Fs=7.2kHz, 2.048MHz
for Fs=8kHz)
Negative digital ground
Serial data input (or output from the controller to 73M1902)
Serial data output (or input to the controller from 73M1902)
Positive digital supply, positive transformer supply
FS delayed
Frame synchronization
Negative digital ground
Configurable digital input/output pins
Configurable digital input/output pins
Rev. 1.6
DS_1x22_001
2.4
73M1822/73M1922 Data Sheet
73M1912 32-Pin QFN Pinout
GPO
GPI
VNS
RGP
RGN
DCI
DCG
DCS
32
31
30
29
28
27
26
25
Figure 5 shows the 73M1912 32-pin QFN pinout.
CKO
1
24
DCD
OFH
2
23
RST
CKI
3
22
TST
VND/VNX
4
21
TXM
20
SACIN
73M1912
15
16
VNS
VPS
ACS
17
14
8
VBG
VPX
13
RXP
VNS
18
12
7
SRB
SCM
11
RXM
SRE
19
10
6
BYP
MID
9
5
RCT
SCP
Figure 5: 73M1912 32-Pin QFN Pinout
Table 4 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 4: 73M1912 32-Pin QFN Pin Definitions
Pin
Number
1
Pin
Name
CKO
2
Type
Description
O
Test point for recovered clock
OFH
O
Off-hook control
3
CKI
I
Test input for clock
4
5
6
7
8
VND/VNX
SCP
MID
SCM
VPX
9
RCT
I
10
11
12
13
14
15
16
BYP
SRE
SRB
VNS
VBG
ACS
VNS
I
I
O
GND
O
I
GND
Rev. 1.6
GND
I/O
I/O
I/O
PWR
Digital/analog negative supply voltage
Positive side of the secondary pulse transformer winding
Charge pump midpoint
Negative side of the secondary pulse transformer winding
Supply from the barrier side, connect to VPD
External rectification – disables internal rectifier when low, leave
open
Factory test mode – leave open
Voltage regulator sense
Voltage regulator drive
Analog/digital negative supply voltage
VBG bypass, connect to 0.1μF capacitor to VPS
AC current sense
Analog/digital negative supply voltage
13
73M1822/73M1922 Data Sheet
DS_1x22_001
Pin
Number
17
Pin
Name
VPS
18
19
RXP
RXM
I
I
Receive plus – signal input
Receive minus – signal input
20
21
SACIN
TXM
I
O
Caller ID mode AC impedance connection
Transmit minus – transhybrid cancellation output
22
23
24
TST
RST
DCD
I
I
O
Factory test mode – leave open
Factory test mode – leave open
DC loop drive
25
26
27
28
29
30
31
32
DCS
DCG
DCI
RGN
RGP
VNS
GPI
GPO
I
O
I
I
I
GND
I
O
14
Type
Description
PWR
Analog/digital positive supply voltage
DC loop current sense
DC loop drive
DC loop input
Ring detect negative voltage input
Ring detect positive voltage input
Analog/digital negative supply voltage
General purpose input (test pin)
General purpose output (test pin)
Rev. 1.6
DS_1x22_001
2.5
73M1822/73M1922 Data Sheet
73M1822 Pinout
VPX
MID
SCP
VND/VNX
M20BP
OFH
RGP
RGN
DCI
DCG
DCS
42
41
40
39
38
37
36
35
34
33
32
Figure 6 shows the 73M1822 42-pin pinout.
31
DCD
30
TXM
29
RXM
PRM
1
28
RXP
PRP
2
27
VPS
VPD/VPT
3
26
VNS
INT/RGDT
4
25
ACS
SCLK
5
24
VBG
SDIN
6
23
SRB
SDOUT
7
22
SRE
FSD
8
FS
9
11
12
13
14
15
16
17
18
19
20
21
VND
VPD/VPPLL
OSCIN/MCLK
OSCOUT
VNA/VNPLL
VNA
AOUT
VPA/VPM
VNA
M/S
10
GPIO
VND
73M1822
Figure 6: 73M1822 42-Pin Pinout
Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 5: 73M1822 Pin Definitions
Pin
Number
1
2
3
Pin Name
Type
Description
PRP
PRM
VPD/VPT
I/O
I/O
PWR
4
INT/RGDT
O
5
SCLK
O
6
7
8
9
10
11
12
13
SDIN
SDOUT
FSD
Pulse transformer primary plus
Pulse transformer primary minus
Positive digital/transformer supply
Ring detection indicator or other Interrupts
Open drain
Serial interface clock. With continuous SCLK selected,
Frequency = 256∗Fs (=1.8432 MHz for Fs=7.2 kHz, 2.048 MHz
for Fs=8 kHz)
Serial data input (or output from the controller to the 73M1822)
Serial data output (or input to the controller from the 73M1822)
FS delayed
Frame synchronization
Negative digital ground
Configurable digital input/output pins
Negative digital ground
Positive digital supply
Rev. 1.6
FS
VND
GPIO
VND
VPD/VPPLL
I
O
O
O
GND
I/O
GND
PWR
15
73M1822/73M1922 Data Sheet
DS_1x22_001
Pin
Number
Pin Name
14
OSCIN/MCLK
15
16
17
18
19
20
OSCOUT
VNA/VNPLL
VNA
AOUT
VPA/VPM
VNM/VNT
O
GND
GND
O
PWR
GND
Crystal oscillator circuit input pin.
Input from an external clock source. Crystal frequency range
supported is 9 MHz – 27 MHz.
Crystal oscillator output pin. (N.C. with external oscillator)
Negative PLL ground
Negative analog ground
Call progress audio output
Positive analog supply
Negative transformer supply
21
22
23
24
25
26
27
28
29
30
31
M/S
SRE
SRB
VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
I
I
O
O
I
GND
PWR
I
I
O
O
Master or slave selection / reset - active during transition
S/Sh regulator sense
S/Sh regulator drive
VBG bypass, connect to 0.1uF capacitor to VPS
AC current sense
LIC analog/digital negative ground
LIC analog/digital positive supply voltage
Receive plus -signal input
Receive minus - signal input
Transmit minus - signal output
DCD for integrated Darlington
32
33
34
35
36
37
38
DCS
DCG
DCI
RGM
RGP
OFH
M20BP
39
40
41
42
VND/VNX
SCP
MID
VPX
2.6
Type
I
I
O
I
I
I
O
I
GND
I/O
I/O
PWR
Description
DC loop current sense
DC loop drive
DC loop input
Ring minus voltage input
Ring plus voltage input
Off-hook control
Substrate connection. Connect to VNX.
LIC digital/analog negative ground
Positive side of the secondary pulse transformer winding
Charge pump -normally left open
LIC supply from the barrier side
Exposed Bottom Pad on 73M1x66B QFN Packages
The 73M1822 and 73M1922 QFN packages have exposed pads on the underside that are intended
for device manufacturing purposes. These exposed pads are not intended for thermal relief (heat
dissipation) and should not be soldered to the PCB. Soldering of the exposed pad could also
compromise electrical isolation/insulation requirements for proper voltage isolation. Avoid any PCB
traces or through-hole vias on the PCB beneath the exposed pad area.
16
Rev. 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
3 Electrical Characteristics and Specifications
3.1
Isolation Barrier Characteristics
Table 6 provides the characteristics of the 73M1x22 Isolation Barrier.
Table 6: Isolation Barrier Characteristics at 8 kHz Sample Rate
Parameter
Barrier frequency
Data transfer rate across the barrier
3.2
Rating
768 kHz
1.536 Mbps
Electrical Specifications
This section provides the absolute maximum ratings, the recommended operating conditions and the DC
characteristics.
3.2.1 Absolute Maximum Ratings
Table 7 lists the maximum operating conditions for the 73M1x22. Permanent device damage may occur if
absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for
extended periods may affect device reliability.
Table 7: Absolute Maximum Device Ratings
Parameter
Supply voltage
Pin input voltage (except OSCIN)
Pin input voltage (OSCIN)
Min
-0.5
-0.5
-0.5 to VDD
Max
4.0
6.0
0.5
Unit
V
V
V
3.2.2 Recommended Operating Conditions
Function operation should be restricted to the recommended operating conditions specified in Table 8.
Table 8: Recommended Operating Conditions
Parameter
Supply voltage (VDD) with respect to VSS
Operating temperature
Rev. 1.6
Min
3.0 V
0
Max
3.6
85
Unit
V
°C
17
73M1822/73M1922 Data Sheet
DS_1x22_001
3.2.3 DC Characteristics
Table 9 lists the 73M1x22 DC characteristics.
Table 9: DC Characteristics
Parameter
Input low voltage
Input high voltage
(except OSCIN)
Input High Voltage
OSCIN
Output low voltage
(except OXCOUT, FS,
SCLK, SDOUT)
Output low voltage
OSCOUT
Output Low Voltage
FS, SCLK, SDOUT
Output high voltage
(except OSCOUT, FS,
FSD, SCLK, SDOUT)
Output High Voltage
OSCOUT
Output high voltage
FS, FSD, SCLK, SDOUT
Input low leakage current
Input high leakage current
Input Leakage Current
OSCIN
Input High Leakage Current
OSCIN
Active digital current
Active PLL current
Active analog current
IDD total current*
IDD total current*
IDD current
PWDN=1
IDD current
SLEEP=1 (Ext Ref Clk)
IDD current
IDL2=1 (Ext Ref Clk)
IDD current
ENFEH=0 (Ext Ref Clk)
VIL
VIH1
Condition
–
–
Min
-0.5
0.7 VDD
Nom
–
–
Max
0.2 ∗ VDD
5.5
Unit
V
V
VIH2
–
0.7 VDD
–
VDD + 0.5
V
VOL
IOL=4 mA
–
–
0.45
V
VOLOSC
IOL=3 mA
–
–
0.7
V
VOL
IOL = 1mA
–
–
0.45
V
VOH
IOH=-4 mA
VDD - 0.45
–
–
V
VOHOSC
IOH =-3.0 mA
VDD - 0.9
–
–
V
VOH
IOH=-1 mA
VDD - 0.45
–
–
V
IIL1
VSS < Vin < VIL1
10
–
40
μA
IIH1
IIL2
VIH1 < Vin < 5.5
VSS < Vin < VIL2
1
–
–
1
30
μA
μA
IIH2
VIH2 < Vin < VDD
1
–
10
μA
1.0
1.0
12
15
20
1.0
1.5
1.5
17
20
30
5
mA
mA
mA
mA
mA
μA
IDD current at 3.0 V – 3.6 V Nominal at 3.3 V
–
–
IDD1dig
–
–
IDD1pll
–
–
IDD1ana
–
–
IDD1
–
–
IDD2
–
–
IDD2
IDD3
–
–
0.5
1.0
mA
IDD4
–
–
10
15
mA
IDD5
–
–
1.0
1.5
mA
*Note: IDD1 is with the secondary of the barrier left open.
IDD2 is with the secondary of the barrier connected to the 73M1912 fully powered.
18
Rev. 1.6
DS_1x22_001
3.3
73M1822/73M1922 Data Sheet
Serial Interface Timing Specification
The 73M1x22 has a synchronous serial interface, called the MAFE interface, to transfer data to and from a
host. Table 10 provides the timing specification for the MAFE interface.
Table 10: Serial Data Port Timing at 8 kHz Sample Rate
Parameter
SCLK period (Tsclk)
SCLK to FS delay (td1) – mode1
SCLK to FS delay (td2) – mode1
SCLK to SDOUT delay (td3) with 10 pf load
Setup time SDIN to SCLK (tsu)
Hold time SDIN to SCLK (th)
SCLK to FS delay (td4) – mode 0
SCLK to FS delay (td5) – mode 0
Min
–
–
–
–
15
10
–
–
Nom
1/1.536 MHz
–
–
–
–
–
–
–
Max
–
20
20
20
–
–
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
FS
(mode1)
SDOut
SDIN
FS
(mode0)
Figure 7: MAFE Timing Diagram
3.4
Analog Specifications
This section provides the electrical characterizations of the 73M1x22 analog circuitry.
3.4.1 DC Specifications
VBG is to be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not
intended for any other external use.
Table 11: Reference Voltage Specifications
Parameter
VBG
VBG Noise
VBG PSRR
Rev. 1.6
Test Condition
VDD=3.0 V – 3.6 V
300 Hz – 3.3 kHz
300 Hz – 30 kHz
Min
0.9
–
40
Nom
1.19
-86
–
Max
1.4
-80
–
Units
V
dBm600
dB
19
73M1822/73M1922 Data Sheet
DS_1x22_001
3.4.2 Call Progress Monitor
The Call Progress Monitor monitors activities on the line. The audio output contains both transmit and
receive data with a configurable level individually set by Register 0x10.
Figure 8 shows the frequency response of the Call Progress Monitor Filter based upon the characteristics of
the device plus the external circuitry as shown.
Figure 8: Call Progress Monitor Frequency Response
C1 0.1uF R1 120K
R2
120K
-VIN
CD
VOUT1
VOUT2
LS1
AOUT
VCC
R3 120K
4
1
2
3
+
C2
2.2uF
VREF1
VREF2
C4
1uF
U1
V+
GND
5
8
AT-2308
INTERVOX
VCC
6
7
C3
NJM2135
1uF
Figure 9: Demo Board Circuit Connecting AOUT to a Speaker
Table 12: Component Values for the Speaker Driver
Quantity
1
1
2
1
3
1
Reference
C1
C2
C3, C4
LS1
R1, R2, R3
U1
Part Description
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Sound transducer
1/8 W resistor
Audio amplifier
Part
0.1 μF
2.2 μF (optional)
1 μF
Speaker (Intervox)
120 kΩ
NJM2135 (New Japan Radio)
All measurements are at the AOUT pin with CMVSEL=0. Note that when CMVSEL=1, the peak signal at
AOUT is increased to approximately 1.11 Vpk.
20
Rev. 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
Table 13: Call Progress Monitor Specification
Parameter
AOUT for transmit
AOUT transmit THD
AOUT for receive
AOUT receive THD
AOUT output
impedance
Rev. 1.6
Test Condition
1 kHz full swing code word at
SDIN pin
CMRXG=11(Mute)
Observe AOUT pin
CMTXG=00
CMTXG=01 relative
to CMTXG=00
CMTXG=10 relative
to CMTXG=00
CMTXG=11(Mute)
CMTXG=00
1.0 Vpk, 1 kHz at the line or 0.5
Vpk at RXP/RXM with
RXG=10 (+6 dB)
CMTXG=11(Mute)
Observe AOUT pin
CMRXG=00
CMRXG=01 relative
to CMRXG=00
CMRXG=10 relative
to CMRXG=00
CMRXG=11(Mute)
CMRXG=00
–
Min
Nom
Max
Units
–
–
–
–
–
0.98
–
Vpk
–
-6
–
dB
–
-12
–
dB
–
–
Mute
40
–
–
dB
dB
–
–
–
–
–
0.96
–
Vpk
–
-6
–
dB
–
-12
–
dB
–
–
Mute
40
–
–
dB
dB
–
10
–
kΩ
21
73M1822/73M1922 Data Sheet
3.5
DS_1x22_001
73M1x22 Line-Side Electrical Specifications (73M1912)
Table 14 lists the absolute maximum ratings for the line side. Operation outside these rating limits may
cause permanent damage to this device.
Table 14: Line-Side Absolute Maximum Ratings
Parameter
Pin input voltage from VPX to VNX
Pin input voltage (all other pins) to VNS
3.6
Min
-0.5
-0.5
Max
6.0
4.0
Unit
V
V
Reference and Regulation
Table 15 lists the VBG specifications. VBG should be connected to an external bypass capacitor with a
minimum value of 0.1μF. This pin is not intended for any other external use.
The following conditions apply: VPX=5 V; Barrier Powered Mode; Barrier Data Rate across the Barrier=1.5
Mbps; VBG connected to 0.1 μF external cap.
Table 15: VBG Specifications
Parameter
VBG
VBG Noise
VBG PSRR
VPS
VPS PSRR
3.7
Test Condition
See conditions above.
300 Hz – 3.3 kHz
300 Hz – 30 kHz
VPX=5.5 V
VPX=4.5 V to 5.5 V
Min
–
–
40
–
–
Nom
1.19
-86*
–
3.15
40
Max
–
-80
–
–
–
Units
V
dBm600
dB
V
dB
AC Signal Levels
Table 16 shows the maximum transmit levels that the 73M1912 Line-Side Device is capable of delivering.
Table 16: Maximum Transmit Levels
Transmit Type
V.90
QAM
DPSK
FSK
DTMF (high tone)
DTMF (low tone)
22
Maximum
Level at the
Line (dBm)
-12.0
-7.3
-5.1
-3.0
-7.8
-9.8
Peak to
RMS
Ratio
4
2.31
1.81
1.41
1.41
1.41
RMS Voltage
on the Line
(V)
0.195
0.334
0.431
0.548
0.316
0.251
Peak
Voltage on
the Line (V)
0.778
0.772
0.779
0.775
0.446
0.354
Rev. 1.6
DS_1x22_001
3.8
73M1822/73M1922 Data Sheet
DC Transfer Characteristics
Table 17 lists the maximum DC output levels. All tests are driven at pin DCI and measured at pin DCS.
DCEN=1 and pin DCI is shorted to pin DCS. ILM=0 unless stated otherwise.
Table 17: Maximum DC Transmit Levels
Parameter
VDCON
(DC "On" Voltage)
With ENAC=0
DC Gain
IDCI before ILIM
IDCI after ILIM
*Noise
Rev. 1.6
Test Condition
DCIV=00
DCIV=01
DCIV=10
DCIV=11
DCIV=XX
VDCON 55 mA if ILM=1.
Rev. 1.6
DS_1x22_017
13
73M1822/73M1922 Data Sheet
Loopback and Testing Modes
Figure 36 show the five loopback modes available in the 73M1x22.
73M1822 HIC/
73M1902
73M1822 LIC/
73M1912
CTL
STA
Ring
Buffer
Aux A/D
STA
Tip
Interp.
Filter
PRP
TxD
SCP
LSBI
MSBI
DSDM
TxD
Onchip
LIC
TBS
TxAFE
TxA
TxData
RxData
MAFE
Interface
DIGLB1
DIGLB2
INTLB1
Decim.
Filter
RxD
RxD
PRM
SCM
SinC3
Filter
External
LIC
ALB
INTLB2
RxAFE
RBS
RxA
Ring
Figure 36: Loopback Modes Highlighted
Table 47 describes how the above control bits interact to provide each of the six loopback modes.
Table 47: Loopback Modes
Rev. 1.6
TEST
TMEN
DTST
0000
0
00
0000
1
10
0000
1
11
0001
0
00
0010
0
00
0011
0
00
Loopback Mode
Normal mode. (Default)
Mnemonic
No Loops
Digital Loopback mode. Interpolated
TxData (TxD) is looped back to the
Decimated RxData input (RxD).
Remote Analog Loopback. Received RxD
is looped back as TxD and transmitted
back to the 73M1922
Line-Side Device; RxD is D/A converted to
yield the analog transmit signal (TxA).
Digital Loopback mode. Transmit Bit
Stream (TBS) is looped back to receive
digital channel and received (DIGLB2).
Remote Analog Loopback. Receive
analog signal is converted to Received Bit
Stream (RBS) and is looped back to TBS
and the analog transmit channel (INTLB2).
Analog Loopback. The transmit data is
connected to the receiver at the analog
interface and received (ALB).
DIGLB1
INTLB1
DIGLB2
INTLB2
ALB
75
73M1822/73M1922 Data Sheet
DS_1x22_017
13.1 Loopback Controls
Table 48 describes the registers used for loopback control.
Table 48: Loopback Controls
Function
Mnemonic
TMEN
DTST
Register
Location
0x02[7]
0x07[3:0]
Type
W
W
Description
Test Mode Enable
Used to enable the activation of the test loops controlled by
the DTST bits (DIGLB1 and INTLB1).
0 = No DTST loops enable. (Default)
1 = DTST loops enable.
TMEN has to be set to 1 before the setting of the DTST
bits.
These control bits enable DIGLB1 and INTLB1.
Prior to writing to these bits, TMEN must be set to 1.
TEST
76
0x18[7:4]
W
DTST1
DTST0
Selected Test Mode
0
0
Normal (Default)
1
0
DIGLB1
1
1
INTLB1
This four-bit field is used to enable the loopback mode per the
following table:
TEST
Loopback Mode
0000
Normal mode. (Default)
Transmit and receive channels are independent.
0001
Digital loopback mode. Transmit Bit Stream (TBS)
is looped back to receive digital channel and
received (DIGLB2).
0010
Remote Analog loopback. Receive analog signal
is converted to Received Bit Stream (RBS) and is
looped back to TBS and the analog transmit
channel (INTLB2).
0011
Analog loopback. The transmit data is connected
to the receiver at the analog interface and
received (ALB).
Rev. 1.6
DS_1x22_017
73M1822/73M1922 Data Sheet
14 Performance
This section provides an overview of typical performance characteristics measured using a 73M1x22
production device on a Teridian Reference Board. The measurements were made at the tip and ring pins.
14.1 DC VI Characteristics
14.1.1 Off-Hook Tip and Ring DC Characteristics
Tip and Ting DC Voltage (volt)
Figure 37: Off-Hook Tip and Ring DC Characteristics
5
0
DCIV=00, ILM=1
DCIV=01, ILM=1
DCIV=10, ILM=1
4
0
3
0
TBR21
Not allowed
2
0
Not allowed
1
0
0
0
2
4
6
8
9
1
1
2
2
3
3
0
5
0
5
0
5
Tip and Ring DC Current (mA)
4
0
4
5
5
0
5
5
6
0
Figure 38: ES 203 021-2 DC Mask with Current Limit Enabled
Rev. 1.6
77
73M1822/73M1922 Data Sheet
DS_1x22_017
14
Australian
Prohibited
Region
Tip and Ring DC voltage
12
10
DCIV=11
8
6
Australian not recommended
Region
4
2
95
85
75
65
55
45
35
25
15
8
4
0
0
Loop current
Figure 39: Australian Hold State Characteristics
14.2 Receive
50
US
45
TBR21
40
China
Australia
Return Loss dB
35
30
25
20
15
Australia Limit
USA Limit
10
TBR21 Limit
5
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
900
800
700
600
500
400
300
200
100
0
Frequency
Figure 40: Return Loss
78
Rev. 1.6
DS_1x22_017
73M1822/73M1922 Data Sheet
15 Package Layout
Figure 41: 20-Pin TSSOP Package Dimensions
0.85 NOM./ 0.9MAX.
5
0.00 / 0.005
2.5
0.20 REF.
1
2.5
2
3
5
SEATING
PLANE
TOP VIEW
SIDE VIEW
0.35 / 0.45
3.0 / 3.75
CHAMFERED
0.30
0.18 / 0.3
1.5 / 1.875
1
2
3
3.0 / 3.75
0.25
1.5 / 1.875
0.5
0.2 MIN.
0.35 / 0.45
0.5
0.25
BOTTOM VIEW
Figure 42: 32-Pin QFN Package Dimensions
Rev. 1.6
79
73M1822/73M1922 Data Sheet
DS_1x22_017
Figure 43: 42-Pin QFN Package Dimensions
80
Rev. 1.6
DS_1x22_017
73M1822/73M1922 Data Sheet
16 Ordering Information
Table 49 lists the order numbers and packaging marks used to identify 73M1822 and 73M1922 products.
Table 49: Order Numbers and Packaging Marks
Part Description
73M1922 32-Pin QFN, Lead free
Order Number
73M1922-IM/F
73M1922 32-Pin QFN, Lead free,
Tape and Reel
73M1922 20-Pin TSSOP, Lead free
73M1922-IMR/F
73M1922 20-Pin TSSOP, Lead free
Tape and Reel
73M1822 42-Pin QFN, Lead free
73M1822 42-Pin QFN, Lead free,
Tape and Reel
73M1922-IVT/F
73M1922-IVTR/F
73M1822-IM/F
73M1822-IMR/F
Packaging Mark
73M1912-M
73M1902-M
73M1912-M
73M1902-M
73M1912VT
73M1902A
73M1912VT
73M1902A
73M1822A-IM
73M1822A-IM
Host/Line
Line-Side IC
Host-Side IC
Line-Side IC
Host-Side IC
Line-Side IC
Host-Side IC
Line-Side IC
Host-Side IC
17 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73M1822 or
73M1922, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: modem.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
Rev. 1.6
81
73M1822/73M1922 Data Sheet
DS_1x22_017
Revision History
Revision
Date
Description
1.0
10/26/2007
First publication.
1.1
11/7/2007
1.1.1
4/11/2008
1.2
8/28/2008
1.3
3/23/2009
1.4
8/6/2009
1.5
10/16/2009
1.6
4/7/2010
Changed the values in Table 17.
Replaced the schematics in Figure 10 and Figure 11.
Updated the Bill of Materials in Table 27.
Added the ACCEN bit to Table 30 and Table 31.
Corrected the Types (R, W, WO) in Table 31.
Added clarification to the description of the PLDM bit.
Added clarification to the description of the RGDT bit.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
MicroDAA is a registered trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without notice
and does not make any commitment to update the information contained herein. Accordingly, the reader is
cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
82
Rev. 1.6
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