73M1866B/73M1966B
MicroDAA™ with PCM Highway
DATA SHEET
Simplifying System Integration™
DS_1x66B_001
DESCRIPTION
The 73M1866B and 73M1966B use the Teridian
patented Data Access Arrangement function
®
(MicroDAA ) designed exclusively for ForeignExchange-Office (FXO) in Voice-over-IP (VoIP)
applications. These devices provide much of the
circuitry required to connect PCM formatted
voice channels to a PSTN via a two-wire twisted
pair interface. The package options provide the
necessary functional programmability and
protection required for easy worldwide
homologation.
The family of devices consists of the 73M1866B
and the 73M1966B. The 73M1866B MicroDAA
is the world’s first single-package silicon Data
Access Arrangement (DAA). Suitable
applications for the 73M1866B and 73M1966B
devices include VoIP equipment that must
provide connectivity to the PSTN for purposes of
guaranteeing emergency service calling,
redundancy for supplementary connectivity for
voice, and maintenance services.
The 73M1966B device set consists of the
73M1906B Host-Side Device that provides digital
data, control interfaces and power to the
73M1916 Line-Side Device.
These devices are based on an innovative and
patented technology, which sets new standards
in reliability and cost. A small pulse transformer
forms a digital isolation barrier, transferring both
power and data to the PSTN line-side
components. This method results in reliable
operation in the presence of EMI and a tolerance
to line voltage variations by providing power to
the Line-Side Device across the barrier. The
devices also support the ability to provide up to
an additional +6 dB of analog gain to the lineside transmit and +3 dB in the receive signal
paths. The device supports transmit and receive
digital gain ranging from –18 dB to +7.375 dB by
increments of 0.125 dB.
April 2010
Through its PCM interface, the 73M1966B can
be connected to other PCM enabled devices
such as POTS codecs, ISDN codecs, E1/T1
framers, etc.
Additional DAA functions supported by the
73M1x66B devices include a call progress
monitor, Caller ID Type I and II, ring detection,
pulse dialing, billing tone detection and polarity
reversal detection.
APPLICATIONS
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Computer Telephony
VOIP Equipment
PBX Systems
Internet Appliances
Voicemail Systems
POTS Termination Equipment
FEATURES
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PCM highway data interface supporting both
slave and master modes
PCM highway interface supporting both E-1
and T-1
SPI control interface, with daisy chain
support for up to 16 devices
Designed to meet global DAA compliance
FCC, ETSI ES 203 021-2, JATE and other
PTT standards.
8 kHz and 16 kHz sample rates
16-bit linear mode
TX and RX gains adjustable in 0.125 dB
increments
μ-Law, A-law ITU-T Recommendation G.711
compliant compander operation
Automatic clock rate detection
Low power modes
Polarity Reversal detection
GPIO for user-configurable I/O ports
Call Progress Monitor
Isolation up to 6 kV
THD -80 dB
5 V tolerant I/O on selected pins
3.0 V – 3.6 V operating voltage
Industrial temperature range (-40 °C to +85 °C)
5x5 mm 32-pin QFN or 20-pin TSSOP
packages
RoHS compliant (6/6) lead-free package
The digital side provides a PCM highway
interface with automatic clock rate detection.
With an 8-kHz sampling rate, the devices include
an ITU-T G.711 compliant codec with selectable
µ-law and A-law companding modes. The
devices also provide a 16-bit linear mode, which
•
is suitable for interfacing with wide band codecs,
as well as 16 kHz sampling rate. Device control
is performed over an SPI interface. The SPI
supports daisy chain operation.
Rev. 1.6
© 2010 Teridian Semiconductor Corporation
1
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Table of Contents
1
Introduction ................................................................................................................................... 6
2
Pinout ............................................................................................................................................. 8
2.1 73M1906B 20-Pin TSSOP Pinout............................................................................................ 8
2.2 73M1916 20-Pin TSSOP Pinout .............................................................................................. 9
2.3 73M1906B 32-Pin QFN Pinout .............................................................................................. 10
2.4 73M1916 32-Pin QFN Pinout ................................................................................................ 12
2.5 73M1866B Pinout ................................................................................................................. 14
2.6 Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN Packages .......... 15
Electrical Characteristics and Specifications............................................................................. 16
3.1 Isolation Barrier Characteristics ............................................................................................. 16
3.2 Electrical Specifications......................................................................................................... 16
3.2.1 Absolute Maximum Ratings ....................................................................................... 16
3.2.2 Recommended Operating Conditions ........................................................................ 16
3.2.3 DC Characteristics..................................................................................................... 17
3.3 Interface Timing Specification................................................................................................ 18
3.3.1 SPI Interface ............................................................................................................. 18
3.3.2 PCM Highway Interface ............................................................................................. 19
3.4 Analog Specifications ............................................................................................................ 20
3.4.1 DC Specifications ...................................................................................................... 20
3.4.2 Call Progress Monitor ................................................................................................ 21
3.5 73M1x66B Line-Side Electrical Specifications (73M1916)...................................................... 22
3.6 Reference and Regulation ..................................................................................................... 23
3.7 DC Transfer Characteristics .................................................................................................. 23
3.8 Transmit Path ....................................................................................................................... 24
3.9 Receive Path ........................................................................................................................ 25
3.10 Transmit Hybrid Cancellation ................................................................................................ 26
3.11 Receive Notch Filter .............................................................................................................. 26
3.12 Detectors .............................................................................................................................. 27
3.12.1 Over-Voltage Detector ............................................................................................... 27
3.12.2 Over-Current Detector ............................................................................................... 27
3.12.3 Under-Voltage Detector ............................................................................................. 27
3.12.4 Over-Load Detector ................................................................................................... 27
3
4
Applications Information ............................................................................................................. 28
4.1 Example Schematic of the 73M1966B and 73M1866B .......................................................... 28
4.2 Bill of Materials...................................................................................................................... 30
4.3 Over-Voltage and EMI Protection .......................................................................................... 31
4.4 Isolation Barrier Pulse Transformer ....................................................................................... 32
5
SPI Interface................................................................................................................................. 33
6
Control and Status Registers ...................................................................................................... 37
7
Hardware Control Functions ....................................................................................................... 41
7.1 Device Revision .................................................................................................................... 41
7.2 Interrupt Control .................................................................................................................... 41
7.3 Power Management .............................................................................................................. 42
7.4 Device Clock Management.................................................................................................... 42
7.5 GPIO Registers ..................................................................................................................... 43
7.6 Call Progress Monitor ............................................................................................................ 44
7.7 16 kHz Operation of Call Progress Monitor ............................................................................ 44
7.8 Device Reset ........................................................................................................................ 44
PCM Highway Interface and Signal Processing ......................................................................... 45
8.1 PCM Highway Interface Timing ............................................................................................. 45
8.2 PCM Clock Frequencies........................................................................................................ 47
8.3 Master Mode ......................................................................................................................... 47
8.4 A-law / μ-law Compander ...................................................................................................... 47
8
2
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
8.5
9
10
11
12
13
Transmit and Receive Levels ................................................................................................ 48
8.5.1 A-Law........................................................................................................................ 48
8.5.2 μ-Law ........................................................................................................................ 48
8.5.3 Transmit and Receive Level Control .......................................................................... 48
8.6 Transmit Path Signal Processing........................................................................................... 49
8.6.1 General Description ................................................................................................... 49
8.6.2 Total Transmit Path Response................................................................................... 49
8.6.3 73M1x66B Transmit Spectrum................................................................................... 50
8.7 Receive Path Signal Processing............................................................................................ 50
8.7.1 General Description ................................................................................................... 50
8.7.2 Total Receive Path Response.................................................................................... 51
8.7.3 Receiver DC Offset Subtraction ................................................................................. 51
8.8 PCM Control Functions ......................................................................................................... 52
8.8.1 Transmit and Receive Level Control .......................................................................... 57
8.8.2 Time Slot Assignment Example ................................................................................. 59
Barrier Information ...................................................................................................................... 60
9.1 Isolation Barrier ..................................................................................................................... 60
9.2 Barrier Powered Options ....................................................................................................... 60
9.2.1 Barrier Powered Operation ........................................................................................ 60
9.2.2 Line Powered Operation ............................................................................................ 60
9.3 Synchronization of the Barrier ............................................................................................... 60
9.4 Auto-Poll ............................................................................................................................... 61
9.5 Barrier Control Functions ...................................................................................................... 61
9.6 Line-Side Device Operating Modes ....................................................................................... 63
9.7 Fail-Safe Operation of Line-Side Device ................................................................................ 63
Configurable Direct Access Arrangement (DAA) ....................................................................... 64
10.1 Pulse Dialing ......................................................................................................................... 64
10.2 DC Termination ..................................................................................................................... 64
10.3 AC Termination ..................................................................................................................... 66
10.4 Billing Tone Rejection ........................................................................................................... 67
10.5 Trans-Hybrid Cancellation ..................................................................................................... 68
10.6 Direct Access Arrangement Control Functions....................................................................... 68
10.7 International Register Settings Table for DC and AC Terminations ........................................ 72
Line Sensing and Status ............................................................................................................. 73
11.1 Auxiliary A/D Converter ......................................................................................................... 73
11.2 Ring Detection ...................................................................................................................... 73
11.3 Line In Use Detection (LIU) ................................................................................................... 73
11.4 Parallel Pick Up (PPU) .......................................................................................................... 73
11.5 Polarity Reversal Detection ................................................................................................... 73
11.6 Off-hook Detection of Caller ID Type II .................................................................................. 73
11.7 Voltage and Current Detection .............................................................................................. 74
11.8 Under Voltage Detection (UVD)............................................................................................. 74
11.9 Over Voltage Detection (OVD) .............................................................................................. 74
11.10 AC Signal Overload Detection ............................................................................................. 74
11.11 Over Current Detection (OID).............................................................................................. 74
11.12 Line Sensing Control Functions........................................................................................... 75
Loopback and Testing Modes ..................................................................................................... 78
14
Performance ................................................................................................................................ 80
13.1 Transmit................................................................................................................................ 80
13.2 Receive................................................................................................................................. 82
Package Layout ........................................................................................................................... 85
15
Ordering Information ................................................................................................................... 87
16
Contact Information..................................................................................................................... 87
Revision History .................................................................................................................................. 88
Rev. 1.6
3
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Figures
Figure 1: Simple 73M1x66B Reference Block Diagram ............................................................................ 6
Figure 2: 73M1906B 20-Pin TSSOP Pinout.............................................................................................. 8
Figure 3: 73M1916 20-Pin TSSOP Pinout ................................................................................................ 9
Figure 4: 73M1906B 32-Pin QFN Pinout ................................................................................................ 10
Figure 5: 73M1916 32-Pin QFN Pinout .................................................................................................. 12
Figure 6: 73M1866B 42-Pin Pinout ........................................................................................................ 14
Figure 7: SPI Timing Diagram ................................................................................................................ 18
Figure 8: PCM Timing Diagram for Positive Edge Transmit Mode and Negative Edge Receive Mode ..... 19
Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode ..... 20
Figure 10: Frequency Response of the Call Progress Monitor Filter ....................................................... 21
Figure 11: Demo Board Circuit Connecting AOUT to a Speaker ............................................................. 21
Figure 12: Recommended Circuit for the 73M1966B .............................................................................. 28
Figure 13: Recommended Circuit for the 73M1866B .............................................................................. 29
Figure 14: Suggested Over-Voltage Protection and EMI Suppression Circuit ......................................... 31
Figure 15: Daisy-Chain Configuration .................................................................................................... 34
Figure 16: SPI Write Operation – 8-bit Mode .......................................................................................... 34
Figure 17: SPI Read Transaction – 8-bit Mode....................................................................................... 35
Figure 18: SPI Write Transaction – 16-bit Mode ..................................................................................... 35
Figure 19: SPI Read Transaction – 16-bit Mode..................................................................................... 35
Figure 20: 8-bit Transmission Example .................................................................................................. 45
Figure 21: 16-bit Transmission Example ................................................................................................ 46
Figure 22: Example of PCM Highway Interconnect................................................................................. 46
Figure 23: Example of PCM Highway Interconnect for Typical Large Systems ....................................... 46
Figure 24: Mapping of A-law Code to 16-bit Code .................................................................................. 48
Figure 25: Mapping of μ-law Code to 16-bit Code .................................................................................. 48
Figure 26: Transmit Path Overall Frequency Response to Fs of 8 kHz ................................................... 49
Figure 27: Transmit Path Passband Response for an 8 kHz Sample Rate.............................................. 49
Figure 28: Transmit Spectrum to 32 kHz for an 8 kHz Sample Rate ....................................................... 50
Figure 29: Overall Frequency Response of the Receive Path ................................................................. 51
Figure 30: Pass-band Response of the Overall Receive Path................................................................. 51
Figure 31: Timing Relationships with Various TTS, TCS, TPOL, and RTS, RCS, RPOL Settings............ 59
Figure 32: Line-Side Device AC and DC Circuits.................................................................................... 63
Figure 33: DC-IV Characteristics............................................................................................................ 64
Figure 34: Tip-Ring Voltage versus Current Using Different DCIV Settings............................................. 65
Figure 35: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings ......................... 66
Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2) ........... 67
Figure 37: Magnitude Response of Billing Tone Notch Filter .................................................................. 67
Figure 38: Trans-hybrid Cancellation ..................................................................................................... 68
Figure 39: Loopback Modes Highlighted ................................................................................................ 78
Figure 40: Variation of Transmit Gain Digital Input to Analog Output at the Line ..................................... 80
Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line..................................... 81
Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line...... 81
Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output .................................. 82
Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output ......................... 83
Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output... 83
Figure 46: Return Loss, @ 80 mA .......................................................................................................... 84
Figure 47: 20-Pin TSSOP Package Dimensions..................................................................................... 85
Figure 48: 32-Pin QFN Package Dimensions ......................................................................................... 85
Figure 49: 42-Pin QFN Package Dimensions ......................................................................................... 86
4
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Tables
Table 1: 73M1906B 20-Pin TSSOP Pin Definitions .................................................................................. 8
Table 2: 73M1916 20-Pin TSSOP Pin Definitions ..................................................................................... 9
Table 3: 73M1906B 32-Pin QFN Pin Definitions ..................................................................................... 10
Table 4: 73M1916 32-Pin QFN Pin Definitions ....................................................................................... 12
Table 5: 73M1866B Pin Definitions ........................................................................................................ 14
Table 6: Isolation Barrier Characteristics ................................................................................................ 16
Table 7: Absolute Maximum Device Ratings .......................................................................................... 16
Table 8: Recommended Operating Conditions ....................................................................................... 16
Table 9: DC Characteristics ................................................................................................................... 17
Table 10: SPI Interface Switching Characteristics .................................................................................. 18
Table 11: Switching Characteristics – PCM Interface (Slave Mode) ........................................................ 19
Table 12: Switching Characteristics – PCM Interface (Master Mode) ...................................................... 19
Table 13: Reference Voltage Specifications ........................................................................................... 20
Table 14: Component Values for the Speaker Driver .............................................................................. 21
Table 15: Call Progress Monitor Specification ........................................................................................ 22
Table 16: Line-Side Absolute Maximum Ratings .................................................................................... 22
Table 17: VBG Specifications ................................................................................................................ 23
Table 18: Maximum DC Transmit Levels ................................................................................................ 23
Table 19: Transmit Path......................................................................................................................... 24
Table 20: Receive Path ......................................................................................................................... 25
Table 21: Transmit Hybrid Cancellation Characteristics .......................................................................... 26
Table 22: Receive Notch Filter ............................................................................................................... 26
Table 23: Over-voltage Detector ............................................................................................................ 27
Table 24: Over-current Detector............................................................................................................. 27
Table 25: Under-voltage Detector .......................................................................................................... 27
Table 26: Over-load Detector ................................................................................................................. 27
Table 27: Reference Bill of Materials for 73M1x66B ............................................................................... 30
Table 28: Reference Bill of Materials for Figure 14 ................................................................................. 31
Table 29: Compatible Pulse Transformer Sources ................................................................................. 32
Table 30: Pulse Transformer Electrical Characteristics ........................................................................... 32
Table 31: Control and Status Register Map ............................................................................................ 37
Table 32: Alphabetical Bit Map .............................................................................................................. 38
Table 33: PCM Control Functions .......................................................................................................... 52
Table 34: Transmit Gain Control ............................................................................................................ 57
Table 35: Recommended Gain Setting................................................................................................... 57
Table 36: Receive Gain Control ............................................................................................................. 59
Table 37: Barrier Control Functions........................................................................................................ 61
Table 38: DAA Control Functions ........................................................................................................... 68
Table 39: Recommended Register Settings for International Compatibility ............................................. 72
Table 40: Line Sensing Control Functions .............................................................................................. 75
Table 41: Loopback Modes.................................................................................................................... 78
Table 42: Loopback Modes Summary .................................................................................................... 79
Table 43: Order Numbers and Packaging Marks .................................................................................... 87
Rev. 1.6
5
73M1866B/73M1966B Data Sheet
DS_1x66B_001
1 Introduction
The 73M1966B is a two-device chip set that provides embedded FXO functionality by connecting a PCM
interface to a voice-band PSTN. The device set supports ITU-T Recommendation G.711 µ-law and A-law
companding, and also a 16-bit linear mode. High-voltage isolation is provided by the physical separation
of the Host-Side (73M19106) and Line-Side (73M1916) Devices. The Host-Side and the Line-Side
Devices communicate with each other using a single pulse transformer. A few low-cost components
complete the DAA interface to the network. The pulse transformer transmits encoded digital data rather
than analog signals as with other transformer designs. Data is transmitted and received without the usual
degradation from common mode noise and magnetic coupling typical of other capacitive and voice-band
transformer techniques. The data stream passed between the Host-Side and Line-Side Devices includes
the media stream data, control, status, and clocking information.
This data sheet describes both the 73M1966B and 73M1866B, which will be collectively referred to as the
73M1x66B in this document.
A unique capability of the 73M1x66B Host Side device (73M1906B) is its ability to provide power to the
73M1x66B Line Side device (73M1916) via the pulse transformer.
The 73M1906B exchanges control and status information with the host using the SPI interface, while the
PCM encoded media streams connect with other PCM-enabled devices using the PCM highway bus
interface.
Figure 1 shows a reference block diagram of the 73M1x66B connected by a pulse transformer and
example external line interface circuitry shown for clarification.
Host -Side Device
Line-Side Device
73M1906B
73M1916
SPI
SPI
Interface
Aux A/D
Tip
PRP
Transmit
Interpolation
Filter
PCM
PCM
Interface
Receive
Decimation
Filter
SCP
Line
Side
Barrier
Interface
(LSBI)
Host
Side
Barrier
Interface
(HSBI)
PRM
SCM
Digital
Sigma
Delta
Modulator
Transmit
Analog
Front End
SinC3
Filter
Receive
Analog
Front End
(with Sigma
Delta
Modulator)
TxA
Off-Chip
LIC
(OffLIC)
On-Chip
LIC
(OnLIC)
Call Progress Monitor Audio Out
RxA
Ring
Figure 1: Simple 73M1x66B Reference Block Diagram
The Host-Side Device (73M1906B) consists of:
1.
2.
3.
4.
5.
6
PCM Interface Block (PCM)
SPI Interface Block (SPI)
Transmit Interpolation Filter
Receive Decimation Filter
Host-Side Barrier Interface Circuit (HSBI)
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
The Line-Side Device (73M1916) consists of:
1.
2.
3.
4.
5.
6.
Digital Sigma Delta Modulator
Transmit Analog Front End
Receive Analog Front End including Sigma Delta Modulator
3
Sinc Filter (Sinc3)
On-chip Line Interface Circuit
Line-Side Barrier Interface Circuit (LSBI)
Received data from a host connected to the PCM bus is interpolated from the sampling frequency of
8 kHz or 16 kHz (for PCM encoded streams) to twice the sampling frequency. The control information is
multiplexed with the audio stream signals and transmitted across the isolation barrier to the Line-Side
Device. In the Line-Side Device, the two streams are separated and the audio signal is converted to
analog for transmission to the line.
An audio stream received at the analog line input pins is converted to a serialized data stream and, along
with status information such as line condition from the Auxiliary Analog to Digital Converter, is transmitted
over the isolation barrier using the pulse transformer. The data is extracted with status information being
transmitted on the SPI. The audio stream is sent to a host using the PCM bus.
The 73M1x66B is an enhanced version of the 73M1966 that includes the additional functionality of finer
resolution of transmit and receive gain, receiver DC offset subtraction and support for T-1 PCLK
frequencies.
Rev. 1.6
7
73M1866B/73M1966B Data Sheet
DS_1x66B_001
2 Pinout
The 73M1906B and the 73M1916 are supplied as 20-pin TSSOP packages and as 32-pin QFN packages.
2.1
73M1906B 20-Pin TSSOP Pinout
Figure 2 shows the 73M1906B 20-pin TSSOP pinout.
CS
1
20
SCLK
VPD
2
19
INT
DR
3
18
SDO
DX
4
17
SDI
FS
5
16
SDIT
PCLKO
6
15
RST
PCLKI
7
14
VPT
VNA/VND
8
13
PRP
AOUT
9
12
PRM
VPA
10
11
VNT
73M1906B
Figure 2: 73M1906B 20-Pin TSSOP Pinout
Table 1 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 1: 73M1906B 20-Pin TSSOP Pin Definitions
Pin
Number
Pin
Name
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CS
VPD
DR
DX
FS
PCLKO
PCLKI
VNA/VND
AOUT
VPA
VNT
PRM
PRP
VPT
RST
SDIT
SDI
SDO
INT
SCLK
I
PWRI
I
O
I/O
O
I
GND
O
PWRI
GND
I/O
I/O
PWRI
I
O
I
O
O
I
8
Description
SPI chip select (active low)
Positive digital supply
PCM transmit data sent to the D to A
PCM received data from the A to D
PCM frame synchronization
PCM clock output
PCM clock in
Negative analog/digital ground
Audio output – must be buffered for speaker
Positive analog supply
Negative transformer supply
Transformer primary minus
Transformer primary plus
Positive transformer supply
Hardware reset (active low)
SPI data out for daisy chain mode
SPI data in
SPI data out
Interrupt / ring detect (active low – open drain)
SPI clock
Rev. 1.6
DS_1x66B_001
2.2
73M1866B/73M1966B Data Sheet
73M1916 20-Pin TSSOP Pinout
Figure 3 shows the 73M1916 20-pin TSSOP pinout.
DCI
1
20
DCG
RGN
2
19
DCS
RGP
3
18
DCD
OFH
4
17
TXM
VNX
5
16
RXM
SCP
6
15
RXP
MID
7
14
VPS
VPX
8
13
VNS
SRE
9
12
ACS
SRB
10
11
VBG
73M1916
Figure 3: 73M1916 20-Pin TSSOP Pinout
Table 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 2: 73M1916 20-Pin TSSOP Pin Definitions
Pin
Number
Pin Name
Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
DCI
RGN
RGP
OFH
VNX
SCP
MID
VPX
SRE
SRB
VBG
ACS
VNS
I
I
I
O
GND
I/O
I/O
PWR
I
O
O
I
GND
DC loop input
Ring detect negative voltage input
Ring detect positive voltage input
Off-hook control
Negative supply voltage (line side of the barrier)
Positive side of the secondary pulse transformer winding
Charge pump midpoint
Supply from the barrier
Voltage regulator sense
Voltage regulator drive
VBG bypass, connect to 0.1 μF capacitor to VNS
AC current sense
Analog negative supply voltage
14
VPS
PWRO
15
16
17
18
19
20
RXP
RXM
TXM
DCD
DCS
DCG
I
I
O
O
I
O
Rev. 1.6
Analog positive supply voltage (output)
Receive plus – signal input
Receive minus – signal input
Transmit minus – transhybrid cancellation output
DC loop output
DC loop current sense
DC loop control
9
73M1866B/73M1966B Data Sheet
2.3
DS_1x66B_001
73M1906B 32-Pin QFN Pinout
GPIO6
DR
VPD
CS
SCLK
INT
VND
GPIO5
32
31
30
29
28
27
26
25
Figure 4 shows the 73M1906B 32-pin QFN pinout.
GPIO7
1
24
SDO
TSC
2
23
SDI
DX
3
22
SDIT
VPD
4
21
RST
20
VPD
FS
73M1906B
5
14
15
16
N/C
N/C
PRM
VNT
17
13
8
N/C
VND
12
PRP
VPA /
VPPLL
18
11
7
AOUT
PCLKI
10
VPT
VBG
19
9
6
VNA /
VNPLL
PCLKO
Figure 4: 73M1906B 32-Pin QFN Pinout
Table 3 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 3: 73M1906B 32-Pin QFN Pin Definitions
Pin
Number
1
2
3
4
5
6
7
Pin Name
Description
FS
PCLKO
PCLKI
I/O
O
O
PWR
I/O
O
I
Configurable input/output pin
PCM time slot control (active low)
PCM received data from the A to D
Positive digital supply
PCM frame synchronization
PCM clock output
PCM clock in
8
9
VND
VNA/VNPLL
GND
GND
Negative digital ground
Negative analog/PLL ground
10
11
12
13
14
15
16
VBG
AOUT
VPA/VPPLL
N/C
VNT
N/C
N/C
O
O
PWR
–
GND
–
–
Band gap voltage reference monitor
Audio output – must be buffered for speaker
Positive analog/PLL supply
No connect
Negative transformer supply
No connect
No connect
10
GPIO7
TSC
DX
VPD
Type
Rev. 1.6
DS_1x66B_001
Pin
Number
17
18
19
20
21
22
23
24
PRM
PRP
VPT
VPD
RST
SDIT
SDI
SDO
25
26
27
28
29
30
31
32
Rev. 1.6
Pin Name
73M1866B/73M1966B Data Sheet
Type
Description
GPIO5
VND
I/O
I/O
PWR
PWR
I
O
I
O
I/O
GND
Transformer primary minus
Transformer primary plus
Positive transformer supply
Positive digital supply
Hardware reset (active low)
SPI data out for daisy-chain mode
SPI data in
SPI data out
Configurable input/output pin
Negative digital ground
INT
SCLK
CS
VPD
DR
GPIO6
O
I
I
PWR
I
I/O
Interrupt / ring detect (active low – open drain)
SPI clock
SPI chip select (active low)
Positive digital supply
PCM transmit data sent to the D to A
Configurable input/output pin
11
73M1866B/73M1966B Data Sheet
2.4
DS_1x66B_001
73M1916 32-Pin QFN Pinout
GPO
GPI
VNS/VND
RGP
RGN
DCI
DCG
DCS
32
31
30
29
28
27
26
25
Figure 5 shows the 73M1916 32-pin QFN pinout.
CKO
1
24
DCD
OFH
2
23
RST
CKI
3
22
TST
VNX
4
21
TXM
SCP
5
20
SACIN
MID
6
19
RXM
SCM
7
18
RXP
VPX
8
17
16
VNS
13
VNS
15
12
SRB
ACS
11
SRE
14
10
BYP
VBG
9
RCT
73M1916
VPS
Figure 5: 73M1916 32-Pin QFN Pinout
Table 4 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 4: 73M1916 32-Pin QFN Pin Definitions
Pin
Number
1
2
3
4
5
6
7
8
9
Pin
Name
CKO
OFH
CKI
VNX
SCP
MID
SCM
VPX
RCT
10
11
12
13
14
15
BYP
SRE
SRB
VNS
VBG
ACS
12
Type
O
O
I
GND
I/O
I/O
I/O
PWR
I
I
I
O
GND
O
I
Description
Test point for recovered clock
Off-hook control
Test input for clock
Negative supply voltage
Positive side of the secondary pulse transformer winding
Charge pump midpoint
Negative side of the secondary pulse transformer winding
Supply from the barrier
External rectification – disables internal rectifier when low,
leave open
Test pin, leave open
Voltage regulator sense
Voltage regulator drive
Digital negative supply voltage
VBG bypass, connect to 0.1μF capacitor to VNS
AC current sense
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Pin
Number
16
17
18
Pin
Name
VNS
VPS
RXP
GND
PWRO
I
19
20
RXM
SACIN
I
I
Receive minus – signal input
Caller ID mode AC impedance connection
21
22
23
TXM
O
I
I
Transmit Minus – transhybrid cancellation output
Factory test mode, leave open
Resets the control registers to default – weakly pulled high
24
25
26
27
28
29
30
31
32
Rev. 1.6
TST
RST
DCD
DCS
DCG
DCI
RGN
RGP
VNS
GPI
GPO
Type
O
I
O
I
I
I
GND
I
O
Description
Analog negative supply voltage
Analog positive supply voltage (output)
Receive plus – signal input
DC loop output
DC loop current sense
DC loop control
DC loop input
Ring detect negative voltage input
Ring detect positive voltage input
Negative supply voltage (line side of the barrier)
General purpose input (test pin)
General purpose output (test pin)
13
73M1866B/73M1966B Data Sheet
2.5
DS_1x66B_001
73M1866B Pinout
RGP
RGN
DCI
DCG
DCS
36
35
34
33
32
OFH
M20PB
38
37
VNX
39
SCP
MID
41
40
VPX
42
Figure 6 shows the 73M1866B 42-pin pinout.
31
DCD
30
TXM
29
RXM
DX
1
28
RXP
VPD
2
27
VPS
FS
3
26
VNS
PCLKO
4
25
ACS
VNA
5
24
VBG
PCLKI
6
23
SRB
AOUT
7
22
SRE
VPA
8
VNT
9
21
DR
18
INT
20
17
VND
CS
16
SDO
19
15
SDI
SCLK
14
SDIT
13
12
VPT
RST
11
10
PRP
PRM
73M1866B
Figure 6: 73M1866B 42-Pin Pinout
Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 5: 73M1866B Pin Definitions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
14
Pin Name
Type
DX
O
PWR
I/O
O
GND
I
O
PWR
GND
I/O
I/O
PWR
I
O
I
O
VPD
FS
PCLKO
VNA
PCLKI
AOUT
VPA
VNT
PRM
PRP
VPT
RST
SDIT
SDI
SDO
Description
PCM received data from the A to D
Positive digital supply
PCM frame synchronization
PCM clock output
Negative analog ground
PCM clock in
Audio output – must be buffered for speaker
Positive analog supply
Negative transformer supply
Transformer primary minus
Transformer primary plus
Positive transformer supply
Hardware reset (active low)
SPI data out for daisy-chain mode
SPI data in
SPI data out
Rev. 1.6
DS_1x66B_001
Pin
Number
17
18
19
20
Pin Name
Type
VND
GND
O
I
INT
SCLK
CS
21
22
23
24
25
26
DR
27
28
29
30
31
32
33
34
35
36
37
VPS
38
39
40
41
42
M20PB
2.6
73M1866B/73M1966B Data Sheet
SRE
SRB
VBG
ACS
VNS
RXP
RXM
TXM
DCD
DCS
DCG
DCI
RGN
RGP
OFH
VNX
SCP
MID
VPX
Description
Negative digital ground
Interrupt / ring detect (active low – open drain)
SPI clock
I
I
SPI chip select (active low)
PCM transmit data sent to the D to A
I
O
O
Voltage regulator sense
Voltage regulator drive
VBG bypass, connect to 0.1μF capacitor to VNS
I
GND
PWRO
I
I
O
O
I
O
I
I
I
O
I
GND
I/O
I/O
PWR
AC current sense
Analog negative supply voltage
Analog positive supply voltage (output)
Receive plus – signal input
Receive minus – signal input
Transmit Minus – transhybrid cancellation output
DC loop output
DC loop current sense
DC loop control
DC loop input
Ring detect negative voltage input
Ring detect positive voltage input
Off-hook control
Test pin. Connect to VNX.
Negative supply voltage
Positive side of the secondary pulse transformer winding
Charge pump midpoint
Supply from the barrier
Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN
Packages
The exposed bottom pad is not intended for thermal relief (heat dissipation) and should not be
soldered to the PCB. Soldering of the exposed pad could also compromise electrical
isolation/insulation requirements for proper voltage isolation. Avoid any PCB traces or through-hole
vias on the PCB beneath the exposed pad area.
Rev. 1.6
15
73M1866B/73M1966B Data Sheet
DS_1x66B_001
3 Electrical Characteristics and Specifications
3.1
Isolation Barrier Characteristics
Table 6 provides the characteristics of the 73M1x66B Isolation Barrier.
Table 6: Isolation Barrier Characteristics
Parameter
Barrier frequency
Data transfer rate across the barrier for the sampling rate of 8 kHz
Rating
768 kHz
1.536 Mbps
When 16 kHz sampling rate is selected, the frequency and data transfer rates are twice those shown
above.
3.2
Electrical Specifications
This section provides the absolute maximum ratings, the recommended operating conditions and the DC
characteristics.
3.2.1 Absolute Maximum Ratings
Table 7 lists the maximum operating conditions for the 73M1x66B. Permanent device damage may occur
if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for
extended periods may affect device reliability.
Table 7: Absolute Maximum Device Ratings
Parameter
Supply voltage
Pin input voltage (except OSCIN)
Pin input voltage (OSCIN)
Min
-0.5
-0.5
-0.5 to VDD
Max
4.0
6.0
0.5
Unit
V
V
V
3.2.2 Recommended Operating Conditions
Function operation should be restricted to the recommended operating conditions specified in Table 8.
Table 8: Recommended Operating Conditions
Parameter
Supply voltage (VDD) with respect to VSS
Operating temperature
16
Min
3.0
-40
Max
3.6
85
Unit
V
°C
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
3.2.3 DC Characteristics
Table 9 lists the 73M1x66B DC characteristics.
Table 9: DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output low voltage
FSB,SCLK,
Output high voltage
Output high voltage
FSB, FSBD, SCLK
Input low leakage current
Input high leakage
current
Active digital current
Active PLL current
Active analog current
IDD total current*
IDD total current*
IDD current
PWDN=1
IDD current
SLEEP=1 (Ext Ref Clk)
IDD current
ENFEH=0 (Ext Ref Clk)
VIL
VIH1
VOL
VOL
Condition
–
–
IOL=4 mA
IOL=1 mA
Min
-0.5
0.7 VDD
–
–
Nom
–
–
–
–
VOH
VOH
IOH=-4 mA
IOH=-1 mA
IIL1
IIH1
VDD - 0.45
VDD - 0.45
–
–
VSS < Vin < VIL1
10
–
40
μA
VIH1 < Vin < 5.5
–
–
1
μA
1.5
1.5
17
20
30
5
mA
mA
mA
mA
mA
μA
IDD current at 3.0 V – 3.6 V Nominal at 3.3 V
–
–
IDD1dig
1.0
–
–
IDD1pll
1.0
–
–
IDD1ana
12
–
–
IDD1
15
–
–
IDD2
20
–
–
IDD3
1.0
Max
0.2 ∗ VDD
5.5
0.45
0.45
Unit
V
V
V
V
V
V
IDD4
–
–
0.5
1.0
mA
IDD6
–
–
1.0
1.5
mA
*Note: IDD1 is with the secondary of the barrier left open.
IDD2 is with the secondary of the barrier connected to 73M1916 fully powered.
Rev. 1.6
17
73M1866B/73M1966B Data Sheet
3.3
DS_1x66B_001
Interface Timing Specification
There are three interfaces associated with the 73M1x66B: the SPI interface, the PCM highway interface
and the line interface. This section provides the timing specification for the SPI interface and the PCM
highway interface.
3.3.1 SPI Interface
Table 10 lists the characteristics for the SPI interface.
Table 10: SPI Interface Switching Characteristics
Parameter
SCLK cycle time1
SCLK rise time
SCLK fall time
CS setup time
CS hold time
SDI setup time
SDI hold time
SDO turn on delay
SDO turn off delay
SDO hold time
SDI to SDITHRU propagation delay
Symbol
tscy
tscr
tscf
tics
tich
tids
tidh
todd
todo
todh
tidt
Min
62.5
–
–
25
20
25
20
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
6
Max
–
25
25
–
–
–
–
20
20
20
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note1: The minimal value of this parameter is for the case where only one 73M1906B is connected to the
host. If the daisy chain mode is used, the minimum SCLK cycle time increases according to the number
of slaves in the chain.
SCLK
tscy
tics
tich
CS
tids
tidh
SDI
todd
todh
todo
SDO
Figure 7: SPI Timing Diagram
18
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
3.3.2 PCM Highway Interface
Table 11: Switching Characteristics – PCM Interface (Slave Mode)
Parameter
PCLK_IN cycle time
PCLK_IN rise time
PCLK_IN fall time
FS setup time
FS hold time
FS cycle time
DR setup time
DR hold time
DX turn on delay
DX turn off delay
DX hold time
Symbol
tpcy
tpcr
tpcf
tifs
tifh
tifc
tids
tidh
todd
todo
todh
Min
122
–
–
25
20
–
25
20
–
–
–
Typ
–
–
–
–
–
125
–
–
–
–
–
Max
3906
25
25
–
–
–
–
–
20
20
20
Unit
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
Table 12: Switching Characteristics – PCM Interface (Master Mode)
Parameter
PCLK_OUT cycle time
PCLK_OUT rise time
PCLK_OUT fall time
FS setup time
FS hold time
FS cycle time
DR setup time
DR hold time
DX turn on delay
DX turn off delay
DX hold time
Symbol
tpcy
tpcr
tpcf
tifs
tifh
tifc
tids
tidh
todd
todo
todh
Min
–
–
–
50
50
–
25
20
–
–
–
Typ
488
–
–
–
–
125
–
–
–
–
–
Max
–
25
25
–
–
–
–
–
20
20
20
Unit
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
tifc
PCLK
tifs
tifh
tpcy
FS
tird
tids
tidh
DR
todd
todh
todo
DX
Figure 8: PCM Timing Diagram for Positive Edge Transmit Mode and Negative Edge Receive Mode
Rev. 1.6
19
73M1866B/73M1966B Data Sheet
DS_1x66B_001
PCLK
tifh
tifs
tpcy
FS
tird
tids
tidh
DR
todh
todd
todo
DX
Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode
3.4
Analog Specifications
This section provides the electrical characterizations of the 73M1x66B analog circuitry.
3.4.1 DC Specifications
VBG is to be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not
intended for any other external use.
Table 13: Reference Voltage Specifications
Parameter
VBG
VBG Noise
VBG PSRR
20
Test Condition
VDD=3.0 V – 3.6 V
300 Hz – 3.3 kHz
300 Hz – 30 kHz
Min
0.9
–
40
Nom
1.19
-86
–
Max
1.4
-80
–
Units
V
dBm600
dB
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
3.4.2 Call Progress Monitor
The Call Progress Monitor monitors activities on the line. The audio output contains both transmit and
receive data with a configurable level individually set by Register 10h.
Figure 10 shows the frequency response of the Call Progress Monitor Filter based upon the
characteristics of the device plus the external circuitry as shown.
Figure 10: Frequency Response of the Call Progress Monitor Filter
C1 0.1uF R1 120K
R2
120K
-VIN
CD
VOUT1
VOUT2
LS1
AOUT
VCC
R3 120K
4
1
2
3
+
C2
2.2uF
C4
1uF
VREF1
VREF2
U1
V+
GND
5
8
AT-2308
INTERVOX
VCC
6
7
C3
NJM2135
1uF
Figure 11: Demo Board Circuit Connecting AOUT to a Speaker
Table 14: Component Values for the Speaker Driver
Quantity
1
1
2
1
3
1
Reference
C1
C2
C3, C4
LS1
R1, R2, R3
U1
Part Description
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Sound transducer
1/8 W resistor 0603
Audio amplifier
Part
0.1 μF
2.2 μF (optional)
1 μF
Speaker (Intervox)
120 kΩ
NJM2135 (New Japan Radio)
All measurements are at the AOUT pin with CMVSEL=0. Note that when CMVSEL=1, the peak signal at
AOUT is increased to approximately 1.11 Vpk.
Rev. 1.6
21
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Table 15: Call Progress Monitor Specification
Parameter
AOUT for transmit
AOUT transmit THD
AOUT for receive
AOUT receive THD
AOUT output
impedance
3.5
Test Condition
1 kHz full swing code (ATX)
CMRXG=11 (Mute)
Observe AOUT pin
CMTXG=00
CMTXG=01 relative
to CMTXG=00
CMTXG=10 relative
to CMTXG=00
CMTXG=11 (Mute)
CMTXG=00
1.0 Vpk, 1 kHz at the line or 0.5
Vpk at RXP/RXM with
RXG=10
CMTXG=11 (Mute)
Observe AOUT pin
CMRXG=00
CMRXG=01 relative
to CMRXG=00
CMRXG=10 relative
to CMRXG=00
CMRXG=11 (Mute)
CMRXG=00
Min
–
Nom
–
Max
–
Units
–
–
–
0.98
-6
–
–
Vpk
dB
–
-12
–
dB
–
–
–
Mute
40
–
–
–
–
dB
dB
–
–
–
0.96
-6
–
–
Vpk
dB
–
-12
–
dB
–
–
–
Mute
40
10
–
–
–
dB
dB
kΩ
73M1x66B Line-Side Electrical Specifications (73M1916)
Table 16 lists the absolute maximum ratings for the line side. Operation outside these rating limits may
cause permanent damage to this device.
Table 16: Line-Side Absolute Maximum Ratings
Parameter
Pin input voltage from VPX to VNX
Pin input voltage (all other pins) to VNS
22
Min
-0.5
-0.5
Max
6.0
4.0
Unit
V
V
Rev. 1.6
DS_1x66B_001
3.6
73M1866B/73M1966B Data Sheet
Reference and Regulation
Table 17 lists the VBG specifications. VBG should be connected to an external bypass capacitor with a
minimum value of 0.1 μF. This pin is not intended for any other external use.
The following conditions apply: VPX=5 V; Barrier Powered Mode; Barrier Data Rate across the
Barrier=1.5 Mbps; VBG connected to 0.1 μF external cap.
Table 17: VBG Specifications
Parameter
VBG
VBG noise
VBG PSRR
VPS
VPS PSRR
3.7
Test Condition
See conditions above.
300 Hz – 3.3 kHz
300 Hz – 30 kHz
VPX=5.5 V
VPX=4.5 V to 5.5 V
Min
–
–
40
–
–
Nom
1.19
-86*
–
3.15
40
Max
–
-80
–
–
–
Units
V
dBm600
dB
V
dB
DC Transfer Characteristics
Table 18 lists the maximum DC transmit levels. All tests are driven at pin DCI and measured at pin DCS.
DCEN=1. ILM=1.
Table 18: Maximum DC Transmit Levels
Parameter
VDCON
(DC "On" Voltage)
With ENAC=0
DC Gain
IDCI before ILIM
IDCI after ILIM
Delta VDCS
Delta IDCI
*Noise
Rev. 1.6
Test Condition
DCIV=00
DCIV=01
DCIV=10
DCIV=11
DCIV=XX
VDCON26 dB. This
function can be enabled or disabled.
Tx Buf
TXM
17.4 kΩ
-
Rn
RXM
Rx Buf
+
Vin
-
21 kΩ
Rp
RXP
From the Line
Vin+
52.3 kΩ
4.7 uF
Figure 38: Trans-hybrid Cancellation
10.6 Direct Access Arrangement Control Functions
These Transmit Control Registers contain control information to set up the line side of the 73M1x66B.
Included are DC-IV characteristics, off-hook control, etc.
Table 38: DAA Control Functions
Function
Mnemonic
ACZ
Register
Location
0x16[3:0]
Type
W
Description
Active Termination Loop
Controls the selection of the active termination loops per the table
shown below. ATEN must be set to 1 for selection to be enabled.
ACZ Field
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
68
Active Termination Loop Setting
600 Ω
900 Ω
270 Ω + 750 Ω || 150 nF and 275 Ω +
780 Ω || 150 nF (ETSI ES 203 021-2)
220 Ω + 820 Ω || 120 nF and 220 Ω +
820 Ω || 115 nF (Australia)
370 Ω + 620 Ω || 310 nF
320 Ω + 1050 Ω || 230 nF
370 Ω + 820 Ω || 110 nF
275 Ω + 780 Ω || 115 nF
120 Ω + 820 Ω || 110 nF
350 Ω + 1000 Ω || 210 nF
200 Ω + 680 Ω || 100 nF (China)
600 Ω + 2.16 µF
900 Ω + 1 µF
900 Ω + 2.16 µF
220 Ω + 400 Ω || 70 nF (China)
270 Ω + 600 Ω || 150 nF (Global
Impedance)
Rev. 1.6
DS_1x66B_001
Function
Mnemonic
ATEN
Register
Location
0x16[4]
DCIV
0x13[7:6]
73M1866B/73M1966B Data Sheet
Type
W
W
ENAC
0x12[5]
WO
ENDC
0x12[6]
WO
ENFEL
0x12[2]
WO
Rev. 1.6
Description
Active Termination Loop Enable
Enables or disables Active Termination Loop.
0 = Disable. (Default)
1 = Enable Active Termination Loop.
Note: normal operation requires this bit to be set to always enable a
termination circuit.
DC Current Voltage Characteristic Control
Hold state with ENDC and ENAC=1, at 20 mA DC loop current
measured at DCI. The Tip/Ring voltage assumes that there is a 5:1
attenuation of off-hook voltage at the DCI input pin.
DCIV1
0
DCIV0
0
0
1
1
0
1
1
Description
DC Loop On Voltage of 0.73 V
(5.60 V at Tip/Ring assuming a
5:1 step down of off-hook
voltage)
DC Loop On Voltage of 0.977 V
(6.75 V at Tip/Ring assuming a
5:1 step down of off-hook
voltage)
DC Loop On Voltage of 1.232 V
(7.65 V at Tip/Ring assuming a
5:1 step down of off-hook
voltage)
DC Loop On Voltage of 1.488 V
(9.35 V at Tip/Ring assuming a
5:1 step down of off-hook
voltage)
*Seize state with ENDC=1 and ENAC=0, 20 mA loop current.
DCIV =xxProvides a DC Loop “On” Voltage of 0.281V (3.9 V at Tip/Ring
assuming 5:1 step down of off-hook voltage)
Enable AC Transconductance Circuit
0 = Shut Down AC Transconductance Circuit. Aux A/D input = Ring
Detect Buffer (RGP/RGN) / Line Voltage (DCI). Seize state for going
off hook. (Default)
1 = Enable AC Transconductance Circuit. Aux A/D input = Line Current
(DCS) / Line Voltage (DCI).
Enable DC Transconductance Circuit
0 = Shut down Transconductance Circuit. (Default)
1 = Enable Transconductance Circuit.
Enable Front End Line-Side Circuit
0 = Power down Front End Line-Side circuits. (Default)
1 = Enable Front End blocks excluding DCGM, ACGM, shunt regulator.
69
73M1866B/73M1966B Data Sheet
Function
Mnemonic
ENLVD
Register
Location
0x12[3]
ENNOM
0x12[0]
ENSHL
IDISPD
0x12[4]
0x13[1]
Type
Description
WO
LeV Detection (OVDET, UVDET, OIDET monitors)
0 = Enable LeV detection. (Default)
1 = Disable LeV detection (used in line-powered mode to save power).
This bit will be 0 when Line Powered Mode is detected (ENLPW is set
in Register 0x02[2]) and set to 1 when an interrupt occurs within the
73M1916. This bit must be reset prior to switching back to Barrier
Powered Mode.
Enable Nominal Operation
0 = Speeds up the on and off hook transitions time by increasing the
DC loop bandwidth of the DC transconductance circuit in the
73M1x66B. This should be used for pulse dialing, going on and off
hook, etc. In addition, ENNOM=0 prevents the reset of all bits in
Register 0x12. (Default)
1 = Enter Nominal Operation. Reduces the loop bandwidth of the DC
transconductance circuit. Allows reset of Register 0x12 caused by bits
UVDET, OVDET or OIDET.
Enable Shunt Loading
0 = Disable shunt loading. (Default)
1 = Enable shunt loading of the line. Not used for most applications.
Discharge and Pulse Dialing
Controls the DC discharge current and how fast the loop turns off.
Affects pulse dialing waveform. Controls the amount of discharge
current during hook switch transitions.
0 = Minimum current. (Default)
1 = Maximum current.
It is recommended to set IDISPD to 1 prior to hook switching
operations.
Current Limit Enable
This control enables or disables loop current limit.
0 = No current limit. (Default)
1 = 42 mA current limit enabled.
Current Limit Mode On
This status bit is effective only when the ILM bit is set to 1.
0 = Loop current is lower than 42 mA.
1 = Loop current is higher than 42 mA and the current limiting mode is
active.
Off-Hook Enable
This bit controls the state of the Hook signal.
0 = On-Hook. (Default)
1 = Off-Hook.
Pulse Dialing Mode Enable
Alleviates the strict timing requirements for the Host having to control
ENDC and OFH during pulse dialing. With PLDM = 1, the Host only
has to toggle OFH to perform pulse dialing.
0 = Pulse Dialing Mode is disabled. (Default)
1 = Pulse Dialing Mode is enabled.
Receive Low Pass Notch Enable
0 = Billing Tone Receive Low Pass Notch (RLPN) filter bypassed.
(Default)
1 = RLPN Filter Enabled. See RLPNH for notch frequency selection.
WO
WO
WO
ILM
0x13[5]
WO
ILMON
0x1E[7]
R
OFH
0x12[7]
WO
PLDM
0x13[3]
WO
RLPNEN
70
0x16[5]
DS_1x66B_001
W
Rev. 1.6
DS_1x66B_001
Function
Mnemonic
RLPNH
THEN
Rev. 1.6
Register
Location
0x14[2]
0x15[3]
73M1866B/73M1966B Data Sheet
Type
W
W
Description
Receive Low Pass Notch
0 = Selects Receive Low Pass Notch (RLPN) at 12 kHz. (Default)
1 = Selects RLPN at 16 kHz. See RLPNEN (Register 0x16[5]) to
enable the filter.
Enable Transhybrid Circuit
The rejection of the transmit signal from the receive signal path.
0 = Transhybrid Circuit disabled. (Default)
1 = Transhybrid Circuit enabled.
This bit should always be set for optimal performance.
71
73M1866B/73M1966B Data Sheet
DS_1x66B_001
10.7 International Register Settings Table for DC and AC Terminations
Table 39 lists the recommended ACZ and DCIV register settings for various countries. Other parameters
can also be set in addition to the AC and DC termination. These settings along with the reference
schematic (see Figure 12) can realize a single design for global usage without country-specific
modifications. For more information on worldwide approvals, refer to the 73M1x66 Worldwide Design
Guide Application Note.
Table 39: Recommended Register Settings for International Compatibility
Country
ACZ(3:0)
Argentina
0000
DCIV(1:0)
Country
10
Hungary
2
1
ACZ(3:0)
DCIV(1:0)
Country
ACZ(3:0)
DCIV(1:0)
0010
10
Pakistan
0000
10
Australia
0011
11
Iceland
0010
10
Peru
0000
10
Austria1
0010
10
India
0000
10
Philippines
0000
10
Bahrain
0000
10
Indonesia
0000
10
Poland1
0010
10
Belgium1
0010
10
Ireland1
0010
10
Portugal1
0010
10
Bolivia
0000
10
Israel
0000
10
Romania
0010
10
1
1
Brazil
0000
10
Italy
0010
10
Russia
0000
10
Bulgaria1
0010
10
Japan
0000
00
Saudi Arabia
0000
10
Canada
0000
10
Jordan
0000
10
Singapore
0000
10
0000
10
0010
10
0010
10
Chile
0000
3
China
1110
10
10
Kuwait
1
0000
10
Croatia
0010
10
Cyprus1
0010
10
Columbia
1
Kazakhstan
0000
0010
10
Lebanon
0000
10
Leichtenstein2
0010
10
Latvia
1
0010
10
Denmark
0010
10
Ecuador
0000
10
Egypt
0000
10
El Salvador
0000
10
Estonia1
0010
10
1
0010
10
Morocco
France
0010
10
Netherlands
Germany1
0010
10
New Zealand3
Greece
0010
10
Guam
0000
10
Hong Kong
0000
10
Czech Rep
1
Finland
1
1
10
1
Slovakia
1
Slovenia
3
0011
10
South Korea
0000
10
Spain1
0010
10
South Africa
1
0010
10
Luxembourg
0010
10
Macao
0000
10
Malaysia
0000
10
Taiwan
0000
10
Malta
0010
10
ES 203 021-2
0010
10
Mexico
0000
10
Thailand
0000
10
0000
10
Turkey
0000
10
0010
10
UAE
0000
10
0100
10
UK1
0010
10
Nigeria
0000
10
Ukraine
0000
00
Norway2
0010
10
USA
0000
10
Oman
0000
10
Yemen
0000
10
Lithuania
1
1
1
0010
10
Switzerland
0010
10
Syria
0000
10
Sweden
2
1
These countries are members of the European Union, where there are no longer any regulatory
requirements for AC impedance. The suggested setting complies with ETSI ES 203 021-2. Other
settings can be used if desired.
2
These countries are members of the European Free Trade Association, and their regulations
generally follow the European Union model. The suggested setting complies with ETSI ES 203 021-2.
3
72
These countries can use the suggested complex setting for voice or data products
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
11 Line Sensing and Status
The 73M1x66 supports the means to implement several line status functions such as ring detection, Line
In Use detection, parallel pickup detection, and line voltage polarity reversals. To support these
functions, 73M1x66 is able to measure the line voltage and current characteristics. In conjunction with
these measurements, procedures can be implemented in the host to fully support these capabilities in an
application.
11.1 Auxiliary A/D Converter
An 8-bit auxiliary A/D converter integrated in the 73M1x66B provides line monitoring and sensing
capabilities. The A/D converter input signals are connected to the RGP and RGN pins of the device. It is
possible to use this A/D converter to sample signals unrelated to PSTN DAA functions. However, in this
application, it is necessary to isolate the input signal with optical or other means since the 73M1x66B is
connected directly to the PSTN. Under normal conditions, RGP and RGN are AC coupled to the line
through high voltage (250 V) capacitors.
Through the use of this auxiliary A/D converter, the following line status sensing features are supported
by the 73M1x66B:
•
•
•
•
•
Ring detection.
PSTN line already in use detection.
Off-hook detection that a parallel phone has been picked-up – parallel pick-up detection (PPU).
On-hook detection of DC loop voltage polarity reversals.
On-hook detection of Type II Caller ID.
11.2 Ring Detection
Ring Detection is provided through circuitry connected to the device pins RGP and RGN. Any large
voltage transition (ringing or line reversal) will be a source for the “Wake up” signal to the 73M1x66B.
Upon reception of a wake-up signal, the 73M1x66B passes the detected signal to the host where it is to
be qualified for frequency and cadence (on and off timing of the ring tone bursts) as a valid ring signal.
11.3 Line In Use Detection (LIU)
If the 73M1x66B is preparing to go off-hook and dial, it is required to be aware whether the phone line is
already in use by another device. If the 73M1x66B determines that the phone line is presently in use, it
can avoid going off-hook and interrupting the call in progress. The timing of the FXO’s off-hook transition
can be delayed until the FXO determines that the phone line is available. LIU sensing is done at pin
DCIN with the Aux A/D.
11.4 Parallel Pick Up (PPU)
Parallel Pick Up is a means for the 73M1x66B to determine and notify a host in the case when the DAA is
off-hook and a second or parallel-connected device during the course of a connection is also made to go
off-hook.
11.5 Polarity Reversal Detection
A third type of line sensing requirement is associated with Caller ID protocols found in Japan and some
European countries. In these countries, the Caller ID signals are sent prior to the start of normal ringing.
A polarity reversal is used to indicate to the FXO that transmission of Caller ID information is about to
begin. The detection of a polarity reversal takes place while the FXO is in the on-hook state.
11.6 Off-hook Detection of Caller ID Type II
It is also possible to receive Caller ID signals while the telephone is in use, referred to as Type II CID.
This requires the 73M1916 to constantly monitor the line for signals, such as special in-band or CAS
tones, while the FXO is in the off-hook state. This is done through the normal receive path.
Rev. 1.6
73
73M1866B/73M1966B Data Sheet
DS_1x66B_001
11.7 Voltage and Current Detection
The 73M1x66B is capable of detecting the following circumstances:
•
•
•
Under voltage on the line.
Over voltage on the line.
Over current.
These 73M1x66B built-in mechanisms provide protection to both the device itself and the external line
circuitry.
If enabled, Over Voltage and Over Current detection will cause the 73M1x66B to go on-hook without the
intervention of the host.
If configured in Line Powered Mode, the detection of an under-voltage condition causes the 73M1x66B to
switch automatically to Barrier Powered Operation (see Section 9.2.1). This is done without the
intervention of the host.
For each of the detection functions there are enable control bits and detection status bits. For each
function there is a master detection function enable bit that must be set in order for the functions to work.
11.8 Under Voltage Detection (UVD)
Under Voltage Detection is an important feature of 73M1x66B. It determines if the phone line is not
capable of supplying the current that the 73M1x66B requires from the line for proper operation. If this
function is enabled and if the line is not capable of providing this current, the UVD condition will be
asserted and can become a source of interrupt from the 73M1x66B to its connected host.
11.9 Over Voltage Detection (OVD)
If enabled, Over Voltage Detection is indicated if the device senses that the line voltage exceeds a
defined threshold. The device allows the selection of choice of either 60 Vpk or 70 Vpk (depending upon
the attenuation ratio, typically this is 100:1).
If enabled, the 73M1x66B will automatically go on-hook if over voltage is detected.
11.10 AC Signal Overload Detection
This is the same feature as used for the detection of billing tones (see Section 10.4). In this most generic
sense, this detector provides an indicator that the AC signal on the line exceeds a value of 3.5 Vpk.
11.11 Over Current Detection (OID)
When the line current exceeds the safe operating range of the 73M1x66B or the external transistors, the
device indicates this condition. If enabled, the 73M1x66B will automatically go on-hook if an over current
event is detected.
74
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
11.12 Line Sensing Control Functions
These registers contain control information to set up and use the 73M1x66B line sensing functions.
Table 40: Line Sensing Control Functions
Function
Mnemonic
CIDM
Register
Location
0x15[4]
RXBST
0x14[3]
Type
Description
W
Caller ID Mode
0 = Disable Caller ID Mode. (Default)
1 = Enables Caller ID Mode by coupling the signal from the RGN/RGP
pins to the PCM DX pins in the appropriate PCM codec format. A 20 dB
gain boost is included in the signal path. The RXBST bit should also be
set to allow the total nominal gain of 40 dB in the Caller ID path. The
normal signal path is disconnected.
Received Boost
If set to 1, Receive signal is increased by 20 dB. Default is 0. This is
used to amplify signals that are passed through the auxiliary A/D when
On-Hook.
Ring Detection Status Bits
Enable Ring Detection Interrupt
This control bit enables the ring detection interrupt.
0 = Ring Detection Interrupt Disabled.
1 = Ring Detection Interrupt Enabled. (Default)
When 73M1922 detects an incoming ring signal, this bit will be set, if
enabled, and reset when read.
Ring or Line Reversal Detection
Voltage greater than the Ring Detect Threshold was detected at
RGP/RGN. This value is latched upon the event and cleared on read.
The threshold is determined by RGTH. This is a maskable interrupt. It is
enabled by the ENRGDT bit.
0 = No Latched Ring or Line Reversal Detection event. (Default)
1 = A Latched Ring or Line Reversal Detection event.
Ringing Monitor
Bit 3 monitors the activity of Ringing for further cadence check by the
host:
0 = Silent
1 = Ringing
This bit is not latched. This status bit is reset when read.
Ring Detect Threshold
Controls the Ring Detect Threshold assuming a 100:1 reduction of Ring
Voltage into the RGP/RGN pins.
WO
ENRGDT
0x05[0]
W
RGDT
0x03[0]
R
RGMON
0x03[3]
R
0x0E[1:0]
W
RGTH
Rev. 1.6
RGTH1
RGTH0
Description
0
0
0
1
1
0
1
1
Ring Detect disabled. For ring
detection to occur, these bits
must be programmed to a nonzero state.
0.15 Vpk equivalent to ±15 Vpk
at Auxiliary A/D input.
0.30 Vpk equivalent to ±30 Vpk
at Auxiliary A/D input.
0.45 Vpk equivalent to ±45 Vpk
at Auxiliary A/D input.
75
73M1866B/73M1966B Data Sheet
Function
Mnemonic
Register
Location
Type
DS_1x66B_001
Description
Auxiliary A/D Converter Status Bits
LC
0x1C[7:1]
R
LV
0x1B[7:1]
R
Loop Current In DC Path
Result of Auxiliary A/D measuring the Loop Current (7-bit resolution,
least significant bits only).
Note: LC0=1 lsb=1.31/128=~10.23 mV=1.25 mA; magnitude only.
The value of the resistor between the rectifier bridge and the DCS pin is
assumed to be 8.2 Ω.
Example: 0000011 30.7 mV/RE=3.74 mA; 0010000 20 mA
Note: The AC path also has ~7 mA of loop current that should be added
to get the total loop current provided by the line.
Line Voltage On and Off Hook
Contains the seven most significant bits of an 8-bit A/D representation of
the voltage of the input of pin DCI. The voltage at the DCI pin is equal to
the decimal value of LV bits [7:1] x 11 mV. For example, if the value of
0100000x is read from LV bits [7:1], this has a decimal value of 64,
therefore DCI voltage equals 64 x 11 = 704 mV.
RNG
0x1A[7:0]
R
DET
0x03[2]
R
ENDET
0x05[2]
W
ENDT
0x12[1]
WO
Note that the voltage at the DCI pin is the voltage divided by 5 (off hook)
or 100 (on hook). When offhook the diode bridge, switch saturation
voltage, etc. should also be added to calculate the voltage at tip and ring.
Result of Auxiliary A/D measuring the attenuated ring voltage.
Note: 1 lsb=1.31/128=~10.23 mV; 1’s compliment.
Example: 00100000 327 mV or Ring Voltage=32.7 V
Line Sensing Control
Detection of Voltage or Current Fault
0 = None of the three conditions is detected.
1 = Indicates the detection of one of three conditions:
Under Voltage, Over Voltage and Over Current.
This status bit is reset when read. This is a maskable interrupt. It is
enabled by the ENDET bit.
Enables Line Sensing Interrupt On Host-Side Device
This bit controls whether an interrupt is generated based upon the
detection of Under Voltage, Over Voltage and Over Current.
0 = Disable detector interrupt (Default)
1 = Enable detector interrupt.
Enable Detectors On Line-Side Device
0 = UVD, OVD and OID conditions are ignored. (Default)
1 = Enables UVD, OVD and OID in the Line-Side Device and allows
them to be used in the Host-Side Device.
Under-Voltage Detection Control and Status
ENUVD
0x15[2]
WO
UVDET
0x1E[6]
R
76
Enable Under Voltage Detector On Line-Side Device
0 = Under Voltage Detector not enabled.
1 = Under Voltage Detector enabled. When enabled, the ENNOM bit is
temporarily set to the wide bandwidth mode if an
under-voltage condition detected to allow fast reacquisition of the line.
Under-Voltage Detector On Line-Side Device
0 = Under Voltage condition is not detected at VPS.
1 = Under Voltage condition is detected at VPS.
Rev. 1.6
DS_1x66B_001
Function
Mnemonic
Register
Location
73M1866B/73M1966B Data Sheet
Type
Description
Over-Voltage Detection Control and Status
ENOVD
0x15[1]
OVDET
0x1E[5]
OVDTH
0x13[2]
ENOLD
0x15[7]
OLDET
0x1E[3]
ENOID
0x15[0]
OIDET
0x1E[4]
Rev. 1.6
WO
Enable Over-Voltage Detector On Line-Side Device
0 = Over Voltage Detector not enabled.
1 = Over Voltage Detector enabled (not latched). Over voltage detector
is enabled if ENOVD, ENFEL and ENNOM all equal 1.
R
Over-Voltage Detector On Line-Side Device
0 = Over Voltage condition is not detected at RGP/RGN inputs.
1 = Over Voltage Condition is detected at RGP/RGN inputs.
WO Over-Voltage Threshold Setting
0 = Over Voltage Threshold is 0.6 Vpk at the chip or 60 Vp on the line.
1 = Over Voltage Threshold is 0.7 Vpk at the chip or 70 Vp on the line.
Over-Load Detection Control and Status
WO Enable Over-Load Detector
0 = Over Load Detector is not enabled.
1 = Over Load Detector is enabled (not latched).
R
Over-Load Detector
0 = Over-Load condition is not detected.
1 = Over-Load condition detected. Asserted when the line voltage
exceeds 3.5 Vpk typically. OLDET is performed partially in analog
domain and partially in digital domain. OLDET is asserted when the
delta from aux A/D between two consecutive DCI samples is greater
than 76.
Over-Current Detection Control and Status
WO Enable Over-Current Detector On Line-Side Device
0 = Over-Current Detector is not enabled. (Default)
1 = Over-Current Detector is enabled.
R
Over-Current (I) Detector On Line-Side Device
0 = Over-Current (I) condition is not detected.
1 = Over-Current (I) condition is detected at the DCS pin when Loop
Current is > 125 mA if ILM=0, or > 55 mA if ILM=1.
77
73M1866B/73M1966B Data Sheet
12
DS_1x66B_001
Loopback and Testing Modes
Figure 39 shows the six loop back modes available within the 73M1x66B.
73M1916
73M1906B
CTL
SPI
Interface
STA
Aux A/D
STA
Tip
Interp.
Filter
PRP
TxD
SCP
LSBI
MSBI
DSDM
Onchip
LIC
TBS
TxAFE
TxA
TxData
PCMLB
RxData
PCM
Interface
DIGLB1
DIGLB2
INTLB1
Decim.
Filter
RxD
PRM
SCM
SinC3
Filter
External
LIC
ALB
INTLB2
RxAFE
RBS
RxA
Ring
Figure 39: Loopback Modes Highlighted
Table 41 describes how the above control bits interact to provide each of the six loopback modes.
Table 41: Loopback Modes
TEST
TMEN
DTST
LB
0000
0
00
0
0000
0
00
1
0000
0000
0001
0010
0011
78
1
1
0
0
0
10
11
00
00
00
0
0
0
0
0
Loopback Mode
Normal Mode. (Default)
Mnemonic
No Loops
Loopback between PCM Compander
and FXO core.
Digital Loopback Mode
Interpolated TxData (TxD) is looped
back to the Decimated RxData input
(RxD).
Remote Analog Loopback
Received RxD is looped back as TxD
and transmitted back to the
73M1x66B
Line-Side Device; RxD is D/A
converted to yield the analog transmit
signal (TxA).
Digital Loopback Mode
DR Transmit Bit Stream (TBS) is
looped back to receive digital channel
and received at DX (DIGLB2).
Remote Analog Loopback
Receive analog signal is converted to
Received Bit Stream (RBS) and is
looped back to TBS and the analog
transmit channel (INTLB2).
Analog Loopback
The transmit DR data is connected to
the receiver at the analog interface
and received at the DX pin (ALB).
PCMLB
DIGLB1
INTLB1
DIGLB2
INTLB2
ALB
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
12.1 Loopback Controls
Table 42 describes the registers used for loopback control.
Table 42: Loopback Controls
Function
Mnemonic
TMEN
DTST
Register
Location
0x02[7]
0x07[1:0]
Type
W
W
Description
Test Mode Enable
Used to enable the activation of the test loops controlled by
the DTST bits (DIGLB1 and INTLB1).
0 = Disables DTST loops.
1 = Enables DTST loops.
TMEN has to be set to 1 before the setting of the DTST
bits.
Digital Test Mode Select
These control bits enable DIGLB1 and INTLB1.
Prior to writing to these bits, TMEN must be set to 1.
DTST1
0
1
1
LB
0x24[0]
W
TEST
0x18[7:4]
W
DTST0
0
0
1
Selected Test Mode
Normal (Default)
DIGLB1
INTLB1
Loopback
0 = Disables PCM Loopback.
1 = Enables PCM Loopback within the Host-Side Device.
This four-bit field is used to enable the loopback mode per the
following table:
TEST
Loopback Mode
0000 Normal Mode. (Default)
Transmit and receive channels are independent.
0001 Digital Loopback Mode.
DR Transmit Bit Stream (TBS) is looped back to
receive digital channel and received at DX (DIGLB2).
0010 Remote Analog Loopback.
Receive analog signal is converted to Received Bit
Stream (RBS) and is looped back to TBS and the
analog transmit channel (INTLB2).
0011 Analog Loopback.
The transmit DR data is connected to the receiver at
the analog interface and received at the DX pin
(ALB).
Rev. 1.6
79
73M1866B/73M1966B Data Sheet
DS_1x66B_001
13 Performance
This section provides an overview of typical performance characteristics measured using 73M1x66B
production devices on a Teridian Reference Board. The measurements were made using a Wandel and
Goltermann PCM-4 test unit. The tests conform to ITU-T Recommendation G.712 (2001). For more
information, see the 73M1966B Performance Characterization.
13.1 Transmit
Figure 40 provides performance characteristics for transmit gain tracking.
Figure 40: Variation of Transmit Gain Digital Input to Analog Output at the Line
80
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Figure 41 provides performance characteristics for receive gain variation against frequency.
Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line
Figure 42 provides performance characteristics for distortion in the direction of the digital port to analog port.
Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line
Rev. 1.6
81
73M1866B/73M1966B Data Sheet
DS_1x66B_001
13.2 Receive
Figure 43 provides performance characteristics for receive gain tracking.
Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output
82
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Figure 44 provides performance characteristics for gain variation against frequency.
Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output
Figure 45 provides performance characteristics for distortion in the direction of the analog port to digital
port.
Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output
Rev. 1.6
83
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Figure 46: Return Loss, @ 80 mA
84
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
14 Package Layout
Figure 47: 20-Pin TSSOP Package Dimensions
0.85 NOM./ 0.9MAX.
5
0.00 / 0.005
2.5
0.20 REF.
1
2.5
2
3
5
SEATING
PLANE
TOP VIEW
SIDE VIEW
0.35 / 0.45
3.0 / 3.75
CHAMFERED
0.30
0.18 / 0.3
1.5 / 1.875
1
2
3
3.0 / 3.75
0.25
1.5 / 1.875
0.5
0.2 MIN.
0.35 / 0.45
0.5
0.25
BOTTOM VIEW
Figure 48: 32-Pin QFN Package Dimensions
Rev. 1.6
85
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Figure 49: 42-Pin QFN Package Dimensions
86
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
15 Ordering Information
Table 43 lists the order numbers and packaging marks used to identify 73M1x66B products.
Table 43: Order Numbers and Packaging Marks
Part Description
73M1966B 32-Pin QFN, Lead free
Order Number
73M1966B-IM/F
73M1966B 32-Pin QFN, Lead free,
Tape and Reel
73M1966B 20-Pin TSSOP, Lead free
73M1966B-IMR/F
73M1966B 20-Pin TSSOP, Lead free,
Tape and Reel
73M1866B 42-Pin QFN, Lead free
73M1866B 42-Pin QFN, Lead free,
Tape and Reel
73M1966B-IVT/F
73M1966B-IVTR/F
73M1866B-IM/F
73M1866B-IMR/F
Packaging Mark
73M1916A-M
73M1906B
73M1916A-M
73M1906B
73M1916AVT
73M1906BVT
73M1916AVT
73M1906BVT
73M1866B-IM
73M1866B-IM
Host/Line
Line-Side IC
Host-Side IC
Line-Side IC
Host-Side IC
Line-Side IC
Host -Side IC
Line-Side IC
Host -Side IC
16 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the
73M1966B, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: fxo.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
Rev. 1.6
87
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Revision History
Revision
Date
1.0
11/7/2007
1.1
1.2
1.3
1.4
5/13/2008
7/30/2008
11/17/2008
7/21/2009
1.5
1.6
10/16/2009
4/2/2010
Description
First publication.
Replaced Table 16 with a new table.
Replaced the schematics in Figure 12 and Figure 13 with new schematics.
Moved the steps to enable the calibration of receive DC offset from Section
8.8.3 to the 73M1866B/73M1966B Implementer’s Guide.
Corrected the Types (R, W, WO) in Table 32.
Rewrote the description of the ADJ bit.
Added clarification to the description of the PLDM bit.
Added clarification to the description of the RGDT bit.
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All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
88
Rev. 1.6
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