Simplifying System IntegrationTM
73S1209F
Evaluation Board User Guide
August 19, 2009
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
UG_1209F_034
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Microsoft, Windows and Vista are registered trademarks of Microsoft Corporation.
Signum is a trademark of Signum Systems Corporation.
Keil is a trademark of ARM® Ltd.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
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73S1209F Evaluation Board User Guide
Table of Contents
1
Introduction ................................................................................................................................... 4
1.1
Evaluation Kit Contents......................................................................................................... 5
1.2
Evaluation Board Features .................................................................................................... 5
1.3
Recommended Equipment and Test Tools ............................................................................ 5
2
Evaluation Board Setup................................................................................................................. 6
2.1
Connecting the Evaluation Board with an Emulation Tool ...................................................... 7
2.2
Loading User Code into the Evaluation Board ....................................................................... 8
3
Using the PCCID Application ...................................................................................................... 10
3.1
Host Demonstration Software Installation ............................................................................ 10
4
Evaluation Board Hardware Description .................................................................................... 11
4.1
Jumpers, Switches and Modules ......................................................................................... 11
4.2
Test Points ......................................................................................................................... 16
4.3
Schematic........................................................................................................................... 17
4.4
PCB Layouts....................................................................................................................... 18
4.5
Bill of Materials ................................................................................................................... 24
4.6
Schematic Information ........................................................................................................ 27
4.6.1 Reset Circuit.............................................................................................................. 27
4.6.2 Oscillators ................................................................................................................. 27
4.6.3 LCD .......................................................................................................................... 28
4.6.4 Smart Card Interface ................................................................................................. 29
5
Ordering Information ................................................................................................................... 30
6
Related Documentation ............................................................................................................... 30
7
Contact Information..................................................................................................................... 30
Revision History .................................................................................................................................. 31
Figures
Figure 1: 73S1209F Evaluation Board ..................................................................................................... 4
Figure 2: 73S1209F Evaluation Board Basic Connections ........................................................................ 6
Figure 3: 73S1209F Evaluation Board Basic Connections with ADM-51 ICE ............................................ 7
Figure 4: Emulator Window Showing RESET and ERASE Buttons........................................................... 9
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu ..................................... 9
Figure 6: 73S1209F Evaluation Board Jumper, Switch and Module Locations ........................................ 15
Figure 7: 73S1209F Evaluation Board Electrical Schematic ................................................................... 17
Figure 8: 73S1209F Evaluation Board Top View (Silkscreen) ................................................................. 18
Figure 9: 73S1209F Evaluation Board Bottom View (Silkscreen) ............................................................ 19
Figure 10: 73S1209F Evaluation Board Top Signal Layer ...................................................................... 20
Figure 11: 73S1209F Evaluation Board Middle Layer 1 – Ground Plane................................................. 21
Figure 12: 73S1209F Evaluation Board Middle Layer 2 – Supply Plane ................................................. 22
Figure 13: 73S1209F Evaluation Board Bottom Signal Layer ................................................................. 23
Figure 14: External Components for RESET .......................................................................................... 27
Figure 15: Oscillator Circuit .................................................................................................................... 27
Figure 16: LCD Connections .................................................................................................................. 28
Figure 17: Smart Card Connections ....................................................................................................... 29
Tables
Table 1: Flash Programming Interface Signals ......................................................................................... 8
Table 2: Evaluation Board Jumper, Switch and Module Description ....................................................... 11
Table 3: Evaluation Board Test Point Description................................................................................... 16
Table 4: 73S1209F Evaluation Board Bill of Materials ............................................................................ 24
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73S1209F Evaluation Board User Guide
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1 Introduction
The Teridian Semiconductor Corporation (TSC) 73S1209F Evaluation Board is used to demonstrate the
capabilities of the 73S1209F Smart Card Controller device. It has been designed to operate either as a
standalone or as a development platform.
The 73S1209F Evaluation Board can be programmed to run any of the Teridian turnkey applications or a
user-developed custom application. Teridian provides its USB CCID application preloaded on the board
and an EMV testing application on the CD.
Applications can be downloaded through the In-Circuit-Emulator (ICE) or through the TSC Flash
Programmer Model TFP2. As a development tool, the evaluation board can operate in conjunction with
an ICE to develop and debug 73S1209F based embedded applications.
The 73S1209F Evaluation Board uses the same PWB as the 73S1215F. The 73S1215F has
some features that the 73S1209F does not contain. These include the 32 kHz oscillator, USB
interface, LED2 and LED3. These features are depopulated on the 73S1209F.
Figure 1: 73S1209F Evaluation Board
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1.1
73S1209F Evaluation Board User Guide
Evaluation Kit Contents
The 73S1209F Evaluation Kit contains the following:
•
73S1209F Evaluation Board: 4-layer, rectangular PWB as shown in Figure 1 (identification number
E1215N12C1 Rev C), containing the 73S1209F with the preloaded turnkey program PCCID.
•
•
•
12 VDC/1,000 mA universal wall transformer with 2.1 mm plug ID (CUI Inc. – EPAS-101W-12).
Serial cable: DB9, male/female, 2 meter length (Digi-Key AE1379-ND).
CD containing documentation (data sheet, and user guides), Software API libraries, evaluation code,
and utilities.
1.2
Evaluation Board Features
The 73S1209F Evaluation Board (see Figure 1) includes the following:
•
•
•
RS-232 interface
Dual smart card interface
ICE/Programmer interface
•
•
•
2 line x 16 character LCD module
6 x 5 Keypad
2 LEDs
1.3
Recommended Equipment and Test Tools
The following equipment and tools (not provided) are recommended for use with the 73S1209F
Evaluation Kit:
•
•
For functional evaluation: PC with Microsoft® Windows® XP or Vista®.
For software development (MPU code)
Signum™ ICE (In Circuit Emulator): ADM-51. Refer to
http://signum.temp.veriohosting.com/Signum.htm.
Keil™ 8051 C Compiler Kit: CA51. Refer to http://www.keil.com/c51/ca51kit.htm and
http://www.keil.com/product/sales.htm
Rev. 1.3
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73S1209F Evaluation Board User Guide
UG_1209F_034
2 Evaluation Board Setup
Figure 2 shows the basic connections of the evaluation board with the external equipment.
The power supply can come from two sources:
•
•
A regulated lab power supply connected to the banana plugs J2, J3 and J5. In this case, the board
main switch S1 has no effect.
Any AC-DC converter block (default), able to generate a DC power supply of 7 V min / 12 V max /
400 mA. In this case, the board main switch S1 connects or disconnects the supply to the board.
The communication with an external host is accommodated via a standard RS-232 serial interface
(TX/RX only).
The board is loaded by default with the PCCID application. It requires a PC to be connected through its
serial port. When powered-up, the board is able to run with the PC Exerciser host application. Refer to
the 73S1209F Evaluation Board Quick Start Guide to setup and run the PCCID application.
1
+2.7 V to
+3.6 V
400 mA
Power Supply:
1) Lab DC dual (3.3 V,
5 V) supply
or
2) Non-regulated DC
Block
+4.0 V to
+6.5 V
400 mA
2
+7 V to +12 V
400 mA
RS232
DB9 Cable
Figure 2: 73S1209F Evaluation Board Basic Connections
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2.1
73S1209F Evaluation Board User Guide
Connecting the Evaluation Board with an Emulation Tool
The 73S1209F Evaluation Board has been designed to operate with an In-Circuit-Emulator (ICE) from
Signum Systems (model ADM-51). Figure 3 shows the connections between the ICE and the evaluation
board. The Signum System POD has a ribbon cable that must be directly attached to connector J11.
Signum Systems offers different POD options depending on user needs. The standard pod allows users
to perform typical emulator functions such as symbolic debugging, in-line breakpoints, memory
examination/modification, etc. Other pod options enable code trace capability and/or complex
breakpoints at an additional cost.
Figure 3: 73S1209F Evaluation Board Basic Connections with ADM-51 ICE
Rev. 1.3
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73S1209F Evaluation Board User Guide
2.2
UG_1209F_034
Loading User Code into the Evaluation Board
Hardware Interface for Programming
The signals listed in Table 1 are necessary for communication between the TFP2 or ICE and the
73S1209F.
Table 1: Flash Programming Interface Signals
Signal
Direction
Function
E_TCLK
Output from 73S1209F
Data clock
E_RXTX
Bi-directional
Data input/output
Bi-directional
Flash Downloader Reset (active low)
1
E_RST
1
The E_RST signal should only be driven by the TFP2 when enabling these
interface signals. The TFP2 must release E_RST at all other times.
These signals, along with 3.3 V and GND are available on the emulator header J11. Production modules
may be equipped with much simpler programming connectors, e.g. a 5x1 header.
Programming of the flash memory requires either the Signum Systems ADM51 in-circuit emulator or the
TSC Flash Programmer Model TFP2 provided by Teridian.
Loading Code with the In-Circuit Emulator
If firmware exists in the 73S1209F flash memory, the memory must be erased before loading a new file
into memory. In order to erase the flash memory, the RESET button in the emulator software must be
clicked followed by the ERASE button (see Figure 4).
Once the flash memory is erased, the new file can be loaded using the Load command in the File menu.
The dialog box shown in Figure 5 makes it possible to select the file to be loaded by clicking the Browse
button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC.
At this point, the emulator probe (cable) can be removed. Once the 73S1209F device is reset using the
reset button on the evaluation board, the new code starts executing.
Loading Code with the TSC Flash Programmer Model TFP2
Follow the instructions given in the TSC Flash Programmer Model TFP2 User's Manual.
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UG_1209F_034
73S1209F Evaluation Board User Guide
RESET
BUTTON
ERASE
BUTTON
Figure 4: Emulator Window Showing RESET and ERASE Buttons
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu
Rev. 1.3
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73S1209F Evaluation Board User Guide
UG_1209F_034
3 Using the PCCID Application
The PCCID firmware is pre-installed on the 73S1209F Evaluation Board. It requires a PC with the serial
RS-232 port. When powered-up, the board is able to run the PCCID demonstration host application which
allows:
•
•
•
3.1
Smart card activation and deactivation, in ISO or EMV mode.
Smart card APDU commands to be exchanged with the smart card inserted in the board.
Starting a test sequence in order to test and evaluate the board performance against an EMV test
environment.
Host Demonstration Software Installation
Installation on Windows XP
Follow these steps to install the software on a PC running Windows XP:
•
Extract “PCCID Vz.zz Release.zip” (where z.zz is the latest version of the firmware release).
o Create an install directory. For example: “C:\TSC\”.
o Unzip “PCCID Vz.zz Release.zip” to the just created folder. All applications and documentation
needed to run the board with a Windows PC will be loaded to this folder.
•
•
•
•
Plug the supplied adapter into the 5V DC jack and a wall outlet.
Connect the serial cable between the host system and the 73S1209F Evaluation Board.
Press the ON/OFF switch to turn the board on.
Run “TSCP-CCID.exe” (located in the path - x:\yyy\ PCCID Vz.zz Release\Host
Applications\Windows App\App\Bin\Release) on the host system to execute the host demonstration
application (where x refers to the drive, yyy refers to the directory the installation .zip file was
expanded to and z.zz is the latest version of the firmware release).
At this point the application window should appear. For additional information regarding the use of the
Teridian Host application, refer to the Pseudo-CCID Host GUI Users Guide (UG_12xxF_037).
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73S1209F Evaluation Board User Guide
4 Evaluation Board Hardware Description
4.1
Jumpers, Switches and Modules
Table 2 describes the 73S1209F Evaluation Board jumpers, switches and modules. The Item # in Table 2
references Figure 6. The default setting refers to setup for running USB-CCID application.
Table 2: Evaluation Board Jumper, Switch and Module Description
Schematic
Item
and
#
Silkscreen
Reference
1
J2, J3, J5
Default
Name
setting
No
Banana plugs for
Connect external regulated
power supply
Use
Must be used to connect an external regulated
power supply. These inputs are intended to allow
control of the input supply voltage of the board
(e.g. different than 5.0 V and 3.3 V on-board
regulators).
JP5 must be in position “5V EXT” and JP1 must be
in position “5V ”when using this 5 V power supply
input. JP6 must be in position “EXT” ”when using
this 3.3 V power supply input.
The evaluation board is sensitive to the polarity:
One red plug is +3.3 V nominal and the other red plug is +5.0 V. The black plug is ground. The
voltage supply input should be in the range +2.7 V to +3.6 V and 4.75 V to 5.5 V respectively.
2
JP4
Inserted VDD jumper
In normal use, a jumper must be inserted in this
header, to connect the +3.3 V power supply of the
board to the VDD pins of the 73S1209F. This
jumper can be replaced by a µA / mA-meter to
measure the actual current drawn by the 73S1209F.
3
JP3
Inserted 3.3 V jumper
In normal use, a jumper must be inserted in this
header, to connect the +3.3 V power supply of the
RS-232 transceiver and the 73S8010R. This
jumper can be removed to minimize power
consumption if these devices are not used.
4
JP6
‘INT’
5
S1
Rev. 1.3
Jumper:
A jumper must be inserted to select one of the
power supply selection following settings:
(#1)
• In position “EXT”, the evaluation board 3.3 V is
supplied from the external power supply inputs
(banana plug J3). In this case, the voltage must
be externally regulated. The power supply line is
directly applied to the board power supply. This
external power supply must not exceed 3.6 V.
• In position “INT”, the evaluation board is
powered from the 3.3 V voltage regulator U1.
The regulator can be powered either from the
USB bus power supply (USB-powered
application), or from an external non-regulated
power supply (connector PJ1).
Main switch
This switch turns the power On / Off to the
evaluation board, when the jumper JP1 is in
position “VOUT”. When using a lab regulated
power supply connected to the banana plugs J2
and J3, this switch has no effect.
11
73S1209F Evaluation Board User Guide
Schematic
Item
and
#
Silkscreen
Reference
Default
Name
setting
UG_1209F_034
Use
6
PJ1
Connect DC jack
Plug to connect an external DC block. Must be
used in conjunction with appropriate settings of
S1, JP1 and JP6 (see details above).
Power supply features are:
Voltage: 7 V min; 12 V max
Current: 400 mA
7
J11
No
In-Circuit Emulator
Connect connector
This connector must be used when using an external
In-Circuit Emulator (SIGNUM 8052 ADM51 ICE).
Refer to the Electrical Schematic for pin assignment.
8
JP20
9
P1
10
D2, D3, D4,
D5
11
U5
12
RV1
13
S2 to S31
14
–
12
Not
Jumper:
Inserted analog in
Jumper will select between the VBUS or analog in
test point for the analog input. Using VBUS on the
analog input will free up the USR7 interrupt for
other uses. The analog input can be set up to use
the compare to detect when the USB cable is
inserted/removed.
No
DB9 RS232 female
Connect socket
This socket allows connection of an RS232 cable
to a computer. Use a crossed wires (RX/TX)
cable. The evaluation board has an on-board
level shifter (U7) to allow direct connection to a
computer.
Connection of a RS232 link is required when using
the
pre-downloaded application.
LEDs:
Serial link activity and
four dedicated LED
pins.
These LEDs (D2, D3) reflect the activity on the
serial link (RS232 or serial), and the others are
used for general purpose indicators without the
need for current limiting resistors.
• D2 reflects the activity on the RX line (Data
going TO the 73S1209F)
• D3 reflects the activity on the TX line (Data
coming FROM the 73S1209F)
• D4 to D5 are the LED0-LED1 output pins .
LCD Module
On-board LCD module:
• 2 lines of 16 characters, each character dot
matrix is 5x7.
• Includes an embedded Hitachi HD44780 LCD
driver, controlled from the on-board 73S1209F
USR interface.
Adjustable resistor to
adjust LCD brightness
Can be used to adjust the brightness of the onboard LCD module.
On-board keypad
5x6 keyboard directly connected to the on-board
73S1209F IC. The assignment of the keys, as
silk-printed on the PCB is the one supported by
the TSC Application Programming Interface.
Board reference and
serial number
Should be mentioned in any communication with
TSC Application Engineers when requesting
support.
Rev. 1.3
UG_1209F_034
Schematic
Item
and
#
Silkscreen
Reference
73S1209F Evaluation Board User Guide
Default
Name
setting
15
JP2
16
–
17
JP16,
JP17
Inserted Jumper: LED pins
In normal use, a jumper must be inserted in this
header, to connect the LEDs to the LED pins of
the 73S1209F. This jumper can be replaced by a
µA / mA-meter to measure the actual current
drawn by the LED outputs of the 73S1209F.
18
JP12
Inserted Jumper: 73S8010R
VPC connect
Insertion of the jumper will provide 5.0 V to the
73S8010R VPC pin. If the 73S8010R is not used,
the jumper can be removed.
19
JP13
Not
Jumper: USR7/SDA
Inserted select
This jumper selects which signal is connected to
the daughter board connector pin USR7:
• In position “USR7”, the 73S1209F USR7 signal
is connected to the daughter card pin USR7.
• In position “SDA”, the I2C SDA signal is
connected to the daughter card pin USR7. This
allows the SDA line to connect to an SDA pin
on a 73S8010R daughter card.
20
JP14
Not
Jumper: USR5/AUX2
Inserted select
This jumper allows the on board 73S8010 AUX2
pin to be connected to USR5 if needed. If not
needed the jumper should be removed.
21
U4
On board 73S8010R
The board contains a built-in 73S8010R that is
connected to the external smart card interface of
the 73S1209F. If not used, this device can be
disconnected from the 73S1209F by removing
jumpers JP12 and JP21.
22
JP21
Inserted Jumper: 73S8010R
interrupt
This jumper will allow the on-board 73S8010
interrupt output to connect to INT2 on the
73S1209F. Remove this jumper if the on-board
73S8010 is not used.
23
J7,J8
Not
Optional 73S80xxX
Inserted Daughter Board
interface
When developing applications that require more
than 2 smart card interfaces, an optional daughter
board can be populated to use the 73S1209F
external smart card interface (lines SCIO and SCK),
in conjunction with the USR(0:7) port and the INT2
interrupt input of the 73S1209F). Refer to the
Electrical Schematic for pin assignment.
Rev. 1.3
Inserted Jumper VPC
Use
Breadboard area
In normal use, a jumper must be inserted in this
header to connect the +5.0 V power supply of the
board to the VPC pins of the 73S1209F. This
jumper can be replaced by a µA / mA-meter to
measure the actual current drawn by the
73S1209F.
This breadboard area allows engineers to add
their own circuitry / connection of peripherals,
when prototyping and developing a 73S1209F
based application. User I/Os, GPIOs, interrupt
pins and power supply pins are located close to
this area to allow easy connection.
13
73S1209F Evaluation Board User Guide
Schematic
Item
and
#
Silkscreen
Reference
Default
Name
setting
Use
24
J9, J10
25
JP11
Not
Jumper: USR6/SCL
Inserted select
This jumper selects which signal is connected to
the daughter board connector pin USR6:
• In position “USR6”, the 73S1209F USR6 signal
is connected to the daughter card pin USR6.
• In position “SCL”, the I2C SCL signal is
connected to the daughter card pin USR6. This
allows the SCL line to connect to an SCL pin on
a 73S8010R daughter card.
26
JP10
Not
Jumper: USR6/AUX1
Inserted select
This jumper allows the on board 73S8010 AUX1
pin to be connected to USR6 if needed. If not
needed the jumper should be removed.
27
JP8
‘Active
High’
Jumper:
Selection of the
polarity of the card
detection switches of
internal smart card
connector
On-board smart card connectors and SIM/SAM
connectors are equipped with card presence
switches, normally open when no card is inserted.
When the switches are closed (card inserted), the
polarity must be selected by a jumper on JP8:
• In position “ACTIVE HIGH”, the card detection
switches connect +3.3 V to the card detection
inputs of the 73S1209F.
• In position “ACTIVE LOW”, the card detection
switches connect ground to the card detection
inputs of the 73S1209F.
The 73S1209F firmware can handle both polarities
for card detection. Therefore, this setting is
firmware dependent. The default firmware
settings are JP8 = ACTIVE HIGH and JP7 =
PRES.
28
S27
Reset button
Evaluation board main reset: Asserts a hardware
reset to the on-board 73S1209F IC.
29
JP7
‘PRES’
Jumper: Selection of
the PRES and PRESB
inputs
Selects the card detect input PRES or PRESB.
PRES is the active high input and PRESB is the
active low input.
See item 29 for more detail.
30
JP15
‘GND’
Jumper: security fuse
control
This jumper should be removed at all times.
Connecting the jumper will allow the security fuses
to be blown under firmware control. Refer to the
73S1209F Data Sheet for further information
about the security fuse.
14
SIM / SAM and Smart
Card connectors –
external interface (#2)
UG_1209F_034
Allows the evaluation board to communicate with a
smart card using either the standard (credit card
size) or SIM/SAM format. This slot is connected to
the 73S1209F external card interface # 2.
Note that J10 is wired is parallel to the smart card
connector J9 (underneath the PCB). Both
connectors cannot be populated at the same time.
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
4
1
2
6
3
5
8
7
9
10
11
35
34
33
32
12
31
30
29
28
27
13
26
TERIDIAN
25
24
23
21
16
18
20
22
19
15
14
17
Figure 6: 73S1209F Evaluation Board Jumper, Switch and Module Locations
Rev. 1.3
15
73S1209F Evaluation Board User’s Guide
4.2
UG_1209F_034
Test Points
The test point numbers listed in Table 3 refer to the test point numbers shown in the electrical schematic
and in the silkscreen of the PCB.
Table 3: Evaluation Board Test Point Description
Test
Point #
Name
Use
TP2, TP3
+3.3V
+3.3 V main board power supply, coming from the internal or external
source, as defined from the jumpers JP3 and JP6. TP3 and TP4 are close
to the breadboard area for easy wiring of the power supply.
TP6
TP7
VDD
VPC
2-pin test point, with one ground and one VDD signal directly connected to
the 73S1209F and its decoupling capacitors. Can be used to measure the
integrity of the digital power supply of the 73S1209F, or to add a decoupling
capacitor.
TP8
+5V
+5 V coming from the external DC block (connected to JP5), as selected
with jumper on JP1. Can be used to test voltage presence.
TP9
+3.3VFIX
+3.3 V coming from the on-board regulator (powered up from the external
DC block). Can be used to test voltage presence.
TP10
Smart Card
Contacts –
Interface #1
TP11 to
TP17
GND
TP18
16
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC1, RST1, CLK1, C81 and C41. Each contact
has its own ground pin on the header.
Ground test points. Can be used for grounding of lab equipment probes.
Card Detect – Card detect signal coming directly from the card connectors.
Interface #1
TP21
USR(7:0)
Standard 8-bit user I/O port of the 73S1209F.
Some of the user I/Os are shared by the extension 73S80xx daughter
board and the LCD interface. Only one should be used at a time.
TP22
USB – N/A
TP22 is not populated with the 73S1209F.
TP24
VBUS – N/A
TP24 is not populated with the 73S1209F.
TP25
Smart Card
Contacts –
Interface #2
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC2, RST2, CLK2, C42 and C82. Each contact
has its own ground pin on the header.
TP26
INT3
TP27
ROW[0:5]
Interrupt input #3 secondary test points.
TP28
LED0-1
The LED outputs from the 73S1209F. (LED2 and LED3 are N/C on the
73S1209F)
TP29
COL[0:4]
The column pins used for the keypad interface.
TP30
INT2-3
Interrupt input #2 and #3 of the 73S1209F. This header is close to the
breadboard area for easy wiring.
TP31
RX, TX
The TX and RX serial UART I/O signals (3.3 V digital logic level).
TP32
ANALOG IN
Analog input test point. Analog voltage can be connected to this test point
for voltage comparison.
TP34
CPUCLK
This pin outputs the oscillator clock of the 73S1209F device. Can be used
as a clock source for any purpose.
The row pins used for the keypad interface.
Rev. 1.3
UG_1209F_034
Schematic
TP22
1
3
TP12
TP13
TP14
TP15
TP16
TP17
3.3V
GND
D+
GND
D-
GND
D+
D-
+5VDC
VCC
HEADER 2X2
1
1
1
1
1
1
3
R2
24
DPLUS
R3
24
DMINUS
VBUS
1
100k VBUS_MON
R4
JP23
R5
6
C17
0.1uF
HEADER 2
200k
USB_CONN_4
OSC_IN_12
Y2
OSC_OUT_12
1
2
3
SCL
OSC_OUT_32
OSC_IN_32
12.000MHz
R34
SDA
C22
3
2
1
22pF
USR7
C23
GND
3.3V
JP13
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HEADER 9
J7
3
1
3
3
3
1
1
2
3
4
1
2
3
4
5
COL0
COL1
COL2
COL3
COL4
HEADER 4
3.3V
HEADER 2 x 4
TP25
GND
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
VPC
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
INT
GND
VDD
SDA
SCL
VDD_ADJ
VCC
RST
CLK
SAD0
SAD1
SAD2
GND
N/C
VPC
N/C
N/C
N/C
PRES
I/O
AUX2
AUX1
GND
CARD # 2 DETECT
POLARITY SELECT
C18
1uF
0
C20
AUX2
AUX1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SMARTCARD
SLOT #2
J9
1
2
3
4
5
6
7
8
C21
27p
27p
9
10
3.3V
SDA
SCL
VCC
RST
CLK
C4
GND
VPP
I/O
C8
SW-1
SW-2
Smart Card Connector
J10
1
2
3
4
5
6
7
8
C1
C2
C3
C5
C6
C7
SW1
SW2
SIM/SAM Connector
73S8010R
HEADER 5
HEADER 6
B
UP
ROW1
SW_MOM
SW_MOM
SW_MOM
LED0
LED1
LED2
LED3
1
2
3
4
5
6
S11
S10
1
SW_MOM
SW_MOM
A
ROW0
SW_MOM
SW_MOM
S9
3
2
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
3
1
ON/CE
F3
SW_MOM
2
4
6
8
10
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
1
3
1
3
1
3
1
S8
S7
1
3
F2
SW_MOM
S6
S5
S4
S3
1
3
F1
SW_MOM
CARD #1 DETECT
POLARITY SELECT
JP12
HEADER 2
S2
1
1uF
CARD DET
ACTIVE LOW
R6
1
2
SW-1
SW-2
Smart Card Connector
C16
U4
JP14
TP29
PRES
SIM/SAM Connector
VCC
RST
CLK
C4
GND
VPP
I/O
C8
TP18
1
2
3
VPC
C26
TP28
1
2
3
73S8009R
AUX2
TP27
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
GND
PRES
I/O
AUX1
AUX2
VCC
RST
GND
CLK
N/C
N/C
PRES
VPC
VDD
JP8
0.1uF
TSM_110_01_L_SV
TSM_110_01_L_SV
ACTIVE HIGH
C19
SCLK
SIO
SC4
SC8
INT2
GND
GND
GND
+5V
+5V
1
2
3
4
5
6
7
8
9
10
0.1uF
30-SWITCH
KEYPAD
C15
27p
27p
CS
RESET
N/C
0FF
I/OUC
AUX1UC
AUX2UC
CMDVCC5
CMDVCC3
RSTIN
CLKIN
RDY
PWRDN
TEST
J8
SCLK
SIO
AUX1
AUX2
INT2
GND
GND
GND
5V
5V
USR0
USR1
USR2
USR3
USR4
USR5
USR6/SCL
USR7/SDA
GND
+3.3V
1
2
3
4
5
6
7
8
9
10
C14
JP7
C1
C2
C3
C5
C6
C7
SW1
SW2
J4
1
2
3
4
5
6
7
8
0
PRES
SMARTCARD
SLOT #1
J1
1
2
3
4
5
6
7
8
R1
VDD
HEADER 2
USR5
22pF
22pF
JP11
32.768kHz
C25
C24
22pF
1M
USR0
USR1
USR2
USR3
USR4
USR5
AUX1
USR6
0
0
0
0
0
0
0
0
0
0
U3
SC I/F EXPANSION
VBUS
Y1
VDD
HEADER 2
TP24
GND
9
10
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
USR8
1
2
3
4
5
6
7
8
9
USR7
JP10
SCx_CLK and Vcc tracksC14, C15, C16, C18,
should be routed away C20 and C21 should be
from other Smart card located close to the
signalsand should be Smart Card Connector
surrounded by GND.
TP21
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
USR8
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
2
1
GND
4
HEADER 2 x 4
TP10
JP4
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
JP6
EXTERNAL
SUPPLY
GND
2
1
3.3V
2
4
TP7
10uF
HEADER 2
HEADER 2
1
2
GND
D-
0.1uF 0.1uF 0.1uF
JP3
INTERNAL
SUPPLY
1
2
3
+ C6
JP2
Layout TP10 & TP25 as 8x2 header and TP23 and TP26 as 4x2 header.
Populate 2pin header to every other rows such as pin1-2, pin5-6,
pin9-10 and pin13-14 for TP10 and TP25.
1
2
1
D+
5
10uF
VDD
These test pins should be located between two rows (4 pads each)
of SC connector and signal pins locate within 5mm from pads.
CLK track should be routed away from RST and C4.
VPC
VPC
VCC tracks should be
wider than 0.5mm.
GND GND GND GND GND GND GND
J6
5V
0.1uF
2
1
(BLK)
5V
2
1
0.01uF
TP11
GND
J5
Banana
C9
0.1uF
C13
LP2985
1
(RED)
EXTERNAL POWER
SUPPLY
GND
C8
4.7uF
USB_5V
J3
Banana
+3.3VDC
10uF
4
1
2
3
(RED)
VPC
5V
1
2
TP6
+ C7
HEADER 2
C10 +
GND
ON/OFF
BY PASS
JP5
+5VDC EXT
J2
Banana
+5.0VDC
3
2.2uF
VDD
C5
1
3
5
7
9
11
2
+ C12
10uF
VDD
C4
C3
C4
CLK
RST
VCC
C8
IO
C11
3
POWER_SWITCH
+5VDC
+ C2
5
V_OUT
V_IN
3.3V
2
4
6
8
10
12
1
+3.3V
1
3
5
7
9
11
1
5V
TP6(VDD), TP9(VPC) and
decoupling capacitors should
be located close to U6.
TP3
+3.3V
TP9
1
2
Vout
Vin
+5V
MBR0520L
+3.3VFIX
C11 and C10 to
be placed within
1cm of U2
U2
TP8
+5VDC
Reg
C4
CLK
RST
VCC
C8
IO
3
2
TP2
JP1
4
1
2
1
1
1
2
3
1
2
3
C1
10uF
D1
S1
PJ1
+5V SOURCE
SELECT
LM1117DT-5.0
GND.
1
2
3
Area of copper pattern
for U1 Vout should be
larger than 0.3 in2.U1
1
+7 to +15
VDC UnReg
+
4.3
73S1209F Evaluation Board User Guide
3.3V
Note: For u5 configure board according to the
following table.
JP17
HEADER 2
D5
JP18
HEADER 2
P1
V-
C2+
C2-
R1IN
R2IN
R3IN
ENB
SHDNB
R1OUTBF
R1OUT
R2OUT
R3OUT
2
1
HEADER 2
ANALOG SELECT ANALOG IN
C35
0.1uF
TP32
JP20
3
24
23
22
19
17
SCL
SDA
3.3V
R12
R13
3k
3k
VBUS_MON
16
21
20
18
RXD
1
2
3
4
5
6
OSC_OUT_32 7
OSC_IN_32
8
9
OSC_IN_12 10
OSC_OUT_12 11
COL0
12
COL1
13
COL2
14
15
COL3
16
17
LED0
LED2
LED1
LED3
SCL
SDA
X32OUT
X32IN
GND
X12IN
X12OUT
COL0
COL1
COL2
ANAIN
COL3
RXD
1200/15
INT3
SIO
TBUS1
SCLK
TBUS2
NC
RXTX
GND
TBUS3
VDD
TCLK
ERST
CPUCLK
ROW5
ROW4
USR0
USR1
HEADER 2
VDD
PROTO TY PE AREA
NC
DB7
14
15
USR3
DB4
DB6
DB5
11
12
13
USR0
USR2
USR1
DB1
DB3
DB2
9
10
DB0
E
6
USR4
8
R/W*
RS
VO
VDD
RV1
10K
2
LCD
BRIGHTNESS
ADJUST
SCLK
3.3V
R11
62
GND
R14
VDD
R18
R19
ROW5
ROW4
USR0
USR1
R21
62
62
62
R20
R22
62
62
R23
62
CPUCLK
Place R11, R14, R18,
R19, R20, R21, R22
and R23 close to U6
G1 G2 G3 G4 G5 G6 G7 G8 G9
SY M1
R15
10K
R16
10K
R17
3K
DNI
DNI
DNI
J11
ISY NC/BRKRQ
TBUS[0]
TBUS[1]
TBUS[2]
TBUS[3]
RXTX
TCLK
RST_EMUL
62
TP34
TXD
J12
0.1uF
INT3
SIO
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
15
13
14
T1IN
T2IN
T3IN
T4IN
T5IN
MBAUD
8
9
11
3.3V
T1OUT
T2OUT
T3OUT
T4OUT
T5OUT
D7
GND
5
6
7
10
12
1
JP19
LED
LED3
2
5
9
4
8
3
7
2
6
1
SERIAL
PORT
4
C33
0.1uF
25
C30
1uF
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
Emulator IF
DNI C37
1000pF
C38 C39 C40 C41 C42
20 pF 20 pF20 pF 20 pF 20 pF
1
C34
0.1uF
DB9_RS232
28
C29 +
JP21
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C1-
1
C1+
1
2
3
V+
LED0
LED2
LED1
LED3
D6
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
26
27
VCC
C32
0.1uF
INT2
U6
LED
LED1
5
D4
1
LED2
C31
0.1uF
5V
Unpopulated & unlabled
10k
LED
U7
MAX3237CAI
1
USR5
LED0
TP35
4
COL4
VDD
C43
1000pF
R10
HEADER 2
LED
3.3V
CLOSED
3
TXD
470
JP16
OPEN
U3, C19
GND
R9
D3
F
ROW5
SW_MOM
C28
C28
0.1uF
C28
R8
10
SEC
COL3
TXD
3
1
SW_MOM
COL2
COL1
S32
3
Z
Y
SW_MOM
SW
CW
COL0
1
3
1
U3, C19
1215
MDL-16265
2
1
+ C27
10uF
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
3
X
SW_MOM
1200
RESET
S27
RXD
470
1
LED
1
3
W
SW_MOM
S31
S30
S29
S28
1
R7
D2
2
RXD
DNI
1
E
ROW4
SW_MOM
2
1
LED
3
1
SW_MOM
INSTALL
3
S26
3
ENTER
/
SW_MOM
2
1
1
3
1
2
1
3
0
SW_MOM
SW1
DEVICE
7
3.3V
1
3
.
SW_MOM
S25
S24
S23
S22
1
OPTIONAL LCD DISPLAY SYSTEM
16 CHARACTER BY 2 LINES
U5
STATUS INDICATOR
3.3V
USR6
3
D
ROW3
SW_MOM
1
2
1
CLR
SW_MOM
MOUNT HOLES FOR STAND OFFS
1
9
SW_MOM
HEADER 3_0
1
3
1
3
1
8
SW_MOM
1
2
3
Matches up to
daughter board
1
1
3
1
3
7
SW_MOM
S21
1
1
S20
DNI
JP15
SEC
1
S19
TP26
TXD
RXD
1
S18
ROW2
SW_MOM
1
2
1
S17
SW_MOM
TP31
TXD
RXD
INT2
INT3
1
2
1
SW_MOM
C
USR5
USR4
USR3
USR8
USR2
ROW3
SW_MOM
INT2
INT3
3
1
DPLUS
DMINUS
SW_MOM
TP30
S16
3
DOWN
ISBR
SEC
RESET
VDD
DETCARD/PRES
I/O / I/O
C4/AUX1
C8/AUX2
CMDVCC5B/VCC
CMDVCC3B/RST
RST/GND
CLKIN/CLK
RDY/PRESB
SCPWRDN/VPC
TEST
TBUS0
INT2
1
3
6
TXD
COL4
USR7
ROW0
ROW1
USR6
ROW2
GND
DP
DM
VDD
USR5
USR4
USR3
USR8
USR2
ROW3
1
5
COL4
USR7
ROW0
ROW1
USR6
ROW2
3
1
3
4
S15
S14
S13
S12
1
Logo
TERIDIAN LOGO
Figure 7: 73S1209F Evaluation Board Electrical Schematic
Rev. 1.3
17
73S1209F Evaluation Board User Guide
4.4
UG_1209F_034
PCB Layouts
Figure 8: 73S1209F Evaluation Board Top View (Silkscreen)
18
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
Figure 9: 73S1209F Evaluation Board Bottom View (Silkscreen)
Rev. 1.3
19
73S1209F Evaluation Board User Guide
UG_1209F_034
Figure 10: 73S1209F Evaluation Board Top Signal Layer
20
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
Figure 11: 73S1209F Evaluation Board Middle Layer 1 – Ground Plane
Rev. 1.3
21
73S1209F Evaluation Board User Guide
UG_1209F_034
Figure 12: 73S1209F Evaluation Board Middle Layer 2 – Supply Plane
22
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
Figure 13: 73S1209F Evaluation Board Bottom Signal Layer
Rev. 1.3
23
73S1209F Evaluation Board User Guide
4.5
UG_1209F_034
Bill of Materials
Table 4 provides the bill of materials for the 73S1209F Evaluation Board schematic provided in Figure 7.
Table 4: 73S1209F Evaluation Board Bill of Materials
Qty. Reference
Part
PCB Footprint
Digi-key Part
Number
Part Number
Manufacturer
1
2
3
3
3
14
C2,C7,C27
C1, C6,C12
C3,C4,C5,C8,C9,C19,
C26,C28,C30,C31,C32,
C33, C34,C35
10 µF
10 µF
0.1 µF
3528-21 (EIA)
805
603
478-1672-1-ND
PCC2225CT-ND
PCC1762CT-ND
TAJB106K010R
ECJ-2FB0J106M
ECJ-1VB1C104K
AVX Corporation
Panasonic
Panasonic
4
5
6
7
1
1
1
4
C10
C11
C13
C14,C15,C20,C21
4.7 µF
2.2 µF
0.01 µF
27 pF
603
805
603
603
ECJ-1VB0J475K
ECJ-2YB0J225K
C1608X7R1H103K
ECJ-1VC1H270J
Panasonic
Panasonic
TDK Corporation
Panasonic
8
9
3
2
C16,C18,C29
C22,C23
1 µF
22 pF
603
603
10
5
C38, C39, C40, C41, C42 20 pF
603
11
12
13
14
1
1
4
9
1000 pF
MBR0520L
LED
HEADER 3
603
SOD-123
805
1 x 3 pin
15
9
HEADER 2
1 x 2 pin
S1011E-36-ND
16
2
C43
D1
D2,D3,D4,D5
JP1,JP5,JP6,JP7,JP8,
JP11, JP13,JP15, JP20
JP2,JP3,JP4,JP10,JP12,
JP14, JP16,JP17,JP21
J1,J10
PCC2396CT-ND
PCC1923CT-ND
445-1311-1-ND
PCC270ACVCTND
PCC2174CT-ND
PCC220ACVCTND
PCC200ACVCTND
PCC2151CT-ND
MBR0520LCT-ND
160-1414-1-ND
S1011E-36-ND
17
18
19
2
1
2
J2,J3
J5
J9,J4
20
21
2
1
J8,J7
J11
SIM/SAM
Connector
Banana (red)
Banana (black)
Smart Card
Connector
TSM_110_01_L_SV
Emulator IF
ITT_CCM003_3754 CCM03-3754CTND
Banana
Banana
ITT_CCM002CCM02-2504-ND
2504
TSM_110_01_L_SV
10 X 2 pin
A3210-ND
Item
24
C1608X5R1A105K TDK Corporation
ECJ-1VC1H220J
Panasonic
ECJ-1VC1H200J
Panasonic
ECJ-1VC1H102J
MBR0520L
LTST-C170FKT
PBC36SAAN
Panasonic
Fairchild
LITE-ON INC
Sullins Electronics
PBC36SAAN
Sullins Electronics
CCM03-3754CTND
16BJ381
16BJ382
CCM02-2504-ND
C&K
Mouser
Mouser
C&K
TSM_110_01_L_SV Samtec
104068-1
AMP/Tyco
Electronics
Rev. 1.3
UG_1209F_034
Item
Qty. Reference
73S1209F Evaluation Board User Guide
Part
PCB Footprint
Digi-key Part
Number
Part Number
Manufacturer
22
23
1
1
PJ1
P1
+12VDC
DB9_RS232
RAPC722
AMP_745781
SC1153-ND
A2100-ND
RAPC722
745781-4
24
25
26
27
28
29
1
12
2
1
1
8
10 kΩ
0Ω
470 Ω
10 Ω
10 kΩ
62 Ω
3266W
603
603
603
603
603
3266W-103-ND
P0.0GCT-ND
P470GCT-ND
P10GCT-ND
P10KGCT-ND
P62GCT-ND
3266W-1-103
ERJ-3GEY0R00V
ERJ-3GEYJ471V
ERJ-3GEYJ100V
ERJ-3GEYJ103V
ERJ-3GEYJ620V
30
31
32
33
2
1
1
30
3 Ωk
1 MΩ
POWER_SWITCH
SW_MOM
603
603
POW_SW
Pushbutton SW
P3.0KGCT-ND
P1.0MGCT-ND
EG2364-ND
401-1885-ND
ERJ-3GEYJ302V
ERJ-3GEYJ106V
100SP1T2B4M7RE
D6 C 10 LFS
Panasonic
Panasonic
E-Switch
ITT Industries
34
35
1
11
RV1
R1,R6,R24-33
R7,R9
R8
R10
R11,R14,R18,R19,R20,
R21, R22,R23
R12,R13
R34
S1
S2,S3,S4,S5,S6,S7,S8,
S9,S10,S11,S12,S13,
S14S15,S16,S17,S18,
S19,S20,S21,S22,S23,
S24,S25,S26,S28,S29,
S30,S31,S32
S27
TP8,TP9,TP13,TP14,
TP15,TP16,TP17,TP26,
TP32, TP34, TP35
Switchcraft
AMP/Tyco
Electronics
Bourns
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
SW
TP
Panasonic EVQ
1 Pin
P8051SCT
S1011E-36-ND
EVQ-PJX05M
PZC36SAAN
Panasonic
Sullins Electronics
36
1
TP18
TP
1 pin White
5012K-ND
5012
37
2
TP2,TP3
TP
1 pin Red
5010K-ND
5010
38
2
TP11,TP12
TP
1 pin Black
5011K-ND
5011
39
40
41
42
43
44
4
2
1
1
1
1
TP6,TP7,TP30,TP31
TP10,TP25
TP21
TP27
TP28
TP29
TP2
HEADER 2 x 4
HEADER 9
HEADER 6
HEADER 4
HEADER 5
1
6
1
6
4
5
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
PBC36SAAN
PBC36SAAN
PBC36SAAN
PBC36SAAN
PBC36SAAN
PBC36SAAN
Keystone
Electronics
Keystone
Electronics
Keystone
Electronics
Sullins Electronics
Sullins Electronics
Sullins Electronics
Sullins Electronics
Sullins Electronics
Sullins Electronics
Rev. 1.3
x 2 pin
x 2 pin
x 9 pin
x 1 pin
x 1 pin
x 1 pin
25
73S1209F Evaluation Board User Guide
Item
Qty. Reference
UG_1209F_034
Part
PCB Footprint
Digi-key Part
Number
TO-252-3
LM1117DT-5.0-ND LM1117DT-5.0
45
1
U1
LM1117DT-5.0
46
1
U2
LP2985
47
1
U4
73S8010R
48
49
1
1
U5
U6
MDL-16265
73S1209F
50
51
1
1
U7
Y1
MAX3237CAI
12.000 MHz
26
68 QFN
Part Number
Manufacturer
National
Semiconductor
LP2985IM5-3.3CT- LP2985IM5-3.3
National
ND
Semiconductor
73S8010R
Teridian
Semiconductor
153-1078-ND
MDL-16265-SS-LV Varitronix
73S1209F
Teridian
Semiconductor
MAX3237CAI-ND MAX3237CAI
Maxim
X1116-ND
ECS-120-20-4XDN ECS
Rev. 1.3
UG_1209F_034
4.6
73S1209F Evaluation Board User Guide
Schematic Information
This section provides recommendations on proper schematic design that will help in designing circuits
that are functional and compatible with the PCCID software library APIs.
4.6.1 Reset Circuit
The 73S1209F Evaluation Board provides a reset pushbutton that can be used when prototyping and
debugging software. The RESET pin should be supported by the external components shown in Figure 14.
R8 should be around 10 Ω. The capacitor C27 should be 10 µF. R8 and C27 should be mounted as
close as possible to the IC.
C43 (1000 pF) is shown for EFT protection and is optional.
3.3V
RESET
S27
2
1
+ C27
10uF
SW
R8
10
RESET
R10
10k
C43
1000pF
Figure 14: External Components for RESET
4.6.2 Oscillators
The 73S1209F contains an oscillator for the primary system clock. The system clock should use a
12 MHz crystal to provide the proper system clock rates for the serial and smart card interfaces. The
system oscillator requires a 1 MΩ parallel resistor to insure proper oscillator startup (Figure 15).
73S1209F
C36
OSC_IN_12
22pF
R35
1M
Y3
12.000MHz
C44
OSC_OUT_12
22pF
Figure 15: Oscillator Circuit
Rev. 1.3
27
73S1209F Evaluation Board User Guide
UG_1209F_034
4.6.3 LCD
The 73S1209F does not contain an on-chip LCD controller. However, an LCD module (with built-in
controller) can be used with the 73S1209F via use of specific USR (GPIO) pins. The LCD API libraries
support up to a 2 line/16 character display. Figure 16 shows the basic connection for this type of LCD.
The LCD module must connect to the USR pins as shown and it requires an external brightness adjust
circuit.
73S1209F
Figure 16: LCD Connections
28
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
4.6.4 Smart Card Interface
The smart card interface on the 73S1209F requires few external components for proper operation.
Figure 17 shows the recommended smart card interface connections.
•
•
•
•
•
The RST and CLK signals should have 27 pF capacitors at the smart card connector.
It is recommended that a 0 Ω resistor be added in series with the CLK signal. If necessary, in noisy
environments, this resistor can be replaced with a small resistor to create a RC filter on the CLK
signal to reduce CLK noise. This filter is used to soften the clock edges and provide a cleaner clock
for those environments where this could be problematic.
The VCC output must have a 1.0 µF capacitor at the smart card connector for proper operation.
The VPC input is the power supply input for the smart card power. It is recommended that both a
10 µF and a 0.1 µF capacitor are connected to provide proper decoupling for this input.
The PRES input on the 73S1209F contains a very weak pull down resistor. As a result, an additional
external pull down resistor is recommended to prevent any system noise from triggering a false card
event. The same holds true for the PRES input, except a pull up resistor is utilized as the logic is
inverted from the PRES input.
The smart card interface layout is important. The following guidelines should be followed to provide the
optimum smart card interface operation:
•
•
•
•
•
•
•
Route auxiliary signals away from card interface signals
Keep CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to
one layer (avoid vias to other plane). Keep CLK trace away from other traces especially RST and
VCC. Filtering of the CLK trace is allowed for noise purpose. Up to 30 pF to ground is allowed at the
CLK pin of the smart card connector. Also, the zero ohm series resistor, R7, can be replaced for
additional filtering (no more than 100 Ω).
Keep VCC trace as short as possible. Make trace a minimum of 0.5 mm thick. Also, keep VCC away
from other traces especially RST and CLK.
Keep CLK trace away from VCC and RST traces. Up to 30 pF to ground is allowed for filtering
Keep 0.1 µF close to VDD pin of the device and directly take other end to ground
Keep 10 µF and 0.1 µF capacitors close to VPC pin of the device and directly take other end to
ground
Keep 1.0 µF close to VCC pin of the smart card connector and directly take other end to ground
1215
Figure 17: Smart Card Connections
Rev. 1.3
29
73S1209F Evaluation Board User Guide
UG_1209F_034
5 Ordering Information
Part Description
Order Number
73S1209F 68-Pin QFN Evaluation Board
73S1209F-EB
6 Related Documentation
The following 73S1209F documents are available from Teridian Semiconductor Corporation:
73S1209F Data Sheet
73S1209F Evaluation Board Quick Start Guide
TSC Flash Programmer Model TFP2 User's Manual
7 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S1209F
contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: scr.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
30
Rev. 1.3
UG_1209F_034
73S1209F Evaluation Board User Guide
Revision History
Revision
Date
Description
1.0
January 22, 2007
Document Creation.
1.1
April 2, 2007
Update BOM and change to Rev C PWB. Remove board errata section.
1.2
August 8, 2007
Modify incorrect part number for S1 in BOM.
1.3
August 19, 2009
Remove 44-pin board and LAPIE references.
Miscellaneous editorial modifications.
Rev. 1.3
31
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