73S8023C
Smart Card Interface
Simplifying System Integration™
DATA SHEET
April 2009
DESCRIPTION
FEATURES
The Teridian 73S8023C is a low-power, high efficiency,
single smart card interface IC suitable for 3V and 5V
cards. It provides full electrical compliance with ISO7816-3 and EMV 4.0 (EMV2000) specifications.
•
Card Interface:
Complies with ISO-7816-3, EMV 4.0
A DC-DC Converter provides 3V / 5V to the card
from an external power supply input
High-efficiency converter: > 80% @ V DD =3.3 V,
V CC =5 V and I CC = 65 mA
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation
Protection includes 2 voltage supervisors which
detect voltage drops on card V CC and on V DD
power supply
The V DD voltage supervisor threshold value can be
externally adjusted
True over-current detection (150 mA max.)
2 card detection inputs, 1 for either possible switch
configuration
Full support of synchronous cards
•
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
3 Digital inputs control the card clock (division rate
and card clock source selection)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults
1 Power down digital input (places the 73S8023C
in a very low-power mode (card deactivated)
1 Chip select digital input for parallel operation of
several 73S8023C ICs.
1 External clock input (STROBE), used for
synchronous operation
1 Digital output clock, buffered version of signal on
XTALIN
Crystal oscillator or host clock (XTALIN), up to
27 MHz
•
Power Supply: V DD 2.7 V to 3.6 V
•
6 kV ESD Protection on the card interface
Hardware support for any type of synchronous cards
(memory cards) is provided.
Interfacing with the system controller is done through the
control bus; composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults. Data exchange
with the card is managed from the system controller using
the I/O line (and eventually the auxiliary I/O lines).
A chip select input allows multiple 73S8023C ICs to share
the same control bus. When chip select is set low, the
host microcontroller inputs are latched and outputs are
taken to a high impedance state.
The card clock signal can be generated by an on-chip
oscillator using an external crystal or by connecting an
external clock signal.
The 73S8023C device incorporates an ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Emergency card deactivation is initiated upon
card extraction or upon any fault generated by the
protection circuitry.
The 73S8023C requires only a single 2.7 V to 3.6 V power
supply, and features a high-efficiency embedded DC-DC
converter. This architecture, plus a Power Down digital
input that allow placing the IC in a very low-power mode
making the 73S8023C particularly suitable for low-power
applications (cell-phones, PDAs, payphones, hand-held
POS terminals…).
ADVANTAGES
•
•
•
•
•
Supports both synchronous and asynchronous smart
cards
Replacement for TDA8002, with up to 600 mW in
power savings (@ EMV ICCmax condition) !
The inductor-based DC-DC converter provides higher
current and efficiency
Ideal for battery-powered applications
Suitable for high current cards and SAMs: (100 mA
max)
Single 2.7 V to 3.6 V power supply allows removal
of 5 V from the system
Power down mode: 2 µA typical
Package: Small Format (5x5mm) 32-QFN
Rev. 1.5
APPLICATIONS
•
•
•
•
Point of Sales and Transaction Terminals
Payphones
Set-Top-Boxes, DVD / HDD Recorders
Payment card interfaces in portable devices (PDAs,
mobile phones…)
© 2009 Teridian Semiconductor Corporation
1
73S8023C Data Sheet
DS_8023C_019
FUNCTIONAL DIAGRAM
VDDF_ADJ
VDD
LIN
17
20
6
VDD
2
3
6
4
NC
21
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
GND
1
ICC FAULT
VDD FAULT
VCC FAULT
5
GND
DC-DC
CONVERTER
CMDVCC
GND
15
PWRDN
CS
12
VCC
R-C
OSC.
8
18
DIGITAL
CIRCUITRY
&
FAULT LOGIC
19
RSTIN
31
5V/3V
ICC RESET
BUFFER
14
ICC CLOCK
BUFFER
13
RST
Int_Clk
22
CLK
OFF
29
25
CLKDIV1
STROBE
30
CLKDIV2
23
XTALIN
24
XTALOUT
XTAL
OSC
CLKSEL
7
PRES
CLOCK
GENERATION
6
PRES
OVER
TEMP
32
CLKOUT
16
ISO-7816-3
SEQUENCER
TEMP FAULT
9
26
IOUC
27
I/O
ICC I/O BUFFERS
AUX1UC
11
AUX1
10
28
AUX2
AUX2UC
Figure 1: 73S8023C Block Diagram
2
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
Table of Contents
1
Pin Description .................................................................................................................................... 5
1.1 Card Interface ............................................................................................................................... 5
1.2 Miscellaneous Inputs and Outputs................................................................................................ 5
1.3 Power Supply and Ground............................................................................................................ 5
1.4 Microcontroller Interface ............................................................................................................... 6
2
System Controller Interface ............................................................................................................... 7
3
Oscillator.............................................................................................................................................. 8
4
DC-DC Converter – Card Power Supply .......................................................................................... 8
5
Voltage Supervision ........................................................................................................................... 9
6
Power Down....................................................................................................................................... 10
7
Over-Temperature Monitor............................................................................................................... 10
8
Activation and Deactivation ............................................................................................................. 11
8.1 Activation Sequence (Synchronous Mode) ................................................................................ 11
8.2 Deactivation Sequence (Synchronous Mode) ............................................................................ 11
8.3 Activation Sequence (Asynchronous Mode) ............................................................................... 12
8.4 Deactivation Sequence (Asynchronous Mode) .......................................................................... 14
9
OFF and Fault Detection .................................................................................................................. 14
10
I/O Circuitry and Timing ................................................................................................................... 15
11
Typical Application Schematic ........................................................................................................ 17
12
Electrical Specification..................................................................................................................... 18
12.1 Absolute Maximum Ratings ........................................................................................................ 18
12.2 Recommended Operating Conditions......................................................................................... 18
12.3 Package Thermal Parameters .................................................................................................... 18
12.4 Card Interface Characteristics .................................................................................................... 19
12.5 Digital Signals ............................................................................................................................. 22
12.6 DC Characteristics ...................................................................................................................... 23
12.7 Voltage / Temperature Fault Detection Circuits.......................................................................... 23
13
Mechanical Drawing (32-QFN) ......................................................................................................... 24
14
Package Pin Designation (32-QFN) ................................................................................................. 25
15
Ordering Information ........................................................................................................................ 26
16
Related Documentation .................................................................................................................... 26
17
Contact Information .......................................................................................................................... 26
Revision History ........................................................................................................................................ 27
Rev. 1.5
3
73S8023C Data Sheet
DS_8023C_019
Figures
Figure 1: 73S8023C Block Diagram ............................................................................................................. 2
Figure 2: Power Down Mode Operation: CS = high.................................................................................... 10
Figure 3: Activation Sequence – Synchronous Mode ................................................................................. 11
Figure 4: Synchronous Deactivation Operation – CKSEL = High............................................................... 12
Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low ......................... 13
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2 ......................................................... 13
Figure 7: Asynchronous Deactivation Sequence ........................................................................................ 14
Figure 8: Timing Diagram – Management of the Interrupt Line OFF .......................................................... 15
Figure 9: I/O and I/OUC State Diagram ...................................................................................................... 16
Figure 10: I/O – I/OUC Delays Timing Diagram.......................................................................................... 16
Figure 11: 73S8023C – Typical Application Schematic .............................................................................. 17
Figure 12: DC – DC Converter efficiency (V CC = 5 V) ................................................................................ 20
Figure 13: DC – DC Converter Efficiency (V CC = 3 V) ................................................................................ 20
Figure 14: 32-QFN Mechanical Drawing..................................................................................................... 24
Figure 15: 32-QFN 73S8023C Pin Out ....................................................................................................... 25
Table
Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 8
4
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
1 Pin Description
1.1
Card Interface
Name
Pin
Description
I/O
9
Card I/O: Data signal to/from card. Includes a pull-up resistor to V CC.
AUX1
11
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC.
AUX2
10
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC.
RST
14
Card reset: Provides reset (RST) signal to card.
CLK
13
Card clock: Provides clock (CLK) signal to card. The rate of this clock is
determined by crystal oscillator frequency and CLKDIV selections.
PRES
7
Card Presence switch: Active high indicates card is present. Includes a
pull-down current source.
PRES
6
Card Presence switch: Active low indicates card is present. Includes a pull-up
current source.
VCC
15
Card power supply: Logically controlled by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
GND
12
Card ground.
1.2
Miscellaneous Inputs and Outputs
Name
Pin
Description
XTALIN
23
Crystal oscillator input: can either be connected to crystal or driven as a
source for the card clock.
XTALOUT
24
Crystal oscillator output: connected to crystal. Left open if XTALIN is being
used as external clock input.
VDDF_ADJ
17
V DD fault threshold adjustment input: this pin can be used to adjust V DDF
value (that controls deactivation of the card). Must be left open if unused.
NC
4
Non-connected pin. Must be left open.
1.3
Power Supply and Ground
Name
Pin
Description
VDD
3, 20
GND
1
DC-DC converter ground.
GND
21
Digital ground.
LIN
2
External inductor. Connect external inductor from pin 2 to V DD . Keep the
inductor close to pin 2.
Rev. 1.5
System controller interface supply voltage: Supply voltage for internal power
supply and DC-DC converter power supply source.
5
73S8023C Data Sheet
1.4
DS_8023C_019
Microcontroller Interface
Name
Pin
Description
CMDVCC
18
Command V CC (negative assertion): Logic low on this pin causes the DC-DC
converter to ramp the V CC supply to the card and initiates a card activation
sequence.
5V/#V
31
5 volt / 3 volt card selection: Logic one selects 5 volts for V CC and card
interface, logic low selects 3 volt operation. When the part is to be used with
a single card voltage, this pin should be tied to either GND or V DD . However,
it includes a high impedance pull-up resistor to default this pin high (selection
of 5V card) when unconnected
PWRDN
5
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8023C in
its lowest power consumption mode. The PD mode is allowed only out of a
card session (PWRDN high is ignored when CMDVCC = 0). Must be tied to
ground when power down function is not used.
CLKDIV1
CLKDIV2
29
30
Sets the divide ratio from the XTALIN oscillator (or external clock input) to the
card clock. These pins include pull-down resistors.
CLKDIV1
0
0
1
1
CLKDIV2
0
1
1
0
Clock Rate
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
OFF
22
Interrupt signal to the processor: Active Low. Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20 kΩ pull-up to V DD.
RSTIN
19
Reset Input: This signal controls the RST signal to the card.
I/OUC
26
System controller data I/O to/from the card. Includes internal pull-up resistor
to V DD.
AUX1UC
27
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V DD.
AUX2UC
28
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V DD.
CS
8
When CS = 1, the control and signal pins are configured normally. When CS
is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2,
CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high
impedance pull-up mode and won’t pass data to or from the smart card. OFF
output is tri-stated.
CLKSEL
16
Selects CLK and RST operational mode. When CLKSEL is low (default), the
circuit is configured for asynchronous card operation and the sequencer
manages the control of CLK and RST. When CLKSEL is high, the signal
CLK is a buffered copy of STROBE and the signal RST is directly controlled
by RSTIN.
STROBE
25
When CLKSEL = 1, the signal CLK is controlled directly by STROBE.
CLKOUT
32
CLKOUT is the buffered version of the signal on pin XTALIN.
6
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
2 System Controller Interface
•
The CS (chip select) input allows multiple devices to operate in parallel. When CS is high, the system
interface signals operate as described. When CS is taken low, the system interface signals are
latched internally. The pins I/OUC, AUX1UC, and AUX2UC are weakly pulled up and the OFF signal
is put into a high impedance state.
•
The CLKSEL signal selects between synchronous and asynchronous operation. When CLKSEL is
low, asynchronous operation is selected. When CLKSEL is high, synchronous operation is selected.
•
Digital inputs allow direct control of the card interface from the host as follows:
Pin CMDVCC: When set low, starts an activation sequence if a card is present.
Pin 5V/#V: Defines the card voltage.
•
The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to
the host:
Pin RSTIN: controls the card RST signal. When enabled by the sequencer, RST is equal to
RSTIN for both synchronous and asynchronous modes.
Pin I/OUC: data transfer to card I/O contact.
Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/Os which are
connected to the C4 and C8 card connector contacts).
•
Two digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the
card clock frequency from the input clock frequency (crystal or external clock). The division rate is
defined as follows:
CLKDIV2
0
CLKDIV1
0
CLK
⅛ XTAL
0
1
1
1
0
1
XTAL
¼ XTAL
½ XTAL
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN.
When other division rates are used, the 73S8023C circuitry guarantees a duty-cycle in the
range 45% to 55%, conforming to ISO-7816-3 and EMV 4.1 specifications.
•
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about
the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation
sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card
removedl during a card session, or voltage fault, or thermal / over-current fault) that automatically
initiates a deactivation sequence.
•
Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8023C in
its Power Down state. This pin can only be activated outside of a card session.
•
The CLKOUT signal is a buffered output of the signal applied to the XTALIN pin whether it is an
external clock source or it is configured as a crystal oscillator. CLKOUT can be used when using
multiple 73S8023C devices to share a single clock signal.
•
The STROBE input directly drives the smart card CLK signal when operating in synchronous mode.
STROBE is ignored in asynchronous mode.
Rev. 1.5
7
73S8023C Data Sheet
DS_8023C_019
3 Oscillator
The 73S8023C device has an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the
card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin
XTALOUT should be left unconnected. Signal CLKOUT is the buffered version of the signal on XTALIN.
4 DC-DC Converter – Card Power Supply
An internal DC-DC converter provides the card power supply. This converter is able to provide either 3 V
or 5 V card voltage from the power supply applied on the V DD pin. The digital ISO-7816-3 sequencer
controls the converter. Card voltage selection is carried out by the digital input 5V/#V.
The circuit is an inductive step-up converter/regulator. The external components required are 2 filter
capacitors on the power-supply input V DD (next to the LIN pin, 100 nF + 10 µF), an inductor, and an
output filter capacitor on the card power supply V CC . The circuit performs regulation by activating the
step-up operation when V CC is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage
and the input supply V DD is less than the set point for V CC . When V DD is greater than the set point for V CC
(V DD = 3.6 V, V CC =3 V) the circuit operates as a linear regulator.
Depending on the inductor values, the voltage converter can provide current on V CC as high as 100 mA.
The circuit provides over-current protection and limits I CC to 150 mA. When an over-current condition is
sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host
controller a fault on the interrupt output OFF.
Choice of the inductor
The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 2)
and the V DD supply voltage. The inductor value can be optimized to meet a particular configuration
(I CC_MAX ). The inductor should be located on the PCB as close as possible to the LIN pin of the IC.
Choice of the V CC capacitor
Depending on the applications, the requirements in terms of both the V CC minimum voltage and the
transient currents that the interface must provide to the card are different. Table 1 shows the
recommended capacitors for each V CC power supply configuration and applicable specification.
Table 1: Choice of VCC Pin Capacitor
Specification Requirement
Specification
EMV 4.1
ISO-7816-3
NDS
8
Application
Min V CC Voltage
Allowed During
Transient Current
Max Transient
Current Charge
Capacitor
Type
Capacitor
Value
4.6 V
4.5 V
4.65 V
30 nAs
20 nAs
40 nAs
X5R/X7R w/
ESR < 100 mΩ
3.3 µF
1 µF
3.3 µF
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
5 Voltage Supervision
Two voltage supervisors constantly check the presence of the voltages V DD and V CC . A card deactivation
sequence is triggered upon a fault detected by these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. V DD also defines the voltage
range for the interface with the system controller. The V DD Voltage supervisor is also used to initialize the
ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The
voltage threshold of the V DD voltage supervisor is internally set by default to 2.3 V nominal. However, it
may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 17) is
used to connect an external resistor R EXT to ground to raise the V DD fault voltage to another value, V DDF .
The resistor value is defined as follows:
R EXT = 180 kΩ /(V DDF - 2.33)
An alternative (more accurate) method of adjusting the V DD fault voltage is to use a resistive network of
R3 from the pin to supply and R1 from the pin to ground (see Figure 11: 73S8023C – Typical Application
Schematic). In order to set the new threshold voltage, the equivalent resistance must be determined.
This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.649 / V TH ) - 0.6042 where V TH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas:
R3 = 72000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a V DD fault threshold voltage of 2.7 V is desired, solving for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0.377
Solving for R3 gives:
Solving for R1 gives:
R3 = 72000 / 0.377 = 191 kΩ.
R1 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ.
Using standard 1 % resistor values gives R3 = 191 kΩ and R1 = 115 kΩ. These values give an
equivalent resistance of Kx = 0.376, a 0.3% error.
Using 1% external resistors and a parallel resistance of 72 k ohms will result in a +/- 6% tolerance in the
value of VDD Fault. The sources of variation due to integrated circuit process variations and mismatches
include the internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset
(less than +/- 1.7% for part-to-part, processing and environment), the internal resistor value mismatch and
value variations (less than 1.8%), and the external resistor values (1%).
If the 2.3 V default threshold is acceptable, this pin must be left unconnected.
Rev. 1.5
9
73S8023C Data Sheet
DS_8023C_019
6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8023C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from
the host controller).
The host controller invokes the power down state when it is desirable to save power. The signals PRES
and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller
must then set PWRDN low and wait for the internal stabilization time prior to starting any card session
(prior to turning CMDVCC low).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators and
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, OFF can be used as an indication that the circuit has completed its
recovery from power-down state. OFF will go high at the end of the stabilization period. Should
CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be
taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.
Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
PRES
OFF
PWRDN
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
PWRDN has effect when
the cardi s deactivated
Internal RC OSC
~10ms
CMDVCC
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
CMDVCC=0
EMV / ISO deactivation
time ~= 100 uS
Figure 2: Power Down Mode Operation: CS = high
7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
10
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
8 Activation and Deactivation
8.1
Activation Sequence (Synchronous Mode)
The 73S8023C smart card interface IC has an internal ~10 ms delay at power-on reset or on application
of V DD > V DDF . No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to
activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low:
1. CMDVCC is set low.
2. Turn on V CC and I/O (AUX1, AUX2) to reception mode at the end of (t ACT ).
3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t 1 ).
CMDVCC
VCC
IO
RSTIN
RST
STROBE
CLK
tACT
t1
tACT ~= 500µs
t1 > 0.5µs after tACT, RST = RSTIN, CLK = STROBE
Figure 3: Activation Sequence – Synchronous Mode
8.2
Deactivation Sequence (Synchronous Mode)
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V DD fault and card extraction
during the session and are indicated to the system controller by the fall of OFF.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or a fault condition sets OFF low:
1.
2.
3.
4.
RST goes low at time t 1 .
CLK stops low at time t 2 .
I/O goes low at time t 3 . Out of reception mode.
V CC is shut down at time t 4 . After a delay t 5 (discharge of the V CC capacitor), V CC is low.
Rev. 1.5
11
73S8023C Data Sheet
DS_8023C_019
CMDVCC
-- OR --
OFF
VCC
IO
RSTIN
RST
STROBE
CLK
t0 t1 t2 t3
t4
t5
t0 - Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault
t1 - RST falls approx. 0.5us after deactivation begins
t2 - CLK falls approx. 7.5us after RST falls
t3 - IO falls approx 2us after CLK falls
t4 - VCC is shut down
t5 - VCC goes to 0 after discharge of VCC capacitor, approx 100us after deactivation begins
(Note: Host should set STROBE low when CMDVCC is set high, otherwise CLK may be truncated.
CLK truncation may occur if an OFF event is triggered)
Figure 4: Synchronous Deactivation Operation – CKSEL = High
8.3
Activation Sequence (Asynchronous Mode)
The 73S8023C smart card interface IC has an internal 10 ms delay at power-on reset or upon application
of V DD > V DDF or upon exit of Power Down mode. The card interface may only be activated when OFF is
high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered)
must then be set low to activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
1. CMDVCC is set low.
2. Next, the internal V CC control circuit checks the presence of V CC at the end of t 1 . In normal operation,
the voltage V CC to the card becomes valid during t 1 . If V CC does not become valid, then OFF goes
low to report a fault to the system controller, and the power V CC to the card is turned off.
3. Turn I/O (AUX1, AUX2) to reception mode at the end of t 2 .
4. CLK is applied to the card at the end of t 3 .
5. RST is a copy of RSTIN after t 4 . RSTIN may be set high before t 4 , however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
12
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
CMDVCC
VCC
IO
CLK
RSTIN
RST
t1
t3
t2
t4
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 µs, I/O goes to reception state
t3 ≥ 0.5 µs, CLK starts
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low
The following steps list the activation sequence and the timing of the card control signals when the
system controller pulls the CMDVCC low while the RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal V CC control circuit checks the presence of V CC at t 1 . In normal operation, the
voltage V CC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power V CC to the card is turned off.
3. Due to the fall of RSTIN at t 2 , turn I/O (AUX1, AUX2) to reception mode.
4. CLK is applied to the card at the end of t 3 after I/O is in reception mode.
5. RST is to be a copy of RSTIN after t 4 . RSTIN may be set high before t 4 , however the sequencer
won’t set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
RST
t1
t1
t2
t3
t4
t2
t3
t4
= 0.510 ms (timing by 1.5MHz internal Oscillator)
= 1.5µs, I/O goes to reception state
= > 0.5µs, CLK active
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2
Rev. 1.5
13
73S8023C Data Sheet
8.4
DS_8023C_019
Deactivation Sequence (Asynchronous Mode)
Deactivation is initiated either by the system controller by setting CMDVCC high, or automatically in the
event of hardware faults. Hardware faults are over-current, overheating, V DD fault, V CC fault, and card
extraction during the session.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
1.
2.
3.
4.
RST goes low at the end of time t 1 .
CLK stops low at the end of time t 2 .
I/O goes low at the end of time t 3 . Out of reception mode.
V CC is shut down at the end of time t 4 . After a delay t 5 (discharge of the V CC capacitor), V CC is low.
CMDVCC
-- OR -OFF
RST
CLK
I/O
VCC
t1
t2
t3
t4
t5
t1 ≥ 0.5 µs, timing by 1.5 MHz internal Oscillator
t3 ≥ 0.5 µs t4 ≥ 0.5 µs
t2 ≥ 7.5 µs
t5 = depends on VCC filter capacitor.
t1 + t2 + t3 + t4 + t5 ~= 100 µs
Figure 7: Asynchronous Deactivation Sequence
9 OFF and Fault Detection
There are two cases for which the system controller can monitor the OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.
Monitoring Outside a Card Session
In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is
present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No
deactivation is required during this time.
Monitoring During a Card Session
CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same
time that OFF is set low, the sequencer starts the deactivation process.
Figure 8 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and
outside the card session:
14
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
OFF is low by
card extracted
OFF is low by
any fault
PRES
OFF
CMDVCC
VCC
outside card session
within card session
within card
session
Figure 8: Timing Diagram – Management of the Interrupt Line OFF
10 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power-on reset and they are in the high state
when the activation sequencer turns on the I/O reception state. See Section 8 Activation and
Deactivation for more details on when the I/O reception is on.
The state of the I/OUC, AUX1UC, and AUX2UC pins is high after power-on reset. Within a card session
and when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the
input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected,
both I/O lines return to their neutral state.
Figure 9 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals is shown in Figure 10.
In order to be compliant to the NDS specifications, a 27 pF capacitor must be added between pins
I/O (C7) and GND (C5) at the smart card connector.
Rev. 1.5
15
73S8023C Data Sheet
DS_8023C_019
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
No
I/OUC
&
not I/O
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
I/O
yes
yes
Figure 9: I/O and I/OUC State Diagram
IO
IOUC
tIO_HL
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tIO_LH
tIOUC_HL
tIOUC_LH
t IO_HL = 100ns
t IO_LH = 25ns
t I/OUC_HL = 100ns t I/OUC_LH = 25ns
Figure 10: I/O – I/OUC Delays Timing Diagram
16
Rev. 1.5
73S8023C Data Sheet
DS_8023C_019
11 Typical Application Schematic
AUX2UC_to/from_uC
AUX1UC_to.from_uC
See NOTE 6
I/OUC_to/from_uC
STROBE_from_uC
CLKDIV1_from_uC
CLKDIV2_from_uC
See NOTE 3
See note 7
5V/3V_select_from_uC
CLKOUT_to_uC
CLKOUT 32
5V/3V 31
CLKDIV2 30
CLKDIV1 29
AUX2UC 28
AUX1UC 27
I/OUC 26
STROBE 25
VDD
C4
C5
10uF
100nF
VDD
See NOTE 1
External_clock_from uC
VDD
L1
10uH
1
2
3
4
5
6
7
8
See note 2
PWRDN_from_uC
XTALOUT
XTALIN
OFF
GND
73S8023C VDD
RSTIN
CMDVCC
VDDF_ADJ
GND
LIN
VDD
NC
PWRDN
PRES
PRES
CS
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
CS_from_uC
C2
22pF
VDD
See NOTE 1
C9
100nF
I/O
AUX2
AUX1
GND
CLK
RST
VCC
CLKSEL
See NOTE 5
- OR R3
Rext2
Y1
C3
CRYSTAL
22pF
See NOTE 4
R1
Rext1
32QFN
CLKSEL_from_uC
OFF_interrupt_to_uC
NOTES:
RSTIN_from_uC
27pF
27pF
C7
C8
27pF
Card detection
switch is
normally
closed.
CMDVCC_from_uC
C1 Low ESR ( 4.6 or 2.7 V as
selected, L=10 µH
mA
100
125
180
mA
C F on V CC = 1 uF
0.05
0.15
0.25
V/µs
C F on V CC = 1 uF
0.1
0.3
0.5
V/µs
0.47
3.3
4.7
µF
µH
10
Limax
Imax in inductor
V CC = 5 V, I CC = 65 mA,
V DD = 2.7 V
η
Efficiency
V CC = 5 V, I CC = 65 mA,
V DD = 3.3 V
Rev. 1.5
100
400
87
mA
%
19
73S8023C Data Sheet
DS_8023C_019
1011B01 Converter efficiency (VCC 5V)
Converter Efficiency (VCC 5 V)
100
95
90
Efficiency [%]
85
80
75
70
2.7V
3.0V
65
3.3V
60
3.6V
55
50
0
20
40
60
80
100
Icc [mA]
Figure 12: DC – DC Converter efficiency (V CC = 5 V)
Output current on Vcc at 5 V. Input voltage on V DD at 2.7, 3.0, 3.3 and 3.6 volts.
1011B01
Converter
efficiency
(VCC
Converter
Efficiency
(VCC
3 V)3V)
100
95
90
Efficiency [%]
85
80
75
2.7V
70
3.0V
3.3V (Linear)
65
3.6V (Linear)
60
55
50
0
20
40
60
80
100
Icc [mA]
Figure 13: DC – DC Converter Efficiency (V CC = 3 V)
Output current on Vcc at 3 V. Input voltage on V DD at 2.7, 3.0, 3.3 and 3.6 volts.
20
Rev. 1.5
DS_8023C_019
Symbol
73S8023C Data Sheet
Parameter
Condition
Min
Typ
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. I SHORTL , I SHORTH , and V INACT requirements do not pertain to I//OUC, AUX1UC, and AUX2UC.
I OH = 0 1
0.9 V CC
V CC + 0.1
V
I OH = -40 µA
0.75 V CC
V CC + 0.1
V
I OH = 0
0.9 V DD
V DD + 0.1
V
I OH = -40 µA
0.75 V DD
V DD + 0.1
V
0.3
V
1.8
V CC + 0.30
V
Input level, high (I/OUC,
AUX1UC, AUX2UC)
1.8
V DD + 0.30
V
V IL
Input level, low
-0.3
0.8
V
V INACT
Output voltage when outside
of session
I OL = 0
0.1
V
I OL = 1 mA
0.3
V
I LEAK
Input leakage
V IH = V CC
10
µA
V IL = 0, CS = 1
0.65
mA
V IL = 0, CS = 0
5
µA
V IL = 0
2
mA
V OH
Output level, high (I/O, AUX1,
AUX2)
V OH
Output level, high (I/OUC,
AUX1UC, AUX2UC)
V OL
Output level, low
V IH
Input level, high (I/O, AUX1,
AUX2)
V IH
I IL
Input current, low (I/OUC,
AUX1UC, AUX2UC)
Input current, low (I/O, AUX1,
AUX2)
I SHORTL
Short circuit output current
For output low,
shorted to V CC
through 33 Ω
15
mA
I SHORTH
Short circuit output current
For output high,
shorted to ground
through 33 Ω
15
mA
tR, tF
Output rise time, fall times
C L = 80 pF, 10% to
90%. For I/OUC,
AUX1UC, AUX2UC,
C L = 50 pF
100
ns
t IR , t IF
Input rise, fall times
1
µs
R PU
Internal pull-up resistor
14
kΩ
Ipuhiz
Pull-up current, Hi-Z state
5
µA
FD MAX
Maximum data rate
1
MHz
T FDIO
C IN
1
I OL =1 mA
Output stable for
> 200 ns
8
11
For pins IOUC,
AUX1UC, AUX2UC
when CS = 0
Delay, I/O to I/OUC,
I/OUC to I/O
(falling edge to falling edge)
100
Delay, I/O to I/OUC,
I/OUC to I/O
(rising edge to rising edge)
10
Started
ns
Input capacitance
10
pF
NDS applications require a 27 pF capacitor on I/O placed at the smart card connector.
Rev. 1.5
21
73S8023C Data Sheet
Symbol
Parameter
DS_8023C_019
Condition
Min
Typ
Max
Unit
Reset and Clock for card interface, RST, CLK
V OH
Output level, high
I OH = -200 µA
0.9 V CC
V CC
V
V OL
Output level, low
I OL = 200 µA
0
0.2
V
V INACT
Output voltage when outside
of a session
I OL = 0
0.1
V
I OL = 1 mA
0.3
V
I RST_LIM
Output current limit, RST
30
mA
I CLK_LIM
Output current limit, CLK
70
mA
C L = 35 pF for
CLK, 10% to 90%
8
ns
C L = 200 pF for
RST, 10% to 90%
100
ns
CLKSEL = 1, Cap.
load on CLK and
RST is minimal,
else rise, fall times
are a factor
20
ns
55
%
Max
Unit
tR, tF
Output rise time, fall time
Td
Delay time STROBE to CLK,
RSTIN to RST
δ
Duty cycle for CLK
C L = 35 pF,
48% < δ IN < 52%
45
12.5 Digital Signals
Symbol
Parameter
Condition
Min
Typ
Digital I/O Except for OSC I/O
V IL
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
1.8
V DD + 0.3
V
V OL
Output Low Voltage
I OL = 2 mA
0.45
V
V OH
Output High Voltage
I OH = -1 mA
R OUT
Pull-up resistor, OFF
t SL
Time from CS going high to
interface active
50
ns
t DZ
Time from CS going low to
interface inactive, Hi-Z
50
ns
t IS
Set-up time, control signals
to CS rising edge
50
ns
t SI
Hold time, control signals
from CS rising edge
t ID
Set-up time, control signals
to CS fall
t DI
Hold time, control signals
from CS fall
|I IL1 |
Input Leakage Current
22
V DD - 0.45
V
20
kΩ
50
50
GND < V IN < V DD
-5
ns
ns
50
ns
5
μA
Rev. 1.5
DS_8023C_019
Symbol
73S8023C Data Sheet
Parameter
Condition
Min
Typ
Max
Unit
Oscillator (XTALIN) I/O Parameters
V ILXTAL
Input Low Voltage - XTALIN
-0.3
0.3 V DD
V
V IHXTAL
Input High Voltage - XTALIN
0.7 V DD
V DD +0.3
V
I ILXTAL
Input Current - XTALIN
-30
30
μA
f MAX
Max freq. Osc or external clock
27
MHz
δin
External input duty cycle limit
52
%
GND < V IN < V DD
tR/F < 10% fIN,
45% < δ CLK < 55%
48
12.6 DC Characteristics
Symbol
I DD
I DD_PD
Parameter
Supply Current on V DD
Supply Current on V DD in
Power Down mode
Condition
Linear mode, ICC = 0
I/O, AUX1, AUX2 = high
Step up mode, ICC = 0
I/O, AUX1, AUX2 = high
PWRDN = 1,
Start/stop bit = 0
All digital inputs driven
with a true logical 0 or 1
Min
Typ
Max
Unit
4.9
mA
4.7
mA
0.11
2.5
µA
Typ
Max
Unit
12.7 Voltage / Temperature Fault Detection Circuits
Symbol
Parameter
Condition
Min
V DDF
V DD fault – V DD Voltage
supervisor threshold)
No external resistor on
VDDF_ADJ
2.15
2.4
V
V CCF
V CC fault – V CC Voltage
supervisor threshold
V CC = 5 V
4.20
4.6
V
V CC = 3 V
2.5
2.7
V
TF
Die over temperature fault
115
145
°C
I CCF
Card over current fault
100
150
mA
Rev. 1.5
23
73S8023C Data Sheet
DS_8023C_019
13 Mechanical Drawing (32-QFN)
0.85 NOM./ 0.9MAX.
5
0.00 / 0.005
2.5
0.20 REF.
1
2.5
2
3
5
SEATING
PLANE
TOP VIEW
SIDE VIEW
0.35 / 0.45
3.0 / 3.75
CHAMFERED
0.30
0.18 / 0.3
1.5 / 1.875
1
2
3
3.0 / 3.75
0.25
1.5 / 1.875
0.5
0.2 MIN.
0.35 / 0.45
0.5
0.25
BOTTOM VIEW
Figure 14: 32-QFN Mechanical Drawing
24
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
14 Package Pin Designation (32-QFN)
CLKOUT
5V/3V
CLKDIV2
CLKDIV1
AUX2UC
AUX1UC
I/OUC
STROBE
32
31
30
29
28
27
26
25
Use handling procedures necessary for a static sensitive component.
GND
1
24
XTALOUT
LIN
2
23
XTALIN
VDD
3
22
OFF
NC
4
21
GND
PRDWN
5
20
VDD
PRES
6
19
RSTIN
PRES
7
18
CMDVCC
CS
8
17
VDDF_ADJ
13
14
15
16
CLK
RST
VCC
CLKSEL
11
AUX1
12
10
AUX2
GND
9
I/O
TERIDIAN
73S8023C
(Top View)
Figure 15: 32-QFN 73S8023C Pin Out
Rev. 1.5
25
73S8023C Data Sheet
DS_8023C_019
15 Ordering Information
Part Description
Order Number
Packaging Mark
73S8023C-QFN 32-pin Lead-Free QFN
73S8023C-IM/F
73S8023C
73S8023C-QFN 32-pin Lead-Free QFN Tape / Reel
73S8023C-IMR/F
73S8023C
16 Related Documentation
The following 73S8023C documents are available from Teridian Semiconductor Corporation:
73S8023C Data Sheet (this document)
73S8023C QFN Demo Board User’s Guide
17 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the
73S8023C, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: scr.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
26
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
Revision History
Revision
Date
Description
1.0
6/13/2005
First publication.
1.1
7/15/2005
Converted to Teridian format.
1.2
12/5/2007
Add EMV and ISO logo, remove leaded package option, change 32QFN
punched to SAWN package.
1.3
1/17/2008
Changed dimension of bottom exposed pad on 32QFN mechanical package
figure.
1.4
1/8/2009
Added NDS logo to page 1 and assigned document number.
1.5
4/3/2009
Removed all references to VPC as VPC must be tied to VDD.
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com
Rev. 1.5
27
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