78P2352-DB-CMI

78P2352-DB STM1e/E4/OC3 Demo Board DEMO BOARD MANUAL AUGUST 2005 INTRODUCTION FEATURES This manual will explain the design and operation of the 78P2352-DB demo board (Board rev. D2352T8C). The 78P2352 is TERIDIAN’s latest dual channel Line Interface Unit (LIU) for 155Mbit/s SONET/SDH (OC-3 or STM-1e) and 140Mbit/s PDH (E4) applications. • Allows easy evaluation of the 78P2352 • Includes configuration headers and dipswitches for HW control options • Link status LEDs for both channels • Options for using on-board crystal oscillator or external reference clock DESCRIPTION • 17.408MHz and 19.44MHz on-board crystal oscillators allow easy evaluations of PDH and SDN/SONET applications. • 48-pin box interface • SMA connectors for serial (LVPECL) interface • 3.3V power supply The 78P2352-DB demo board is designed to facilitate easy evaluation of the 78P2352 Line Interface Unit (LIU) in the electrical (coaxial) domain. The board can be easily configured into different operating modes with the on board configuration headers and dipswitches. On the line side, all the necessary discrete components are included for transmitting and receiving CMI signal on the 75Ω coaxial line. for parallel PART DESCRIPTION ORDER NUMBER 78P2352-IGT Demo Board 78P2352-DB BNC BNC BNC BNC TRANSFORMERS & PROTECTION DIODES Optics module SMA EXT. CLOCK configuration switch SW1 configuration switch SW2 CMI/ECL MONITOR PARALLEL/SERIAL E4/STM1/STS3 configuration switch S1 _ 78P2352 RCSL TXPD O + FRST LPBK2 LPBK1 CKMODE TXOUT0 TXOUT1 CKSL SMA Connectors: Channel 1 Serial Interface (nibble) ORDERING INFO If needed, all other discrete components can be populated to support the optical line interface. Optics module connector 48-pin Connector: Parallel (nibble) Interface FIGURE 1: D2352T8C board block diagram 1 SMA Connectors: Channel 2 Serial Interface 78P2352-DB Demo Board Manual SW2 REQUIRED EQUIPMENT • TERIDIAN D2352T8C demo board • Power Supply, 3.3V, 1.5Amp • Banana Plug Connection Cable for Power Supply • 75Ω coax cable set. • Test Equipment (Signal Source generator, Jitter Measurement, etc.) Pin 1: Transmitter Power Down - Enabled or Disabled - See TXPD pin description in datasheet Pin 2: Redundant Channel - Enabled or Disabled - Not used in 78P2352 S1 GETTING STARTED Pin 1: FIFO phase initialization - Float (normal operation) - See FRST pin description in datasheet Pin 2: Channel 2 Loopback - Float (remote loopback) - See LPBK2 pin description in datasheet Pin 3: Channel 1 Loopback - Float (remote loopback) - See LPBK1 pin description in datasheet Pin 4: Clock (timing) Mode Select - High (plesiochronous mode) - See CKMODE pin description in datasheet Pin 5: CMI Tx Amplitude Boost - Low (normal) - See TXOUT0 pin description in datasheet Pin 6: CMI Tx Peaking Control - Float (no peaking) - See TXOUT1 pin description in datasheet Pin 7: Reference clock frequency - Low (17.408MHz or 19.44MHz) - See CKSL pin description in datasheet Pin 8: unused 1. Configurations for the headers: a) JP1: Shunt connects to P/S to use SW1 b) JP2: Shunt connects to E/S to use SW1 c) JP3: Shunt connects to GND to use hardware control mode d) JP4: Shunt connects to MON to use SW1 e) JP5: Shunt connects to C/E to use SW1 f) JP6: Connect shunt to E4 to use 19.44M XO for STM-1/STS-3 mode or connect to STM1 to use 17.408M XO for E4 mode g) JP7: Connect shunt to LOC to use on-board crystal oscillators for reference clock or connect to EXT to use external clock source provided at (CKREF) SMA connector 2. Configurations for the dipswitches: Typical settings in Bold SW1 Pin 1: Line Interface Select - CMI or ECL - _ See SEN_CMI pin description in datasheet Pin 2: Receiver Monitor Mode - Enabled or Disabled - See SCK_MON pin description in datasheet Pin 3: System Interface Select - Parallel or Serial - See SDI_PAR pin description in datasheet Pin 4: Rate Select - E4 or SMT1/STS3 - See SDO_E4 pin description in datasheet O + FRST LPBK2 LPBK1 CKMODE TXOUT0 TXOUT1 CKSL N/C Typical S1 settings 3. Apply 3.3V power to the demo board 2 78P2352-DB Demo Board Manual DEMO BOARD DESCRIPTION TRANSMIT SIGNAL PATH CONFIGURING BIT RATE The D2352T8C can be configured for either E4 or STS3/STM1 rates by SW1 (pin 4). The transmitter’s coaxial connectors are connected to the LIU transmitter pins (CMxP, CMxN) through a 1:1CT (center-tapped) transformer. The transformer center tap is tied to Vcc to bias the transmitter drivers. The signal path is differentially terminated with a 75Ω resistor on the LIU side of the transformer. The termination resistor, in combination with the characteristic impedance of the transformer and the line impedance create the required pulse shaping impedance for the LIU’s driver. A corresponding reference clock input is required for operation. The compatible reference clocks for each rate are as follows: Rate Reference Clock E4 17.408MHz, 139.264 MHz STS3 /STM1 19.44MHz, 77.76MHz, 155.52 MHz The user may configure serial or parallel interface by changing SW1 (pin 3), although Serial Plesiochronous mode is recommended to eliminate the need for a synchronous timing relationship between the transmit clock/data and the reference clock. S1 (pin 7) is used to configure the reference clock frequency based on the selected bit rate. CKSL Reference Clock High 139.264 MHz, 155.52 MHz Float 77.76MHz Low 17.408MHz, 19.44MHz When the parallel (system) interface is chosen, the 48-pin box connector U2 can be used to connect other digital control boards. By default the LIU expects transmit data to clock in on the rising clock edge so the transmitter source (i.e framer) should clock out transmit data on the clock’s falling edge. If using this interface, the user must ensure the reference clock is synchronous with the transmit clock/data source. The 78P2352-DB provides on-board 17.408MHz and 19.44MHz crystal oscillators as well as an SMA connector for use of external reference clock sources. Headers JP6 and JP7 allow easy selection of the reference clock source. SMA connectors support the option for a serial (system) interface. Each channel provides four SMA connectors, two for the differential clock (SIxCKP/N) and two for the respective differential data signal (SIxDP/N). These inputs accept LVPECL differential signals, which are AC-coupled and differentially terminated with 100Ω at the LIU. If using any serial timing mode other than Plesiochronous mode, the user must ensure the reference clock is synchronous with the transmit clock/data source. NOTE: If using any system/timing interface other than the recommended Serial Plesiochronous mode, an external reference clock source must be provided at the SMA input labeled CKREF and must be synchronous to the transmit data (and timing) source. LINE INTERFACE The 78P2352-DB is pre-configured and shipped to allow easy evaluation of the CMI encoded, coaxial line interface. Footprints for optics modules, however, are provided for evaluating the optical line interface of the 78P2352. For more information on configuring the D2352T8C board in optical (NRZ) mode, please contact TERIDIAN’s applications support group. 3 78P2352-DB Demo Board Manual RECEIVE SIGNAL PATH Test Point Signal Description The line side (coax) receiver interface has the same architecture as the transmit interface, except the transformer winding’s center tap is left open. The received signal is internally equalized for dispersive cable attenuation and decoded in the CMI to NRZ decoder. PDT1 PDT2 PWR Power plane test points PDT3 SI2CKP/N PDT4 SI2DP/N Channel 2 transmit serial clock / data input PDT5 SO2CKP/N PDT6 SO2DP/N PDT7 SI1CKP/N PDT8 SI1DP/N PDT9 SO1CKP/N PDT10 SO1DP/N PDT13 RXxP/N Receive serial CMI or LVPECL input CMIxP/N Transmit serial CMI data output ECLxP/N Transmit serial (NRZ) LVPECL data output The user may configure serial or parallel interface by changing SW1 (pin 3), although Serial Plesiochronous mode is recommended. If selecting the parallel interface, data to the system (i.e. framer) passes through the 48-pin box connector. The receive data is clocked out at the falling edge of the receive clock. This is the default state of the LIU. SMA connectors support the option for a serial (system) interface. Each channel’s serial interface provides four SMA connectors, two for the differential clock (SOxCKP/N) and two for the respective differential data signal (SOxDP/N). These outputs provide LVPECL differential signals, which are AC-coupled to the system at the SMA connectors. PDT16 PDT14 PDT17 PDT15 PDT17 SUPPLEMENTAL SURGE PROTECTION Channel 2 receive serial clock / data output Channel 1 transmit serial clock / data input Channel 1 receive serial clock / data output STATUS PINS Optional surge protection circuitry is included on the coax line side to ensure proper operation of the device during the presence of differential voltage surges, as called for by ITU-T, Bellcore, and IEC specifications. Protection diode U3 provides additional protection against ESD and power supply transients at the power supply banana jacks. The 78P2352 provides both open drain and CMOS versions for the status pins. On the demo board, resistor population options are available to evaluate different version of chips. The demo boards are populated by open drain chips. Open drain: Consult the application note for more information on supplemental surge protection for electrical interfaces. LOS1: R7 -- 0Ω, R96 -- 300Ω LOOPBACK OPERATION LOL1: R8 -- 0Ω, R98 -- 300Ω S1 (pins 2 and 3) also provides controls for configuring the internal loopback modes. LOL2: R38 -- 0Ω, R99 -- 300Ω LOS2: R39 -- 0Ω, R97 -- 300Ω INTTX1B: R92 – 10KΩ, R42 -- 300Ω When the pin is pulled low, the chip is in the normal mode. INTTX2B: R94 – 10KΩ, R46 -- 300Ω When the pin is pulled high, the receiver uses the transmitter output signal as its input, known as local (analog) loopback. INTRX2B: R95 – 10KΩ, R47 -- 300Ω INTRX1B: R93 – 10KΩ, R43 -- 300Ω CMOS: When the pin is floating, the received signal is looped back to the transmitter, known as remote (digital) loopback. LOS1: R7 -- 300Ω, R96 – DNP LOS2: R39 -- 300Ω, R97 – DNP DIFFERENTIAL TEST POINTS LOL1: R8 -- 300Ω, R98 – DNP The following test points are provided to facilitate test and measurement. LOL2: R38 -- 300Ω, R99 – DNP INTTX1B: R92 – DNP, R42 -- 300Ω INTTX2B: R94 – DNP, R46 -- 300Ω INTRX1B: R93 – DNP, R43 -- 300Ω INTRX2B: R95 – DNP, R47 -- 300Ω 4 78P2352-DB Demo Board Manual DECOUPLING PCB DESIGN DESCRIPTION Two decades of caps are used on the D2352T8C demo board, e.g. a mix of 0.1uF and 0.001uF. Consult the application note for general guidelines. The 78P2352-DB (D2352T8C) demo board is constructed as a four-layer PC board. The top layer has the major components and signal routes. The bottom layer has bypass capacitors and mostly miscellaneous discrete components, as well as additional signal routes. The internal two layers have ground and power supply planes only. The power supply and ground pins of the 78P2352 LIU are connected directly to these planes. ANALOG TRACES All CMI transmitter and receiver differential pair signal routes have a differential impedance of 75Ω to the secondary side of the transformer. The ground layer is directly under the component side of the board, followed by the power plane layer, then the bottom layer. The line-side transmit pair (primary side of transformer), as well as the line side receive pair, is a 75Ω single-ended trace. The coax shield is connected directly to the line-side chassis ground. GROUND TR ANSFOR MER S The ground layer uses a split plane to divide system ground and frame (or chassis) ground. The frame ground plane is on the line side (the primary side of the transformer and the BNCs) and system digital ground is the LIU side (the secondary side of the transformer). The 78P2352-DB (D2352T8C) uses 1:1CT wide band transformers on transmit and receive. The following table lists the recommended transformers from different vendors that can be fitted on the 78P2352-DB demo board: The chassis plane typically will be connected to the equipment chassis, which connects to the facilities Earth ground structure. The coax shield also typically connects to the chassis at equipment or patch panel bulkhead, providing a solid common bonding tie-point to the facility’s grounding structure, as specified in the ITU-T recommendation K.27. Part Number Halo TG04-TDK1N1 TAMURA TTC-300 See application note for transformer specifications and other recommended vendors and part numbers. COPPER VOID FRAME GROUND Dual core transformers Manufacturer SAMPLE TEST RESULTS COMPONENT GROUND Refer to Appendix A for sample test results. SCHEMATICS Refer to Appendix B for schematics and bill of material. TX- COAX LIU TEST SETUP Refer to Appendix C for recommended test setups. RX-COAX VCC PLANE As with the digital ground plane, the power plane layer should only extends to the LIU side of the transformer. The outer edge of the power plane is kept 10 mils short of the ground plane’s outer edge to avoid plane-to-plane current fringing at the plane edges. 5 78P2352-DB Demo Board Manual Appendix A: Sample Test Results MASK MEASURMENTS The following is a typical mask measurement for an STM-1e (CMI 0) pulse. Figure A1: STM-1e pulse mask (CMI 0) The following is a typical mask measurement for an STM-1e (CMI 1) pulse. Figure A2: STM-1e pulse mask (CMI 1) 6 78P2352-DB Demo Board Manual JITTER TOLERANCE: The following are typical STM-1 jitter tolerance measurements when tested in remote loopback (see Appendix C2). Figure A3: STM-1e jitter tolerance test result JITTER TRANSFER FUNCTION: The following scope pics show the jitter transfer performance of the 78P2352. when tested in remote loopback (see Appendix C2). Figure A4: STM-1e jitter transfer test result 7 Size A Date: 8 CMIO2P CMIO2N CMIO1P CMIO1N TX2CKN TX2CKP ECLO1P ECLO1N ECLO2P ECLO2N TX1CKP TX1CKN ECLI2P ECLI2N CMIO2P CMIO2N CMIO1P CMIO1N TX2CKN TX2CKP ECLO1P ECLO1N ECLO2P ECLO2N TX1CKP TX1CKN ECLI2P ECLI2N ECLI1P ECLI1N CMII2P CMII2N CMII2P CMII2N ECLI1P ECLI1N CMII1P CMII1N Front End CMII1P CMII1N Monday, April 26, 2004 RCSL CKMODE SPSL TXPD SO2CKP SO2CKN SO2DP SO2DN SI2CKP SI2CKN SI2DP SI2DN PTO2CK PO2CK PO23D PO22D PO21D PO20D PTO1CK PO1CK PO13D PO12D PO11D PO10D PI2CK PI20D PI21D PI22D PI23D PI13D PI12D PI11D PI10D PI1CK CKREFP PORB SDI SEN SCK SDO SI1DN SI1DP SI1CKN SI1CKP SO1DN SO1DP SO1CKP SO1CKN LOS1 LOS2 LPBK1 LPBK2 RCSL CKMODE SPSL TXPD SO2CKP SO2CKN SO2DP SO2DN SI2CKP SI2CKN SI2DP SI2DN PTO2CK PO2CK PO23D PO22D PO21D PO20D PTO1CK PO1CK PO13D PO12D PO11D PO10D PI2CK PI20D PI21D PI22D PI23D PI13D PI12D PI11D PI10D PI1CK CKREFP PORB SDI SEN SCK SDO SI1DN SI1DP SI1CKN SI1CKP SO1DN SO1DP SO1CKP SO1CKN LOS1 LOS2 LPBK1 LPBK2 78P2352-DB Demo Board Manual Appendix B: Schematics & Bill of Material Digital Interface Digital Side 78P2352 LIU Front End TDK Semiconductor Corp. 6440 Oak Canyon Irvine, CA 92618 714-508-8800 Title 78P2352 Customer Demo Board Document Number D2352T8C Rev 1 Sheet 1 of 4 78P2352-DB Demo Board Manual PDT13 PDT14 1 3 RSEL3 3 0 CMII1N RSEL4 2 R31 VCC GND O/P 19.44MHz-20ppm E4 3JP6 2 1 PDT17 OSC2 C18 C19 C20 C21 C22 C23 1 C17 1 C16 1 3 C24 2 VCC 2 2 0.1uF 0.1uF 2 2 2 2 2 2 2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2 C87 2 1 1 VCC C86 2 0 2 R38 R39 1 D4 INTRX@B VCC 17.408MHz-20ppm 10k 1 0 4 1 O/P 1 VCC GND 1 ENA 1 2 LOL2 LOS2 1 R41 2 R40 1 1 10k TXPD RCSL 2 1 3 4 SW2 10k R23 R24 45 45 R26 R27 45 45 R28 R29 45 45 R30 45 R32 45 R36 1 2 0 1 2 0 SO1CKN SO1CKP 1 2 RED LED D3 SI1DN SI1DP C3 C4 C5 C6 C7 C8 1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF C9 PO21D PO20D PO10D PO11D C10 0.01uF PO12D PO13D PTO1CK 2 0 R34 1 C11 C12 2 0 2 0 C13 LOS1 LOS2 LPBK1 LPBK2 RCSL CKMODE SPSL TXPD PI13D PI12D PI11D PI10D PI1CK LOS1 LOS2 LOL1 LOL2 RED LED 2 C14 C15 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF LOS1 LOS2 LPBK1 LPBK2 RCSL CKMODE SPSL TXPD PO1CK VCC R96 R97 R98 R99 300 300 300 300 TDK Semiconductor 6440 Oak Canyon Irvine, CA 92618 714-508-8800 Title 78P2352 Customer Demo Board Size B Date: 9 C2 PO23D PO22D 2 45 45 VCC 1R47 PO2CK 1 R21 R22 PTO2CK 1 45 1R43 1R46 CMOS: LOS1: R7 - 300, R96 - DNP LOS2: R39 - 300, R97 - DNP LOL1: R8 - 300, R98 - DNP LOL2: R38 - 300, R99 - DNP INTTX1B: R92 - DNP, R42 - 300 INTTX2B: R94 - DNP, R46 - 300 INTRX1B: R93 - DNP, R43 - 300 INTRX2B: R95 - DNP, R47 - 300 2 R20 1 0 1 45 SI1CKN SI1CKP SW-2 2 2 0 SO1DN SO1DP INTTX@B TXOUT1 TXOUT2 CKMODE LPBK1 LPBK2 VCC 1 R91 PDT18 VCC 1 1 ECLI1N 1 SONET ECLI1P R37 1 2 R18 R35 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 100 3 0 R16 1 R33 VCC 4 VCC 1 ENA 2 2 GND 2 1 1 129 2 2 1 OSC1 ECLO1P ECLO1N 0 1 0 R90 10k TX1CKP 1 TX1CKN 2 VCC CMIO1P CMIO1N 1 0 CMII1P PDT15 TSC78P2352-exposed pad 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2 D7 PI2CK PI20D PI21D PI22D PI23D 1 1 2 1 2 1 2 1 2 3 PDT16 2 U1 PI22D PI23D PTO2CK GND VCC PO2CK GND VCC PO23D PO22D GND VCC PO21D PO20D GND VCC VCC GND PO10D PO11D VCC GND PO12D PO13D VCC GND PO1CK VCC GND PTO1CK PI13D PI12D 0 D6 1 300 2 RED LED 2 300 1 2 D8 RED LED 2 2 LOC ECL2N ECL2P VCC TX2CKN TX2CKP GND CMI2N CMI2P VCC RX2N RX2P GND VCC CKREFN CKREFP GND GND VTOP VTON VCC GND RX1P RX1N VCC CMI1P CMI1N GND TX1CKP TX1CKN VCC ECL1P ECL1N R17 INTRX@B 2 1R42 2 1 RSEL1 JP7 1 VCC R13 0 2 2 300 1 2 RED LED 2 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 RSEL2 EXT 2 INTTX@B 1 300 RED LED 2 1 1k 2 1k 1 0 0 3 1 1 D5 2 2 2 0 3 SIP3 JP3 R15 CMIO2N CMIO2P 0 10k 2 INTRX!B 1 R14 TX2CKN TX2CKP 2 R19 10k SO2CKP SO2CKN INTRX!B R12 ECLO2N ECLO2P 2 10k 1 100 R95 10k 2 R5 1k 2 1k R94 10k 1 R11 2 CMII2N R93 10k 2 1 1 ECLI2N CMII2P R92 VCC 1 R10 2 D1 SO2DP SO2DN R9 2 ECLI2P RED LED 2 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 1 2 1 R3 VCC VCC 49.9 C1 0.1uF VCC 1 D2 SPSL 1 SER_SEN 2 LIU_SEN 3 CMI SW1 R87 2 1 RED LED INTTX!B 1 SMA_TOP 1 2 1 5 3 1 2 3 4 1 4 8 7 6 5 1 R7 0 2 R8 0 300 300 300 300 2 SW DIP-4 J1 LOS1 LOL1 1 1 JP5 1 SER_SCK 2 LIU_SCK 3 MON 300 DIP-8 TRI STATE 1 JP4 HEADER10 2 2 2 4 6 8 10 1 1 JP8 SI2DP SI2DN PORB 1 SER_SDO 2 LIU_SDO 3 E4 VCC R78 10 2 1 3 5 7 9 0 INTTX!B 3 2 1 VCC LIU_SDI LIU_SDO LIU_SCK LIU_SEN R2 SCK_MON SEN_CMI SDI_PAR SDO_E4 VCC GND SI2CKP SI2CKN INTTX1B SI2DP SI2DN VCC GND PORB GND CKSL LOS1 LOL1 FRST SPSL NC2 NC1 VCC GND SO2CKP SO2CKN INTRX1B SO2DP SO2DN PI2CK PI20D PI21D 2 0 33 Open drain: LOS1: R7 - 0, R96 - 300 LOS2: R39 - 0, R97 - 300 LOL1: R8 - 0, R98 - 300 LOL2: R38 - 0, R99 - 300 INTTX1B: R92 - 10K, R42 INTTX2B: R94 - 10K, R46 INTRX1B: R93 - 10K, R43 INTRX2B: R95 - 10K, R47 - 9 2 JP2 2 1SER_SDI 2LIU_SDI 3PAR Tristate 2 JP1 S1 8 7 6 5 4 3 2 1 1 R6 1 R1 CKSL TXOUT1 TXOUT2 CKMODE LPBK1 LPBK2 FRST CKREFP SCK SEN SDO SDI SI2CKP SI2CKN 2 0 2 R4 1 TXOUT1 TXOUT0 NC NC VCC GND SI1CKP SI1CKN INTTX2B SI1DP SI1DN VCC GND TXPD CKMODE RCSL LPBK1 LPBK2 LOS2 LOL2 VCC GND VCC GND SO1CKP SO1CKN INTRX2B SO1DP SO1DN PI1CK PI10D PI11D 1 CKREFP Document Number D2352T8C Monday, September 27, 2004 Rev 1 Sheet 2 of 4 1 3 4 5 2 3 4 5 5 4 2 1 4 3 2 5 4 3 2 5 4 SMA_top 3 2 C37 1 J12 1 0.1uF SO1DP 4 5 3 2 2 2 4 5 2 1 4 5 J14 1 PDT10 J17 C39 1 SO1DN 2 J16 1 SMA_top 0.1uF SMA_top 4 5 SMA_top 0.1uF TP SMA_top 3 2 3 2 1 SO1CKN J15 SMA_top C35 2 1 0.1uF J10 1 5 C40 SO2DN J13 2 1 0.1uF SO2DN 1 1 1 2 0.1uF TP SMA_top PDT6 TP C33 1 1 SO2DP R86 2 C38 SMA_top 0.1uF 2 1 0.1uF J8 1 PDT9 4 5 1 2 130 SO1CKP SMA_top 3 2 SO2CKN J11 2 1 C36 SO2DP 82 2 4 3 2 2 1 0.1uF SO2CKN R82 82 130 PDT5 TP R81 R85 C34 SMA_top 3 1 2 3 2 SMA_top 130 SO2CKP 1 J6 1 C31 VCC R84 SO2CKP 2 0.1uF 5 4 3 TP 2 130 J9 5 0.1uF 1 82 2 2 1 1 R80 82 R83 U2 SMA_top 2 PI10D RCSL CKMODE SPSL R79 SMA_top PDT8 SI1DN 4 5 PI11D PI1CK J4 1 C29 1 SI1DP 2 1 3 2 PTO1CK PI12D 1 VCC J7 R50 R51 R52 R53 5 PO1CK PI13D SI2DN 2 PO11D PO13D C32 2 PO20D PO12D 2 0.1uF Note: Populate 0-ohm resistors on C29,C30,C31,C32 when connecting to the optical board. 2 1 0.1uF TP 2 PO2CK PO22D TXPD PO21D PO10D C27 SMA_top PDT4 1 PTO2CK PO23D C30 1 SI2DP 1 PI21D PI23D SMA_top 0.1uF 1 SI1CKN 4 M2 LPBK1 PI2CK LPBK2 PI20D PI22D R44 100 J2 1 R54 R55 R56 R57 M1 SDI SEN LOS1 LOS2 PORB TP 2 AMP-48-M-Connector A16 B16 C16 C15 B15 A15 A14 B14 C14 C13 B13 A13 A12 B12 C12 C11 B11 A11 A10 B10 C10 C9 B9 A9 A8 B8 C8 C7 B7 A7 A6 B6 C6 C5 B5 A5 A4 B4 C4 C3 B3 A3 A2 B2 C2 C1 B1 A1 SCK SDO J5 2 1 0.1uF CKREFP SMA_top PDT7 2 1 3 C28 2 1 0.1uF SI2CKN C25 1 SI1CKP 5 R45 100 TP 2 VCC J3 2 1 PDT3 2 3 C26 1 SI2CKP 4 78P2352-DB Demo Board Manual PS-Diode PDT2 TP TP 1 PDT1 1 C50 2 C49 1 C48 1 C47 1 C46 1 C45 1 1 1 C44 2 2 2 2 2 2 2 1 VCC VCC C62 C63 1 C61 1 C60 1 C59 1 C58 1 C57 C64 All decoupling capacitors should be placed on the bottom of the board right under the chip. No two caps can be tied together through the same connection 2 2 2 0.001uF0.001uF0.001uF0.001uF0.001uF0.001uF0.001uF0.001uF0.001uF0.001uF 2 Green LED C56 2 4.7uF C55 1 1 D9 2 0.01uF C54 C43 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2 1 0.01uF C53 300 2 2 2 4.7uF C52 2 C51 1 1 1 BANA-Red J19 R58 1 C42 1 1 VCC J18 C41 2 VCC 2 3 4 1 I/O1 I/O2 GNDVCC 2 1 U3 2 1 1 1 170 170 170 170 1 1 TP2 GND 2 1 TP1 GND 2 G6 1 G5 2 G4 1 G3 2 G2 1 170 170 170 170 G1 BANA-Black TDK Semiconductor Corp. 6440 Oak Canyon Irvine, CA 92618 714-508-8800 Title 78P2352 Customer Demo Board Size B Date: 10 Document Number D2352T8C Monday, April 26, 2004 Rev 1 Sheet 3 of 4 0.1uF 0.1uF 1 L1 3.3uH C67 C68 10uF 10uF C69 0.1uF 1 1 1 0 C66 2 L2 3.3uH VCC C70 R60 R61 R62 R63 170 170 170 170 0.1uF 2 0.1uF 2 1 11 C65 CMIO2N 2 3 6 C71 75 2 10 VEERX RD RD M2 SD VCCRX VCCTX TD M1 TD VEETX 7 D11 VCC R101 HFBR-5805B 1 2 3 4 5 6 7 8 9 16 9 1 1 8 FTCVR1 2 DNP 1 15 2 2 R59 2 21 C88 0 1 3 BAV99 12 BAV99 5 4 1 CMIO2P Transformer Dual CT T1 3 14 2 D10 3 BNC1 BNC_RA 11 R100 VCC 10 78P2352-DB Demo Board Manual 1 ECLO2P R65 ECLO2N R67 J21 1 3 D14 2 3 2 3 5 4 SMA-top BNC3 BNC_RA R104 BAV99 2 3 2 170 R71 1 1 CMII1P 0 TP C75 2 TX1CKP 0.1uF R72 ECLO1N 2 ECLI1N TX1CKN PDT12 1 SMA-top 4 R70 1 R105 D15 3 BAV99 2 0.1uF J23 1 170 3 2 5 4 DNP 4 75 TX2CKP C74 1 SMA-top 5 2 0 C90 21 12 1 2 0.1uF J22 1 CMII1N TP C73 1 TX2CKN 0.1uF 2 2 3 5 4 2 3 CMII2N 0 2 PDT11 SMA-top 2 D13 C72 1 1 170 2 R103 BAV99 J20 1 170 75 2 0 DNP R68 1 1 1 R66 5 21 12 C89 5 4 1 CMII2P 1 100 ECLI2N 2 R102 BAV99 2 D12 3 2 ECLI2P 3 BNC2 BNC_RA 100 C82 R107 75 C77 0.1uF C78 C79 10uF 10uF 2 C80 L4 1 3.3uH 1 2 3.3uH 0.1uF CMIO1P 0.1uF C81 170 170 170 R75 R76 R64 R69 0.1uF 2 1 2 3 4 5 6 7 8 9 0.1uF L3 1 1 C76 170 2 T2 Transformer Dual CT D17 0 R73 2 21 12 BAV99 1 11 ECLO1P VCC VCC 1 10 R74 CMIO1N 2 7 DNP 6 C91 R106 1 16 9 2 1 8 VCC 1 15 2 14 2 3 5 1 4 3 BAV99 2 3 BNC4 BNC_RA D16 1 3 ECLI1P FTCVR2 VEERX RD RD SD VCCRX VCCTX TD M1 TD VEETX HFBR-5805B VCC M2 R100-R107 are intended for improve RL. Values could be vary on different boards. FRGND TDK Semiconductor Corp. C84 1 1 C83 6440 Oak Canyon Irvine, CA 92618 714-508-8800 Title 78P2352 Customer Demo Board C85 2 0.001uF 0.001uF 0.001uF 2 2 1 Connect frame to digital ground if needed The Frame GND and digital ground should be totally isolated and ONLY the transformers should act as a bridge between the both grounds 10 0 TP5 TP6 11 TP3 TP4 Size B Date: 11 Document Number D2352T8C Monday, April 26, 2004 Rev 1 Sheet 4 of 4 78P2352-DB Demo Board Manual BILL OF MATERIAL Item Quantity Reference Part PCB Footprint Part Number BNC_RT A24611-ND/413558-1 Vendor DIGIKEY AMP 1 4 BNC1, BNC2, BNC3, BNC4 BNC_RA 2 53 C1-C6, C16-C50, C65, C66, C69, C70, C71, C76, C77, C80, C81, C82, C86, C87 CAP., 0.1uF, 16V C_0603 PCC2277CT-ND ECJ-1VB1E104K C1608X7R1E104k DIGIKEY Panasonic TDK 3 6 C7, C8, C9, C10, C52, C53 CAP, 0.01uF, 50V C_0603 399-1091-1-ND C0603C103K5RACTU C0603X5R0J103k DIGIKEY Kemet TDK 4 18 C11, C12, C13, C14, C15, C55, C56, C57, C58, C59, C60, C61, C62, C63, C64, C83, C84, C85 PCC1772CT-ND ECJ-1VB1H102K C1608X7R1H102k DIGIKEY Panasonic TDK 5 2 C51, C54 CAP, 4.7uF, 10V sacap 6 4 C67, C68, C78, C79 10uF 7 8 D1, D2, D3, D4, D5, D6, D7, D8 RED LED 8 1 D9 Green LED C_0805 ledsmd 0805 ledsmd 0805 9 8 D10-D17 BAV99 SOT-23 DIGIKEY Kemet N/A DIGIKEY Chicago Miniature Lamp DIGIKEY Chicago Miniature Lamp DIGIKEY Infineon Technologies 10 6 G1, G2, G3, G4, G5, G6 MTHOLE MTHOLE 399-1587-1-ND T491A475K016AS Not installed L62411CT-ND CMD17-21SRC L62505CT-ND CMD17-21VG BAV99INCT-ND BAV99E6327 1809k-ND H704-ND 11 7 JP1, JP2, JP3, JP4, JP5, JP6, JP7 SIP3 SIP\3P 12 1 J1 SMA_Top SMA_Top S1011-03-ND PZC03SAAN LTI-SASF54GT DIGIKEY Sullins Electronics Corp Lighthorse Technologies 13 16 J2,J3,J4,J5,J6,J7,J8,J9,J10,J11,J12,J13,J14, J15,J16,J17,J20,J21,J22,J23 SMA_Edge SMA_Edge J502-ND 142-0701-801 DIGIKEY Jonson Components 14 1 J18 BANA-Red BAN 15 1 J19 BANA-Black BAN 16BJ381 16BJ381 16BJ382 16BJ382 Mouser DGS Pro-Audio Mouser DGS Pro-Audio 16 16 PDT1,PDT2,PDT3,PDT4,PDT5,PDT6,PDT7,PDT8, PDT9,PDT10,PDT11,PDT12, PDT13,PDT14,PDT15,PDT16, PDT17,PDT18 TP sip\2p S1011-02-ND PZC02SAAN DIGIKEY Sullins Electronics Corp CAP, 0.001uF, 10V C_0603 12 DIGIKEY 78P2352-DB Demo Board Manual Item Quantity Part PCB Footprint RES, 0, 5% RSEL RES, 0, 5% R_0603 Reference RSEL1,RSEL2, RSEL3,RSEL4 R1,R2,R4,R7,R8,R13,R14,R15,R16,R17,R33, R34,R35,R36,R37,R38,R39 17 4 18 17 19 8 R3,R5,R90-95 RES, 10k, 5% R_0603 20 1 R6 RES, 33, 5% R_0603 21 10 R42,R43,R46,R47,R58,R78, R96-R99 RES, 300, 5% R_0603 22 4 R9,R10,R11,R12 RES, 1k, 1% R_0603 23 12 R18,R20,R21,R22,R23,R24,R26,R27,R28,R29,R30,R32 RES, 43, 5% R_0603 24 6 R19,R31,R44,R45, R65,R74 RES, 100, 1% R_0603 25 2 R41,R40 RES, 10k, 5% R_0805 26 16 R50,R51,R52,R53,R54,R55,R56,R57,R60,R61,R62,R63, R64,R67,R68,R69,R71,R72,R75,R76 RES, 169, 1% R_0603 27 4 R59,R66,R70,R73 RES, 75, 1% R_0603 28 4 R83,R84,R85,R86 RES, 130, 1% R_0603 29 4 R79,R80,R81,R82 RES, 82, 1% R_0603 30 1 R87 RES, 49.9, 1% R_0603 31 1 SW1 SW DIP-4 DIP8 32 1 SW2 SW-2 DIP4 33 1 S1 34 2 T1,T2 DIP-8 TRI STATE TG04-TDK1N1 13 DIP8_TRIS Dual CT Part Number Vendor P0.0GCT-ND ERJ-3GEY0R00V P0.0GCT-ND ERJ-3GEY0R00V P10KGCT-ND ERJ-3GEYJ103V P33GCT-ND ERJ-3GEYJ330V P300GCT-ND ERJ-3GEYJ301V P1.00KHCT-ND ERJ-EEKF1001V P43GCT-ND ERJ-3GEYJ430V P100HCT-ND ERJ-3EKF1000V P10KACT-ND ERJ-6GEYJ103V DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic DIGIKEY Panasonic P169HCT-ND ERJ-3EKF1690V DIGIKEY Panasonic P75.0HCT-ND ERJ-3EKF75R0V P130HCT-ND ERJ-3EKF1300V DIGIKEY Panasonic DIGIKEY Panasonic 311-82.0HCT-ND 9C06031A82R0FKHFT DIGIKEY YAGEO P49.9HCT-ND ERJ-3EKF49R9V GH1004-ND 76SB04S GH1002-ND 76SB02S 138991 ETA-108E TG04-TDK1N1 DIGIKEY Panasonic DIGIKEY Grayhill, Inc. DIGIKEY Grayhill, Inc Jameco ECE HALO 78P2352-DB Demo Board Manual 35 36 37 1 1 1 U1 OSC1 OSC2 78P2352 19.44MHz 17.408MHz PCB Footprint TQFP128 SO4 SO4 38 1 TP1/TP2 Ground strip TP-025SQ 39 40 1 U3 1 U2 Item Quantity Reference Part DIODE SOT-143 AMP-48 AMP-48R Female Connector 14 Part Number 78P2352-IGT ASV-19.44MHz-J ASV-17.408MHz-J C2118B-100-ND/ C2118 SR3.3 650893-5-ND 650893-5 Vendor TERIDIAN Semiconductor Abracon Corporation Abracon Corporation Digikey General cable Semtech DIGIKEY AMP 78P2352-DB Demo Board Manual Appendix C Test Measurement Setups Transmit Pulse Mask Coax STM1e / E4 CMI Signal Source RX 78P2352-DB DUT SCOPE COAX 3' TX AMT 75 PROBE Figure C1. Notes: ƒ ƒ ƒ Signal source (i.e. Test Equipment) transmits CMI coded data to the demo board. The demo board is configured in remote loopback mode. A 50Ω to 75Ω adaptor (i.e. Tektronix AMT 75) is needed for 50Ω Scopes. Jitter Tolerance & Transfer TX COAX Test Equipment RX RX 78P2352-DB DUT COAX TX Figure C2. Notes: ƒ ƒ ƒ Test equipment transmits CMI coded data to the demo board. The demo board is configured in remote loopback mode. Run the Receive Jitter Tolerance and/or Jitter Transfer Function (JTF) tests on the Test Equipment. 15 78P2352-DB Demo Board Manual Intrinsic (transmit) Jitter TX RX Test Equipment RX 78P2352-DB DUT COAX TX STM1/E4 NRZ Signal Source, No jitter Figure C3. Notes: ƒ ƒ ƒ NRZ signal generator transmits data to the demo board via SMA LVPECL inputs. The demo board is in thru-mode (no loopbacks). Input signal should be free of jitter. This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com 08/05 – rev 1.1 © 2005 TERIDIAN Semiconductor Corporation 16