DS1077L
3V EconOscillator/Divider
www.maxim-ic.com
FEATURES
§
§
§
§
§
§
§
§
§
§
§
Processor-controlled or stand-alone solidstate oscillator
Frequency changes on the fly
Dual, low-jitter, synchronous fixedfrequency outputs
2-wire serial interface
Frequency outputs 4.87kHz to 66.666MHz
±1.25% variation over temperature and
voltage
±0.5% initial tolerance
Nonvolatile frequency settings
Single 2.7V to 3.6V supply
No external components
Power-down mode
Synchronous output gating
STANDARD FREQUENCY OPTION
Note: x denotes package option
DS1077Lx-40
40.000MHz to 4.87kHz
DS1077Lx-50
50.000MHz to 6.09kHz
DS1077Lx-60
60.000MHz to 7.32kHz
DS1077Lx-66
66.666MHz to 8.13kHz
Contact the factory for the availability of
additional frequencies.
PIN ASSIGNMENTS
OUT1
1
8
SCL
OUT0
2
7
SDA
VCC
3
6
CTRL1
GND
4
5
CTRL0
150mil SO
118mil µSOP
PIN DESCRIPTIONS
OUT1
OUT0
VCC
GND
CTRL1
CTRL0
SDA
SCL
- Main Oscillator Output
- Reference Output
- Power-Supply Voltage
- Ground
- Control Pin for OUT1
- Control Pin for OUT0
- 2-Wire Serial Data
Input/Output
- 2-Wire Serial Clock
ORDERING INFORMATION
Note: XXX denotes frequency option
DS1077LZ-XXX 8-pin 150mil SO
DS1077LU-XXX 8-pin 118mil µSOP
DESCRIPTION
The DS1077L is a dual-output, programmable, fixed-frequency oscillator requiring no external
components for operation. The DS1077L can be used as a processor-controlled frequency synthesizer or
as a stand-alone oscillator. The two synchronous output operating frequencies are user-adjustable in
submultiples of the master frequency through the use of two on-chip programmable prescalers and
dividers. The specific output frequencies chosen are stored in nonvolatile (EEPROM) memory. The
DS1077L defaults to these values upon power-up.
The DS1077L features a 2-wire serial interface that allows in-circuit on-the-fly programming of the
programmable prescalers (P0 & P1) and divider (N) with the desired values being stored in nonvolatile
(EEPROM) memory. Design changes can be accommodated in-circuit, on-the-fly by simply programming
different values into the device (or reprogramming previously programmed devices). Alternatively, for
fixed-frequency applications previously programmed devices can be used and no connection to the serial
interface is required. Preprogrammed devices can be ordered in customer-requested frequencies.
The DS1077L is available in SO or µSOP packages, allowing the generation of a clock signal easily,
economically, and using minimal board area. Chip-scale packaging is also available on request.
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011006
DS1077L
BLOCK DIAGRAM DS1077L Figure 1
CONTROL
LOGIC
(TABLE 1)
SEL0
EN0
PDN 0
INTERNAL
OSCILLATOR
Enable
Select
DIV1
MCLK
Power-Down
0M1
0M0
1M1
CTRL0
P0 PRESCALER
(M DIVIDER)
MUX
OUT0
1M0
EN0
SEL0
PDN0
0M1
0M0
DIV1
PDN1
CONTROL
REGISTERS
PROGRAMMABLE
“N” DIVIDER
P1 PRESCALER
(M DIVIDER)
2-WIRE
INTERFACE
Power-Down
1M1
1M0
PDN1
SDA
Enable
CONTROL
LOGIC
(TABLE 2)
SCL
2 of 21
OUT1
CTRL1
DS1077L
OVERVIEW
A block diagram of the DS1077L is shown in Figure 1. The DS1077L consists of four major components:
1) internal master oscillator, 2) prescalers, 3) programmable divider, and 4) control registers.
The internal oscillator is factory trimmed to provide a master frequency (master clk) that can be routed
directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be
routed through an additional divider (N).
The prescaler (P0) divides the master clock by 1, 2, 4, or 8 to be routed directly to the OUT0 pin.
The prescaler (P1) divides the master clock by 1, 2, 4, or 8 that can be routed to the OUT1 pin or to the
divider (N) input, which is then routed to the OUT1 pin.
The programmable divider (N) divides the prescaler output (P1) by any number selected between 2 and
1025 to provide the main output (OUT1) or it can be bypassed altogether by use of the DIV1 register bit.
The value of N is stored in the N register.
The control registers are user-programmable through a 2-wire serial interface to determine operating
frequency (values of P0, P1, and N) and modes of operation. The register values are stored in EEPROM
and, therefore, only need to be programmed to alter frequencies and operating modes.
PIN DESCRIPTIONS
OUTPUT 1 (OUT1) – This pin is the main oscillator output; its frequency is determined by the control
register settings for the prescaler P1 (mode bits 1M1 and 1M0) and divider N (DIV WORD).
OUTPUT 0 (OUT0) – A reference output, OUT0, is taken from the output of the reference-select MUX.
Its frequency is determined by the control register settings for CTRL0 and values of prescaler P0 (mode
bits 0M1 and 0M0). (See Table 1.)
CONTROL PIN 0 (CTRL0) – A multifunctional input pin that can be selected as a MUX select, output
enable, and/or a power-down. The user-programmable control register values EN0, SEL0, and PDN0
determine its function. (See Table 1.)
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DS1077L
TABLE 1
EN0
(BIT)
SEL0
(BIT)
PDN0
(BIT)
0
0
0
CTRL0
(PIN)
1
0
OUT0
CTRL0
(PIN)
FUNCTION
Hi-Z
(OUT1 and OUT2) Power-Down*
Hi-Z
DEVICE
MODE
Power-Down
Active
Master Clk/M
MUX Select
Active
Master Clk
Hi-Z
1
0
0
Output Enable
Active
Master Clk
Hi-Z
1
1
0
Output Enable
Active**
Master Clk/M
Hi-Z
1
Power-Down
(OUT1 and OUT2) Power-Down
X
0
1
0
Master Clk
Active
1
Hi-Z
Power-Down
X
1
1
Power-Down
0
Master Clk/M
Active
*This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
**Default Condition
0
1
0
1
0
1
0
1
0
CONTROL PIN 1 (CTRL1) – A multifunctional input pin that can be selected as an output enable
and/or a power-down. Its function is determined by the user-programmable control register value of
PDN1. (See Table 2.)
TABLE 2
PDN1
(BIT)
CTRL1
(PIN)
CTRL1
FUNCTION
OUT 1
DEVICE MODE
0
0
Output Enable
Out Clk
Active*
0
1
Output Enable
Hi-Z
Active*
1
0
Power-Down
Out Clk
Active
1
1
Power-Down
Hi-Z
(OUT1 and OUT2)
Power-Down
*Default Condition
NOTE:
Both CTRL0 and CTRL1 can be configured as power-downs, they are internally “OR” connected so that
either of the control pins may be used to provide a power-down function for the whole device, subject to
appropriate settings of the PDN0 and PDN1 register bits. (See Table 3.)
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DS1077L
TABLE 3
PDN0
PDN1
SHUTDOWN CONTROL
(BIT)
(BIT)
0
0
None*
0
1
CTRL1
1
0
CTRL0
1
1
CTRL0 or CTRL1
*CTRL0 performs a power-down if SEL0 and EN0 are both 0. (See Table 1.)
Serial Data Input/Output (SDA) – Input/output pin for the 2-wire serial interface used for data transfer.
Serial Clock Input (SCL) – Input pin for the 2-wire serial interface used to synchronize data movement
on the serial interface.
REGISTER FUNCTIONS
The user-programmable registers can be programmed by the user to determine the mode of operation
(MUX), operating frequency (DIV) and bus settings (BUS). Details of how these registers are
programmed can be found in a later section; in this section the functions of the registers are described.
The register setting are nonvolatile, the values are stored automatically or as required in EEPROM when
the registers are programmed via the SDA and SCL pins.
MUX WORD
MSB
Name
*
0
Default setting
LSB
PDN1
0
PDN0
0
SEL0
1
EN0
1
0M1
0
0M0
0
1M1
0
MSB
1M0
0
first data byte
LSB
DIV1
0
x
x
x
x
x
x
second data byte
*This bit must be set to zero.
DIV1 (bit)
This bit allows the output of the prescaler P1 to be routed directly to the OUT1 pin (DIV1 = 1). The N
divider is bypassed so the programmed value of N is ignored. If DIV1 = 0 (default) the N divider
functions normally.
0M1, 0M0, 1M1, 1M0 (bits)
These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See Table 4.)
TABLE 4
0M1
0M0
0
0
PRESCALER
P0 DIVISOR
“M”
1*
1M1
1M0
0
0
PRESCALER
P1 DIVISOR
“M”
1*
0
1
2
0
1
2
1
0
4
1
0
4
1
1
8
1
1
8
*Default Condition
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DS1077L
EN0 (bit)
(Default EN0 = 1)
If EN0 = 1 and PDN0 = 0, the CTRL0 pin functions as an output enable for OUT0, the frequency of the
output is determined by the SEL0 bit.
If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, output OUT0 will always be
enabled on power-up, and its frequency is determined by the SEL0 bit.
If EN0 = 0, the function of CTRL0 is determined by the SEL0 and PDN0 bits. (See Table 1.)
SEL0
(Default SEL0 = 1)
If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX, (i.e., the output
frequency of OUT0).
If CTRL0 = 0, the output will be the master clock frequency.
If CTRL0 = 1, the output will be the output frequency of the M prescaler.
If either EN0 or PDN0 = 1, then SEL0 determines the frequency of OUT0 when it is enabled.
If SEL0 = 0, the output will be the master clock frequency.
If SEL0 = 1, the output will be the output frequency of the M prescaler. (See Table 1.)
PDN0
(Default PDN0 = 0)
This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the
other bits.
If PDN0 = 0, the function of CTRL0 is determined by the values of EN0 and SEL0.
NOTE:
When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all
the OUT0 circuitry is disabled even when the device is powered up. This feature can be used to save
power when OUT0 is not used. (See Table 1.)
PDN1
(Default PDN1 = 0)
If PDN1 = 1, CTRL1 will function as a power-down.
If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only. (See Table 2.)
NOTES (ON OUTPUT ENABLE AND POWER-DOWN):
1.
2.
3.
4.
5.
Both enables are “smart” and wait for the output to be low before going to Hi-Z.
Power-down sequence first disables both outputs before powering down the device.
On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles).
The device cannot be programmed in power-down mode.
A power-down command must persist for at least 2 cycles of the lowest output frequency plus 10µs.
DIV WORD
MSB
N9 N8
N7
N6 N5 N4
first data byte
N3
LSB MSB
N2 N1 N0
X
X
X
X
second data byte
X
LSB
X
N
These ten bits determine the value of the programmable divider (N). The range of divisor values is from 2
to 1025, and is equal to the programmed value of N plus 2. (See Table 5.)
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DS1077L
TABLE 5
BIT VALUE
0 000 000 000*
0 0 00 0 00 001
—
—
—
—
1 111 111 111
*Default Condition
DIVISOR (N)
2
3
—
—
—
—
1025
BUS WORD
NAME
—
—
—
Factory Default
0*
0*
0*
*These bits are reserved and must be set to zero.
—
0*
WC
0
A0, A1, A2
A2
0
A1
0
A0
0
(Default Setting = 000)
These are the device select bits that determine the address of the device.
WC
(Default Setting WC = 0)
This bit determines when/if the EEPROM is written to after register contents have been changed.
If WC = 0, the EEPROM is automatically written after a write register command.
If WC = 1, the EEPROM is only written when the WRITE command is issued.
Regardless of the value of the WC bit, when the BUS register (A0, A1, A2) is written, the current value in
all registers (DIV, MUX, and BUS) are immediately written to the EEPROM.
2-WIRE SERIAL DATA BUS
The DS1077L supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1077L operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pullup resistor (5k) is
connected to SDA.
The following bus protocol has been defined (see Figure 2):
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in
the data line while the clock line is high will be interpreted as control signals.
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DS1077L
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data line from high to low while the clock is high
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high while the clock line is high
defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1077L works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. When the DS1077L EEPROM is being written
to, it will not be able to perform additional responses. In this case, the slave DS1077L will send a ‘not
acknowledge’ to any data transfer request made by the master. It will resume normal operation when the
EEPROM operation is complete.
A master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the
master to generate the STOP condition.
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 2
SDA
MSB
slave address
R/W
direction
bit
acknowledgement
signal from receiver
acknowledgement
signal from receiver
SCL
1
START
CONDITION
2
6
7
8
9
1
2
3-8
ACK
9
ACK
repeated if more bytes
are transferred
8 of 21
8
STOP CONDITION
OR
REPEATED
START CONDITION
DS1077L
Figure 2 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the
R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next, follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next, follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1077L can operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1077L while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
SLAVE ADDRESS
A control byte is the first byte received following the START condition from the master device. The
control byte consists of a four-bit control code; for the DS1077L, this is set as 1011 binary for read and
write operations. The next three bits of the control byte are the device select bits (A2, A1, and A0) and
can be written to the EEPROM. They are used by the master device to select which of eight devices are to
be accessed. The select bits are in effect the three least significant bits of the slave address. The last bit of
the control byte (R/ W ) defines the operation to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is selected. Following the START condition, the
DS1077L monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the
1011 code (changeable with one mask) and appropriate device select bits, the slave device outputs an
acknowledge signal on the SDA line.
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DS1077L
2-WIRE SERIAL COMMUNICATION WITH DS1077L Figure 3
Send a “Standalone” Command
SCL
SDA
S
1
Start
0
1 1
A2 A1 A0 W
Address Byte
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
P
DS1077L Stop
ACK
Write MSB of a Two-Byte Register
SCL
SDA
S
1
0
Start
1 1
A2 A1 A0 W
Address Byte
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
D7 D6 D5 D4 D3 D2 D1 D0
DS1077L
ACK
MSByte
A
P
DS1077L Stop
ACK
Write to a Two-Byte Register
SCL
SDA
S
1
0
Start
1 1
A2 A1 A0 W
Address Byte
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
D7 D6 D5 D4 D3 D2 D1 D0
DS1077L
ACK
MSByte
A
D7 D6 D5 D4 D3 D2 D1 D0
DS1077L
ACK
LSByte
A
P
DS1077L Stop
ACK
Write a Single Byte to an Addressed Register
SCL
SDA
S
1
0
Start
1 1
A2 A1 A0
Control Byte
W
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
A7 A6 A5 A4 A3 A2 A1 A0
DS1077L
ACK
Byte Address
A
D7 D6 D5 D4 D3 D2 D1 D0
DS1077L
ACK
Data Byte
A
DS1077L
ACK
P
Stop
Write Multiple Bytes to an Addressed Register
SCL
SDA
S
Start
1
0
1 1
A2 A1 A0 W
Control Byte
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
A7 A6 A5 A4 A3 A2 A1 A0
DS1077L
ACK
D7 D6 D5 D4 D3 D2 D1 D0
Byte (n+1)
A
DS1077L
ACK
D7 D6 D5 D4 D3 D2 D1 D0
Byte N
D7 D6 D5 D4 D3 D2 D1 D0
Starting Byte Address DS1077L
ACK
SCL
SDA
A
A
P
DS1077L Stop
ACK
10 of 21
Byte n
A
DS1077L
ACK
DS1077L
2-WIRE SERIAL COMMUNICATION WITH DS1077L Figure 3 (cont.)
Read Single Byte Register or MSB from a Two-Byte Register
SCL
SDA
S
1
0
Start
1
1
A2 A1 A0
W
Control Byte
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
R 1
0
1
1
A2 A1 A0 Rd
DS1077L Repeated Control Byte
ACK
Start
A
D7 D6 D5 D4 D3 D2 D1 D0
DS1077L
ACK
MSByte
N
Master Stop
NACK
Read from a Two-Byte Register
SCL
SDA
S
1
0
Start
1
1
A2 A1 A0
W
Control Byte
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
R 1
0
1
1
A2 A1 A0 Rd
DS1077L Repeated Control Byte
ACK
Start
A
D7 D6 D5 D4 D3 D2 D1 D0
DS1077L
ACK
MSByte
A
Master
ACK
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
LSByte
N
P
Master Stop
NACK
Read Multiple Bytes from an Addressed Register
SCL
SDA
S
1
Start
0
1
1
A2 A1 A0
Control Byte
W
A
C7 C6 C5 C4 C3 C2 C1 C0
DS1077L
ACK
Command Byte
A
A7 A6 A5 A4 A3 A2 A1 A0
DS1077L
ACK
Starting Byte
Address
A
R 1
0
1
1
A2 A1 A0 Rd
DS1077L Repeated Control Byte
ACK
Start
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
Byte n
A D7 D6 D5 D4 D3 D2 D1 D0
Master
ACK
Byte (n+1)
A
D7 D6 D5 D4 D3 D2 D1 D0
Master
ACK
Byte N
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N
P
Master Stop
NACK
P
A
DS1077L
ACK
DS1077L
COMMAND SET
Data and control information is read from and written to the DS1077L in the format shown in Figure 3. To
write to the DS1077L, the master will issue the slave address of the DS1077L and the R/ W bit will be set to
0. After receiving an acknowledge, the bus master provides a command protocol. After receiving this
protocol, the DS1077L will issue an acknowledge, and then the master can send data to the DS1077L. If the
DS1077L is to be read, the master must send the command protocol as before, and then issue a repeat
START condition and then the control byte again, this time with the R/ W bit set to one to allow reading of
the data from the DS1077L. The command set for the DS1077L is as follows:
Access DIV [01]
If R/ W = 0, this command writes to the DIV register. After issuing this command, the next data byte value
is to be written into the DIV register.
If R/ W = 1, the next data byte read is the value stored in the DIV register.
Access MUX [02]
If R/ W = 0, this command writes to the MUX register. After issuing this command, the next data byte value
is to be written into the MUX register.
If R/ W = 1, the next data byte read is the value stored in the MUX register.
Access BUS [0D]
If R/ W = 0, this command writes to the BUS register. After issuing this command, the next data byte value
is to be written into the BUS register.
If R/ W = 1, the next data byte read is the value stored in the BUS register.
Write E2 [3F]
If WC = 0, the EEPROM is automatically written to at the end of each command, this is a DEFAULT
condition. In this case the command WRITE E2 is not needed
If WC = 1, the EEPROM is written when the WRITE E2 command is issued. On receipt of the WRITE E2
command the contents of the BUS, DIV, and MUX registers are written into the EEPROM, thus locking in
the register settings.
EXCEPTION: The BUS, DIV, and MUX registers are always automatically written to EEPROM after a
write to the BUS register regardless of the value of the WC bit.
APPLICATION INFORMATION
Power-Supply Decoupling
To achieve best results, decouple the power supply with 0.01µF and 0.1µF high-quality, ceramic, surfacemount capacitors as close as possible to VCC/GND of the device. Surface-mount components minimize lead
inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency
response for decoupling applications.
Current Consumption
The active supply current can be significantly reduced by disabling OUT0 when not required and setting its
prescaler to divide by 8. Likewise, bypassing OUT1’s divider (and using only the prescaler) also
significantly reduces the supply current.
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DS1077L
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Programming Temperature Range
Storage Temperature Range
Soldering Temperature
-0.5V to 6.0V
-40°C to +85°C
0°C to +70°C
-55°C to +125°C
See J-STD-020A Specification
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Supply Voltage
VCC
High-Level Output
Voltage
(OUT1, OUT0)
Low-Level Output
Voltage
(OUT1, OUT0)
CONDITION
IOH = -4mA,
VCC = MIN
VOL
IOL = 4mA
VIH
Low-Level Input Voltage
VIL
SDA and SCL
CTRL0 and CTRL1
SDA and SCL
CTRL0 and CTRL1
IIH
VIH = VCC = 3.6V
IIL
VCC = 3.6V,
VIL = 0
ICC
ICCQ
MIN
TYP
2.7
VOH
High-Level Input Voltage
High-Level Input Current
(CTRL1, CTRL0, SDA,
SCL)
Low-Level Input Current
(CTRL1, CTRL0, SDA,
SCL)
Supply Current (Active)
DS1077L-66
DS1077L-60
DS1077L-50
DS1077L-40
Standby Current
(Power-Down Mode)
(TA = -40°C to +85°C, VCC = 2.7V to 3.6V)
13 of 21
UNITS
NOTES
3.6
V
1
2.4
V
0.4
V
0.7VCC
1.4
VCC + 0.3
V
VCC - 0.3
0.3VCC
0.6
V
1
µA
-1
µA
CL = 15pF
(both outputs)
(-40°C to +85°C)
0°C to +70°C
-40°C to +85°C
MAX
1
30
25
20
15
5
10
mA
µA
DS1077L
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Output Frequency
Tolerance (from Nominal)
Combined Freq. Variation
(from Nominal)
(TA = -40°C to +85°C, VCC = 2.7V to 3.6V)
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
∆fO
VCC = 3.15V
TA = +25°C
-0.5
0
+0.5
%
10
∆fO
Over Temp
(0°C to +70°C)
& Voltage
Over Temp
(-40°C to +25°C)
& Voltage
Over Temp
(25°C to 85°C)
& Voltage
-1.25
+1.25
-2.4
+1.5
-1.5
+1.5
66.66
kHz
MHz
2
0.1
1
ms
4
tSTAB
0.1
1
ms
Enable OUT0 from CTRL0
tSTAB
0.1
1
ms
OUT1 Hi-Z from CTRL1
tSTAB
1
ms
OUT0 Hi-Z from CTRL0
tSTAB
1
ms
50
pF
60
%
Output Frequency Min
Output Frequency Max
f OUT
Power-Up Time
tPOR +
tSTAB
Enable OUT1 from CTRL1
Load Capacitance
4.87
%
CL
15
Output Duty Cycle
(OUT1, OUT0)
Output Jitter
40
FOUT = 66MHz
M = 1; DIV1 =1
CL = 12pF
3 sigma pk-to-pk
14 of 21
50
psec
3
9
DS1077L
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(-40°C to +85°C, VCC = 2.7V to 3.6V)
PARAMETER
SCL Clock Frequency
SYMBOL
fSCL
Bus Free Time Between
a STOP and START
Condition
Hold Time (Repeated)
START Condition.
LOW Period of SCL
HIGH Period of SCL
tBUF
tHD:STA
tLOW
tHIGH
Setup Time for a
Repeated START
Data Hold Time
tSU:STA
tHD:DAT
Data Setup Time
tSU:DAT
Rise Time of Both SDA
and SCL Signals
Fall Time of Both SDA
and SCL Signals
Setup Time for STOP
Capacitive Load for Each
Bus Line
Input Capacitance
tR
tF
tSU:STO
CONDITION
Fast Mode
Standard Mode
Fast Mode
Standard Mode
MIN
TYP
MAX
400
100
UNITS
kHz
1.3
4.7
µs
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
µs
NOTES
5
µs
µs
µs
0.9
µs
6, 7
ns
300
1000
300
20 +
0.1CB
20 +
0.1CB
0.6
4.0
ns
8
ns
8
µs
CB
400
CI
5
pF
8
pF
NONVOLATILE MEMORY CHARACTERISTICS
PARAMETER
Writes
SYMBOL
CONDITION
+85°C
MIN
10,000
15 of 21
TYP
MAX
UNITS
NOTES
DS1077L
NOTES:
1)
2)
3)
4)
5)
All voltages are referenced to ground.
4.87kHz is obtained from a -40MHz standard part.
Output voltage swings may be impaired at high frequencies combined with high output loading.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH
MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
6) The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the
SCL signal.
7) A fast mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
8) CB — Total capacitance of one bus line in pF.
9) Jitter accumulates over N clock cycles as: (3 sigma jitter)(no. of cycles)0.65.
10) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 3 preconditioning with
1000 temperature cycles of -55°C to +125°C, 336hr max VCC biased +125°C bake. Level 3
preconditioning consists of a 24hr +125°C storage bake, 192hr moisture soak at +30°C/60% R.H., and
three solder reflow passes.
TIMING DIAGRAM
SDA
tBUF
tLOW
tHD:STA
tR
tF
t SP
SCL
t HD:STA
STOP
START
t HD:DAT
tHIGH
t SU:DAT
t SU:STA
REPEATED
START
ORDERING INFORMATION:
DS1077L
Master Frequency (MHz)
40, 50, 60, 66.66
PACKAGE TYPE:
Z = SO (150MIL)
U = µSOP
16 of 21
t SU:STO
DS1077L
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25ºC, unless otherwise specified)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT (mA)
13
12
11
10
9
8
66MHz device
7
60MHz device
50MHz device
40MHz device
6
0
10
20
30
40
TEMPERATURE (C)
50
60
70
SUPPLY CURRENT vs. VOLTAGE
16
SUPPLY CURRENT (mA)
15
14
13
12
11
10
9
66MHz device
8
60MHz device
50MHz device
7
40MHz device
6
2.7
2.8
2.9
3
3.1
3.2
VCC (V)
17 of 21
3.3
3.4
3.5
3.6
DS1077L
TYPICAL OPERATING CHARACTERISTICS (cont.)
(VCC = 3.3V, TA = +25ºC, unless otherwise specified)
SUPPLY CURRENT vs. DIVISOR (FREQUENCY)
3.4
SUPPLY CURRENT (mA)
3.2
3
2.8
2.6
2.4
0C
25C
2.2
70C
2
0
100
200
300
400
500
600
700
800
900
DIVISOR (N)
SUPPLY CURRENT vs. DIVISOR (FREQUENCY)
SUPPLY CURRENT (mA)
4.5
4
3.5
2.7
3
3.6
3
2.5
2
0
100
200
300
400
500
DIVISOR (N)
18 of 21
600
700
800
900
DS1077L
19 of 21
DS1077L
TYPICAL OPERATING CHARACTERISTICS (cont.)
(VCC = 3.3V, TA = +25ºC, unless otherwise specified)
DS1077L SHUTDOWN CURRENT vs. TEMPERATURE
SHUTDOWN CURRENT (mA)
0.880
0.860
0.840
0.820
0.800
66MHz device
0.780
0.760
0
10
20
30
40
50
60
70
TEMPERATURE (C)
DS1077L TEMPCO
FREQUENCY CHANGE FROM 25°C (%)
1
0.8
0.6
0.4
0.2
0
-0.2
-66 device
-60 device
-0.4
-50 device
-40 device
-0.6
-0.8
-1
0
10
20
30
40
TEMPERATURE (C)
20 of 21
50
60
70
DS1077L
TYPICAL OPERATING CHARACTERISTICS (cont.)
(VCC = 3.3V, TA = +25ºC, unless otherwise specified)
DS1077L VOLTCO
1
FREQUENCY CHANGE 3.1V (%)
0.8
0.6
0.4
0.2
0
-0.2
-66 device
-60 device
-0.4
-50 device
-40 device
-0.6
-0.8
-1
2.7
2.8
2.9
3.0
3.1
3.2
3.3
SUPPLY VOLTAGE (V)
21 of 21
3.4
3.5
3.6
ENGLISH • ???? • ??? • ???
WHAT'S NEW PRODUCTS SOLUTIONS DESIGN
APPNOTES SUPPORT
BUY
COMPANY MEMBERS
DS1077L
Part Number Table
Notes:
1. See the DS1077L QuickView Data Sheet for further information on this product family or download the DS1077L full
data sheet (PDF, 296kB).
2. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
3. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one
business day.
4. Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: See full data
sheet or Part Naming Conventions.
5. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses.
Part Number
Free
Sample
Buy
Temp
Package: TYPE PINS SIZE
Direct
DRAWING CODE/VAR *
RoHS/Lead-Free?
Materials Analysis
DS1077LZ-66+T&R
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-60+T&R
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-50+T&R
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-40+T&R
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-40/T&R
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8-4*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LZ-40
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8-4*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LZ-40+
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-66+
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-50+
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-60+
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8+4*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LZ-66
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8-4*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LZ-60
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8-4*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LZ-50
SOIC;8 pin;150
Dwg: 56-G2008-001C (PDF)
Use pkgcode/variation: S8-4*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LU-60+
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-50+
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-40+
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-60+T
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-50+T
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-40+T
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-66+T
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
DS1077LU-66
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8-1*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LU-60
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8-1*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LU-50
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8-1*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LU-40
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8-1*
-40C to +85C RoHS/Lead-Free: No
Materials Analysis
DS1077LU-66+
uSOP;8 pin;118
Dwg: 21-0036J (PDF)
Use pkgcode/variation: U8+1*
-40C to +85C RoHS/Lead-Free: Yes
Materials Analysis
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