DS1089L
3.3V Center Spread-Spectrum EconOscillator™
General Description
The DS1089L is a clock generator that produces a
spread-spectrum (dithered) square-wave output of frequencies from 130kHz to 66.6MHz. The DS1089L is
shipped from the factory programmed at a specific
frequency. The DS1089L is pin-for-pin compatible with
the DS1087L, however, the DS1089L dithers at equal
percentages above and below the center frequency. The
user still has access to the internal frequency divider,
selectable ±1%, ±2%, ±4%, or ±8% dithered output, dithering rate, and programmable output power-down/disable
mode through an I2C-compatible programming interface.
All the device settings are stored in nonvolatile (NV)
EEPROM allowing it to operate in stand-alone applications. The DS1089L also has power-down and output-enable control pins for power-sensitive applications.
Applications
●●
●●
●●
●●
●●
Features
●● Factory-Programmed Square-Wave Generator from
33.3MHz to 66.6MHz
●● Center Frequency Remains Constant Independent of
Dither Percentage
●● No External Timing Components Required
●● EMI Reduction
●● Variable Dither Frequency
●● User Programmable Down to 130kHz with Divider
(Dependent on Master Oscillator Frequency)
●● ±1%, ±2%, ±4%, or ±8% Selectable Dithered Output
●● Glitchless Output-Enable Control
●● I2C-Compatible Serial Interface
●● Nonvolatile Settings
●● Power-Down Mode
Printers
Copiers
Computer Peripherals
POS Terminals
Cable Modems
●● Programmable Output Power-Down/Disable Mode
Ordering Information
Pin Configuration and Typical Operating Circuits appear at
end of data sheet.
PART
DS1089LU-yxx*
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
8 µSOP (118 mil)
*See Standard Frequency Options Table.
Standard Frequency Options
PART
FREQUENCY (MHz)
SPREAD (±%)
DITHER FREQUENCY
DS1089LU-21G
14.7456
1
DS1089LU-4CL
18.432
2
fMOSC/4096
DS1089LU-22F
24.576
1
DS1089LU-23C
33.3
1
DS1089LU-450
50.0
2
DS1089LU-866
66.6
4
DS1089LU-yxx
Fixed up to 66.6
1, 2, 4, or 8
Add “/T” for Tape and Reel.
Custom frequencies available, contact factory.
EconOscillator is a trademark of Maxim Integrated Products, Inc.
19-7501; Rev 3; 2/15
fMOSC/4096
fMOSC/2048
fMOSC/4096
fMOSC/4096
fMOSC/4096
fMOSC/2048 or 4096 or 8192
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Absolute Maximum Ratings
Voltage on VCC Relative to Ground.....................-0.5V to +6.0V
Voltage on SPRD, PDN, OE, SDA,
SCL Relative to Ground*....................... -0.5V to (VCC + 0.5V)
Operating Temperature Range............................ -40°C to +85°C
Programming Temperature Range..........................0°C to +70°C
Storage Temperature Range............................. -55°C to +125°C
Soldering Temperature.................. See IPC/JEDEC J-STD-020A
*This voltage must not exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended Operating Conditions
(TA = -40°C to +85°C.)
PARAMETER
Supply Voltage
High-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE)
Low-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE)
SYMBOL
VCC
CONDITION
(Note 1)
VIH
MIN
TYP
MAX
UNITS
2.7
3.3
3.6
V
VCC +
0.3
V
0.3 x
VCC
V
MAX
UNITS
0.7 x VCC
VIL
-0.3
DC Electrical Characteristics
(VCC = +2.7V to +3.6V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
High-Level Output Voltage (OUT)
VOH
IOH = -4mA, VCC = min
VOL1
Low-Level Output Voltage (OUT)
Low-Level Output Voltage (SDA)
High-Level Input Current
Low-Level Input Current
Supply Current (Active)
Standby Current (Power-Down)
www.maximintegrated.com
VOL
VOL2
CONDITION
V
0.4
3mA sink current
0.4
6mA sink current
0.6
VIH = VCC
ICC
CL = 15pF, fOUT = fMOSCmax
ICCQ
TYP
2.4
IOL = 4mA
IIH
IIL
MIN
VIL = 0V
Power-down mode
V
V
1
µA
12
mA
10
µA
-1
µA
Maxim Integrated │ 2
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Master Oscillator Characteristics
(VCC = +2.7V to +3.6V, TA = -40°C to +85°C.)
PARAMETER
Internal Master Oscillator
Frequency
Master Oscillator Frequency
Tolerance
SYMBOL
CONDITION
MAX
UNITS
33.3
66.6
MHz
VCC = 3.3V,
TA = +25°C (Notes 2, 10)
-0. 5
+0. 5
%
TA = +25°C (Note 3)
-0.75
+0.75
%
TA = 0°C to +85°C
-0.75
+0.75
TA = -40°C to 0°C
-2.00
+0.75
fMOSC
∆f MOSC
f MOSC
∆f
Voltage Frequency
Variation
f MOSC
Temperature Frequency Variation
(Note 4)
f MOSC
∆f
Dither Frequency Range
(Note 5)
VCC = 3.3V,
fOUT = fMOSCmax
MIN
J3 = J2 = GND
±1
J3 = GND, J2 = VCC
±2
fMOD
%
%
J3 = VCC, J2 = GND
±4
J1 = GND, J0 = VCC
fMOSC / 2048
J1 = J0 = VCC
fMOSC / 8192
J3 = J2 = VCC
Dither Frequency
(Note 5)
TYP
±8
J1 = VCC, J0 = GND
fMOSC / 4096
Hz
AC Electrical Characteristics
(VCC = +2.7V to +3.6V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
Frequency Stable After
PRESCALER Change
Power-Up Time
tPOR +
tSTAB
(Note 6)
Enable of OUT After Exiting
Power-Down Mode
tSTAB
(Note 6)
OUT Disabled After Entering
Power-Down Mode
tPDN
7
CL
15
Load Capacitance
Output Duty Cycle (fOUT)
www.maximintegrated.com
40
50
MAX
UNITS
1
Period
200
µs
512
clock
cycles
µs
50
pF
%
Maxim Integrated │ 3
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
AC Electrical Characteristics—I2c Interface
(VCC = +2.7V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER
SYMBOL
SCL Clock Frequency
Bus Free Time Between Stop and
Start Conditions
fSCL
Hold Time (Repeated) Start
Condition
Low Period of SCL
High Period of SCL
Data Hold Time
Data Setup Time
Start Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
CONDITIONS
(Note 7)
TYP
0
MAX
UNITS
400
kHz
tBUF
1.3
µs
tHD:STA
0.6
µs
tLOW
1.3
µs
tHD:DAT
0
tHIGH
0.6
tSU:DAT
100
ns
0.6
µs
tSU:STA
tR
(Note 8)
tF
(Note 8)
SDA and SCL Capacitive
Loading
CB
(Note 8)
EEPROM Write Time
tWR
(Note 9)
Stop Setup Time
MIN
µs
0.9
20 + 0.1CB
20 + 0.1CB
tSU:STO
µs
300
ns
300
ns
0.6
µs
400
pF
10
20
ms
TYP
MAX
UNITS
Nonvolatile Memory Characteristics
(VCC = +2.7V to +3.6V.)
Writes
PARAMETER
SYMBOL
+70°C
CONDITION
MIN
10,000
Note
Note
Note
Note
Note
1: All voltages are referenced to ground.
2: This is the absolute accuracy of the master oscillator frequency at the default settings with spread disabled.
3: This is the change that is observed in master oscillator frequency with changes in voltage at TA = +25°C.
4: This is the change that is observed in master oscillator frequency with changes in temperature at VCC = 3.3V.
5: The dither deviation of the master oscillator frequency is bidirectional and results in an output frequency centered at the
undithered frequency.
Note 6: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tSTAB is equivalent to 512 master clock cycles and will depend on the programmed
master oscillator frequency.
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 8: CB—total capacitance of one bus line in picofarads.
Note 9: EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when WC = 0.
The EEPROM write time begins after a stop condition occurs.
Note 10: Typical frequency shift due to aging is ±0.25%. Aging stressing includes Level 1 moisture reflow conditioning (24hr) +125°C
bake, 168hr +85°C/85°RH moisture soak, and three solder reflow passes +269 +0/-5°C peak) followed by 408hr max VCC
biased 125°C HTOL, 500 temperature cycles at -55°C to +125°C, 96hr +130°C/85%RH/3,6V HAST and 168hr +121°C/2
ATM Steam/Unbiased Autoclave.
www.maximintegrated.com
Maxim Integrated │ 4
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
6
4
50MHz
130kHz
33MHz
2
8
66MHz
7
6
5
4
50MHz
3
33MHz
2
130kHz
SUPPLY CURRENT
vs. PRESCALER
10
DS 1089L toc03
TA = +25ºC,
OUTPUT
UNLOADED
9
SUPPLY CURRENT (mA)
8
66MHz
10
DS 1089L toc01
TA = +25ºC,
OUTPUT
UNLOADED
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
DS 1089L toc02
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TA = +25ºC,
fMOSC = 50MHz,
OUTPUT UNLOADED
8
6
4
3.6V
3.3V
2.7V
2
1
2.7
3.3
-40
-15
10
35
60
0
85
1
10
1000
100
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
FREQUENCY % CHANGE
vs. SUPPLY VOLTAGE
FREQUENCY % CHANGE
vs. TEMPERATURE
2
1
TA = +25ºC
33MHz
0.25
66MHz
130kHz
0
-0.25
50MHz
-40
-15
10
35
TEMPERATURE (ºC)
www.maximintegrated.com
60
85
-0.50
2.7
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
0.2
FREQUENCY CHANGE (%)
3
0.50
FREQUENCY CHANGE (%)
VCC = 3.3V,
PDN = GND
DS 1089L toc06
PRESCALE DIVIDER (DECIMAL)
DS 1089L toc05
TEMPERATURE (°C)
4
0
0
3.6
SUPPLY VOLTAGE (V)
5
SUPPLY CURRENT (µA)
3.0
DS 1089L toc04
0
VCC = 3.3V
0
130kHz
-0.2
-0.4
50MHz
66MHz
-0.6
-0.8
33MHz
-40
-15
10
35
60
85
TEMPERATURE (ºC)
Maxim Integrated │ 5
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
54
52
50
3.0
3.3
SUPPLY VOLTAGE (V)
50MHz
54
52
33MHz
50
130kHz
2.7
66MHz
48
-40
-15
10
-10
2%
35
60
85
1%
NO SPREAD
-20
DS 1089L toc09
SPECTRUM COMPARISON
(120kHz BW, SAMPLE DETECT)
-30
-40
8%
4%
-50
-60
-70
fMOSC = 50MHz,
DITHER RATE = fMOSC / 4096
-80
130kHz
3.6
0
POWER SPECTRUM (dBm)
33MHz
VCC = 3.3V
56
DUTY CYCLE (%)
DUTY CYCLE (%)
66MHz
50MHz
48
58
DS 1089L toc08
TA = +25ºC
56
DUTY CYCLE vs. TEMPERATURE
DS 1089L toc07
58
DUTY CYCLE
vs. SUPPLY VOLTAGE
-90
TEMPERATURE (ºC)
44
46
48
50
52
54
56
FREQUENCY (MHz)
Pin Description
PIN
NAME
2
SPRD
1
3
OUT
Oscillator Output
FUNCTION
Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.
VCC
Power Supply
4
GND
5
OE
Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled
but the internal master oscillator is still on.
6
PDN
Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator
and the output buffer are disabled (power-down mode).
7
SDA
I2C Serial Data. This pin is for serial data transfer to and from the device.
8
SCL
I2C Serial Clock. This pin is used to clock data into and out of the device.
Ground
www.maximintegrated.com
Maxim Integrated │ 6
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Block Diagram
PDN
H/W GATED OUTPUT
OE
SDA
CONTROL REGISTERS
I2C
I2C SERIAL
ADDRESS
INTERFACE
BITS
SCL
OUTPUT CONTROL
S/W GATED OUTPUT
ADDR
J3
WRITE EE
COMMAND
J2
OE
X
WC
A2
A1
A0
EEPROM
WRITE
CONTROL
fMOSC
PRESCALER
DIVIDE BY 1, 2, 4,
8, 16, 32, 64,
128, OR 256
fOSC SYNCED
OUTPUT
BUFFER
f OUT
OUT
f MOD
DITHER RATE
DITHER %
J1
J0
VCC
GND
FACTORYPROGRAMMED
MASTER
OSCILLATOR
33.3MHz TO
66.6MHz
EEPROM
VCC
DS1089L
LO/
HIZ
X
P3
P2
P1
TRIANGLEWAVE
GENERATOR
fMOSC
P0
PRESCALER SETTING
OUTPUT CONFIGURATION
PRESCALER
SPRD
Detailed Description
Master Oscillator
The internal master oscillator is capable of generating
a square wave with a 33.3MHz to 66.6MHz frequency
range. The master oscillator frequency (fMOSC) is factory
programmed, and is specified in the Ordering Information.
Prescaler
The user can program the prescaler divider to produce an
output frequency (fOUT) as low as 130kHz using bits P0,
P1, P2, and P3 in the PRESCALER register. The output
frequency can be calculated using Equation 1. Any value
programmed greater than 28 will be decoded as 28. See
Table 1 for prescaler divider settings.
Table 1. Prescaler Divider Settings
BITS P3, P2,
P1, P0
2x =
0000
1
0001
2
0010
4
0011
8
0100
16
0101
32
0110
64
0111
128
1000
256
1111
256
fOUT = fOSC
fMOSC
fMOSC / 2
fMOSC / 4
fMOSC / 8
fMOSC / 16
fMOSC / 32
fMOSC / 64
fMOSC / 128
fMOSC / 256
Equation 1
f
Output Frequency (Hz) f OSC = MOSC
2x
fMOSC / 256
where x = P3, P2, P1, P0
www.maximintegrated.com
Maxim Integrated │ 7
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Output Control
Dither Percentage Settings
Additionally, the OE input is OR’ed with the OE bit in the
ADDR register, allowing for either hardware or software
gating of the output waveform (see the Block Diagram).
The location of bits P3, P2, P1, P0, J1, and J0 in the
PRESCALER register and bits J3 and J2 in the ADDR
register are shown in the Register Summary section.
Both controls feature a synchronous enable, which
ensures that there are no output glitches when the output
is enabled. The synchronous enable also ensures a constant time interval (for a given frequency setting) from an
enable signal to the first output transition.
Table 2. Dither Frequency Settings
Two user control signals control the output. The output
enable pin (OE) gates the output buffer and the power-down pin (PDN) disables the master oscillator and
turns off the output for power-sensitive applications.
(Note: the power-down command must persist for at least
two output frequency cycles plus 10µs for deglitching purposes.) On power-up, the output is disabled until power is
stable and the master oscillator has generated 512 clock
cycles.
The dither amplitude (measured in percentage of the
master oscillator center frequency) is set using the J2
and J3 bits in the ADDR register. This circuit uses a sense
current from the master oscillator bias circuit to adjust the
amplitude of the triangle-wave signal to a voltage level
that modulates the master oscillator to a percentage of its
factory-programmed center frequency. This percentage is
set in the application to be ±1%, ±2%, ±4%, or ±8% (see
Table 3).
BITS J1, J0
DITHER FREQUENCY
00
No dither
01
fMOSC/2048
10
Dither Generator
The DS1089L has the ability to reduce radiated emission
peaks. The output frequency can be dithered by ±1%,
±2%, ±4%, or ±8% symmetrically around the programmed
center frequency. Although the output frequency changes when the dither is enabled, the duty cycle does not
change.
The dither rate (fMOD) is controlled by the J0 and J1
bits in the PRESCALER register and is enabled with the
SPRD pin. The maximum spectral attenuation occurs
when the prescaler is set to 1. The spectral attenuation is
reduced by 2.7dB for every factor of 2 that is used in the
prescaler. This happens because the prescaler’s divider
function tends to average the dither in creating the lower
frequency. However, the most stringent spectral emission
limits are imposed on the higher frequencies where the
prescaler is set to a low divider ratio.
11
fMOSC/4096
fMOSC/8192
Table 3. Dither Percentage Settings
BITS J3, J2
DITHER AMOUNT
00
±1%
01
±2%
10
±4%
11
±8%
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
can be calculated based on the master oscillator frequency (see Equation 2).
Equation 2
f
f MOD = MOSC
n
where fMOD = dither frequency, fMOSC = master oscillator
frequency, and n = divider setting (see Table 2).
www.maximintegrated.com
Maxim Integrated │ 8
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
When dither is enabled (by selecting a dither frequency
setting greater than 0 with SPRD high), the master oscillator frequency is dithered around the center frequency
by the selected percentage from the programmed fMOSC
(see Figure 2). For example, if fMOSC is programmed
to 40MHz (factory setting) and the dither amount is
programmed to ±1%, the frequency of fMOSC will dither
between 39.6MHz and 40.4MHz at a modulation frequency determined by the selected dither frequency.
Continuing with the same example, if J1 = 0 and J0 = 1,
selecting fMOSC/2048, then the dither frequency would
be 19.531kHz.
IF DITHER AMOUNT = 0%
(+1, 2, 4,
OR 8% OF fMOSC)
PROGRAMMED
fMOSC
(-1, 2, 4,
OR 8% OF fMOSC)
fMOSC
DITHER
AMOUNT
(2, 4, 8,
OR 16%)
1
fMOD
TIME
Register Summary
Figure 2. Output Frequency vs. Dither Rate
The DS1089L registers are used to change the dither amount, output frequency, and slave address. A bit
summary of the registers is shown in Table 4. Once
programmed into EEPROM, the settings only need to be
reprogrammed if it is desired to reconfigure the device.
ADDR Register
Bits 7 to 6: Dither Percentage. The J3 and J2 bits control the selected dither amplitude (%). When
both J3 and J2 are set to 0, the default dither rate is ±1%.
PRESCALER Register
Bits 7 to 6: Dither Frequency. The J1 and J0 bits
control the dither frequency applied to the
output. See Table 2 for divider settings. If
either of bits J1 or J0 is high and SPRD is
high, dither is enabled.
Bit 5:
Output Enable. The OE bit and the OE pin
state determine if the output is on when the
device is active (PDN = VIH). If (OE = 0 OR
OE is high) AND the PDN pin is high, the
output will be driven.
Output Low or Hi-Z. The LO/HIZ bit determines the state of the output during power-down. While the output is deactivated, if
the LO/HIZ bit is set to 0, the output will be
high impedance (high-Z). If the LO/HIZ bit is
set to 1, the output will be driven low.
Bit 4:
Reserved.
Bit 3:
Write Control. The WC bit determines if
the EEPROM is to be written after register
contents have been changed. If WC = 0
(default), EEPROM is written automatically
after a write. If WC = 1, the EEPROM is
only written when the WRITE EE command
is issued. See the WRITE EE Command
section for more information.
Bit 5:
Bit 4:
Reserved.
Bits 3 to 0: Prescaler Divider. The prescaler bits (bits
P3 to P0) divide the master oscillator frequency by 2x where x can be from 0 to
8. Any prescaler bit value entered that is
greater than 8 will decode as 8. See Table 1
for prescaler settings.
Bits 2 to 0: Address. The A0, A1, A2 bits determine the
lower nibble of the I2C slave address.
Table 4. Register Summary
REGISTER
ADDR
BIT7
BINARY
PRESCALER
02h
J1
J0
LO/
HIZ
X
P3
P2
ADDR
0Dh
J3
J2
OE
X
WC
A2
WRITE EE
3Fh
No Data
BIT0
DEFAULT
ACCESS
P1
P0
xx00xxxxb
R/W
A1
A0
xx100000b
R/W
—
—
X = “don’t care”
x = values depend on custom settings
www.maximintegrated.com
Maxim Integrated │ 9
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
WRITE EE Command
bit, the value of the ADDR register is always written
immediately to EEPROM. When the WRITE EE command has been received, the contents of the registers
are written into the EEPROM, thus locking in the register
settings.
The WRITE EE command is useful in closed-loop applications where the registers are frequently written. In
applications where the register contents are frequently
written, the WC bit should be set to 1 to prevent wearing
out the EEPROM. Regardless of the value of the WC
I2C Serial Port Operation
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
ACK
START
CONDITION
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP
CONDITION
OR REPEATED
START
CONDITION
Figure 3. I2C Data Transfer Protocol
LSB
MSB
1
0
1
DEVICE
IDENTIFIER
1
A2
A1
A0
R/W
DEVICE READ/WRITE BIT
ADDRESS
Figure 4. Slave Address Byte
www.maximintegrated.com
Maxim Integrated │ 10
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
SDA
tBUF
tSP
tHD:STA
tLOW
tR
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tHD:DAT
tSU:STO
Figure 5. I2C AC Characteristics
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
0
1
1
DEVICE IDENTIFIER
A2* A1* A0* R/W
DEVICE
ADDRESS
SLAVE
ACK
READ/
WRITE
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
B0h
START 1 0 11 0 0 0 0
MSB
b7
COMMAND/REGISTER ADDRESS
EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO)
B0h
02h
DATA
SLAVE
SLAVE
A) SINGLE BYTE WRITE
00000010
10000000
START 1 0 11 0 0 0 0
ACK
ACK
-WRITE PRESCALER
REGISTER TO 128
B) SINGLE BYTE READ
-READ PRESCALER
REGISTER
SLAVE
ACK
LSB
b6
b5
b4
b3
b2
b1
b0
SLAVE
STOP
ACK
DATA
SLAVE
ACK
STOP
B1h
DATA
02h
MASTER STOP
SLAVE REPEATED
SLAVE
SLAVE
1 0 11 0 0 0 1
00000010
10000000
NACK
START
ACK
ACK
ACK
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST
MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 6. I2C Transactions
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1089L,
decouple the power supply with 0.01µF and 0.1µF
high-quality, ceramic, surface-mount capacitors.
Surface-mount components minimize lead inductance,
which improves performance, and ceramic capacitors
www.maximintegrated.com
tend to have adequate high-frequency response for
decoupling applications. These capacitors should be
placed as close to the VCC and GND pins as possible.
Stand-Alone Mode
SCL and SDA cannot be left floating even in stand-alone
mode. If the DS1089L will never need to be programmed
in-circuit, including during production testing, SDA and
SCL can be connected high.
Maxim Integrated │ 11
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Typical Operating Circuits
PROCESSOR-CONTROLLED MODE
STAND-ALONE MODE
VCC
DITHERED 130kHz
TO 66.6MHz OUTPUT
VCC
4.7kΩ
OUT
SPRD
4.7kΩ
SCL
DS1089L
SDA
2-WIRE
INTERFACE
VCC
DITHERED 130kHz
TO 66.6MHz OUTPUT
XTL1/OSC1
XTL2/OSC2
N.C.
VCC
VCC
OUT
SPRD
SCL*
DS1089L
SDA*
MICROPROCESSOR
VCC
PDN
VCC
PDN
GND
OE
GND
OE
DECOUPLING CAPACITORS
(0.1µF and 0.01µF)
DECOUPLING CAPACITORS
(0.1µF and 0.01µF)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1089L NEVER
NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
Pin Configuration
Chip Topology
TRANSISTOR COUNT: 5985
TOP VIEW
SUBSTRATE CONNECTED TO GROUND
OUT 1
SPRD 2
8 SCL
DS1089L
7 SDA
VCC 3
6
GND 4
5 OE
µSOP (118 mils)
www.maximintegrated.com
PDN
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package
regardless of RoHS status.
Maxim Integrated │ 12
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Revision History
REVISION
NUMBER
REVISION
DATE
2
5/06
3
2/15
DESCRIPTION
PAGES
CHANGED
—
Removed automotive reference from data sheet
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2015 Maxim Integrated Products, Inc. │ 13
工商网监
湘ICP备2023018690号