DS1100Z-20

19-5735; Rev 3/11 DS1100 5-Tap Economy Timing Element (Delay Line) GENERAL DESCRIPTION FEATURES The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in surface-mount packages to save PCB area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry-standard µMAX and SO packaging. The DS1100 5-tap silicon delay line reproduces the input-logic state at the output after a fixed delay as specified by the extension of the part number after the dash. The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap can drive up to 10 74LS loads.             All-Silicon Timing Circuit Five Taps Equally Spaced 5V Operation Delays are Stable and Precise Both Leading- and Trailing-Edge Accuracy Improved Replacement for DS1000 Low-Power CMOS TTL/CMOS-Compatible Vapor-Phase, IR, and Wave Solderable Custom Delays Available Fast-Turn Prototypes Delays Specified Over Both Commercial and Industrial Temperature Ranges PIN ASSIGNMENT Maxim can customize standard products to meet special needs. IN 1 8 VCC TAP 2 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 5 TAP 5 DS1100Z SO (150 mils) DS1100U µMAX® PIN DESCRIPTION TAP 1 to TAP 5 VCC GND IN µMAX is a registered trademark of Maxim Integrated Products, Inc. 1 of 7 - TAP Output Number - +5V - Ground - Input DS1100 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground ........................... -0.5V to +6.0V Short-Circuit Output Current ...................................................... 50mA for 1s Operating Temperature Range .................................................... -40°C to +85°C Storage Temperature Range ........................................................ -55°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Soldering Temperature (reflow) Lead(Pb)-free........................................................................... +260°C Containing lead(Pb) ................................................................. +240°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Supply Voltage VCC 4.75 High-Level VIH 2.2 Input Voltage Low-Level VIL -0.3 Input Voltage Input-Leakage -1.0 II 0.0V ≤ VI ≤ VCC Current VCC = Max; Freq = Active Current ICC 1MHz High-Level VCC = Min; VOH = 4 IOH Output Current Low-Level VCC = Min; VOL = 0.5 12 IOL Output Current TYP 5.00 30 MAX 5.25 VCC + 0.3 UNITS V NOTES 5 V 5 0.8 V 5 1.0 μA 50 mA -1 mA 6, 8 mA AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN 20% of Input tWI Tap 5 Pulse Width tPLH +25°C 5V -2 Input-to-Tap 0°C to +70°C -3 tPLH, Delay Tolerance tPHL (Delays ≤ 40ns) -40°C to +85°C -4 Input-to-Tap Delay Tolerance (Delays > 40ns) tPLH, tPHL Power-Up Time Input Period tPU Period TYP MAX UNITS NOTES ns 9 1, 3, 4, 7 1, 2, 3, 4, 7 1, 2, 3, 4, 7 1, 3, 4, 7 1, 2, 3, 4, 7 1, 2, 3, 4, 7 Table 1 +2 ns Table 1 +3 ns Table 1 +4 ns +25°C 5V -5 Table 1 +5 % 0°C to +70°C -8 Table 1 +8 % -40°C to +85°C -13 Table 1 +13 % 200 μs ns 2(tWI) 9 CAPACITANCE (TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Input Capacitance CIN 2 of 7 MIN TYP 5 MAX 10 UNITS pF NOTES DS1100 NOTES: 1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and trailing edge. 2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature range, and a supply-voltage range of 4.75V to 5.25V. 3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2. 4) Intermediate delay values are available on a custom basis. For further information, email the factory at custom.oscillators@maxim-ic.com. 5) All voltages are referenced to ground. 6) Measured with outputs open. 7) See Test Conditions section at the end of this data sheet. 8) Frequencies higher than 1MHz result in higher ICC values. 9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e., decoupling, layout). Figure 1. LOGIC DIAGRAM Figure 2. TIMING DIAGRAM: SILICON DELAY LINE 3 of 7 DS1100 TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100. The input waveform is produced by a precision-pulse generator under software control. Time delays are measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. TEST CONDITIONS INPUT Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Time: Pulse Width: Period: +25°C ±3°C 5.0V ±0.1V High = 3.0V ±0.1V Low = 0.0V ±0.1V 50Ω max 3.0ns max (measured between 0.6V and 2.4V) 500ns (1μs for -500 version) 1μs (2μs for -500 version) OUTPUT: Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edge. Note: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. 4 of 7 DS1100 Figure 3. TEST CIRCUIT Table 1. DS1100 PART NUMBER DELAY PART DS1100-xxx -20 -25 -30 -35 -40 -45 -50 -60 -75 -100 -125 -150 -175 -200 -250 -300 -500 TAP 1 4 5 6 7 8 9 10 12 15 20 25 30 35 40 50 60 100 NOMINAL DELAYS (ns) TAP 2 TAP 3 TAP 4 8 12 16 10 15 20 12 18 24 14 21 28 16 24 32 18 27 36 20 30 40 24 36 48 30 45 60 40 60 80 50 75 100 60 90 120 70 105 140 80 120 160 100 150 200 120 180 240 200 300 400 5 of 7 TAP 5 20 25 30 35 40 45 50 60 75 100 125 150 175 200 250 300 500 DS1100 ORDERING INFORMATION PART DS1100Z-xxx DS1100Z-xxx/T&R DS1100Z-xxx+ DS1100Z-xxx+T DS1100U-xxx DS1100U-xxx/T&R DS1100U-xxx+ DS1100U-xxx+T TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 8 SO 8 SO 8 SO 8 SO 8 µMAX 8 µMAX 8 µMAX 8 µMAX xxx Denotes total time delay (ns) (see Table 1). +Denotes a lead(Pb)-free/RoHS-compliant package. T&R and T = Tape and reel. PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 SO (150 mils) S8+4 21-0041 90-0096 8 µMAX U8+1 21-0036 90-0092 6 of 7 DS1100 REVISION HISTORY REVISION DATE DESCRIPTION PAGES CHANGED 3/11 Removed the DIP package from General Description, Pin Assignment, and Ordering Information (no longer available); changed µSOP package type to µMAX; updated the Absolute Maximum Ratings section; added the customer support email address to the electrical characteristics Note 4; added the Ordering Information and Package Information tables 1−6 7 of 7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0  2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.