NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
16k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Directly replaces 2k x 8 volatile static RAM
or EEPROM
Unlimited write cycles
Low-power CMOS
JEDEC standard 24-pin DIP package
Read and write access times as fast as 100 ns
Full ±10% operating range
Optional industrial temperature range of
-40°C to +85°C, designated IND
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
16
15
14
13
VCC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10
DQ0-DQ7
CE
WE
OE
VCC
GND
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
DESCRIPTION
The DS1220Y 16k Nonvolatile SRAM is a 16,384-bit, fully static, nonvolatile RAM organized as 2048
words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that
constantly monitor VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to
the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or
the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
1 of 9
REV: 072808
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
READ MODE
The DS1220Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs
(A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or
tOE for OE rather than address access.
WRITE MODE
The DS1220Y executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1220Y provides full-functional capability for VCC greater than 4.5 volts and write protects at 4.25
nominal. Data is maintained in the absence of VCC without any additional support circuitry. The
DS1220Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write
protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 4.5 volts.
2 of 9
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Caution: Do Not Reflow
-0.3V to +7.0V
0°C to 70°C; -40°C to +85°C for IND parts
-40°C to +70°C; -40°C to +85°C for IND parts
+260°C for 10 seconds
(Wave or Hand Solder Only)
This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input Logic 1
Input Logic 0
SYMBOL
VCC
VIH
VIL
MIN
4.5
2.2
0.0
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE ≥ VIH ≤ VCC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE =2.2V
Standby Current CE =VCC -0.5V
Operating Current tCYC= 200ns
(Commercial)
Operating Current tCYC=200ns
(Industrial)
Write Protection Voltage
(TA : See Note 10)
TYP
5.0
MAX
5.5
VCC
+0.8
NOTES
(TA : See Note 10; VCC = 5V ± 10%)
SYMBOL
IIL
IIO
MIN
-1.0
-1.0
IOH
IOL
ICCS1
ICCS2
ICCO1
-1.0
2.0
TYP
3.0
2.0
ICCO1
VTP
MAX
+1.0
+1.0
UNITS
μA
μA
7.0
4.0
75
mA
mA
mA
mA
mA
85
mA
4.25
NOTES
V
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
UNITS
V
V
V
(T A = 25°C)
SYMBOL
CIN
CI/O
MIN
3 of 9
TYP
5
5
MAX
10
12
UNITS
pF
pF
NOTES
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYM
Read Cycle Time
Access Time
tRC
OE to Output
Valid
CE to Output
Valid
OE or CE to
Output Active
Output High-Z
from Deslection
Output Hold from
Address Change
Write Cycle Time
Write Pulse Width
Address Setup
Time
Write Recovery
Time
Output High-Z
from WE
Output Active
from WE
Data Setup Time
Data Hold Time
tACC
DS1220Y-100
MIN MAX
100
100
DS1220Y-120
MIN MAX
120
120
(TA : See Note 10; VCC =5.0V ± 10%)
DS1220Y-150
MIN
MAX
150
150
DS1220Y-200
MIN
MAX
200
200
UNITS
ns
ns
tOE
50
60
70
100
ns
tCO
100
120
150
200
ns
tCOE
5
5
35
tOD
5
35
5
35
35
NOTE
ns
5
ns
5
tOH
5
5
5
5
ns
tWC
tWP
100
75
120
90
150
100
200
150
ns
ns
tAW
0
0
0
0
ns
tWR1
tWR2
0
10
0
10
0
10
0
10
ns
ns
12
13
ns
5
35
tODW
35
35
35
3
tOEW
5
5
5
5
ns
5
tDS
tDH1
tDH2
40
50
60
80
ns
4
0
10
0
10
0
10
0
10
ns
ns
12
13
4 of 9
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
5 of 9
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
CE at VIH before Power-Down
VCC Slew from VTP to 0V
VCC Slew from 0V to VTP
CE at VIH after Power-Up
SYMBOL
tPD
tF
tR
tREC
MIN
0
100
0
MAX
2
UNITS
μs
μs
μs
ms
NOTES
11
(TA = +25°C)
PARAMETER
Expected Data Retention Time
SYMBOL
tDR
MIN
10
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance
state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6 of 9
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
6. If the CE low transition occurs simultaneously with or later than the WE low transition in write
cycle 1, the output buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1220Y is marked with a 4-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined as starting at the date of
manufacture.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage of VCC .
12. tWR1 , tDH1 are measured from WE going high.
13. tWR2 , tDH2 are measured from CE going high.
14. DS1220Y modules are recognized by Underwriters Laboratories (UL®) under file E99151 (R).
DC TEST CONDITIONS
AC TEST CONDITIONS
Outputs open.
All voltages are referenced to ground.
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input:1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION/SELECTOR GUIDE
PART
TEMP RANGE
DS1220Y-100
DS1220Y-100+
DS1220Y-100IND
DS1220Y-100IND+
DS1220Y-120
DS1220Y-120+
DS1220Y-150
DS1220Y-150+
DS1220Y-200
DS1220Y-200+
DS1220Y-200IND
DS1220Y-200IND+
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
SUPPLY
TOLERANCE
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
+ Denotes a lead-free/RoHS-compliant package.
7 of 9
PIN-PACKAGE
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
24 / 720 EMOD
SPEED GRADE
(ns)
100
100
100
100
120
120
150
150
200
200
200
200
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
24 DIP
—
56-G0002-001
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN
MM
J IN.
MM
K IN.
MM
8 of 9
24-PIN
MIN
MAX
1.320
1.340
33.53
34.04
0.695
0.720
17.65
18.29
0.390
0.415
9.91
10.54
0.100
0.130
2.54
3.30
0.017
0.030
0.43
0.76
0.120
0.160
3.05
4.06
0.090
0.110
2.29
2.79
0.590
0.630
14.99
16.00
0.008
0.012
0.20
0.30
0.015
0.021
0.38
0.53
NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added the Package Information table; removed the DIP module
package drawing and dimension table.
7
072808
Added the DIP module package drawing and dimension table.
8
9 of 9
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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