DS1225AD-200+

19-5625; Rev 11/10 DS1225AB/AD 64k Nonvolatile SRAM www.maxim-ic.com FEATURES            PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 8k x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 28-pin DIP package Read and write access times of 70 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full ±10% VCC operating range (DS1225AD) Optional ±5% VCC operating range (DS1225AB) Optional industrial temperature range of -40°C to +85°C, designated IND 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 DQ1 1 2 3 4 5 6 7 8 9 10 11 12 DQ2 13 16 DQ4 GND 14 15 DQ3 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ5 28-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A12 DQ0-DQ7 CE WE OE VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground - No Connect DESCRIPTION The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 10 DS1225AB/AD READ MODE The DS1225AB and DS1225AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A0 -A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1225AD provides full-functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become highimpedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1225AB and 4.5 volts for the DS1225AD. FRESHNESS SEAL Each DS1225 is shipped from Maxim with the lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP , the lithium energy source is enabled for battery backup operation. 2 of 9 DS1225AB/AD ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Commercial: Industrial: Storage Temperature Lead Temperature (soldering, 10s) Note: EDIP is wave or hand soldered only. -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -40°C to +85°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER DS1225AB Power Supply Voltage DS1225AD Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VCC VIH VIL MIN 4.75 4.50 2.2 0.0 TYP 5.0 5.0 MAX 5.25 5.5 VCC +0.8 SYMBOL IIL MIN -1.0 IIO -1.0 IOH IOL ICCS1 ICCS2 -1.0 2.0 TYP MAX +1.0 UNITS µA +1.0 µA 10.0 5.0 mA mA mA mA ICC01 75 mA ICC01 85 mA 5.0 3.0 VTP 4.50 4.62 4.75 V VTP 4.25 4.37 4.5 V CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance UNITS V V V V NOTES (TA: See Note 10) (VCC =5V ± 5% for DS1225AB) (VCC =5V ± 10% for DS1225AD) DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE > VIH< VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE =2.2V Standby Current CE =VCC -0.5V Operating Current (Commercial) Operating Current (Industrial) Write Protection Voltage (DS1225AB) Write Protection Voltage (DS1225AD) (TA: See Note 10) NOTES (TA = +25°C) SYMBOL CIN CI/O MIN 3 of 9 TYP 5 5 MAX 10 10 UNITS pF pF NOTES DS1225AB/AD (TA: See Note 10) (VCC =5V ± 5% for DS1225AB) (VCC =5V ± 10% for DS1225AD) AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 DS1225AB-70 DS1225AD-70 MIN MAX 70 70 35 70 5 25 5 70 55 0 0 10 25 5 30 0 10 4 of 9 UNITS NOTES ns ns ns ns ns ns 5 5 ns ns ns ns ns ns ns ns ns ns ns 3 12 13 5 5 4 12 13 DS1225AB/AD READ CYCLE SEE NOTE 1 WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13 5 of 9 DS1225AB/AD POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING PARAMETER (TA : See Note 10) SYMBOL tPD MIN VCC slew from VTP to 0V tF 300 µs VCC slew from 0V to VTP tR 300 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms VCC Fail Detect to CE and WE Inactive TYP MAX 1.5 UNITS µs NOTES 11 (TA = +25°C) PARAMETER Expected Data Retention Time SYMBOL MIN TYP tDR 10 MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. 6 of 9 DS1225AB/AD NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1225AB and each DS1225AD has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is guaranteed by design and is not 100% tested. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to +85°C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 , tDH1 are measured from WE going high. 13. tWR2 , tDH2 are measured from CE going high. 14. DS1225 modules are recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Cycle = 200ns for Operating Current All Voltages Are Referenced to Ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns 7 of 9 DS1225AB/AD ORDERING INFORMATION PART TEMP RANGE DS1225AB-70+ DS1225AB-70IND+ DS1225AD-70+ DS1225AD-70IND+ 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C SUPPLY TOLERANCE 5V ± 5% 5V ± 5% 5V ± 10% 5V ± 10% PIN-PACKAGE 28 720 EDIP 28 720 EDIP 28 720 EDIP 28 720 EDIP SPEED GRADE (ns) 70 70 70 70 +Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 EDIP MDT28+2 21-0245 — 8 of 9 DS1225AB/AD REVISION HISTORY REVISION DATE 121907 11/10 DESCRIPTION Added package information table; removed the DIP module package drawing and dimension table Updated the storage information, soldering temperature, and lead temperature information in the Absolute Maximum Ratings section; removed the -85, -150, and -200 MIN/MAX information from the AC Electrical Characteristics table; updated the Ordering Information table (removed -85, -150, and -200 parts and leaded -70 parts) 9 of 9 PAGES CHANGED 9 1, 3, 4, 8