19-5636; Rev 11/10
DS1230W
3.3V 256k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Replaces 32k x 8 volatile static RAM,
EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times of 100ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 28-pin DIP package
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ1
1
2
3
4
5
6
7
8
9
10
11
12
DQ2
13
16
DQ4
GND
14
15
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ5
28-Pin Encapsulated Package
740-Mil Extended
NC
NC
NC
NC
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND VBAT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0 - A14
DQ0 - DQ7
CE
WE
OE
VCC
GND
NC
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- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+3.3V)
- Ground
- No Connect
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DS1230W
DESCRIPTION
The DS1230W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized
as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230W devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W
devices in the PowerCap Module package are directly surface mountable and are normally paired with a
DS9034PC PowerCap to form a complete Nonvolatile SRAM Module. There is no limit on the number of
write cycles that can be executed and no additional support circuitry is required for microprocessor
interfacing.
READ MODE
The DS1230W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1230W executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1230W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1230W device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 3.0 volts, the lithium energy source
is enabled for battery back-up operation.
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DS1230W
PACKAGES
The DS1230W is available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM). The 28pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1230W to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230W module base is reflow soldered, a DS9034PC PowerCap is snapped on top
of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230W module bases and DS9034PC PowerCaps are ordered separately and shipped in
separate containers. See the DS9034PC data sheet for further information.
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DS1230W
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
Industrial:
Storage Temperature Range
EDIP
PowerCap
Lead Temperature (soldering, 10s)
Note: EDIP is wave or hand soldered only.
Soldering Temperature (reflow, PowerCap)
-0.3V to +4.6V
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
+260°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
SYMBOL
VCC
MIN
3.0
Logic 1
VIH
Logic 0
VIL
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage Current
(TA: See Note 10)
TYP
3.3
MAX
3.6
UNITS
V
2.2
VCC
V
0.0
0.4
V
(TA: See Note 10) (VCC = 3.3V ±0.3V)
SYMBOL
IIL
MIN
-1.0
I/O Leakage Current CE ≥ VIH ≤ VCC
IIO
-1.0
Output Current @ 2.2V
IOH
-1.0
mA
Output Current @ 0.4V
IOL
2.0
mA
TYP
MAX
+1.0
UNITS
+1.0
µA
µA
Standby Current CE =2.2V
ICCS1
50
250
µA
Standby Current CE =VCC-0.2V
ICCS2
30
150
µA
Operating Current
ICCO1
50
mA
Write Protection Voltage
VTP
3.0
V
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NOTES
2.8
2.9
NOTES
DS1230W
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
(TA = +25°C)
SYMBOL
CIN
MIN
CI/O
AC ELECTRICAL CHARACTERISTICS
TYP
5
MAX
10
UNITS
pF
5
10
pF
NOTES
(TA: See Note 10) (VCC = 3.3V ±0.3V)
DS1230W-100
PARAMETER
SYMBOL
Read Cycle Time
tRC
Access Time
tACC
100
ns
OE to Output Valid
tOE
50
ns
CE to Output Valid
tCO
100
ns
OE or CE to Output Active
tCOE
Output High-Z from Deselection
tOD
Output Hold from Address Change
tOH
5
ns
Write Cycle Time
tWC
100
ns
Write Pulse Width
tWP
75
ns
3
Address Setup Time
tAW
tWR1
tWR2
0
5
20
ns
ns
ns
12
13
ns
5
Write Recovery Time
MIN
MAX
100
UNITS
NOTES
ns
5
35
5
ns
5
Output High-Z from WE
tODW
Output Active from WE
tOEW
5
ns
5
Data Setup Time
tDS
Data Hold Time
tDH1
tDH2
40
0
20
ns
ns
ns
4
12
13
5 of 10
35
ns
DS1230W
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
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DS1230W
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
POWER-DOWN/POWER-UP CONDITION
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DS1230W
POWER-DOWN/POWER-UP TIMING
PARAMETER
(TA: See Note 10)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
1.5
µs
11
VCC Fail Detect to CE and WE Inactive
tPD
VCC slew from VTP to 0V
tF
150
µs
VCC slew from 0V to VTP
tR
150
µs
VCC Valid to CE and WE Inactive
tPU
2
ms
VCC Valid to End of Write Protection
tREC
125
ms
(TA = +25°C)
PARAMETER
Expected Data Retention Time
SYMBOL
tDR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1230W has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. DS1230 modules are recognized by Underwriters Laboratories (UL) under file E99151.
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DS1230W
DC TEST CONDITIONS
AC TEST CONDITIONS
Outputs Open
Cycle = 200ns for operating current
All voltages are referenced to ground
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART
DS1230W-100+
DS1230WP-100+
DS1230W-100IND+
DS1230WP-100IND+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
SUPPLY
TOLERANCE
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
PIN-PACKAGE
28 740 EDIP
34 PowerCap*
28 740 EDIP
34 PowerCap*
SPEED GRADE
(ns)
100
100
100
100
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
28 EDIP
MDT28+3
21-0245
—
34 PCAP
PC2+4
21-0246
—
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DS1230W
REVISION HISTORY
REVISION
DATE
121907
11/10
DESCRIPTION
Added the Ordering Information table; removed the DIP module
package drawing and dimension table
Updated the storage information, soldering temperature, and lead
temperature information in the Absolute Maximum Ratings section;
removed the -150 MIN/MAX information from the AC Electrical
Characteristics table; updated the Ordering Information table
(removed -150 parts and leaded -100 parts); removed the PowerCap
module drawings and updated the Package Information table
10 of 10
PAGES
CHANGED
8
1, 4, 5, 9