DS1250ABP-100+

19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM www.maxim-ic.com FEATURES             PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Replaces 512k x 8 volatile static RAM, EEPROM or Flash memory Unlimited write cycles Low-power CMOS Read and write access times of 70ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full ±10% VCC operating range (DS1250Y) Optional ±5% VCC operating range (DS1250AB) Optional industrial temperature range of -40°C to +85°C, designated IND JEDEC standard 32-pin DIP package PowerCap Module (PCM) package - Directly surface-mountable module - Replaceable snap-on PowerCap provides lithium backup battery - Standardized pinout for all nonvolatile SRAM products - Detachment feature on PCM allows easy removal using a regular screwdriver A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE A0 1 2 3 4 5 6 7 8 9 10 11 12 DQ0 13 20 DQ6 DQ1 DQ2 14 19 15 DQ5 DQ4 GND 16 18 17 DQ7 DQ3 32-Pin ENCAPSULATED PACKAGE 740-mil EXTENDED NC A15 A16 NC VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 GND VBAT 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin POWERCAP MODULE (PCM) (Uese DS9034PC+ or DS9034PCI+ POWERCAP) PIN DESCRIPTION A0 - A18 DQ0 - DQ7 CE WE OE VCC GND NC 1 of 10 - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground - No Connect DS1250Y/AB DESCRIPTION The DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as 524,288 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1250 devices can be used in place of existing 512k x 8 static RAMs directly conforming to the popular byte-wide 32-pin DIP standard. DS1250 devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. READ MODE The DS1250 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs (A0 A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1250 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1250AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1250Y provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become highimpedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1250AB and 4.5 volts for the DS1250Y. FRESHNESS SEAL Each DS1250 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source is enabled for battery back-up operation. 2 of 10 DS1250Y/AB PACKAGES The DS1250 is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control into a module base along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250 PCM device to be surface mounted without subjecting its lithium backup battery to destructive hightemperature reflow soldering. After a DS1250 PCM module base is reflow soldered, a DS9034PC PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper attachment. DS1250 module bases and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for further information. 3 of 10 DS1250Y/AB ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Commercial: Industrial: Storage Temperature EDIP PowerCap Lead Temperature (soldering, 10s) Soldering Temperature (reflow, PowerCap) Note: EDIP is wave or hand soldered only. -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -40°C to +85°C -55°C to +125°C +260°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10) PARAMETER DS1250AB Power Supply Voltage SYMBOL VCC MIN 4.75 TYP 5.0 MAX 5.25 UNITS V DS1250Y Power Supply Voltage VCC 4.5 5.0 5.5 V Logic 1 VIH 2.2 VCC V Logic 0 VIL 0.0 +0.8 V NOTES DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1250AB) (TA: See Note 10) (VCC = 5V ±10% for DS1250Y) PARAMETER Input Leakage Current SYMBOL IIL MIN -1.0 TYP MAX +1.0 UNITS I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA Output Current @ 2.4V IOH -1.0 mA Output Current @ 0.4V IOL 2.0 mA µA Standby Current CE =2.2V ICCS1 200 600 μA Standby Current CE =VCC-0.5V ICCS2 50 150 μA Operating Current ICCO1 85 mA Write Protection Voltage (DS1250AB) VTP 4.50 4.62 4.75 V Write Protection Voltage (DS1250Y) VTP 4.25 4.37 4.5 V CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance NOTES (TA = +25°C) SYMBOL CIN MIN CI/O 4 of 10 TYP 5 MAX 10 UNITS pF 5 10 pF NOTES DS1250Y/AB A C E L E C T R IC A L C HA R A C T E R IS T IC S (VCC = 5V ±5% for DS1250AB) (TA: See Note 10) (VCC = 5V ±10% for DS1250Y) PARAMETER DS1250AB-70 DS1250Y-70 SYMBOL MIN UNITS NOTES MAX Read Cycle Time tRC Access Time tACC 70 ns OE to Output Valid tOE 35 ns CE to Output Valid tCO 70 ns OE or CE to Output Active tCOE Output High-Z from Deselection tOD Output Hold from Address Change tOH 5 ns Write Cycle Time tWC 70 ns Write Pulse Width tWP 55 ns 3 Address Setup Time 0 Write Recovery Time tAW tWR1 tWR2 ns ns ns 12 13 Output High-Z from WE tODW ns 5 Output Active from WE tOEW 5 ns 5 Data Setup Time tDS tDH1 tDH2 30 ns ns ns 4 Data Hold Time 70 ns 5 25 5 15 25 0 10 5 of 10 ns 5 ns 5 12 13 DS1250Y/AB READ CYCLE SEE NOTE 1 WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12 6 of 10 DS1250Y/AB WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13 POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 7 of 10 DS1250Y/AB POWER-DOWN/POWER-UP TIMING PARAMETER (TA: See Note 10) SYMBOL MIN TYP MAX UNITS NOTES 1.5 µs 11 VCC Fail Detect to CE and WE Inactive tPD VCC slew from VTP to 0V tF 150 µs VCC slew from 0V to VTP tR 150 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms (TA = +25°C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1250 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to +85°C. 11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. DS1250 modules are recognized by Underwriters Laboratories (UL) under file E99151. 8 of 10 DS1250Y/AB DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Cycle = 200 ns for operating current All voltages are referenced to ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns ORDERING INFORMATION PART DS1250AB-70+ DS1250ABP-70+ DS1250AB-70IND+ DS1250ABP-70IND+ DS1250Y-70+ DS1250YP-70+ DS1250Y-70IND+ DS1250YP-70IND+ TEMP RANGE 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C SUPPLY TOLERANCE 5V ± 5% 5V ± 5% 5V ± 5% 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% PIN-PACKAGE 32 740 EDIP 34 PowerCap* 32 740 EDIP 34 PowerCap* 32 740 EDIP 34 PowerCap* 32 740 EDIP 34 PowerCap* SPEED GRADE (ns) 70 70 70 70 70 70 70 70 +Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 EDIP MDT32+6 21-0245 — 34 PCAP PC2+5 21-0246 — 9 of 10 DS1250Y/AB REVISION HISTORY REVISION DATE 121907 12/10 DESCRIPTION Added the Package Information table; removed the DIP module package drawing and dimension table Updated the storage information, soldering temperature, and lead temperature information in the Absolute Maximum Ratings section; removed the -100 MIN/MAX information from the AC Electrical Characteristics table; updated the Ordering Information table (removed -100 parts and leaded -70 parts); updated the Package Information table 10 of 10 PAGES CHANGED 8 1, 4, 5, 9