DS1265W-150+

19-5617; Rev 11/10 DS1265W 3.3V 8Mb Nonvolatile SRAM www.maxim-ic.com FEATURES        PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation Read and write access times of 100ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Optional industrial (IND) temperature range of -40°C to +85°C NC NC A18 A16 A14 A12 A7 A6 A5 A4 A3 36 35 34 33 32 31 30 29 28 27 26 25 VCC A19 NC A15 A17 WE A13 A8 A9 A11 OE A2 1 2 3 4 5 6 7 8 9 10 11 12 A1 13 24 CE A0 DQ0 14 23 15 DQ7 DQ6 DQ1 16 22 21 DQ2 17 20 DQ4 GND 18 19 DQ3 A10 DQ5 36-Pin Encapsulated Package 740mil Extended PIN DESCRIPTION A0–A19 DQ0–DQ7 CE WE OE VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+3.3V) - Ground - No Connect DESCRIPTION The DS1265W 8Mb nonvolatile (NV) SRAMs are 8,388,608-bit, fully static, NV SRAMs organized as 1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 DS1265W READ MODE The DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 20 address inputs (A0–A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than tACC. WRITE MODE The DS1265 devices execute a write cycle whenever WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge. DATA-RETENTION MODE The DS1265W provides full functional capability for VCC greater than 3.0V and write protects by 2.8V. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.5V, the power-switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 3.0V. FRESHNESS SEAL Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation. 2 of 8 DS1265W ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Range Commercial: Industrial: Storage Temperature Range Lead Temperature (soldering, 10s) Note: EDIP is wave or hand soldered only. -0.3V to +4.6V 0°C to +70°C -40°C to +85°C -40°C to +85°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power-Supply Voltage SYMBOL VCC MIN 3.0 Logic 1 Input Voltage VIH Logic 0 Input Voltage VIL DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current (TA: See Note 10) TYP 3.3 MAX 3.6 UNITS V 2.2 VCC V 0.0 +0.4 V (TA: See Note 10; VCC = 3.3V ±0.3V) SYMBOL IIL MIN -2.0 I/O Leakage Current IIO -2.0 Output Current at 2.2V IOH -1.0 mA Output Current at 0.4V IOL 2.0 mA TYP MAX +2.0 UNITS +2.0 µA ICCS1 150 250 µA Standby Current CE = VCC - 0.2V ICCS2 100 150 µA Operating Current ICCO1 50 mA Write Protection Voltage VTP 3.0 V 2.8 2.9 CAPACITANCE Input/Output Capacitance NOTES µA Standby Current CE = 2.2V PARAMETER Input Capacitance NOTES (TA = +25°C) SYMBOL CIN CI/O 3 of 8 MIN TYP 10 MAX 20 UNITS pF 10 20 pF NOTES DS1265W AC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 3.3V ±0.3V) DS1265W-100 PARAMETER SYMBOL Read Cycle Time tRC Access Time tACC 100 ns OE to Output Valid tOE 50 ns CE to Output Valid tCO 100 ns OE or CE to Output Active tCOE Output High-Z from Deselection tOD Output Hold from Address Change tOH 5 ns Write Cycle Time tWC 100 ns Write Pulse Width tWP 75 ns 3 Address Setup Time 0 Write Recovery Time tAW tWR1 tWR2 ns ns ns 12 13 Output High-Z from WE tODW ns 5 Output Active from WE tOEW 5 ns 5 Data Setup Time tDS 40 ns 4 Data Hold Time tDH1 tDH2 0 20 ns ns 12 13 MIN 100 MAX 35 5 20 35 SEE NOTE 1 4 of 8 NOTES ns 5 TIMING DIAGRAM: READ CYCLE UNITS ns 5 ns 5 DS1265W TIMING DIAGRAM: WRITE CYCLE 1 TIMING DIAGRAM: WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13 5 of 8 DS1265W POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING (TA: See Note 10) PARAMETER SYMBOL MIN TYP MAX 1.5 UNITS VCC Fail Detect to CE and WE Inactive tPD VCC Slew from VTP to 0V tF 150 µs VCC Slew from 0V to VTP tR 150 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms µs NOTES 11 (TA = +25°C) PARAMETER Expected Data-Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE or WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to, or simultaneously with, the CE low transition, the output buffers remain in a high-impedance state during this period. 6 of 8 DS1265W 9. Each DS1265W has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to+ 70°C. For industrial products (IND), this range is -40°C to +85°C. 11. In a power-down condition, the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. DS1265 modules are recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs open Cycle = 200ns for operating current All voltages are referenced to ground Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0 to 2.7V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns ORDERING INFORMATION PART TEMP RANGE DS1265W-100+ DS1265W-100IND+ 0°C to +70°C -40°C to +85°C SUPPLY TOLERANCE 3.3V ± 0.3V 3.3V ± 0.3V PIN-PACKAGE 36 740 EDIP 36 740 EDIP SPEED GRADE (ns) 100 100 +Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 36 EDIP MDT36+1 21-0245 — 7 of 8 DS1265W REVISION HISTORY REVISION DATE DESCRIPTION PAGES CHANGED 11/10 Updated the storage information, soldering temperature, and lead temperature information in the Absolute Maximum Ratings section; removed the -150 MIN/MAX information from the AC Electrical Characteristics table; updated the Ordering Information table (removed -150 parts and leaded -100 parts); replaced the package outline drawing with the Package Information table 1, 3, 4, 7 8 of 8