DS1742W-150+

DS1742 Y2KC Nonvolatile Timekeeping RAM FEATURES            Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the Eight Top RAM Locations Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness until Power is Applied for the First Time Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Quartz Accuracy ±1 Minute a Month at +25°C, Factory Calibrated Underwriters Laboratories (UL) Recognized ORDERING INFORMATION PART DS1742-85+ DS1742-100+ DS1742-100IND+ DS1742W-120+ DS1742W-150+ VOLTAGE (V) 5.0 5.0 5.0 3.3 3.3 PIN CONFIGURATION TOP VIEW A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 24 2 23 DS1742 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 13 12 VCC A8 A9 WE OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 ENCAPSULATED DIP TEMP RANGE 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 24 EDIP (0.740a) 24 EDIP (0.740a) 24 EDIP (0.740a) 24 EDIP (0.740a) 24 EDIP (0.740a) TOP MARK** DS1742-85+ DS1742-100+ DS1742-100IND+ DS1742W-120+ DS1742W-150+ +Denotes a lead(Pb)-free/RoHS-compliant device. **The top mark will include a “+” on lead(Pb)-free devices. 1 of 17 19-6715; Rev 6/13 DS1742 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 19 22 23 9 10 11 13 14 15 16 17 12 18 20 21 24 NAME A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND CE OE WE VCC 3B FUNCTION Address Input Data Input/Output Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input DESCRIPTION The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1742 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. 2 of 17 DS1742 CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal clock register updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The READ bit must be a zero for a minimum of 500µs to ensure the external registers will be updated. Figure 1. DS1742 BLOCK DIAGRAM Table 1. TRUTH TABLE VCC CE VIH VIL VCC > VPF VIL VIL VSO < VCC < VPF X VCC < VSO < VPF X 0B OE WE X X VIL VIH X X X VIL VIH VIH X X MODE Deselect Write Read Read Deselect Deselect 1B 3 of 17 DQ High-Z Data In Data Out High-Z High-Z High-Z POWER Standby Active Active Active CMOS Standby Data Retention Mode 2B 32B 3B DS1742 SETTING THE CLOCK As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates to the DS1742 registers. The user can subsequently load correct date and time values into all eight registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings into the clock, allowing timekeeping operations to resume from the new set point. Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts updates to the DS1742 registers. The user can subsequently read the date and time values from the eight registers without those contents possibly changing during those I/O operations. A subsequent write cycle of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the previous set-point. The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a write cycle to Control if either the W or R bits are being set to 1 in that write operation. The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write cycle to Control if the W bit is being cleared to 0 in that write operation. The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write cycle to Control if the R bit is being cleared to 0 in that write operation. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable). CLOCK ACCURACY The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. Dallas Semiconductor calibrates the RTC at the factory using nonvolatile tuning elements. The DS1742 does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information, refer to Application Note 58. 4 of 17 DS1742 Table 2. REGISTER MAP ADDRES S B7 B6 B5 7FF 10 Year 7FE X X 7FD 7FC 7FB 7FA 7F9 7F8 X BF X X X FT X OSC W R DATA B4 B3 10 Month 10 Date X X 10 Hour 10 Minutes 10 Seconds 10 Century B2 B1 Year FUNCTION 42B RANGE 43B Year 00–99 Month Month 01–12 Date Day Hour Minutes Seconds Century Date Day Hour Minutes Seconds Control 01–31 01–07 00–23 00–59 00–59 00–39 X X B0 OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG Note: All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock operation. 5 of 17 DS1742 RETRIEVING DATA FROM RAM OR CLOCK The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE , and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE on CE . The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. 6 of 17 DS1742 BATTERY LONGEVITY The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in the absence of VCC power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable. 7 of 17 DS1742 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………..-0.3V to +6.0V Storage Temperature Range………………………………………………………...-40°C to +85°C Soldering Temperature (EDIP, leads)..……………………..+260°C for 10 seconds (See Note 7) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE Commercial Industrial TEMPERATURE 0°C to +70°C (noncondensing) -40°C to +85°C (noncondensing) VCC 3.3V ±10% or 5V ±10% 3.3V ±10% or 5V ±10% RECOMMENDED DC OPERATING CONDITIONS (Over the operating range) PARAMETER Logic 1 VCC = 5V ±10% Voltage VCC = 3.3V (All Inputs) ±10% Logic 0 VCC = 5V ±10% Voltage VCC = 3.3V (All Inputs) ±10% SYMBOL MIN VIH TYP MAX UNITS NOTES 2.2 VCC + 0.3V V 1 VIH 2.0 VCC + 0.3V V 1 VIL -0.3 +0.8 V 1 VIL -0.3 +0.6 V 1 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, Over the operating range.) PARAMETER SYMBOL 4B Active Supply Current TTL Standby Current ( CE = VIH) CMOS Standby Current ( CE ≥VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT = +2.1mA) Write Protection Voltage Battery Switchover Voltage 5B MIN 6B TYP 7B MAX 8B UNITS 9B NOTES 10B ICC 15 50 mA 2, 3 ICC1 1 3 mA 2, 3 ICC2 1 3 mA 2, 3 IIL -1 +1 µA IOL -1 +1 µA VOH 2.4 1 VOL VPF 0.4 4.25 VSO 4.50 VBAT 8 of 17 1 V 1 1, 4 DS1742 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, Over the operating range.) PARAMETER SYMBOL 1B 12B Active Supply Current TTL Standby Current ( CE = VIH) CMOS Standby Current ( CE ≥VCC - 0.2V) Input Leakage Current (any input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT =2.1mA) Write Protection Voltage Battery Switchover Voltage MIN 13B TYP 14B MAX 15B UNITS 16B ICC 10 30 mA 2, 3 ICC1 0.7 2 mA 2, 3 ICC2 0.7 2 mA 2, 3 IIL -1 +1 µA IOL -1 +1 µA VOH 2.4 1 VOL VPF 0.4 2.80 2.97 VBAT or VPF VSO 1 V 1 V 1, 4 AC CHARACTERISTICS—READ CYCLE (5V) (VCC = 5.0V ±10%, Over the operating range.) 85ns ACCESS PARAMETER SYMBOL MIN MAX Read Cycle Time tRC 85 Address Access Time tAA 85 tCEL 5 CE to DQ Low-Z tCEA 85 CE Access Time tCEZ 30 CE Data Off time tOEL 5 OE to DQ Low-Z tOEA 45 OE Access Time tOEZ 30 OE Data Off Time Output Hold from tOH 5 Address 34B NOTES 17B 100ns ACCESS UNITS 35B 9 of 17 MIN 100 MAX 100 5 100 35 5 55 35 5 ns ns ns ns ns ns ns ns ns DS1742 AC CHARACTERISTICS—READ CYCLE (3.3V) (VCC = 3.3V ±10%, Over the operating range.) PARAMETER 36B Read Cycle Time Address Access Time to DQ Low-Z CE Access Time CE Data Off time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address CE SYMBOL 37B tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH 120ns ACCESS MIN MAX 120 120 5 120 40 5 100 35 5 READ CYCLE TIMING DIAGRAM 10 of 17 150ns ACCESS MIN MAX 150 150 5 150 50 5 130 35 5 UNITS ns ns ns ns ns ns ns ns ns DS1742 AC CHARACTERISTICS—WRITE CYCLE (5V) (VCC = 5.0V ±10%, Over the operating range.) PARAMETER SYMBOL 38B Write Cycle Time Address Access Time tWC tAS Pulse Width CE Pulse Width Data Setup Time Data Hold time Address Hold Time tWEW tCEW tDS tDH tAH tWEZ tWR WE WE Data Off Time Write Recovery Time 85ns ACCESS MIN 85 0 65 70 35 0 5 MAX 30 5 100ns ACCESS MIN MAX 100 0 70 75 40 0 5 35 5 UNITS ns ns ns ns ns ns ns ns ns AC CHARACTERISTICS—WRITE CYCLE (3.3V) (VCC = 3.3V ±10%, Over the operating range.) PARAMETER Write Cycle Time Address Setup Time WE Pulse Width Pulse Width Data Setup Time Data Hold Time Address Hold Time CE Data Off Time Write Recovery Time WE SYMBOL 39B tWC tAS tWEW tCEW tDS tDH tAH tWEZ tWR 120ns ACCESS MIN MAX 120 0 100 110 80 0 0 40 10 11 of 17 150ns ACCESS MIN MAX 150 0 130 140 90 0 0 50 10 UNITS ns ns ns ns ns ns ns ns ns DS1742 WRITE CYCLE TIMING DIAGRAM—WRITE-ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM—CHIP-ENABLE CONTROLLED 12 of 17 DS1742 POWER-UP/POWER-DOWN CHARACTERISTICS (5V) (VCC = 5.0V ±10%, Over the operating range.) PARAMETER 18B SYMBOL 19B MIN 20B TYP 21B MAX 2B UNITS 23B tPD 0 µs VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 µs VCC Fall Time: VPF(MIN) to VSO tFB 10 µs VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 µs CE or WE at VIH, Before Power-Down Power-Up Recover Time Expected Data Retention Time (Oscillator On) tREC tDR 35 10 POWER-UP/POWER-DOWN WAVEFORM TIMING (5V DEVICE) 13 of 17 NOTES 24B ms years 5, 6 DS1742 POWER-UP/POWER-DOWN CHARACTERISTICS (3.3V) (VCC = 3.3V ±10%, Over the operating range.) PARAMETER 25B CE or WE at VIH, Before Power- SYMBOL 26B MIN 27B TYP 28B MAX 29B UNITS 30B tPD 0 µs VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 µs VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 µs Down Power-Up Recovery Time tREC Expected Data Retention Time (Oscillator On) tDR 35 10 NOTES 31B ms years 5, 6 POWER-UP/POWER-DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (TA = +25°C) PARAMETER Capacitance on All Input Pins Capacitance on All Output Pins SYMBOL CIN CO MIN 14 of 17 TYP MAX 7 10 UNITS pF pF NOTES DS1742 AC TEST CONDITIONS Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at +25°C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery voltage or VPF. 5) Data retention time is at +25°C. 6) Each DS1742 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 7) Real-time clock modules can be successfully processed through conventional wavesoldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal. 15 of 17 DS1742 PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 EDIP MDF24+1 21-0245 — 16 of 17 DS1742 REVISION HISTORY REVISION DATE 041305 071905 060706 022207 102808 6/13 DESCRIPTION 40B Added “UL Recognized” bullet to Features and new Ordering Information table Added new Pin Description table Updated note for Table 2 updated Operating Temperature Range for Absolute Maximum Ratings Corrected 24-pin to 28-pin package and top mark items in Ordering Information table Removed reference to J-STD-020 and indicated the lead soldering temperature of +260°C for 10 seconds max Added DS1742-85, DS1742-85+ to the Ordering Information table; removed DS1742P-100+ (PowerCap) package Removed the –70 ordering numbers from the Ordering Information table Updated the Ordering Information table and the Setting the Clock section PAGES CHANGED 41B 1 2 4 7 1 7 1 1 1, 4 17 of 17 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.