EVALUATION KIT AVAILABLE
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
General Description
The DS1856 dual, temperature-controlled, nonvolatile
(NV) variable resistors with three monitors consists of
two 256-position, linear, variable resistors; three analog
monitor inputs (MON1, MON2, MON3); and a direct-todigital temperature sensor. The device provides an
ideal method for setting and temperature-compensating
bias voltages and currents in control applications using
minimal circuitry. The variable resistor settings are
stored in EEPROM memory and can be accessed over
the 2-wire serial bus.
Relative to other members of the family, the DS1856 is
essentially a DS1859 with a DS1852-friendly memory
map. In particular, the DS1856 can be configured so
the 128 bytes of internal Auxiliary EEPROM memory is
mapped into Main Device Table 00h and Table 01h,
maintaining compatibility between both the
DS1858/DS1859 and the DS1852. The DS1856 also
features password protection equivalent to the DS1852,
further enhancing compatibility between the two.
Applications
Features
o SFF-8472 Compatible
o Five Monitored Channels (Temperature, VCC,
MON1, MON2, MON3)
o Three External Analog Inputs (MON1, MON2, MON3)
That Support Internal and External Calibration
o Scalable Dynamic Range for External Analog Inputs
o Internal Direct-to-Digital Temperature Sensor
o Alarm and Warning Flags for All Monitored
Channels
o Two Linear, 256-Position, Nonvolatile TemperatureControlled Variable Resistors
o Resistor Settings Changeable Every 2°C
o Three Levels of Security
o Access to Monitoring and ID Information
Configurable with Separate Device Addresses
o 2-Wire Serial Interface
o Two Buffers with TTL/CMOS-Compatible Inputs and
Open-Drain Outputs
o Operates from a 3.3V or 5V Supply
o -40°C to +95°C Operating Temperature Range
Ordering Information
Optical Transceivers
Optical Transponders
Instrumentation and Industrial Controls
RES0/RES1
RESISTANCE
(kΩ)
PART
RF Power Amps
Diagnostic Monitoring
Typical Operating Circuit
VCC
VCC = 3.3V
4.7kΩ
4.7kΩ
1
2-WIRE
INTERFACE
2
3
Tx-FAULT
4
LOS
VCC
SDA
H1
SCL
L1
OUT1
IN1
5
0.1μF
H0
DS1856
L0
IN2
8
15
14
13
12
DECOUPLING
CAPACITOR
DS1856E-050
50/50
16 TSSOP
DS1856E-050/T&R
50/50
16 TSSOP
DS1856B-050
50/50
16 CSBGA
Ordering Information continued at end of data sheet.
+Denotes lead-free package.
T&R denotes tape-and-reel package.
Note: All devices are specified over the -40°C to +95°C temperature range.
Pin Configurations
TO LASER BIAS
CONTROL
TO LASER
MODULATION
CONTROL
TOP VIEW
A
IN1
SCL
VCC
H1
OUT2
6
7
16
MON3
N.C.
MON2
GND
MON1
11 Rx POWER*
10 Tx POWER*
9 Tx BIAS*
B
DIAGNOSTIC
INPUTS
*SATISFIES SFF-8472 COMPATIBILITY
OUT2
SDA
H0
SDA 1
16 VCC
SCL 2
15 H1
OUT1 3
14 L1
L1
IN1 4
C
D
N.C.
GND
1
Visit www.maximintegrated.com/products/patents for
product patent marking information.
PIN-PACKAGE
IN2
L0
2
OUT1
MON1
3
MON3
MON2
DS1856
OUT2 5
13 H0
12 L0
IN2 6
11 MON3
N.C. 7
10 MON2
GND 8
9
MON1
4
CSBGA (4mm x 4mm)
1.0mm PITCH
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
TSSOP
Rev 1; 2/06
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to Ground ...........-0.5V to +6.0V
Voltage Range on Inputs Relative
to Ground* ..............................................-0.5V to (VCC + 0.5V)
Voltage Range on Resistor Inputs Relative
to Ground* ..............................................-0.5V to (VCC + 0.5V)
Current into Resistors............................................................5mA
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020A
*Not to exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.50
V
VCC + 0.3
V
-0.3
+0.3 x VCC
V
-0.3
VCC + 0.3
V
-3
+3
mA
Supply Voltage
VCC
(Note 1)
2.85
Input Logic 1 (SDA, SCL)
VIH
(Note 2)
0.7 x Vcc
Input Logic 0 (SDA, SCL)
VIL
(Note 2)
Resistor Inputs (L0, L1, H0, H1)
Resistor Current
High-Impedance Resistor Current
IRES
IROFF
0.001
Input logic 1
Input Logic Levels (IN1, IN2)
0.1
1.6
Input logic 0
0.9
µA
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
Supply Current
Input Leakage
SYMBOL
ICC
CONDITIONS
MIN
MAX
2
UNITS
mA
-200
+200
nA
(Note 3)
IIL
TYP
1
VOL1
3mA sink current
0
0.4
VOL2
6mA sink current
0
0.6
Full-Scale Input (MON1, MON2,
MON3)
At factory setting
(Note 4)
2.4875
2.5
2.5125
V
Full-Scale VCC Monitor
At factory setting (Note 5)
6.5208
6.5536
6.5864
V
Low-Level Output Voltage
(SDA, OUT1, OUT2)
V
I/O Capacitance
CI/O
10
pF
Digital Power-On Reset
POD
1.0
2.2
V
Analog Power-On Reset
POA
2.0
2.6
V
2
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
ANALOG RESISTOR CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kΩ
Position 00h Resistance (50kΩ)
TA = +25°C
0.65
1.0
1.35
Position FFh Resistance (50kΩ)
TA = +25°C
40
50
60
kΩ
Position 00h Resistance (30kΩ)
TA = +25°C
0.165
0.275
0.400
kΩ
Position FFh Resistance (30kΩ)
TA = +25°C
22.5
30
37.5
kΩ
Position 00h Resistance (20kΩ)
TA = +25°C
0.20
0.40
0.55
kΩ
Position FFh Resistance (20kΩ)
TA = +25°C
15
20
25
kΩ
Position 00h Resistance (10kΩ)
TA = +25°C
0.075
0.125
0.200
kΩ
Position FFh Resistance (10kΩ)
TA = +25°C
7.5
10
12.5
kΩ
Position 00h Resistance (2.5kΩ)
TA = +25°C
0.1
0.175
0.250
kΩ
Position FFh Resistance (2.5kΩ)
TA = +25°C
2.0
2.50
3.0
kΩ
Absolute Linearity
(Note 6)
-2
+2
LSB
Relative Linearity
(Note 7)
-1
Temperature Coefficient
(Note 8)
+1
50
LSB
ppm/°C
ANALOG VOLTAGE MONITORING
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ΔVMON
610
µV
Supply Resolution
ΔVCC
1.6
mV
Input/Supply Accuracy
(MON1, MON2, MON3, VCC)
ACC
Input Resolution
Update Rate for MON1, MON2,
MON3, Temp, or VCC
At factory setting
tframe
Input/Supply Offset
(MON1, MON2, MON3, VCC)
VOS
(Note 14)
0.25
0.5
% FS
(full scale)
47
60
ms
0
5
LSB
TYP
MAX
UNITS
±3.0
°C
DIGITAL THERMOMETER
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
Thermometer Error
SYMBOL
TERR
CONDITIONS
MIN
-40°C to +95°C
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.85V to 5.5V)
PARAMETER
EEPROM Writes
Maxim Integrated
SYMBOL
CONDITIONS
+70°C (Note 14)
MIN
50,000
TYP
MAX
UNITS
Writes
3
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 6.)
PARAMETER
SYMBOL
SCL Clock Frequency (Note 9)
fSCL
Bus Free Time Between STOP and
START Condition (Note 9)
tBUF
Hold Time (Repeated)
START Condition (Notes 9, 10)
tHD:STA
LOW Period of SCL Clock (Note 9)
tLOW
HIGH Period of SCL Clock (Note 9)
tHIGH
Data Hold Time (Notes 9, 11, 12)
tHD:DAT
Data Setup Time (Note 9)
tSU:DAT
START Setup Time (Note 9)
tSU:STA
Rise Time of Both SDA and SCL
Signals (Note 13)
tR
Fall Time of Both SDA and SCL
Signals (Note 13)
tF
Setup Time for STOP Condition
tSU:STO
Capacitive Load for Each Bus Line
CB
EEPROM Write Time
tW
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
4
CONDITIONS
MIN
TYP
MAX
Fast mode
0
400
Standard mode
0
100
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
Fast mode
0
Standard mode
0
Fast mode
100
Standard mode
250
Fast mode
0.6
Standard mode
4.7
µs
µs
µs
0.9
µs
20 + 0.1CB
300
20 + 0.1CB
1000
Fast mode
20 + 0.1CB
300
Standard mode
20 + 0.1CB
300
Standard mode
4.0
µs
ns
Standard mode
0.6
kHz
µs
Fast mode
Fast mode
UNITS
ns
ns
µs
(Note 13)
10
400
pF
20
ms
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the voltage on the inputs is greater than full scale.
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage.
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
See the Typical Operating Characteristics.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns
before the SCL line is released.
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Note 10: After this period, the first clock pulse is generated.
Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 13: CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC.
Note 14: Guaranteed by design.
Typical Operating Characteristics
(VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
SUPPLY CURRENT vs. VOLTAGE
700
50kΩ VERSION
50
700
RESISTANCE (kΩ)
SUPPLY CURRENT (μA)
750
SDA = SCL = VCC
750
RESISTANCE vs. SETTING
60
DS1856 toc02
DS1856 toc01
SDA = SCL = VCC
650
600
550
30
20
500
650
10
450
600
400
-20
0
20
40
60
80
100
0
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
VOLTAGE (V)
RESISTANCE vs. SETTING
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
15
10
5
0
50
100
150
200
250
SETTING (DEC)
800
RESISTOR 0 INL (LSB)
1.0
SDA = VCC
780
0.8
0.6
RESISTOR 0 INL (LSB)
20kΩ VERSION
5.5
DS1856 toc05
DS1856 toc04
20
ACTIVE SUPPLY CURRENT (μA)
-40
RESISTANCE (kΩ)
40
760
740
DS1856 toc06
SUPPLY CURRENT (μA)
800
DS1856 toc03
SUPPLY CURRENT vs. TEMPERATURE
800
0.4
0.2
0
-0.2
-0.4
-0.6
720
-0.8
0
-1.0
700
0
50
100
150
SETTING (DEC)
Maxim Integrated
200
250
0
100
200
300
SCL FREQUENCY (kHz)
400
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
5
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Typical Operating Characteristics (continued)
(VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
RESISTOR 0 DNL (LSB)
RESISTOR 1 INL (LSB)
0
-0.2
-0.4
0.6
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
25 50 75 100 125 150 175 200 225 250
-1.0
0
25 50 75 100 125 150 175 200 225 250
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
SETTING (DEC)
RESISTANCE
vs. POWER-UP VOLTAGE
RESISTANCE
vs. POWER-UP VOLTAGE
POSITION 00h RESISTANCE
vs. TEMPERATURE
50
40
30
20
10
0
100
2
3
POWER-UP VOLTAGE (V)
4
5
50kΩ VERSION
1.00
90
80
70
60
PROGRAMMED
RESISTANCE
(80h)
50
40
30
20
0.99
0.98
0.97
10
0
1
1.01
DS1856 toc11
20kΩ VERSION
RESISTANCE (kΩ)
PROGRAMMED
RESISTANCE
(80h)
60
>1MΩ
110
RESISTANCE (kΩ)
90
80
70
120
DS1856 toc10
50kΩ VERSION
100
0
0
SETTING (DEC)
>1MΩ
110
DS1856 toc09
0.8
DS1856 toc12
0.2
120
RESISTANCE (kΩ)
0.6
RESISTOR 1 DNL (LSB)
0.4
0
6
0.8
RESISTOR 1 INL (LSB)
RESISTOR 0 DNL (LSB)
0.6
1.0
DS1856 toc08
0.8
RESISTOR 1 DNL (LSB)
1.0
DS1856 toc07
1.0
0.96
0
1
2
3
POWER-UP VOLTAGE (V)
4
5
-40 -25 -10
5
20
35
50
65
80
95
TEMPERATURE (°C)
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Typical Operating Characteristics (continued)
(VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
POSITION FFh RESISTANCE
vs. TEMPERATURE
20kΩ VERSION
0.37
50kΩ VERSION
49.75
20.00
DS1856 toc14
50.00
DS1856 toc13
0.38
POSITION FFh RESISTANCE
vs. TEMPERATURE
20kΩ VERSION
19.80
0.35
RESISTANCE (kΩ)
RESISTANCE (kΩ)
RESISTANCE (kΩ)
49.50
0.36
DS1856 toc15
POSITION 00h RESISTANCE
vs. TEMPERATURE
49.25
49.00
48.75
19.60
19.40
48.50
0.34
19.20
48.25
0.33
48.00
5
20
35
50
65
95
80
19.00
-40 -25 -10
TEMPERATURE (°C)
5
20
35
50
-40 -25 -10
50kΩ VERSION
350
300
250
+25°C TO +95°C
+25°C TO -40°C
200
150
100
50
0
-50
-100
100
150
200
5
20
35
50
65
80
95
TEMPERATURE (°C)
800
TEMPERATURE COEFFICIENT (ppm/°C)
DS1856 toc16
TEMPERATURE COEFFICIENT (ppm/°C)
95
TEMPERATURE COEFFICIENT vs. SETTING
TEMPERATURE COEFFICIENT vs. SETTING
50
80
TEMPERATURE (°C)
400
0
65
DS1856 toc17
-40 -25 -10
20kΩ VERSION
700
600
500
+25°C TO +95°C
+25°C TO -40°C
400
300
200
100
0
-100
250
0
SETTING (DEC)
50
100
150
250
200
SETTING (DEC)
DS1856 toc19
DS1856 toc18
+3 SIGMA
+3 SIGMA
2
1
MEAN
MEAN
0
-1
-2
-3 SIGMA
-3
-3 SIGMA
-4
0
25
50
75
NORMALIZED FULL SCALE (%)
Maxim Integrated
LSB ERROR vs. FULL-SCALE INPUT
3
LSB ERROR
LSB ERROR
LSB ERROR vs. FULL-SCALE INPUT
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
100
0
3.125
6.250
9.375
12.500
NORMALIZED FULL SCALE (%)
7
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Pin Description
PIN
BALL
NAME
1
B2
SDA
FUNCTION
2-Wire Serial Data I/O Pin. Transfers serial data to and from the device.
2
A2
SCL
3
C3
OUT1
2-Wire Serial Clock Input. Clocks data into and out of the device.
4
A1
IN1
5
B1
OUT2
6
C2
IN2
TTL/CMOS-Compatible Input to Buffer
7
C1
N.C.
No Connection
8
D1
GND
Ground
9
D3
MON1
External Analog Input
10
D4
MON2
External Analog Input
11
C4
MON3
External Analog Input
12
D2
L0
Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential
less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor
terminals cannot exceed the power-supply voltage, VCC, or go below ground.
13
B3
H0
High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a
potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of
the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground.
14
B4
L1
Low-End Resistor 1 Terminal
15
A4
H1
High-End Resistor 1 Terminal
16
A3
VCC
Supply Voltage
Open-Drain Buffer Output
TTL/CMOS-Compatible Input to Buffer
Open-Drain Buffer Output
Detailed Description
The user can read the registers that monitor the VCC,
MON1, MON2, MON3, and temperature analog signals.
After each signal conversion, a corresponding bit is set
that can be monitored to verify that a conversion has
occurred. The signals also have alarm and warning flags
that notify the user when the signals go above or below
the user-defined value. Interrupts can also be set for
each signal.
8
The position values of each resistor can be independently programmed. The user can assign a unique
value to each resistor for every 2°C increment over the
-40°C to +102°C range.
Two buffers are provided to convert logic-level inputs
into open-drain outputs. Typically, these buffers are
used to implement transmit (Tx) fault and loss-of-signal
(LOS) functionality. Additionally, OUT1 can be asserted
in the event that one or more of the monitored values
go beyond user-defined limits.
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
AD
MD
MD
MD
AD (AUXILIARY DEVICE ENABLE A0h)
EEPROM
128 x 8 BIT
STANDARDS
TABLE
SELECT
DEVICE
ADDRESS
MD (MAIN DEVICE ENABLE)
DEVICE ADDRESS
IF ADEN = 0,
[00h - 7Fh OF AD]
IF ADEN = 1,
[80h-FFh OF MD,
TABLE 00/01h]
ADDRESS
R/W
ADEN ADFIX
SDA
TABLE
SELECT
TABLE
SELECT
EEPROM
72 x 8 BIT
80h-C7h
ADDRESS
ADDRESS
TABLE 04
RESISTOR 0
LOOK-UP
TABLE
R/W
EEPROM
72 x 8 BIT
80h-C7h
TABLE 05
RESISTOR 1
LOOK-UP
TABLE
R/W
ADDRESS
2-WIRE
INTERFACE
ADEN (BIT)
TEMP INDEX
DATA BUS
SCL
TEMP INDEX
R/W
TxF
Tx FAULT
MD
OUT1
MINT
R/W
EEPROM
96 x 8 BIT
00h-5Fh
LIMITS
TxF
SRAM
32 x 8 BIT
60h-7Fh
MONITORS LIMIT
LOW
H0
REGISTER
MONITORS LIMIT
HIGH
ADDRESS
RESISTOR 0
256 POSITIONS
L0
TEMP INDEX
INV1
RxL
OUT2
LOS
H1
REGISTER
IN1
MINT (BIT)
RESISTOR 1
256 POSITIONS
L1
TABLE SELECT
MEASUREMENT
INV2
RIGHT
SHIFTING
WARNING FLAGS
MD
R/W
ALARM FLAGS
INV1 (BIT)
IN2
TABLE SELECT
VCC
INTERNAL
CALIBRATION
INTERNAL
TEMP
ADDRESS
DS1856
MUX
MON1
ADC
12-BIT
DEVICE ADDRESS
INV2 (BIT)
TABLE 03
EEPROM
80h-B7h
ADEN (BIT)
VENDOR
ADFIX (BIT)
MON2
MON3
MONITORS LIMIT HIGH
A/D
CTRL
VCC
MUX
CTRL
MONITORS LIMIT LOW
MINT
MEASUREMENT
INTERRUPT
VCC
GND
MASKING (TMP, VCC, MON1, MON2, MON3)
COMP CTRL
WARNING FLAGS
COMPARATOR
ALARM FLAGS
Figure 1. Block Diagram
Maxim Integrated
9
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Table 1. Scales for Monitor Channels at
Factory Setting
Table 3. Look-Up Table Address for
Corresponding Temperature Values
+FS
SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)
TEMPERATURE
(°C)
CORRESPONDING LOOK-UP
TABLE ADDRESS
Temperature +127.984°
7FFC
-128°C
8000
+102
C7h
Monitor Conversion Example
Monitored Signals
Each signal (VCC, MON1, MON2, MON3, and temperature) is available as a 16-bit value with 12-bit accuracy
(left-justified) over the serial bus. See Table 1 for signal
scales and Table 2 for signal format. The four LSBs
should be masked when calculating the value. The 3
LSBs are internally masked with 0s.
The signals are updated every frame rate (tframe) in a
round-robin fashion.
The comparison of all five signals with the high and low
user-defined values are done automatically. The corresponding flags are set to 1 within a specified time of
the occurrence of an out-of-limit condition.
Calculating Signal Values
The LSB = 100µV for VCC, and the LSB = 38.147µV for
the MON signals when using factory default settings.
Monitor/VCC Bit Weights
MSB
215
214
213
212
211
210
29
28
LSB
27
26
25
24
23
22
21
20
VCC Conversion Examples
10
+98
+100
MSB (BIN)
LSB (BIN)
VOLTAGE (V)
11000000
00000000
1.875
10000000
10000000
1.255
To calculate VCC, convert the unsigned 16-bit value to
decimal and multiply by 100µV.
To calculate MON1, MON2, or MON3, convert the
unsigned 16-bit value to decimal and multiply by
38.147µV.
To calculate the temperature, treat the two’s complement value binary number as an unsigned binary number, then convert to decimal and divide by 256. If the
result is greater than or equal to 128, subtract 256 from
the result.
Temperature: high byte: -128°C to +127°C signed; low
byte: 1/256°C.
Temperature Bit Weights
S
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Temperature Conversion Examples
MSB (BIN)
LSB (BIN)
TEMPERATURE (°C)
01000000
00000000
+64
MSB (BIN)
LSB (BIN)
VOLTAGE (V)
01000000
00001111
+64.059
10000000
10000000
3.29
01011111
00000000
+95
11000000
11111000
4.94
11110110
00000000
-10
11011000
00000000
-40
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Table 4. ADEN Address Configuration
ADEN
(ADDRESS
ENABLE)
NO. OF SEPARATE
DEVICE
ADDRESSES
ADDITIONAL
INFORMATION
0
2
See Figure 2
1
1 (Main Device Only)
See Figure 3
DEC HEX 2-WIRE ADDRRESS A0h
0
0 00h
DEC HEX
0
0
AUXILIARY DEVICE
AUXILIARY DEVICE
ADEN
ADFIX
AUXILIARY
ADDRESS
MAIN ADDRESS
0
0
A0h
A2h
0
1
A0h
EEPROM
(Table 03, 8Ch)
1
0
—
A2h
1
1
—
EEPROM
(Table 03, 8Ch)
2-WIRE ADDRESS A2h (DEFAULT)
00h
MAIN DEVICE
MAIN DEVICE
EEPROM
AUXILIARY MEMORY
(128 BYTES)
Table 5. ADEN and ADFIX Bits
LOWER MEMORY
NOTE 1: ADEN BIT = 0. AUXILIARY MEMORY IS ADDRESSED USING THE AUXILIARY DEVICE
NOTE 1. 2-WIRE SLAVE ADDRESS OF A0h, AND THE REMAINDER OF THE MEMORY IS
NOTE 1. ADDRESSED USING THE MAIN DEVICE 2-WIRE SLAVE ADDRESS OF A2h
NOTE 1. (WHEN ADFIX = 0).
NOTE 2: TABLES 00h, 01h, AND 02h DO NOT EXIST.
PASSWORD ENTRY
(PWE) (4 BYTES)
127
7F
7Fh
127
7F
128
80
183
B7
199
200
C7
C8
TABLE SELECT BYTE 7Fh
80h
80h
80h
TABLE 03h
TABLE 04h
TABLE 05h
CONFIGURATION
TABLE
RESISTOR 0
LOOK-UP TABLE
(72 BYTES)
RESISTOR 1
LOOK-UP TABLE
(72 BYTES)
B7h
C7h
F0h
F0h
RESERVED AND
CALIBRATION
CONSTANTS
255
FF
C7h
RESERVED AND
CALIBRATION
CONSTANTS
FFh
FFh
Figure 2. Memory Organization, ADEN = 0
Variable Resistors
The value of each variable resistor is determined by
a temperature-addressed look-up table, which can
assign a unique value (00h to FFh) to each resistor for
every 2°C increment over the -40°C to +102°C range
(see Table 3). See the Temperature Conversion section
for more information.
The variable resistors can also be used in manual
mode. If the TEN bit equals 0, the resistors are in manual mode and the temperature indexing is disabled.
Maxim Integrated
The user sets the resistors in manual mode by writing
to addresses 82h and 83h in Table 03 to control resistors 0 and 1, respectively.
Memory Description
The memory of the DS1856 is divided into two areas
referred to as the Main Device and the Auxiliary
Device. The Main Device comprises all of the DS1856
specific memory while the Auxiliary Device consists of
128 bytes of general-purpose EEPROM and is especially useful in GBIC applications. Main and Auxiliary
11
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
DEC HEX 2-WIRE ADDRRESS A2h (DEFAULT)
0
0
00h
NOTE 1: ADEN BIT = 1. ALL MEMORY (INCLUDING THE AUXILIARY MEMORY) IS ADDRESSED USING THE
NOTE 1: MAIN DEVICE 2-WIRE SLAVE ADDRESS.
NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY.
NOTE 3: TABLE 02h DOES NOT EXIST.
LOWER MEMORY
PASSWORD ENTRY
(PWE) (4 BYTES)
127
7F
128
80 80h
TABLE SELECT BYTE 7Fh
80h
TABLE 00h/01h
183
B7
199
200
C7
C8
EEPROM
AUXILIARY MEMORY
(128 BYTES)
80h
80h
TABLE 03h
TABLE 04h
TABLE 05h
CONFIGURATION
TABLE
RESISTOR 0
LOOK-UP TABLE
(72 BYTES)
RESISTOR 1
LOOK-UP TABLE
(72 BYTES)
B7h
C7h
F0h
F0h
RESERVED AND
CALIBRATION
CONSTANTS
255
FF
FFh
C7h
RESERVED AND
CALIBRATION
CONSTANTS
FFh
FFh
Figure 3. Memory Organization, ADEN = 1
memories can be accessed by two separate 2-wire
slave addresses (see Table 4). The Main Device
address is A2h (or determined by the value in Table 03,
byte 8Ch, when ADFIX = 1) and the Auxiliary Device
address is A0h (fixed). A configuration bit, ADEN
(Table 03, byte 89h, bit 5), determines whether the
DS1856 uses one or two 2-wire slave addresses. This
feature can be used to save component count in SFF
applications or other applications where both GBIC
and monitoring functions are implemented and two
device addresses are needed.
The memory organization for ADEN = 0 is shown in
Figure 2. In this configuration, the 128 bytes of
Auxiliary Device EEPROM are located at memory locations 00h to 7Fh and accessed using the Auxiliary
Device 2-wire slave address of A0h (fixed). The
remainder of the DS1856’s memory is accessed using
the Main Device address.
The memory organization of the second configuration,
ADEN = 1, is shown in Figure 3. In this configuration, all
12
of the DS1856’s memory including the Auxiliary memory is accessed using only the Main Device address.
The Auxiliary Device memory is mapped into Table 00
and Table 01 in the Main Device. Both tables map to
the same block of physical memory. This is done to
improve the compatibility between previous members
of this IC family such as the DS1858/DS1859 and the
DS1852. In this configuration, the DS1856 ignores communication using the Auxiliary Device address.
The value of the Main Device address can be changed
to a value other than the default value of A2h (see data
sheet Table 5). There can be up to 128 devices sharing
a common 2-wire bus, with each device having its own
unique address. To change the Main Device address,
first write the desired value to the Chip Address byte
(Table 03, byte 8Ch). Then, enable the new address by
setting ADFIX to a 1. Subsequent 2-wire communication must be performed using the new Main Device
address. When ADFIX = 0, the Chip Address byte is
ignored, and the Main Device address is set to A2h.
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
The DS1856 2-wire interface uses 8-bit addressing,
which allows up to 256 bytes to be addressed traditionally on a given 2-wire slave address. However,
since the Main Device contains more than 256 bytes, a
table scheme is used. The lower 128 bytes of the Main
Device, memory locations 00h to 7Fh, function as
expected and are independent of the currently selected table. Byte 7Fh is the Table Select byte. This byte
determines which memory table will be accessed by
the 2-wire interface when address locations 80h to FFh
are accessed. Memory locations 80h to FFh are accessible only through the Main Device address. The
Auxiliary Device address has no access to the tables,
but the Auxiliary Device memory can be mapped into
the Main Device’s memory space (by setting ADEN =
1). Valid values for the Table Select byte are shown in
the table below.
(PWE) bytes located in the Main Device at 7Bh to 7Eh.
The value entered is compared to both the PW1 and
PW2 settings located in Table 03, bytes B0h to B3h and
Table 03, bytes B4h to B7h, respectively, to determine
if access should be granted. Access is granted until
the password is changed or until power is cycled.
Table 6. Table Select Byte
The following table is the legend used in the memory
map to indicate the access level required for read and
write access.
Each table in the following memory map begins with a
higher level view of a particular portion of the memory
showing information such as row (8 bytes) and byte
names. The tables are then followed, where applicable,
by an Expanded Bytes table, which shows bit names
and values. Furthermore, both tables use the permission legend to indicate the access required on a row,
byte, and bit level.
The memory map is followed by a Register Description
section, which describes bytes and bits in further detail.
TABLE SELECT
BYTE
00
TABLE NAME
01
Auxiliary Device Memory
(When ADEN = 1)
02
Does Not Exist
03
Configuration
04
Resistor 0 Look-up Table
05
Resistor 1 Look-up Table
Before attempting to read and write any of the bits or
bytes mentioned in this section, it is important to look at
the memory map provided in a subsequent section to
verify what level of password is required. Password
protection is described in the following section.
Writing PWE can be done with any level of access,
although PWE can never be read.
Writing PW1 and PW2 requires PW2 access. However,
PW1 and PW2 can never be read, even with PW2 access.
On power-up, PWE is set to all 1s (FFFFh). As long as
neither of the passwords are ever changed to FFFFh,
then User access is the power-up default. Likewise,
password protection can be intentionally disabled by
setting the PW2 password to FFFFh.
Memory Map
Table 7. Password Permission
PERMISSION
Password Protection
The DS1856 uses two 4-byte passwords to achieve
three levels of access to various memory locations. The
three levels of access are:
User Access: This is the default state after power-up. It
allows read access to standard monitoring and status
functions.
Level 1 Access: This allows access to customer data
table (Tables 00 and 01) in addition to everything granted by User access. This level is granted by entering
Password 1 (PW1).
Level 2 Access: This allows access to all memory, settings, and features, in addition to everything granted by
Level 1 and User access. This level is granted by entering Password 2 (PW2).
To obtain a particular level of access, the corresponding password must be entered in the Password Entry
Maxim Integrated
READ
WRITE
At least one byte in the row is different than
the rest of the row, so look at each byte
separately for permissions.
all
PW2
all
NA
all
all (The part also writes to
this byte.)
PW2
PW2 + mode_bit
all
all
NA
all
PW1
PW1
PW2
PW2
NA
PW2
PW2
NA
all
PW1
13
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Memory Map
LOWER MEMORY
Row
(hex)
Row
Name
Word 0
Byte 0/8
Word 1
Byte 1/9
Byte 2/A
Word 2
Byte 3/B
Byte 4/C
Word 3
Byte 5/D
Byte 6/E
Byte 7/F
00
08
VCC Alarm Hi
VCC Alarm Lo
VCC Warn Hi
VCC Warn Lo
10
Mon1 Alarm Hi
Mon1 Alarm Lo
Mon1 Warn Hi
Mon1 Warn Lo
18
Mon2 Alarm Hi
Mon2 Alarm Lo
Mon2 Warn Hi
Mon2 Warn Lo
20
Mon3 Alarm Hi
Mon3 Alarm Lo
Mon3 Warn Hi
Threshold0
Temp Alarm Hi
Threshold1
Threshold2
Threshold3
Threshold4
Temp Alarm Lo
Temp Warn Hi
Temp Warn Lo
Mon3 Warn Lo
28
EE
EE
EE
EE
EE
EE
EE
EE
30
EE
EE
EE
EE
EE
EE
EE
EE
38
EE
EE
EE
EE
EE
EE
EE
EE
40
EE
EE
EE
EE
EE
EE
EE
EE
48
EE
EE
EE
EE
EE
EE
EE
EE
50
EE
EE
EE
EE
EE
EE
EE
EE
58
EE
EE
EE
EE
EE
EE
EE
EE
user ROM
user ROM
user ROM
user ROM
user ROM
user ROM
user ROM
60
68
70
78
Values0
Temp Value
Alrm Wrn
Table Select
Alarm1
Reserved
Reserved
Reserved
Warn1
Status
Warn0
Reserved
Reserved
Reserved
Mon2 Value
Reserved
Alarm0
Mon1 Value
Mon3 Value
Vcc Value
Values1
Update
Reserved
PWE msb
Reserved
PWE lsb
Tbl Sel
EXPANDED BYTES
Byte
(hex)
Byte
Name
Bit7
bit15
User EE
Temp Alarm
Temp Warn
14
Bit6
bit14
bit13
EE
Bit5
bit12
bit11
EE
Bit4
bit10
bit9
EE
Bit3
bit8
bit7
EE
Bit2
bit6
bit5
EE
Bit1
bit4
bit3
EE
Bit0
bit2
bit1
EE
bit0
EE
S
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
S
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
2-8
1
2
15
Volt Alarm
2
Volt Warn
215
14
2
2
13
12
2
2
11
10
2
2
9
8
2
2
7
6
2
2
5
4
2
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
20
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
28
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
30
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
38
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
40
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
48
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
50
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
58
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Memory Map (continued)
60
62
Temp Value
VCC Value
26
S
15
14
2
2
14
24
13
12
2
2
2
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
10
9
8
7
6
5
4
3
2
1
20
1
2
2
2
2
2
2
2
20
66
Mon2 Value
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
Mon3 Value
15
14
13
12
11
2
10
9
8
7
6
5
4
3
2
1
20
SoftHiz
2
2
2
Temp Rdy
VCC Rdy
70
Alarm1
Temp Hi
Temp Lo
VCC Hi
VCC Lo
Mon1 Hi
71
Alarm0
Mon3 Hi
Mon3 Lo
Reserved
Reserved
Reserved
74
Warn1
Temp Hi
Temp Lo
VCC Hi
VCC Lo
Mon1 Hi
Mon1 Lo
Mon2 Hi
Mon2 Lo
75
Warn0
Mon3 Hi
Mon3 Lo
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7B
PWE msb
225
223
221
219
217
7F
Tbl Sel
231
230
229
228
227
226
15
14
13
12
11
10
2
2
2
2
7
2
6
2
2
8
2
5
2
224
9
2
4
2
2
Mon3 Rdy
222
7
TxF
Status
Mon2 Rdy
Reserved
2
Update
Mon1 Rdy
Reserved
2
6F
PWE lsb
Reserved
2
2
6E
7D
Rhiz
2
3
2
2
2
4
2
2
2
5
2
2
6
2
2
2
7
2
2
2
8
2
2
2
9
2
2
10
2
2
2
11
2
2
12
11
Mon1 Value
2
13
23
64
68
15
25
Rdyb
Reserved
Reserved
Mon1 Lo
Mon2 Hi
Mon2 Lo
Reserved
Reserved
Mint
6
2
RxL
Reserved
220
5
2
4
2
3
2
2
2
2
218
3
2
2
2
216
1
20
2
1
0
2
2
AUXILIARY (VALID WHEN ADEN = 0)
Row
(hex)
00–7F
Row
Name
EE
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
EE
EE
EE
EE
EE
EE
EE
EE
TABLE 00/01 (VALID WHEN ADEN = 1)
Row
(hex)
80–FF
Row
Name
Maxim Integrated
EE
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
EE
EE
EE
EE
EE
EE
EE
EE
15
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Memory Map (continued)
TABLE 03 (CONFIGURATION)
Row
(hex)
Row
Name
80
88
Config0
Config1
Word 0
Byte 0/8
Word 1
Byte 1/9
Byte 2/A
Mode
Tindex
Int Enable
Config
Word 2
Byte 3/B
Res0
Res1
Reserved
Byte 4/C
Reserved
Reserved
chip addr
Word 3
Byte 5/D
Reserved
Byte 6/E
Reserved
Reserved
Byte 7/F
Reserved
Rshift1
Rshift0
90
Reserved
98
Scale1
Mon3 Scale
Reserved
Reserved
Reserved
A0
Offset0
Reserved
Vcc Offset
MON1 Offset
MON2 Offset
Offset1
MON3 Offset
Reserved
Reserved
Internal Temp Offset*
Pwd Value
PW1 msb
PW1 lsb
PW2 msb
PW2 lsb
A8
B0
Scale0
Vcc Scale
Mon1 Scale
Mon2 Scale
EXPANDED BYTES
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Byte
(hex)
Byte
Name
80
Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TEN
AEN
81
Tindex
27
26
25
24
23
22
21
20
7
6
5
4
3
2
1
20
1
82
bit15
Res0
bit14
bit13
2
bit12
bit11
2
7
bit9
2
6
2
bit10
bit7
2
5
2
bit8
Mon3
Reserved
Reserved
Reserved
Reserved
Inv 1
Inv 2
22
21
Temp
Vcc
Mon1
Mon2
Config
Reserved
Reserved
ADEN
ADFIX
8C
Chip Addr
27
26
25
24
23
Reserved
8F
Rshift0
Reserved
92
94
96
98
A2
VCC Scale
Mon1 Scale
Mon2 Scale
Mon3 Scale
VCC Offset
15
2
15
2
15
2
15
2
S
14
2
14
2
14
2
14
2
S
Mon1
Mon1
Mon32
13
2
13
2
13
2
13
2
15
2
2
12
2
12
2
12
2
14
2
2
11
2
11
2
11
2
13
2
2
10
2
10
2
10
2
12
2
2
9
2
9
2
9
2
11
2
2
8
2
8
2
8
2
10
2
Reserved
7
2
7
2
7
2
7
2
9
2
2
6
2
6
2
6
2
8
2
2
5
2
5
2
5
2
7
2
2
4
2
4
2
4
2
6
2
3
2
3
2
3
2
3
2
5
2
21
20
2
1
20
1
20
1
20
3
22
3
2
2
2
2
2
2
4
2
2
2
2
2
2
2
2
2
2
22
A6
Mon2 Offset
S
S
215
214
213
212
211
210
29
28
27
26
25
24
23
22
S
S
15
14
13
12
11
10
9
8
7
6
5
4
3
22
S
8
-5
2-6
17
216
1
20
17
216
1
20
AE
B0
B2
B4
B6
Temp Offset*
PW1 msb
PW1 lsb
PW2 msb
PW2 lsb
31
2
15
2
31
2
15
2
2
30
2
14
2
30
2
14
2
2
29
2
13
2
29
2
13
2
2
28
2
12
2
28
2
12
2
2
27
2
11
2
27
2
11
2
2
26
2
10
2
26
2
10
2
3
2
25
2
9
2
25
2
9
2
2
2
2
24
2
8
2
24
2
8
2
2
1
2
23
2
7
2
23
2
7
2
2
0
2
22
2
6
2
22
2
6
2
2
-1
2
21
2
5
2
21
2
5
2
2
-2
2
20
2
4
2
20
2
4
2
2
-3
2
19
2
3
2
19
2
3
2
4
2
2
2
5
Reserved
2
2
4
6
Reserved
2
2
7
4
2
5
8
5
2
2
9
6
2
6
10
Reserved
Mon20
Mon2
2
2
11
8
Mon2
S
7
12
9
Reserved
S
2
13
Mon30
10
20
1
Mon1 Offset
Mon3 Offset
14
11
2
A4
A8
15
Mon31
12
2
Mon1
2
2
bit0
Reserved
Int Enable
89
Rshift1
bit1
20
88
8E
bit2
2
2
0
bit3
2
Res1
1
bit4
2
3
83
2
bit5
2
4
2
bit6
2
-4
2
18
2
2
2
18
2
2
2
2
2
2
2
2
2
*The final result must be XOR’ed with BB40h.
16
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Memory Map (continued)
TABLE 04 (LOOKUP TABLE FOR RESISTOR 0)
Row
(hex)
Row
Name
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
C8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
80
88
90
LUT
LUT
LUT
98
A0
A8
B0
B8
C0
LUT
LUT
LUT
LUT
LUT
LUT
F0
F8
Res0 data
Resistor 0 Calibration Constants (see data sheet Table 8)
EXPANDED BYTES
Byte
(hex)
Byte
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
80–C7
Res0
27
26
25
24
23
22
21
20
F8–FF
Res0 data
Maxim Integrated
Resistor 0 Calibration Constants (see data sheet Table 8 for weighting)
17
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Memory Map (continued)
TABLE 05 (LOOKUP TABLE FOR RESISTOR 1)
Row
(hex)
Row
Name
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
C8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
80
88
90
98
A0
A8
B0
B8
C0
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
F0
F8
Res1 data
Resistor 1 Calibration Constants (see data sheet Table 8)
EXPANDED BYTES
Byte
(hex)
Byte
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
80–C7
Res1
27
26
25
24
23
22
21
20
F8–FF
Res1 data
18
Resistor 1 Calibration Constants (see data sheet Table 8 for weighting)
Maxim Integrated
DS1856
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Register Descriptions
Name of Row
•
•
Name of Byte.............
Name of Byte.............
Threshold0
•
•
•
•
Temp High Alarm ..... Temperature measurements above this
two's complement threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
Temp Low Alarm....... Temperature measurements below this
two's complement threshold set its corresponding alarm bit.
Measurements above this threshold clear the alarm bit.
Temp High Warning . Temperature measurements above this
two's complement threshold set its corresponding warning bit.
Measurements below this threshold clear the warning bit.
Temp Low Warning .. Temperature measurements below this
two's complement threshold set its corresponding warning bit.
Measurements above this threshold clear the warning bit.
Threshold1
•
•
•
•
VCC High Alarm........ Voltage measurements of the VCC
input above this unsigned threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
VCC Low Alarm..........
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