19-4883; Rev 2; 8/09
Burst-Mode PON Controller
With Integrated Monitoring
The DS1863 controls and monitors all the burst-mode
transmitter and video receiver biasing functions for a
passive optical network (PON) transceiver. It has an
APC loop with tracking-error compensation that provides the reference for the laser driver’s bias current
and a temperature-indexed lookup table (LUT) that
controls the modulation current. It continually monitors
for high output current, high bias current, and low and
high transmit power with its internal fast comparators to
ensure that laser shutdown for eye safety requirements
are met without adding external components. Five ADC
channels monitor VCC, internal temperature, and three
external monitor inputs (MON1, MON2, MON3) that can
be used to meet transmitter and receive monitoring
requirements.
Applications
BPON, GPON, and GEPON Burst-Mode Transmitters
Features
♦ Meets BPON, GPON, and GEPON Timing
Requirements for Burst-Mode Transceivers
♦ Bias Current Control Provided by APC Loop with
Tracking Error Compensation
♦ Modulation Current Is Controlled by a
Temperature-Indexed Lookup Table
♦ Supports 0dB, -3dB, -6dB Power Leveling
Settings with No Additional Calibration
♦ Internal Direct-to-Digital Temperature Sensor
♦ Five Analog Monitor Channels: Temperature, VCC,
MON1, MON2, and MON3
♦ Comprehensive Fault Management System with
Maskable Laser Shutdown Capability
♦ Two-Level Password Access to Protect
Calibration Data
♦ 120 Bytes of Password 1 (PW1) Protected
Nonvolatile Memory
Laser Control and Monitoring
Broadband Local Access
♦ 128 Bytes of Password 2 (PW2) Protected
Nonvolatile Memory
♦ I2C-Compatible Interface for Calibration and
Monitoring
♦ Operating Voltage: 2.85V to 3.9V
♦ Operating Temperature: -40°C to +95°C
♦ 16-Pin, Lead-Free TSSOP Package
Pin Configuration
Ordering Information
PART
TOP VIEW
+
BEN 1
16 VCC
TX-D 2
15 BMD
N.C. 3
14 MOD
TX-F 4
FETG 5
TEMP RANGE
PIN-PACKAGE
DS1863E+
-40°C to +95°C
16 TSSOP
DS1863E+T&R
-40°C to +95°C
16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
13 BIAS
DS1863
12 GND
SDA 6
11 MON3
SCL 7
10 MON2
GND 8
9 MON1
TSSOP
(173 mils)
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS1863
General Description
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC, SDA and SCL Pin Relative
to Ground....................................................................-0.5V to 6V
Voltage on BEN, TX-D, TX-F, MON1–MON3,
BMD Relative to Ground ...............................-0.5V to VCC + 0.5V
(subject to not exceeding +6V)
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature ...................See J-STD-020 specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
MAX
UNITS
+2.85
3.9
V
VIH:1
0.7 x VCC
VCC + 0.3
V
VIL:1
-0.3
0.3 x VCC
V
High-Level Input Voltage (TX-D)
VIH:2
2.0
VCC + 0.3
V
Low-Level Input Voltage (TX-D)
VIL:2
-0.3
0.8
V
Supply Voltage
VCC
High-Level Input Voltage (SDA, SCL, BEN)
Low-Level Input Voltage (SDA, SCL, BEN)
CONDITIONS
(Note 1)
MIN
TYP
ELECTRICAL CHARACTERISTICS
(VCC= +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
Supply Current
ICC
Output Leakage (SDA, TX-F)
ILO
Low-Level Output Voltage
(SDA, TX-F, FETG)
VOL
High-Level Output Voltage (FETG)
VOH
FETG Before Recall
CONDITIONS
MIN
(Notes 1, 2)
TYP
5
MAX
UNITS
7
mA
1
µA
IOL = 4mA
0.4
IOL = 6mA
0.6
IOH = 4mA (Note 2)
VCC – 0.4
(Note 3)
V
V
10
100
nA
1
µA
Input Leakage Current (SCL, BEN, TX-D)
ILI:1
Digital Power-On Reset
POD
1.0
2.2
V
Analog Power-On Reset
POA
2.1
2.75
V
MAX
UNITS
ANALOG INPUT CHARACTERISTICS (BMD)
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
BMD Full-Scale Voltage Range
SYMBOL
VAPC
CONDITIONS
MIN
TYP
(Note 4)
2.5
V
Resolution
(Note 4)
8
bits
VAPC Error
TA = +25°C (Note 5)
-1.75
+1.75
%FS
VAPC Integral Nonlinearity
-1
+1
LSB
VAPC Differential Nonlinearity
-1
+1
LSB
+2.5
%FS
65
kΩ
VAPC Temp Drift
-2.5
Input Resistance
35
2
_____________________________________________________________________
50.0
Burst-Mode PON Controller
With Integrated Monitoring
(VCC= +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
BIAS Current
IBIAS Shutdown Current
SYMBOL
IBIAS
CONDITIONS
(Note 1)
0.7
VMOD
TYP
MAX
1.2
IBIAS:OFF
Voltage at IBIAS
MOD Full-Scale Voltage
MIN
UNITS
mA
10
100
nA
1.2
1.4
V
(Note 6)
1.25
V
MOD Output Impedance
(Note 7)
3.14
kΩ
VMOD Error
TA = +25°C (Note 8)
-1.25
+1.25
%FS
VMOD Integral Nonlinearity
-1
+1
LSB
VMOD Differential Nonlinearity
-1
+1
LSB
VMOD Temperature Drift
-2
+2
%FS
MAX
UNITS
CONTROL LOOP AND QUICK-TRIP TIMING CHARACTERISTICS
(VCC= +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
First BMD Sample Following BEN
tFIRST
(Note 9)
Remaining Updates During BEN
tREP
(Note 9)
MIN
BEN High Time
tBEN:HIGH
420
BEN Low Time
tBEN:LOW
96
TYP
ns
ns
BIAS and MOD Turn-Off Delay
tOFF
5
µs
BIAS and MOD Turn-On Delay
tON
5
µs
FETG Turn-On Delay
tFETG:ON
5
µs
FETG Turn-Off Delay
tFETG:OFF
5
µs
Binary Search Time
tSEARCH
13
BIAS
Samples
65
ms
MAX
UNITS
ADC Round-Robin Time
(Note 10)
5
tRR
ANALOG VOLTAGE MONITORING
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
ADC Resolution
Input/Supply Accuracy
(MON1, MON2, MON3, VCC)
Update Rate for Temperature, MON1,
MON2, MON3, VCC
Input/Supply Offset
(MON1, MON2, MON3, VCC)
Factory
Setting
TYP
13
ACC
At factory setting
tFRAME:1
VOS
(Note 11)
MON1, MON2, MON3
VCC
MIN
0.25
0.5
%FS
52
70
ms
0
5
LSB
2.5
Full scales are user programmable
Bits
6.5536
V
_____________________________________________________________________
3
DS1863
ANALOG OUTPUT CHARACTERISTICS
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted, see Figure 9.)
PARAMETER
SYMBOL
CONDITIONS
TYP
0
MAX
UNITS
400
kHz
SCL Clock Frequency
fSCL
Clock Pulse-Width Low
tLOW
1.3
µs
Clock Pulse-Width High
tHIGH
0.6
µs
Bus Free Time Between STOP and
START Condition
tBUF
1.3
µs
tHD:STA
0.6
µs
START Setup Time
tSU:STA
0.6
Data-In Hold Time
tHD:DAT
0
Data-In Setup Time
tSU:DAT
100
START Hold Time
(Note 12)
MIN
µs
0.9
µs
ns
Rise Time of Both SDA and
SCL Signals
tR
(Note 13)
20 + 0.1CB
300
ns
Fall Time of Both SDA and
SCL Signals
tF
(Note 13)
20 + 0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
µs
Capacitive Load for Each Bus Line
CB
(Note 13)
400
pF
EEPROM Write Time
tW
(Note 14)
20
ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER
EEPROM Write Cycles
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
4
SYMBOL
CONDITIONS
+70°C
MIN
TYP
MAX
UNITS
50,000
All voltages are referenced to ground. Currents into the IC are positive and out of the IC are negative.
Digital Inputs are at rail. FETG is disconnected SDA = SCL = 1.
See the Safety Shutdown (FETG) Output section for details.
Eight ranges allow the full-scale range to change from 625mV to 2.5V.
This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Eight ranges allow the full-scale range to change from 312.5mV to 1.25V.
The output impedance of the DS1863 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be 1.5kΩ.
This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
See the APC/Quick-Trip Sample Timing section for details.
Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within 4
steps, the bias current will be within 1% within the time specified by the binary search time.
Guaranteed by design.
I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing.
CB—total capacitance of one bus line in picofarads.
EEPROM write begins after a STOP condition occurs.
_____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
SUPPLY CURRENT vs. SUPPLY VOLTAGE
3.40
3.25
+25°C
2.95
-40°C
3.25
VCC = 2.85V
3.20
VCC = 3.9V
3.15
-0.4
3.10
-0.6
3.05
-0.8
2.50
3.00
3.85
4.35
4.85
5.35
-1.0
-40
-20
0
20
40
60
80
100
VCC (V)
TEMPERATURE (°C)
MOD INL
CALCULATED AND DESIRED % CHANGE
IN VMOD vs. MOD RANGING
100
DS1863 toc04
0.6
0.2
0
-0.2
-0.4
CALCULATED VALUE
80
CHANGE IN VMOD (%)
0.4
DESIRED VALUE
90
70
60
50
40
30
70
60
50
40
30
20
10
10
-1.0
0
150
200
MOD INPUT CODE (DEC)
0
250
000 001 010 011 100 101 110 111
000 001 010 011 100 101 110 111
MOD RANGING VALUE (DEC)
COMP RANGING (DEC)
MON1–3 DNL
VBMD INL vs. APC INDEX
MON1–3 INL
0.6
0.6
MON1–3 INL (LSB)
0.4
0.2
0
-0.2
-0.4
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
0.8
0.8
0.6
0.4
0.4
VBMD INL (LSB)
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
1.0
DS1863 toc08
1.0
DS1863 toc07
1.0
0.8
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
0
0.5
1.0
1.5
CALCULATED VALUE
80
-0.8
100
2.0
MON1–3 INPUT VOLTAGE (V)
2.5
250
DESIRED VALUE
90
20
50
100
150
200
MOD INPUT CODE (DEC)
100
-0.6
0
50
DESIRED AND CALCULATED CHANGE
IN VBMD vs. COMP RANGING
CHANGE IN VBMD (%)
0.8
0
DS1863 toc05
3.35
DS1863 toc03
0
-0.2
2.65
1.0
MON1–3 DNL (LSB)
0.2
2.80
2.85
MOD INL (LSB)
0.4
3.30
DS1863 toc09
3.10
0.6
3.35
DS1863 toc06
3.55
0.8
3.40
MOD DNL (LSB)
+95°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
3.70
SDA = SCL = VCC
3.45
MOD DNL
1.0
DS1863 toc02
SDA = SCL = VCC
3.85
SUPPLY CURRENT vs. TEMPERATURE
3.50
DS1863 toc01
4.00
-1.0
0
0.5
1.0
1.5
2.0
MON1–3 INPUT VOLTAGE (V)
2.5
0
50
100
150
APC INDEX (DEC)
200
250
_____________________________________________________________________
5
DS1863
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Pin Description
PIN
6
NAME
DESCRIPTION
1
BEN
Burst Enable Input. Triggers the sampling of the APC and Quick-trip monitors.
2
TX-D
Transmit Disable Input. Disables BIAS and MOD outputs.
3
N.C.
No Connection
4
TX-F
Transmit Fault Output. Open-drain.
5
FETG
Output to FET Gate. Signals an external N or P Channel MOSFET to enable/disable the laser’s current.
6
SDA
I2C Serial Data I/O
7
SCL
I2C Serial Clock Input
8
GND
Ground
9
MON1
10
MON2
11
MON3
12
GND
13
BIAS
Bias Current Output. This current DAC generates the bias current reference for the MAX3643.
14
MOD
Modulation Output Voltage. This 8-bit voltage output has 8 full-scale ranges from 1.25V to 0.3125V.
This pin is connected to the MAX3643’s VMSET input to control the modulation current.
15
BMD
Monitor Diode Input (Feedback Voltage, Transmit Power Monitor)
16
VCC
Power Supply Input
External Analog Inputs. The voltage at these pins is digitized by the internal analog-to-digital converter
and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the
processor based on the ADC result.
Ground
_____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863 MEMORY ORGANIZATION
SDA
LOWER MEMORY
EEPROM/SRAM
I2C
INTERFACE
SCL
TABLE 01h
EEPROM
VCC
GND
SRAM RESET
ADC CONFIG/RESULTS
SYSTEM STATUS BITS
ALARM/WARNING COMPARISON RESULTS/THRESHOLDS
TABLE 02h
EEPROM
TABLE 03h
EEPROM
TABLE 04h
EEPROM
TABLE 05h
EEPROM
PW1
CONFIGURATION
PW2
MODULATION TRACKING
USER MEMORY
AND
USER MEMORY
LUT
ERROR LUT
AND ALARM
CALIBRATION
TRAPS
VCC
POWER ON ANALOG
VCC > VPOA
NONMASKABLE
INTERRUPT
MON1
ANALOG MUX
TX-F
MON2
MON3
13-BIT
ADC
RIGHT
SHIFT
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
TEMP
SENSOR
BEN
INTERRUPT
MASK
LATCH
ENABLE
INTERRUPT
MASK
SAMPLE
CONTROL
INTERRUPT
LATCH
INTERRUPT
LATCH
FETG
MAX BIAS
QUICKTRIP
MUX
BMD
HBIAS QUICK
TRIP LIMIT
MUX
HTXP QUICK
TRIP LIMIT
LTXP QUICK
TRIP LIMIT
MUX
8-BIT DAC
W/SCALING
DIGITAL APC
INTEGRATOR
13-BIT
DAC
BIAS
8-BIT DAC
W/SCALING
MOD
APC SETPOINT FROM
TRACKING ERROR TABLE
DS1863
TX-D
MODULATION LOOKUP
TABLE (TABLE 04h)
_____________________________________________________________________
7
DS1863
Block Diagram
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Typical Operating Circuit
3.3V
IN+
VCC
IN-
OUT+
BEN+
OUT-
BEN-
BIAS-
DIS
MAX3643
COMPACT BURST MODE
LASER DRIVER
BIAS+
MDIN
BIASMON
BENOUT
BEN
VBEST
BIASSET
BIAS
VREF
MODSET
VMSET
MOD
I2C COMMUNICATION
IMAX
GND
MDOUT
SDA
BMD
SCL
MON1
FAULT OUTPUT
TX-F
DISABLE INPUT
TX-D
DS1863
MON2
BURST MODE
MON3
MONITOR/CONTROL CIRCUIT
FETG
Detailed Description
The DS1863 integrates the control and monitoring functionality required to implement a PON system using
Maxim’s MAX3643 compact burst mode laser driver.
The compact laser driver solution offers a considerable
cost benefit by integrating control and monitoring features in low power CMOS process, while leaving only
the high speed portions to the laser driver IC.
APC Control
BIAS current is controlled by an Average Power Control
(APC) loop. The APC loop uses digital techniques to
overcome the difficulties associated with controlling
burst mode systems.
8
TRANSMIT POWER
RECEIVE POWER
The APC loop’s feedback is the monitor diode (BMD)
current, which is converted to a voltage using an external resistor. The feedback voltage is compared to an 8bit scaleable voltage reference, which determines the
APC set point of the system. Scaling of the reference
voltage along with the modulation output can be utilized to implement GPON power leveling.
The DS1863 has a Lookup Table to allow the APC set
point to change as a function of temperature to compensate for Tracking Error (TE). The TE LUT (Table
05h), has 36 entries that determine the APC setting in
4°C windows between -40°C to +100°C.
Ranging of the APC DAC is possible by programming a
single byte in Table 02h.
_____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
The MOD output is an 8-bit scaleable voltage output that
interfaces with the MAX3643’s VMSET input. An external
resistor to ground from the MAX3643’s MODSET pin sets
the maximum current the voltage at VMSET input can
produce for a given output range. This resistor value
should be chosen to produce the maximum modulation
current the laser type requires over temperature. The
modulation LUT can be programmed in 2°C increments
over the -40°C to +102°C range to provide temperature
compensation for the laser’s modulation. The modulation
DAC’s scaling can be used (with APC scaling) to implement GPON power leveling with a single LUT that works
for all three power levels.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h.
BIAS and MOD Output During
Initial Power-Up
On power-up the modulation and bias outputs will
remain off until VCC is above VPOA, a temperature conversion has been completed, and if the VCC LO ADC
alarm is enabled, then a VCC conversion above the
customer defined VCC low alarm level has cleared the
VCC low alarm. Once all of these conditions are satis-
fied, the MOD output will be enabled with the value
determined by the temperature conversion and the
modulation LUT.
When the MOD output is enabled and BEN is high, the
IBIAS DAC output will be turned on to a value equal to
ISTEP (see above). The start-up algorithm checks if this
bias current causes a feedback voltage above the APC
set-point, and if it does not it continues increasing the
I BIAS by I STEP until the APC set-point is exceeded.
When the APC set point is exceeded, the device will
begin a binary search to quickly reach the bias current
corresponding to the proper power level. After the binary search is completed the APC integrator is enabled,
and single LSB steps are taken to tightly control the
average power.
All quick-trip and ADC alarm flags are masked until the
binary search is completed. However, the BIAS MAX
alarm is monitored during this time to prevent the bias
output from exceeding MAX IBIAS. During the bias current initialization, the bias current is not allowed to
exceed MAX IBIAS. If this occurs during the I STEP
sequence then the binary search routine is enabled. If
MAX IBIAS is exceeded during the binary search, then
the next smaller step is activated. ISTEP or binary increments that would cause IBIAS to exceed MAX IBIAS are
not taken. Many of the alarm sources are likely to trip
POWER-UP TIMING
VPOA
VCC
tON
MOD
VOLTAGE
tSEARCH
4x ISTEP
3x ISTEP
BIAS
CURRENT
APC
INTEGRATOR
ON
BINARY SEARCH
2x ISTEP
ISTEP
BIAS
SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. DS1863 Power-Up.
_____________________________________________________________________
9
DS1863
Modulation Control
The MOD voltage is controlled using an internal temperature indexed Lookup Table.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
during start-up. Masking the alarms until the completion
of the binary search prevents false alarms.
ISTEP is programmed by the customer using the Startup Step register. This value should be programmed to
the maximum safe current increase that is allowable
during start-up. If this value is programmed too low, the
DS1863 will still operate, but it could take significantly
longer for the algorithm to converge and hence to control the average power.
If a fault is detected, and TX-D is toggled to re-enable the
outputs, the DS1863 will power up following a similar
sequence to an initial power up. The only difference is
that the DS1863 already has determined the present temperature, so the tINIT time is not required for the DS1863
to recall the APC and MOD set points from EEPROM.
BIAS and MOD Output as a Function
of Transmit Disable (TX-D)
If TX-D is asserted (logic 1) during operation, the outputs will immediately turn off (t OFF ). When TX-D is
deasserted (logic 0), the DS1863 will turn on the MOD
output with the value associated with the present temperature, and initialize the IBIAS using the same search
algorithm as done at start-up. Soft TX-D (Lower
Memory, Register 6Eh) when asserted would allow a
software control identical to the TX-D pin.
SR3–SR0
MINIMUM TIME
REPEATED SAMPLE
FROM BEN TO FIRST
PERIOD FOLLOWING
SAMPLE (tFIRST)
FIRST SAMPLE (tREP)
±50ns
0000b
350ns
800ns
0001b
550ns
1200ns
0010b
750ns
1600ns
0011b
950ns
2000ns
0100b
1350ns
2800ns
0101b
1550ns
3200ns
TX-D TIMING (NORMAL OPERATION)
0110b
1750ns
3600ns
TX-D
0111b
2150ns
4400ns
1000b
2950ns
6000ns
1001b*
3150ns
6400ns
IBIAS
IMOD
tOFF
tOFF
tON
tON
Figure 2. TX-D Timing (Output Disabled During Normal Operating
Conditions).
APC/Quick-Trip Shared Comparator Timing
The DS1863’s input comparator is shared between the
APC control loop and the three quick-trip alarms
(HTXP, LTXP and HBIAS). The comparator polls the
alarms in a round-robin multiplexed sequence. Six of
every eight of the comparator readings will be used for
APC Loop bias current control. The other two updates
will be used to check the HTXP/LTXP (Monitor Diode
voltage) and the HBIAS (MON1) signals against the
10
internal APC and BIAS reference. The HTXP/LTXP comparison will check HTXP if the last bias-update comparison was above the APC set-point, and LTXP if the last
bias update comparison was below the APC set-point.
The DS1863 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable for burst
mode transmitter data rates between 155Mbits/s and
1250Mbits/s. The rising edge of burst enable (BEN) triggers the sample to occur, and the Sample Rate register
determines the delay. The internal clock is asynchronous
to BEN, causing a 100ns uncertainty as to when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples will occur on a regular
interval. The following sample rate options are available.
*All codes greater than 1001b (1010b–111b) use the maximum
sample time of code 1001b.
Comparisons of the HTXP, LTXP, and HBIAS quick-trip
alarms will not occur during the burst enable low time.
Any quick-trip alarm that is detected will by default
remain active until a subsequent comparator sample
shows the condition no longer exists.
A second bias current monitor compares the DS1863’s
bias current DAC’s code to a digital value stored in the
MAX IBIAS register. This comparison is made every
bias current update to ensure that a high bias current
will be quickly detected.
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
APC LOOP/QUICK TRIP SAMPLE TIMING
tFIRST
BEN
BIAS DAC
CODE
LAST BURST'S
BIAS SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
tREP
H/LTXP
SAMPLE
QUICK-TRIP
SAMPLE TIMES
HBIAS
SAMPLE
Figure 3. APC/Quick-Trip Alarm Sample Timing.
Monitors And Fault Detection
Monitors
Monitoring functions on the DS1863 include four quicktrip comparators and five ADC channels
This monitoring combined with the interrupt masks
determines when/if the DS1863 shuts down its outputs
and triggers the TX-F and FETG outputs. All of the monitoring levels and interrupt masks are user programmable with the exception of POA, which trips at a fixed
range and is non-maskable for safety reasons.
Four Quick-Trip Monitors And Alarms
Four quick-trip monitors are provided to detect potential
laser safety issues. These monitor
1) High Bias Current (HBIAS)
2) Low Transmit Power (LTXP)
3) High Transmit Power (HTXP)
quick-trip alarm levels and masks are programmable
through the I2C interface.
Five ADC Monitors And Alarms
The ADC monitors five channels that measure temperature (internal temp sensor), VCC, MON1, MON2, and
MON3 using an analog multiplexer to measure them
round robin with a single ADC. Each channel has a
customer programmable full scale range and offset
value that will be factory programmed to default value
(see below). Additionally, MON1, MON2, and MON3
have the ability to right shift results by up to 7 bits
before the results are compared to alarm thresholds or
read over the I2C bus. This allows customers with specified ADC ranges to calibrate the ADC full scale to a
factor of 1/2n of their specified range to measure small
signals. The DS1863 can then right shift the results by n
bits to maintain the bit weight of their specification.
ADC Default Monitor Full Scale Ranges
4) Max Output Current (MAX IBIAS)
The high and low transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the BMD voltage to determine if the transmit
power is within specification. The HBIAS quick-trip
compares the MON1 input (generally from the
MAX3643 bias monitor output) against its threshold setting to determine if the present bias current is above
specification. The Max Bias quick-trip is a digital comparison that determines if the Bias Output code indicates the bias current is above specification. The bias
current will not be allowed to exceed the value set in
this register. When the DS1863 detects the bias is at
the limit it will set the BIAS MAX status bit and hold the
bias current at the MAX IBIAS level. The quick-trips are
routed to the TX-F and FETG outputs via interrupt
masks to allow combinations of these alarms to be
used to trigger these outputs. Any time FETG is triggered the DS1863 will also disable its outputs. All the
SIGNAL (UNITS)
+ FS
SIGNAL
+ FS
HEX
- FS
SIGNAL
- FS
HEX
Temperature (oC)
127.996
7FFF
-128
8000
VCC (V)
6.5528
FFF8
0V
0000
MON1, MON2,
MON3 (V)
2.4997
FFF8
0V
0000
The ADC results (after right shifting, if used) are compared to high alarm thresholds (to check if the results
exceeded this threshold), the low alarm thresholds (to
check if the ADC results are below this threshold) and
the warning threshold after each conversion (20 comparisons total), and the corresponding alarms are set
which can be used to trigger the TX-F or FETG outputs.
These ADC thresholds are user programmable via the
I2C interface, as are the masking registers that can be
____________________________________________________________________
11
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
used to prevent the alarms from triggering the TX-F and
FETG outputs. See below for more detail on the TX-F
and FETG outputs.
69h. This is true during the setup of internal calibration
as well as during subsequent data conversions.
ADC Timing
There are five analog channels that are digitized in a
round robin fashion in the order shown in Figure 4. The
total time required to convert all five channels is tRR
(see electrical specifications for details).
The TX-F output has masking registers for the five ADC
alarms and the four QT alarms to select which comparisons cause it to assert. In addition, the FETG alarm is
selectable via the TX-F mask to cause TX-F to assert.
All alarms, with the exception of FETG, will only cause
TX-F to remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, soft TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, then it is indicating that the DS1863 is in shutdown, and will require
TX-D, soft TX-D, or cycling power to reset. The ADC
and Quick-trip alarms (with the exception of BIAS MAX)
are ignored for the first 8-10 bias current updates during power up. Only enabled alarms will activate TX-F.
Right Shifting A/D Conversion Result
If the weighting of the ADC digital reading must conform to a Predetermined Full-Scale (PFS) value defined
by a specification, then right shifting can be used to
adjust the PFS analog measurement range while maintaining the weighting of the ADC results. The DS1863’s
range is wide enough to cover all requirements; when
maximum input value is far short of the FS value, right
shifting can be used to obtain greater accuracy. For
instance, the maximum voltage might be 1/8 of the
specified PFS value, so only 1/8 of the converter’s
range is effective over this range. An alternative is to
calibrate the ADC’s full scale range to 1/8 the readable
PFS value and use a right-shift value of 3. With this
implementation, the resolution of the measurement has
increased by a factor of 8, and because the result is
digitally divided by 8 by right shifting, the bit weight of
the measurement still meets the standard.
The right shift operation on the A/D converter results is
carried out based on the contents of Right Shift Control
Registers (Table 02h Registers 8Eh to 8Fh) in EEPROM.
Three analog channels: MON1 to MON3 each have 3
bits allocated to set the number of right shifts. Up to 7
right shift operations are allowed and will be executed
as a part of every conversion before the results are
compared to the high and low alarm levels, or loaded
into their corresponding measurement registers 62h to
Transmit Fault (TX-F) Output
The following table shows TX-F as a function of TX-D
and the alarm sources.
TX-F as a Function of TX-D and Alarm
Sources
VCC > VPOA
TX-D
NON-MASKED
TX-F ALARM
TX-F
No
X
X
1
Yes
0
0
0
Yes
0
1
1
Yes
1
X
0
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
NORMAL ADC SAMPLE TIMING
ONE ROUND-ROBIN ADC CYCLE
MON3
TEMP
VCC
MON1
MON2
MON3
TEMP
VCC
tRR
Figure 4. ADC Round-Robin Timing.
If VCC low alarm is set for either the TX-F or FETG output, the Round Robin timing will cycle between only TEMP and VCC.
12
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
TX-F LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
TX-F NON-LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-F
Figure 5. DS1863 TX-F Timing.
FETG output is always latched in case it is triggered by
an unmasked alarm condition. Its output polarity is programmable to allow an external N or P MOSFET to open
during alarms to shut off the laser diode current. If the
FETG output triggers indicating the DS1863 is in shutdown, then it requires TX-D, soft TX-D, or cycling power
to be reset. Under all conditions when the analog outputs
are re-initialized after being disabled, all the alarms with
the exception of the VCC low ADC alarm will be cleared.
The VCC low alarm must remain active to prevent the output from attempting to operate when inadequate VCC
exists to operate the laser driver. Once adequate VCC is
present to clear the VCC low alarm, the outputs will be
enabled following the same sequence as power up.
As mentioned before the FETG is an output used to disable the laser current via a series N or P MOSFET. This
requires that the FETG output is capable of sinking or
sourcing current. Because the DS1863 will not know if it
should sink or source current before VCC exceeds
VPOA, which triggers the EE recall, this output will be
high impedance when VCC is below VPOA. (see “Low
Voltage Operation” section for details and diagram).
The application circuit must use a pull-up or pull-down
resistor on this pin that pulls FETG to the alarm/shutdown state (high for a PMOS, low for a NMOS). Once
VCC is above VPOA, the DS1863 will pull the FETG output to the state determined by the FETG DIR bit (Table
02h, Register 89h). FETG DIR will be 0 if an NMOS is
used and 1 if a PMOS is used.
FETG and MOD and BIAS Outputs as a
Function of TX-D and Alarm Sources
MOD AND
BIAS
OUTPUTS
VCC >
VPOA
TX-D
NON-MASKED
FETG ALARM
FETG
Yes
0
0
FETG DIR
Enabled
Yes
0
1
FETG DIR
Disabled
Yes
1
X
FETG DIR
Disabled
Determining Alarm Causes
Using The I2C Interface
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1863’s Alarm Trap
Bytes (ATB) through the I2C interface (in Table 01h). The
ATB have a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1863 sets the
corresponding bit in the ATB. Active ATB bits will remain
set until written to zeros via the I2C interface. On power
up the ATB will be zeros until alarms dictate otherwise.
Die Identification
DS1863 will have an ID hard coded to its die. Two registers (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h will read 63h to identify the part as the
DS1863, byte 87h will read to A1h (for A1 die revision).
Low-Voltage Operation
The DS1863 contains two Power-On Reset (POR) levels. The lower level is a Digital POR (V POD) and the
____________________________________________________________________
13
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
FETG/OUTPUT DISABLE TIMING (FAULT CONDITION DETECTED)
DETECTION OF
FETG FAULT
TX-D
IBIAS
tOFF
IMOD
tOFF
FETG
tFETG:ON
tON
tON
tFETG:OFF
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected).
higher level is an Analog POR (V POA ). At start up,
before the supply voltage rises above VPOA, the outputs are disabled (FETG and BIAS outputs are high
impedance, MOD is low), all SRAM outputs are low
(including Shadowed EEPROM), and all analog circuitry is disabled. When V CC reaches VPOA, the SEE is
recalled, and the analog circuitry is enabled. While
VCC remains above VPOA, the device is in its normal
operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls
below VPOA, but is still above VPOD, then the SRAM
will retain the SEE settings from the first SEE recall, but
the device analog will be shut down and the outputs
disabled. FETG will be driven to its alarm state defined
by the FETG DIR bit (Table 02h, Register 89h). If the
supply voltage recovers back above VPOA, then the
device will immediately resume normal functioning. If
the supply voltage falls below VPOD, then the device
SRAM will be placed in its default state and another
SEE recall will be required to reload the nonvolatile settings. The EEPROM recall will occur the next time V CC
next exceeds VPOA. Figure 7 shows the sequence of
events as the voltage varies.
Any time VCC is above VPOD, the I2C interface can be
used to determine if VCC is below the VPOA level. This
is accomplished by checking the RDYB bit in the Status
14
(6Eh) byte. RDYB is set when VCC is below VPOA; when
VCC rises above VPOA RDYB is timed (within 500µs) to
go to 0, at which point the part is fully functional.
For all Device Addresses sourced from EEPROM (Byte
8Ch, Table 01h in memory) the default Device Address
is A2h until V CC exceeds VPOA allowing the device
address to be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the DS1863 in reset until VCC is at a suitable
level (VCC > VPOA) for the part to accurately measure
with its ADC and compare analog signals with its quicktrip monitors. Because VCC cannot be measured by the
ADC when VCC is less than VPOA, POA also asserts the
VCC low alarm, which must be cleared by a VCC ADC
conversion that is greater than the customer programmable VCC low ADC limit. This prevents the TX-F and FETG
outputs from glitching during a slow power up. The TX-F
and FETG output will not latch until there is a conversion
above VCC low limit.
The POA alarm is non-maskable. The TX-F, and FETG
outputs shuts off any time VCC is below VPOA. See Low
Voltage Operation section for more information.
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
SEE RECALL
SEE RECALL
VPOA
VCC
VPOD
FETG
HIGH
IMPEDANCE
SEE*
PRECHARGED
TO 0
NORMAL
OPERATION
DRIVEN TO
FETG DIR
RECALLED
VALUE
HIGH
IMPEDANCE
PRECHARGED
TO 0
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
RECALLED
VALUE
DRIVEN TO
FETG DIR
HIGH
IMPEDANCE
PRECHARGED
TO 0
Figure 7. DS1863 Digital and Analog Power-On Reset.
DS1863 Memory Map
Memory Organization
The DS1863 features six memory banks that include the
following.
The Lower Memory is addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the Table Select byte. The Table Select Byte determines which Table (01h–05h) will be mapped into the
upper memory locations.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as some Alarm and Warning status bytes.
Table 02h is a multifunction space that contains
Configuration registers, scaling and offset values,
Passwords, interrupt registers as well as other miscellaneous control bytes.
Table 03h is strictly user EEPROM that is protected by
a PW2 level password.
Table 04h contains a temperature indexed Look up
Table (LUT) for control of the modulation voltage. The
modulation LUT can be programmed in 2°C increments
over the -40°C to +102°C range. Access to this register
is protected by a PW2 level password.
Table 05h contains another LUT which allows the APC
set point to change as a function of temperature to
compensate for Tracking Error (TE). This TE LUT, has
36 entries that determine the APC setting in 4°C windows between -40°C to 100°C. Access to this register
is protected by a PW2 level password.
Complete detail of each byte’s function, as well as
Read/Write permissions for each Byte for each table is
provided in the Register Descriptions sections.
Shadowed EEPROM
Many nonvolatile (NV) memory locations (listed within
the Detailed Register Description section) are actually
Shadowed-EEPROM which are controlled by the SEEB
bit in Table 02h, Byte 80h.
The DS1863 incorporates Shadowed EEPROM memory
locations for key memory addresses that may be rewritten many times. By default the Shadowed EEPROM
Bit, SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB these locations function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time, tWR. Because changes made with SEEB
enabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-up value
is the last value written with SEEB disabled. This function can be used to limit the number of EEPROM writes
during calibration or to change the monitor thresholds
periodically during normal operation helping to reduce
the number of times EEPROM is written. The Memory
Map description indicates which locations are shadowed-EEPROM.
____________________________________________________________________
15
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
DEC HEX
0
0
I2C SLAVE ADDRESS A2h
00h
LOWER MEMORY
DIGITAL DIAGNOSTIC
FUNCTIONS
PASSWORD ENTRY (PWE)
(4 BYTES)
127
7F
128
80
TABLE SELECT BYTE
7Fh
80h
80h
80h
80h
80h
TABLE 01h
TABLE 02h
TABLE 03h
TABLE 04h
PW1 LEVEL ACCESS
EEPROM
(120 BYTES)
CONFIGURATION AND
CONTROL
PW2 LEVEL ACCESS
EEPROM
(128 BYTES)
MODULATION VOLTAGE
CONTROL TEMPERATURE
INDEXED LUT
C0h
TABLE 05h
TRACKING ERROR LUT
FOR TEMPERATURE
INDEXED CONTROL OF
APC SET-POINT
A7h
C7h
EMPTY
248
F8
255
FF
F7h
MISC. CONTROL BITS
FFh
FFh
FFh
Figure 8. DS1863 Memory Map.
I2C Definitions
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
16
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing diagram for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing diagram for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS
are commonly used during read operations to identify a
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave will return control of SDA to
the master.
Slave Address Byte: Each slave on the I 2 C bus
responds to a slave addressing byte (Figure 10) sent
immediately following a START condition. The slave
address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit.
The DS1863’s slave address can be configured to any
value between 00h to FEh using the Device Address
Byte (Table 02h, Register 8Ch). The user also has to set
the ASEL bit (Table 02h, Register 89h) for this address to
be active. The default address is A2h (see Figure 10). By
writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the
master will read data from the slave. If an incorrect slave
address is written, the DS1863 will assume the master is
communicating with another I2C device and ignore the
communications until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte transmitted during a write operation following the slave
address byte.
SDA
tBUF
tHD:STA
tLOW
tR
tSP
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tSU:STO
tHD:DAT
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 9. I2C Timing Diagram.
____________________________________________________________________
17
DS1863
specific memory address to begin a data transfer. A
repeated START condition is issued identically to a normal START condition. See the timing diagram for
applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (Figure 9). Data is shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock
pulses including when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
MSB
1
LSB
0
1
0
SLAVE
ADDRESS*
0
0
1
R/W
READ/WRITE
BIT
THE DEFAULT SLAVE ADDRESS IS SHOWN, HOWEVER IT CAN BE CHANGED
USING THE DEVICE ADDRESS BYTE (TABLE 02h, BYTE 8Ch)., AND ASEL BIT.
Figure 10. DS1863 Slave Address Byte (Default)
I2C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the byte of data, and generate a
STOP condition. The master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and generates a stop condition. The DS1863 writes 1 to 8 bytes (1
page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte is
sent. The address counter limits the write to one 8-byte
page (one row of the memory map). Attempts to write to
additional pages of memory without sending a stop
condition between pages results in the address counter
wrapping around to the beginning of the present row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respectively,
and the third data byte, 33h, would be written to
address 00h.
To prevent address wrapping from occurring, the master must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new start condition, and write the slave address byte (R/W = 0) and
the first memory address of the next memory row
before continuing to write data.
18
Acknowledge Polling: Any time an EEPROM location
is written, the DS1863 requires the EEPROM write time
(tW) after the STOP condition to write the contents of
the byte of data to EEPROM. During the EEPROM write
time, the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS1863, which allows the next page to be written as
soon as the DS1863 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to write
again to the device.
EEPROM Write Cycles: When EEPROM writes occur to
the memory, the DS1863 will write to all three EEPROM
memory locations, even if only a single byte was modified. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte repeatedly. The DS1863’s EEPROM write cycles are specified in
the NV Memory Characteristics table. The specification
shown is at the worst-case temperature. If zero-crossing
detection is enabled, EEPROM write cycles cannot begin
until after the zero-crossing detection is complete.
Reading a Single Byte from a Slave: To read a single
byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition. When a single
byte is read, it will always be the Potentiometer 0 value.
Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master reads the last byte, it NACKs to indicate the end of
the transfer and generates a STOP condition. The first
byte read will be the Potentiometer 0 Wiper Setting. The
next byte will be the Potentiometer 1 Wiper Setting. The
third byte is the Configuration Register byte. If an ACK
is issued by the master following the Configuration
Register byte, then the DS1863 will send the
Potentiometer 0 Wiper Setting again. This round robin
reading will occur as long as each byte read is followed
by an ACK from the master.
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
This register map shows each byte/word in terms of the
row it is on in the memory. The first byte in the row is
located in memory at the row address (hexadecimal) in
the left most column. Each subsequent byte on the row is
one/ two memory locations beyond the previous
byte/word’s address. A total of eight bytes are present
on each row. For more information about each of these
bytes see the corresponding register description.
LOWER MEMORY
ROW
(HEX)
WORD 0
ROW
NAME
BYTE 0/8
WORD 1
BYTE 1/9
BYTE 2/A
WORD 2
BYTE 3/B
BYTE 4/C
WORD 3
BYTE 5/D
BYTE 6/E
BYTE 7/F
00
TEMP ALARM HI
TEMP ALARM LO
TEMP WARN HI
08
VCC ALARM HI
VCC ALARM LO
VCC WARN HI
VCC WARN LO
10
MON1 ALARM HI
MON1 ALARM LO
MON1 WARN HI
MON1 WARN LO
18
MON2 ALARM HI
MON2 ALARM LO
MON2 WARN HI
MON2 WARN LO
20
MON3 ALARM HI
MON3 ALARM LO
MON3 WARN HI
MON3 WARN LO
28
THRESHOLD0
THRESHOLD1
THRESHOLD2
THRESHOLD3
THRESHOLD4
SHADOWED EE
TEMP WARN LO
SEE
SEE
SEE
SEE
SEE
SEE
SEE
SEE
30
EE
EE
EE
EE
EE
EE
EE
EE
38
EE
EE
EE
EE
EE
EE
EE
EE
40
EE
EE
EE
EE
EE
EE
EE
EE
48
EE
EE
EE
EE
EE
EE
EE
EE
50
EE
EE
EE
EE
EE
EE
EE
EE
58
EE
EE
EE
EE
EE
EE
EE
EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
60
68
70
78
ADC VALUES0
TEMP VALUE
ADC VALUES1
ALARM/WARN
TABLE SELECT
ALARM3
RESERVED
MON1 VALUE
MON3 VALUE
VCC VALUE
RESERVED
ALARM2
ALARM1
RESERVED
WARN3
RESERVED
RESERVED
ALARM0
MON2 VALUE
STATUS
WARN2
UPDATE
RESERVED
PWE MSB
PWE LSB
TBL SEL
Access Code
Read Access
See each
bit/byte
separately
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1863
Hardware
PW2 +
mode bit
All
All
PW1
PW2
PW2
N/A
PW1
Write Access
____________________________________________________________________
19
DS1863
Lower Memory Register Map
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 01h. Register Map
TABLE 01h (PW1)
ROW
(HEX)
ROW
NAME
WORD 0
WORD 1
WORD 2
WORD 3
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
EE
EE
EE
EE
EE
EE
EE
EE
88
EE
EE
EE
EE
EE
EE
EE
EE
90
EE
EE
EE
EE
EE
EE
EE
EE
98
EE
EE
EE
EE
EE
EE
EE
EE
A0
EE
EE
EE
EE
EE
EE
EE
EE
A8
EE
EE
EE
EE
EE
EE
EE
EE
B0
EE
EE
EE
EE
EE
EE
EE
EE
B8
EE
EE
EE
EE
EE
EE
EE
EE
C0
EE
EE
EE
EE
EE
EE
EE
EE
C8
EE
EE
EE
EE
EE
EE
EE
EE
D0
EE
EE
EE
EE
EE
EE
EE
EE
D8
EE
EE
EE
EE
EE
EE
EE
EE
E0
EE
EE
EE
EE
EE
EE
EE
EE
E8
EE
EE
EE
EE
EE
EE
EE
EE
F0
EE
EE
F8
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
PW1 EE
EE
EE
EE
EE
EE
EE
ALARM TRAP
ALARM3
ALARM2
ALARM1
ALARM0
WARN3
WARN2
RESERVED
Access Code
Read Access
See each
bit/byte
separately
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1863
Hardware
PW2 +
mode bit
All
All
PW1
PW2
PW2
N/A
PW1
Write Access
20
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
TABLE 02h (PW2)
ROW
(HEX)
WORD 0
ROW
NAME
80
88
BYTE 0/8
CONFIG0
CONFIG1
MODE
UPDATE
RATE
WORD 1
BYTE 1/9
BYTE 2/A
TINDEX
MOD DAC
START-UP
STEP
CONFIG
WORD 2
BYTE 3/B
APC DAC
MOD
RANGING
BYTE 4/C
WORD 3
BYTE 5/D
BIAS DAC2
DEVICE
ADDRESS
BIAS DAC2
COMP
RANGING
BYTE 6/E
BYTE 7/F
DEVICE ID
DEVICE VER
RSHIFT1
RSHIFT0
90
RESERVED
VCC SCALE
MON1 SCALE
98
SCALE1
MON3 SCALE
RESERVED
RESERVED
RESERVED
OFFSET0
RESERVED
VCC OFFSET
MON1 OFFSET
MON2 OFFSET
OFFSET1
MON3 OFFSET
RESERVED
RESERVED
INTERNAL TEMP OFFSET*
PWD VALUE
PW1 MSB
PW1 LSB
PW2 MSB
A0
A8
SCALE0
B0
B8
INTERRUPT
C0-F7
F8
MAN IBIAS
PW2 LSB
FETG EN1
FETG EN0
TX-F EN1
TX-F EN0
HTXP
LTXP
HBIAS
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
MAN IBIAS0
MAN IBIAS1
MAN_CNTL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
EMPTY
MON2 SCALE
MAX IBIAS
*The Final Result must be XOR’ed with BB40h before writing to this register.
Access Code
Read Access
See each
bit/byte
separately
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1863
Hardware
PW2 +
mode bit
All
All
PW1
PW2
PW2
N/A
PW1
Write Access
____________________________________________________________________
21
DS1863
Table 02h. Register Map
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 03h. Register Map
TABLE 03h (PW2)
ROW
(HEX)
ROW
NAME
WORD 0
WORD 1
WORD 2
WORD 3
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
EE
EE
EE
EE
EE
EE
EE
EE
88
EE
EE
EE
EE
EE
EE
EE
EE
90
EE
EE
EE
EE
EE
EE
EE
EE
98
EE
EE
EE
EE
EE
EE
EE
EE
A0
EE
EE
EE
EE
EE
EE
EE
EE
A8
EE
EE
EE
EE
EE
EE
EE
EE
B0
EE
EE
EE
EE
EE
EE
EE
EE
B8
EE
EE
EE
EE
EE
EE
EE
EE
C0
EE
EE
EE
EE
EE
EE
EE
EE
C8
EE
EE
EE
EE
EE
EE
EE
EE
D0
EE
EE
EE
EE
EE
EE
EE
EE
D8
EE
EE
EE
EE
EE
EE
EE
EE
E0
EE
EE
EE
EE
EE
EE
EE
EE
E8
EE
EE
EE
EE
EE
EE
EE
EE
F0
EE
EE
EE
EE
EE
EE
EE
EE
F8
EE
EE
EE
EE
EE
EE
EE
EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
PW2 EE
Access Code
Read Access
See each
bit/byte
separately
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1863
Hardware
PW2 +
mode bit
All
All
PW1
PW2
PW2
N/A
PW1
Write Access
22
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
TABLE 04h (LUT FOR MOD)
ROW
(HEX)
ROW
NAME
WORD 0
WORD 1
WORD 2
WORD 3
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
88
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
90
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
98
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
A0
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
A8
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
B0
LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
B8
LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
C0
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
Table 05h. Register Map
TABLE 05h (LUT FOR APC)
ROW
(HEX)
ROW
NAME
WORD 0
WORD 1
WORD 2
WORD 3
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
88
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
90
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
98
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
A0
APC REF
APC REF
APC REF
APC REF
RESERVED
RESERVED
RESERVED
RESERVED
LUT5
LUT5
LUT5
LUT5
LUT5
Access Code
Read Access
See each
bit/byte
separately
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1863
Hardware
PW2 +
mode bit
All
All
PW1
PW2
PW2
N/A
PW1
Write Access
____________________________________________________________________
SPRINGER
23
DS1863
Table 04h. Register Map
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Registers Description
Lower Memory Register 00h to 01h: Temp Alarm Hi
FACTORY DEFAULT:
7FFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
00h
01h
S
-1
2
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
2-8
2
2
2
2
2
2
bit7
bit0
Temperature measurements above this 2’s complement threshold will set its corresponding alarm bit. Measurements equal to or
below this threshold will clear its alarm bit.
Lower Memory Register 02h to 03h: Temp Alarm Lo
FACTORY DEFAULT:
8000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
02h
03h
S
-1
2
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
2-8
2
2
2
2
2
2
bit7
bit0
Temperature measurements above this 2’s complement threshold will set its corresponding alarm bit. Measurements equal to or
below this threshold will clear its alarm bit.
Lower Memory Register 04h to 05h: Temp Warn Hi
FACTORY DEFAULT:
7FFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
04h
05h
S
-1
2
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
2-8
2
2
2
2
bit7
2
2
bit0
Temperature measurements above this 2’s complement threshold will set its corresponding warning bit. Measurements equal to or
below this threshold will clear its warning bit.
24
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory Register 06h to 07h: Temp Warn Lo
FACTORY DEFAULT:
8000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
06h
07h
S
-1
2
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
2-8
2
2
2
2
2
2
bit7
bit0
Temperature measurements below this 2’s complement threshold will set its corresponding warning bit. Measurements above this
threshold will clear its warning bit.
Lower Memory Register 08h to 09h: VCC Alarm Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
08h
09h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the VCC input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 0Ah to 0Bh: VCC Alarm Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
0Ah
0Bh
Nonvolatile (SEE)
15
2
7
2
bit7
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the VCC below above this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
____________________________________________________________________
25
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 0Ch to 0Dh: VCC Alarm Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
0Ch
0Dh
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the VCC input above this unsigned threshold will set its corresponding warning bit. Measurements below
this threshold will clear its warning bit.
Lower Memory Register 0Eh to 0Fh: VCC Warn Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
0Eh
0Fh
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the VCC below above this unsigned threshold will set its corresponding warning bit. Measurements above
this threshold will clear its warning bit.
Lower Memory Register 10h to 11h: MON1 Alarm Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
10h
11h
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
bit7
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the MON1 input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
26
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory Register 12h to 13h: MON1 Alarm Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
12h
13h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON1 input below this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
Lower Memory Register 14h to 15h: MON1 Warn Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
14h
15h
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON1 input above this unsigned threshold will set its corresponding warning bit. Measurements
below this threshold will clear its warning bit.
Lower Memory Register 16h to 17h: MON1 Warn Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
15
16h
2
214
213
212
211
210
29
28
17h
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurements of the MON1 input below this unsigned threshold will set its corresponding warning bit. Measurements
above this threshold will clear its warning bit.
____________________________________________________________________
27
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 18h to 19h: MON2 Alarm Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
18h
19h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON2 input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 1Ah to 1Bh: MON2 Alarm Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
1Ah
1Bh
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON2 input below this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
Lower Memory Register 1Ch to 1Dh: MON2 Alarm Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
1Ch
1Dh
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
bit7
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the MON2 input above this unsigned threshold will set its corresponding warning bit. Measurements
below this threshold will clear its warning bit.
28
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory Register 1Eh to 1Fh: MON2 Warn Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
1Eh
1Fh
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON2 input below this unsigned threshold will set its corresponding warning bit. Measurements
above this threshold will clear its warning bit.
Lower Memory Register 20h to 21h: MON3 Alarm Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
20h
21h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON3 input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 22h to 23h: MON3 Alarm Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
22h
23h
215
7
2
bit7
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the MON3 input below this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
____________________________________________________________________
29
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 24h to 25h: MON3 Warn Hi
FACTORY DEFAULT:
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
24h
25h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON3 input above this unsigned threshold will set its corresponding warning bit. Measurements
below this threshold will clear its warning bit.
Lower Memory Register 26h to 27h: MON3 Warn Lo
FACTORY DEFAULT:
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
26h
27h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON3 input below this unsigned threshold will set its corresponding warning bit. Measurements
above this threshold will clear its warning bit.
Lower Memory Register 28h to 2Fh: Shadowed EEPROM
FACTORY DEFAULT:
00h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
28h-2Fh
SEE
SEE
SEE
SEE
SEE
SEE
SEE
bit7
Shadowed EEPROM memory (see details in Memory Map section). PW2 level access controlled ROM data for end user.
30
____________________________________________________________________
SEE
bit0
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory Register 30h to 5Fh: PW2 EE
FACTORY DEFAULT:
00h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (EE)
30h-5Fh
EE
EE
EE
EE
EE
EE
EE
bit7
EE
bit0
Nonvolatile EEPROM memory. PW2 level access controlled ROM data for end user.
Lower Memory Register 60h to 61h: Temp Value
POWER-ON VALUE
0000h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
60h
S
-1
61h
2
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
2-8
2
2
2
2
2
2
bit7
bit0
Signed 2’s complement Direct-to-Temperature measurement.
Lower Memory, Register 62h–63h: VCC Value
Lower Memory, Register 64h–65h: MON1 Value
Lower Memory, Register 66h–67h: MON2 Value
Lower Memory, Register 68h–69h: MON3 Value
POWER-ON VALUE
0000h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
62h
63h
215
7
2
6
2
5
2
4
2
3
2
2
2
28
1
20
9
2
2
2
2
28
65h
27
26
25
24
23
22
21
20
9
28
1
2
2
2
2
2
2
20
68h
215
214
213
212
211
210
29
28
1
20
2
bit7
2
2
2
3
2
2
2
2
4
3
2
2
5
4
2
2
6
5
2
2
7
6
10
67h
69h
7
11
10
29
2
12
11
210
2
13
12
211
2
14
13
212
2
15
14
213
64h
66h
15
214
2
2
2
bit0
Unsigned voltage measurement.
____________________________________________________________________
31
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory, Register 6Ah to 6D: Reserved
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
These registers are reserved. The value when read is 00h.
Lower Memory, Register 6Eh: Status
POWER-ON VALUE
x000 0x0x b
READ ACCESS
All
WRITE ACCESS
See Below
MEMORY TYPE
Volatile
Write
Access
6Eh
N/A
All
N/A
All
All
N/A
N/A
N/A
FETG
STATUS
SOFT
FETG
RESERVED
TX-F
RESET
SOFT
TX-D
TX-F
STATUS
RESERVED
RDYB
bit7
bit0
bit7
FETG STATUS: Reflects the active state of FETG.
0 = Bias and modulation outputs are enabled.
1 = The FETG output is asserted to disable the bias and modulation outputs.
bit6
SOFT FETG:
0 = (Default)
1 = Force the bias and modulation outputs to their off states and asserts the FETG output.
bit5
Reserved (Default = 0)
bit4
bit3
TX-F RESET:
0 = Does not affect the TX-F output (Default).
1 = Resets the latch for the TX-F output.
This bit is self clearing after the reset.
SOFT TX-D: This bit allows a software control that is identical to the TX-D pin. Please see section on
TX-D for further information. It’s value is wired OR’ed with the logic value on TX-D pin.
0 = Internal TX-D signal is equal to external TX-D pin.
1 = Internal TX-D signal is high.
TX-F STATUS: Reflects the active state of TX-F.
bit2
0 = TX-F pin is not active.
1 = TX-F pin is active.
bit1
RESERVED (Default = 0)
RDYB: Ready Bar.
bit0
0 = VCC is above POA.
1 = VCC is below POA or too low to communicate over the I2C bus.
32
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory, Register 6Fh: Update
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
All + DS1863 Hardware
MEMORY TYPE
Volatile
6Fh
TEMP RDY
VCC RDY
MON1 RDY
MON2 RDY
MON3 RDY
bit7
RESERVED
RESERVED
RESERVED
bit0
Status of completed conversions. At Power-On, these bits are cleared and will be set as each conversion is completed. These bits
can be cleared so that a completion of a new conversion is verified.
bit7
TEMP RDY:
0 = Temperature conversion is not ready (Default).
1 = Temperature conversion is ready.
VCC RDY:
bit6
0 = VCC conversion is not ready (Default).
1 = VCC conversion is ready.
bit5
MON1 RDY:
0 = MON1 conversion is not ready (Default).
1 = MON1 conversion is ready.
bit4
MON2 RDY:
0 = MON2 conversion is not ready (Default).
1 = MON2 conversion is ready.
bit3
MON3 RDY:
0 = MON3 conversion is not ready (Default).
1 = MON3 conversion is ready.
bit2:0
RESERVED
____________________________________________________________________
33
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory, Register 70h: Alarm3
POWER-ON VALUE
10h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
70h
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
bit7
MON2 HI
MON2 LO
bit0
Alarm Status Bits
bit7
TEMP HI: High Alarm Status for Temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit6
TEMP LO: Low Alarm Status for Temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
VCC HI: High Alarm Status for VCC measurement.
bit5
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit4
bit3
VCC LO: Low Alarm Status for VCC measurement. This bit is set when the VCC supply is below the
POA trip point value. It will clear itself when a VCC measurement is completed and the value is above
the low threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
MON1 HI: High Alarm Status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit2
bit1
MON1 LO: Low Alarm Status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
MON2 HI: High Alarm Status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit0
34
MON2 LO: Low Alarm Status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory, Register 71h: Alarm2
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
71h
MON3 HI
MON3 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit7
RESERVED
RESERVED
bit0
Alarm Status Bits
bit7
MON3 HI: High Alarm Status for MON3 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit6
bit5:0
MON3 LO: Low Alarm Status for MON3 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
RESERVED
____________________________________________________________________
35
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory, Register 72h: Alarm1
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
72h
RESERVED
RESERVED
RESERVED
RESERVED
BIAS HI
RESERVED
TX-P HI
bit7
TX-P LO
bit0
Alarm Status Bits
bit7:4
RESERVED
BIAS HI: High Alarm Status Bias; Fast Comparison.
bit3
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit2
RESERVED
bit1
TX-P HI: High Alarm Status TX-P; Fast Comparison.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit0
TX-P LO: Low Alarm Status TX-P; Fast Comparison.
0 = Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
Lower Memory, Register 73h: Alarm0
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
73h
RESERVED
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
bit7
bit3
RESERVED
BIAS MAX: Maximum digital setting for IBIAS.
0 = (Default) The value of IBIAS is equal to or below MAX IBIAS setting.
1 = Requested value of IBIAS is greater than MAX IBIAS setting.
bit2:0
36
RESERVED
bit0
Alarm Status Bits
bit7:4
RESERVED
RESERVED
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory, Register 74h: Warn3
POWER-ON VALUE
10h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
74h
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
bit7
MON2 HI
MON2 LO
bit0
Warning Status Bits
bit7
TEMP HI: High Warning Status for Temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit6
TEMP LO: Low Warning Status for Temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit5
VCC HI: High Warning Status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit4
VCC LO: Low Warning Status for VCC measurement. This bit is set when the VCC supply is below the
POA trip point value. It will clear itself when a VCC measurement is completed and the value is above
the low threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
bit3
MON1 HI: High Warning Status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit2
MON1 LO: Low Warning Status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit1
MON2 HI: High Warning Status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit0
MON2 LO: Low Warning Status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
____________________________________________________________________
37
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory, Register 75h: Warn2
POWER-ON VALUE
10h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
75h
MON3 HI
MON3 LO
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
bit7
RESERVED
bit0
Warning Status Bits
bit7
MON3 HI: High Warning Status for Mon3 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit6
MON3 LO: Low Warning Status for Mon3 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit5
RESERVED
Lower Memory, Register 76h to 7Ah: Reserved
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
These registers are reserved. The value when read is 00h.
Lower Memory, Register 7Bh to 7Eh: Password Entry (PWE)
FACTORY DEFAULT
FFFF FFFFh
READ ACCESS
N/A
WRITE ACCESS
All
MEMORY TYPE
Volatile
7Bh
231
230
229
228
227
226
225
224
7Ch
23
22
21
20
19
18
17
216
9
2
15
2
14
2
13
2
12
2
11
2
2
7Dh
2
2
2
2
2
2
2
28
7Eh
27
26
25
24
23
22
21
20
bit7
10
bit0
Password Entry. There are two passwords for the DS1863. Each password is 4 bytes long. The lower level password (PW1) will
have all the access of a normal user plus those made available with PW1. The higher level password (PW2) will have all of the
access of PW1 plus those made available with PW2. The values of the passwords reside in EE inside of PW2 memory. At Power up
all PWE bits are set to 1. All reads to this location are 0.
38
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Lower Memory Register 7Fh: Table Select (TBL SEL)
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
All
MEMORY TYPE
7Fh
Volatile
7
2
bit7
26
25
24
23
22
21
20
bit0
The upper memory tables (Table 01h–Table 05h) of the DS1863 are accessible by writing the correct table value in this register.
____________________________________________________________________
39
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 01h, Registers
Table 01h, Register 80h to F7h: PW1 EEPROM
POWER-ON VALUE
00h
READ ACCESS
PW1
WRITE ACCESS
PW1
MEMORY TYPE
Nonvolatile(EE)
80h-F7h
EE
EE
EE
EE
EE
EE
EE
bit7
EE
bit0
EEPROM for PW1 level access.
Table 01h, Register F8h: Alarm3
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
F8h
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
bit7
MON2 LO
bit0
Layout is identical to Alarm3 in Lower Memory Register 70h with two exceptions.
1.
VCC Low alarm is not set at power-on.
2.
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register F9h: Alarm2
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
F9h
MON3 HI
MON3 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit7
Layout is identical to Alarm2 in Lower Memory Register 71h with one exception.
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
40
____________________________________________________________________
RESERVED
RESERVED
bit0
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 01h, Register FAh: Alarm1
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
FAh
BIAS HI
TX-P HI
TX-P LO
RESERVED
RESERVED
RESERVED
RESERVED
bit7
RESERVED
bit0
Layout is identical to Alarm1 in Lower Memory Register 72h with one exception.
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FBh: Alarm0
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
72h
RESERVED
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
RESERVED
bit7
RESERVED
bit0
Layout is identical to Alarm0 in Lower Memory Register 73h with one exception.
1.
These bits are latched. They are cleared by power-down or a write with PW1 access
Table 01h, Register FCh: Warn3
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
FCh
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
bit7
MON2 HI
MON2 LO
bit0
Layout is identical to Warn3 in Lower Memory Register 74h with two exceptions.
1.
VCC Low Warning is not set at power-on.
2.
These bits are latched. They are cleared by power-down or a write with PW1 access.
____________________________________________________________________
41
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 01h, Register FDh: Warn2
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
FDh
MON3 HI
MON3 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit7
Table 01h, Register FEh to FFh: Reserved
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
These registers are reserved.
42
RESERVED
bit0
Layout is identical to Warn2 in Lower Memory Register 75h with one exception.
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
POWER-ON VALUE
RESERVED
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Registers
Table 02h, Register 80h: Mode
POWER-ON VALUE
0Fh
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Volatile
80h
SEEB
RESERVED
RESERVED
RESERVED
AEN
bit7
bit7
bit6:4
MOD-EN
APC-EN
BIAS-EN
bit0
SEEB:
0 = Enables EEPROM writes to SEE bytes in Table 02h (Default).
1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is
not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE
locations again for data to be written to the EEPROM.
RESERVED
bit3
AEN:
0 = The temperature calculated index value (‘T Index’) is write-able by the user and the updates of
calculated indexes are disabled. This allows the user to interactively test their modules by controlling
the indexing for the look-up tables. The recalled values from the LUTs will appear in the DAC registers
after the next completion of a temperature conversion (just like it would happen is auto mode). Both
DACs will update at the same time (just like auto mode).
1 = Enables auto control of the LUT (Default).
bit2
MOD-EN:
0 = “MOD DAC” is write-able by the user and the LUT recalls are disabled. This allows the user to
interactively test their modules by writing the DAC value for modulation. The output is updated with
the new value at the end of the write cycle. The I_C Stop condition is the end of the write cycle.
1 = Enables auto control of the LUT for modulation (Default).
bit1
APC-EN:
0 = “APC DAC” is write-able by the user and the LUT recalls are disabled. This allows the user to
interactively test their modules by writing the DAC value for APC reference. The output is updated
with the new value at the end of the write cycle. The I_C Stop condition is the end of the write cycle.
1 = Enables auto control of the LUT for APC reference (Default).
bit0
BIAS-EN:
0 = “BIAS DAC” is controlled by the user and the APC is open loop. The “BIAS DAC” value is written
to the “MAN IBIAS” Register. All values that are written to “MAN IBIAS” and are greater than the “MAX
IBIAS” register setting are not updated and will set the “BIAS MAX” alarm bit. The “BIAS DAC”
register will continue to reflect the value of the Bias DAC. This allows the user to interactively test their
modules by writing the DAC value for bias. The output is updated with the new value at the end of the
write cycle to the “MAN IBIAS” register. The I2C Stop condition is the end of the write cycle.
1 = Enables auto control for the APC feedback (Default).
____________________________________________________________________
43
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register 81h: Tindex
POWER-ON VALUE
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and (AEN = 0)
MEMORY TYPE
Volatile
27
81h
26
25
24
23
22
21
bit7
20
bit0
Tindex =
Temperature + 40°C
+ 80h
2°C
Holds the calculated index based on the Temperature Measurement. This index is used for the address during Look-Up of Tables
04h and 05h.
For Table 04h, the exact address as the value of Tindex is used. For Table 05h the address used is calculated as follows
Tindex − 80h
+ 80h
2
Table 02h, Register 82h: MOD DAC
POWER-ON VALUE
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and (MOD-EN = 0)
MEMORY TYPE
Volatile
27
82h
26
25
24
23
22
21
bit7
20
bit0
The digital value used for MOD and recalled from Table 04h at the adjusted memory address found in Tindex. The address used is
calculated as follows
Tindex =
TEMP + 40h
2
This register is updated at the end of the Temperature conversion.
Table 02h, Register 83h: APC DAC
POWER-ON VALUE
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and (APC-EN = 0)
MEMORY TYPE
83h
Volatile
7
2
26
25
24
23
bit7
22
21
20
bit0
The digital value used for APC reference and recalled from Table 05h at the memory address found in ‘T Index’. This register is
updated at the end of the Temperature conversion.
44
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register 84h to 85h: BIAS DAC
FACTORY DEFAULT
00 00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and (BIAS-EN = 0)
MEMORY TYPE
Volatile
84h
0
0
212
211
210
29
28
27
85h
27
26
25
24
23
22
21
20
bit7
bit0
The digital value used for IBIAS.
Table 02h, Register 86h: Device ID
FACTORY DEFAULT
63h
READ ACCESS
PW2
WRITE ACCESS
N/A
MEMORY TYPE
ROM
86h
0
1
1
0
0
bit7
0
1
1
bit0
Hard wired to show device ID.
Table 02h, Register 87h: Device VER
FACTORY DEFAULT
Device Version
READ ACCESS
PW2
WRITE ACCESS
N/A
MEMORY TYPE
ROM
87h
DEVICE VERSION
bit7
bit0
Hard wired connections to show Device Version.
____________________________________________________________________
45
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register 88h: Update Rate
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
Defines the update rate for comparison of APC control.
88h
0
0
0
0
bit7
bit0
bit7:4
0
bit3:0
SR(3:0) : 4-bit update rate for comparison of APC control.
SR3–SR0
MINIMUM TIME
REPEATED SAMPLE
FROM BEN TO FIRST
PERIOD FOLLOWING
SAMPLE (tFIRST)
FIRST SAMPLE (tREP)
±50ns
0000b
350ns
800ns
0001b
550ns
1200ns
0010b
750ns
1600ns
0011b
950ns
2000ns
0100b
1350ns
2800ns
0101b
1550ns
3200ns
0110b
1750ns
3600ns
0111b
2150ns
4400ns
1000b
2950ns
6000ns
1001b*
3150ns
6400ns
*All codes greater than 1001b (1010b–111b) use the maximum
sample time of code 1001b.
46
SR(3:0)
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register 89h: Config
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
89h
FETG DIR
TX-F EN
RESERVED
ASEL
RESERVED
RESERVED
RESERVED
RESERVED
bit7
bit0
Configure the memory location and the polarity of the digital outputs.
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
bit7
0 = Under normal operation, FETG will be pulled low. (Default)
1 = Under normal operation, FETG will be pulled high.
TX-F EN:
0 = The alarm bits will immediately reflect the status of the last comparison. (Default)
bit6
1 = The alarm bits are latched until cleared by a TX-D transition or Power-down. If VCC low alarm is
enabled for either FETG or TX-F then latching is disabled until after the first VCC measurement is
made above the VCC to set-point to allow for proper operation during slow power-on cycles.
bit5
RESERVED
bit4
bit3:0
ASEL: Address SELect.
0 = Device Address of A2h (Default).
1 = Device-Address is equal to the value found in byte ‘device_address’ (Table 02h, 8Ch).
RESERVED
Table 02h, Register 8Ah: Startup Step
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Ah
212
211
210
29
28
27
bit7
26
25
bit0
This value will define the maximum allowed step for the upper 8 bits of IBIAS output during start-up.
____________________________________________________________________
47
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register 8Bh: MOD Ranging
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Bh
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MOD2
MOD1
bit7
MOD0
bit0
The lower nibble of this byte controls the Full-Scale range of the Modulation DAC
bit7:3
RESERVED (Default = 0)
bit2:0
MOD RANGING: 3-bit value to select FS output voltage for VMOD. Default 0006 and creates a
FS of 1.25V.
MOD2 TO MOD0
% OF 1.25V
FS VOLTAGE
000b
100
1.250
001b
80.05
1.001
010b
66.75
0.833
011b
50.13
0.627
100b
40.16
0.502
101b
33.5
0.419
110b
28.75
0.359
111b
25.18
0.315
Table 02h, Register 8Ch: Device Address
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Ch
27
26
25
24
23
22
bit7
X = Don't care.
This value becomes the Device address for the main memory when ASEL (Table 02h, 89h) bit is set.
48
____________________________________________________________________
21
X
bit0
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register 8Dh: Comp Ranging
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Dh
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
APC2
APC1
bit7
APC0
bit0
This byte controls the Full-Scale range for the Quick-Trip monitoring of the APC reference as well as the closed loop monitoring of
APC.
bit7:3
RESERVED (Default = 0)
bit2:0
APC RANGING: 3-bit value to select the FS comparison voltage for BMD with the APC. Default is
000b and creates a FS voltage of 2.5V.
APC2 TO APC0
% OF 2.5V
FS VOLTAGE
000b
100
2.500
001b
80.07
2.002
010b
66.79
1.670
011b
50.18
1.255
100b
40.22
1.006
101b
33.57
0.839
110b
28.82
0.721
111b
25.26
0.632
Table 02h, Register 8Eh: Right Shift1
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Eh
RESERVED
bit7
MON1_2
MON1_1
MON1_0
RESERVED
MON2_2
MON2_1
MON2_0
bit0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the measurements to
the smallest Full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB.
____________________________________________________________________
49
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register 8Fh: Right Shift0
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Fh
RESERVED
MON3_2
MON3_1
MON3_0
RESERVED
RESERVED
RESERVED
RESERVED
bit7
bit0
Allows for right-shifting the final answer of MON3 voltage measurements. This allows for scaling the measurements to the smallest
full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB.
Table 02h, Register 90h to 91h: Reserved
FACTORY DEFAULT:
0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register 92h to 93h: VCC Scale
FACTORY CALIBRATED
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
92h
93h
Nonvolatile (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
Controls the Scaling or Gain of the VCC measurements. The factory-calibrated value will produce a FS voltage of 6.5536V.
50
____________________________________________________________________
bit0
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register 94h to 95h: MON1 Scale
Table 02h, Register 96h to 97h: MON2 Scale
Table 02h, Register 98h to 99h: MON3 Scale
FACTORY CALIBRATED
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
94h
95h
215
7
2
213
6
5
2
2
2
3
2
2
2
28
1
20
9
2
2
2
2
28
97h
27
26
25
24
23
22
21
20
9
28
1
20
99h
7
2
2
2
6
5
2
2
12
2
4
2
11
2
3
2
10
29
2
13
11
210
2
14
12
211
2
2
13
4
2
15
14
212
96h
98h
15
214
10
2
2
2
2
2
bit7
bit0
Controls the Scaling or Gain of the MON1, MON2, and MON3 measurements. The default hexadecimal value will correspond to
2.5V. The factory-calibrated value will produce a FS voltage of 2.5V.
Table 02h, Register 9Ah to A1h: Reserved
FACTORY DEFAULT
0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register A2h to A3h: VCC Offset
FACTORY DEFAULT
0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
A2h
S
S
A3h
9
8
2
2
215
7
2
bit7
214
6
2
213
5
2
212
4
2
211
3
2
210
22
bit0
Allows for offset control of VCC measurement if desired.
____________________________________________________________________
51
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register A4h to A5h: MON1 Offset
Table 02h, Register A6h to A7h: MON2 Offset
Table 02h, Register A8h to A9h: MON3 Offset
FACTORY DEFAULT
0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
A4h
S
S
A5h
9
8
2
2
215
7
2
6
2
5
2
4
2
210
3
22
11
2
2
2
2
2
2
210
A7h
29
28
27
26
25
24
23
22
S
S
A9h
9
8
2
2
2
7
2
2
6
2
13
2
5
2
12
211
S
14
13
212
S
15
14
213
A6h
A8h
15
214
12
2
4
2
11
210
3
22
2
2
bit7
bit0
Allows for offset control of MON1, MON2, and MON3 measurement if desired.
Table 02h, Register AAh to ADh: Reserved
FACTORY DEFAULT
0000 0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register AEh to AFh: Temp Offset
FACTORY CALIBRATED
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
AEh
S
28
27
26
25
24
23
22
AFh
1
0
-1
-2
-3
-4
-5
2-6
2
2
2
2
2
2
2
bit7
Allows for offset control of Temp measurement if desired. The Final Result must be XOR’ed with BB40h before writing to this
register. Factory calibration contains the desired value for a reading of the temperature in degrees celcius.
52
____________________________________________________________________
bit0
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register B0h to B3h: PW1
FACTORY DEFAULT
FFFF FFFFh
READ ACCESS
N/A
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B0h
31
2
230
229
228
227
226
225
224
B1h
223
222
221
220
219
218
217
216
B2h
15
14
13
12
11
10
B3h
2
7
2
2
2
6
5
2
2
2
4
2
2
3
2
2
2
2
9
28
1
20
2
2
bit7
bit0
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all
ones. Thus writing these bytes to all ones grants PW1 access on power-up without writing the password entry. All reads of this
register are 00h.
Table 02h, Register B4h to B7h: PW2
FACTORY DEFAULT
FFFF FFFFh
READ ACCESS
N/A
WRITE ACCESS
PW2
MEMORY TYPE
B4h
Nonvolatile (SEE)
31
230
229
228
227
226
225
224
23
22
21
20
19
18
17
216
2
B5h
2
B6h
215
B7h
7
2
bit7
2
214
6
2
2
213
5
2
2
212
4
2
2
211
3
2
2
210
2
2
2
29
28
1
20
2
bit0
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all
ones. Thus writing these bytes to all ones grants PW2 access on power-up without writing the password entry. All reads of this
register are 00h.
____________________________________________________________________
53
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register B8h: FETG Enable1
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B8h
TEMP EN
VCC EN
MON1 EN
MON2 EN
MON3 EN
RESERVED
RESERVED
RESERVED
bit7
bit0
Configures the maskable interrupt for the FETG pin.
bit7
TEMP EN: Enables/Disables active interrupts on the FETG pin due to temperature measurements
outside the threshold limits.
0 = Disable (Default)
1 = Enable
bit6
bit5
VCC EN: Enables/Disables active interrupts on the FETG pin due to VCC measurements outside the
threshold limits.
0 = Disable (Default)
1 = Enable
MON1 EN: Enables/Disables active interrupts on the FETG pin due to MON1 measurements
outside the threshold limits.
0 = Disable (Default)
1 = Enable
bit4
MON2 EN: Enables/Disables active interrupts on the FETG pin due to MON2 measurements
outside the threshold limits.
0 = Disable (Default)
1 = Enable
bit3
MON3 EN: Enables/Disables active interrupts on the FETG pin due to MON3 measurements
outside the threshold limits.
0 = Disable (Default)
1 = Enable
bit2:0
54
RESERVED (Default = 0)
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register B9h: FETG Enable0
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B9h
TXP-HI EN
TXP-LO EN
BIAS-HI EN
bit7
BIAS MAX EN
RESERVED
RESERVED
RESERVED
RESERVED
bit0
Configures the maskable interrupt for the FETG pin.
bit7
TX-P-HI EN: Enables/Disables active interrupts on the FETG pin due to Tx-P fast comparisons
above the threshold limit.
0 = Disable (Default)
1 = Enable.
bit6
TX-P-LO EN: Enables/Disables active interrupts on the FETG pin due to Tx-P fast comparisons
below the threshold limit.
0 = Disable (Default)
1 = Enable
bit5
BIAS-HI EN: Enables/Disables active interrupts on the FETG pin due to BIAS fast comparisons
above the threshold limit.
0 = Disable (Default)
1 = Enable
BIAS MAX EN: Enables/Disables active interrupts on the FETG pin due to BIAS fast comparisons
below the threshold limit.
bit4
bit3:0
0 = Disable (Default)
1 = Enable
RESERVED (Default = 0)
____________________________________________________________________
55
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register BAh: TX-F Enable1
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
BAh
TEMP EN
VCC EN
MON1 EN
MON2 EN
MON3 EN
bit7
RESERVED
RESERVED
RESERVED
bit0
Configures the maskable interrupt for the TX-F pin.
bit7
TEMP EN: Enables/Disables active interrupts on the TX-F pin due to temperature measurements
outside the threshold limits.
0 = Disable (Default)
1 = Enable
bit6
bit5
VCC EN: Enables/Disables active interrupts on the TX-F pin due to VCC measurements outside the
threshold limits.
0 = Disable (Default)
1 = Enable
MON1 EN: Enables/Disables active interrupts on the TX-F pin due to MON1measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
bit4
MON2 EN: Enables/Disables active interrupts on the TX-F pin due to MON2 measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable.
bit3
MON3 EN: Enables/Disables active interrupts on the TX-F pin due to MON3 measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
bit2:0
56
RESERVED (Default = 0)
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register BBh: TX-F Enable0
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
BBh
TXP-HI EN
TXP-LO EN
BIAS-HI EN
BIAS MAX EN
RESERVED
bit7
RESERVED
RESERVED
FETG EN
bit0
Configures the maskable interrupt for the Tx-F pin.
bit7
TXP-HI EN: Enables/Disables active interrupts on the Tx-F pin due to Tx-P fast comparisons above
the threshold limit.
0 = Disable (Default)
1 = Enable.
bit6
TXP-LO EN: Enables/Disables active interrupts on the Tx-F pin due to Tx-P fast comparisons below
the threshold limit.
0 = Disable (Default)
1 = Enable
bit5
BIAS-HI EN: Enables/Disables active interrupts on the Tx-F pin due to BIAS fast comparisons
above the threshold limit.
0 = Disable (Default)
1 = Enable
BIAS MAX EN: Enables/Disables active interrupts on the Tx-F pin due to BIAS fast comparisons
above the threshold limit.
bit4
bit3:1
bit0
0 = Disable (Default)
1 = Enable
RESERVED (Default = 0)
FETG EN:
0 = Normal FETG operation (Default)
1 = Enables FETG to act as an input to Tx-F output.
____________________________________________________________________
57
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register BCh: HTXP
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
BCh
Nonvolatile (SEE)
7
2
26
25
24
23
22
21
bit7
20
bit0
Fast comparison DAC adjust for High TXP. This value is added to the APC_DAC value recalled from Table 04h. If the sum is greater
than 0xFF then 0xFF is used. Comparisons greater than APC_DAC plus this value, found on the BMD pin, will create a TX-P HI
alarm.
Table 02h, Register BDh: LTXP
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
BDh
Nonvolatile (SEE)
7
2
26
25
24
23
22
21
bit7
20
bit0
Fast comparison DAC adjust for Low TXP. This value is subtracted from the APC_DAC value recalled from Table 04h. If the
difference is less than 0x00 then 0x00 is used. Comparisons less than APC_DAC minus this value, found on the BMD pin, will
create a TX-PLO alarm.
Table 02h, Register BEh: HBIAS
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
BEh
Nonvolatile (SEE)
7
2
26
25
24
23
bit7
Fast comparison DAC setting for High BIAS.
58
____________________________________________________________________
22
21
20
bit0
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 02h, Register BFh: MAX IBIAS
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
12
BFh
2
211
210
29
28
27
26
25
bit7
bit0
This value will define the maximum DAC value allowed for the upper 8 bits of IBIAS output during all operations. During the initial step
and binary search, this value will not cause an alarm but will still clamp the IBIAS DAC output. After the startup sequence (or normal
APC operations), if the APC loop tries to create an IBIAS value greater than this setting, IBIAS is clamped, and creates a BIAS MAX
alarm. Settings 00h through FEh are intended for normal APC mode of operation. Setting FFh is reserved for manual IBIAS mode.
Table 02h, Register C0h to F7h: Empty
Table 02h, Register F8h–F9h: MAN IBIAS
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and (BIAS-EN = 0)
MEMORY TYPE:
Volatile
F8h
RESERVED
7
F9h
2
RESERVED
6
2
212
5
2
211
4
2
210
3
2
29
28
27
2
1
20
2
2
bit7
bit0
When “BIAS-EN” (Table 02h, 80h) is written to 0, writes to these bytes will control the lower portion of the IBIAS DAC [7:0].
Table 02h, Register FAh: MAN_CNTL
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and (BIAS-EN = 0)
MEMORY TYPE:
Volatile
FAh
RESERVED
bit7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MAN_CLK
bit0
When “BIAS-EN” bit (Table 02h, 80h) is written to zero, bit zero of this byte will control the updates of the MAN IBIAS value to the
Bias output. The Values of MAN IBIAS should be written with a separate write command. Setting bit zero to a ‘1’ will clock the MAN
IBIAS value to the output DAC.
1.
Write the MAN IBIAS value with a write command.
2.
Set the MAN CLK bit to a ‘1’ with a separate write command.
3.
Clear the MAN CLK bit to a ‘0’ with a separate write command.
____________________________________________________________________
59
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register FBh to FFh: Reserved
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
These registers are reserved.
Table 03h, Register Descriptions
Table 03h, Register 80h to FFh: PW2 EEPROM
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (EE)
80h-FFh
EE
EE
EE
EE
EE
EE
EE
bit7
EE
bit0
PW2 general-purpose EEPROM.
Table 04h, Register Descriptions
Table 04h, Register 80h to C7h: Modulation LUT
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (EE)
80h-C7h
27
26
25
24
23
bit7
22
21
20
bit0
The unsigned value for modulation DAC output.
The Modulation LUT is a set of registers assigned to hold the temperature profile for the Modulation DAC. The values in this table
combined with the MOD bits in the MOD Ranging register (Table 02h, Register 8Bh) determine the set point for the Modulation
Voltage. The temperature measurement is used to index the LUT (T INDEX, Table 02h, Register 81h) in 2°C increments from -40°C
to +102°C, starting at 80h in Table 04h. Register 80h defines the -40°C to -38°C MOD output, register 81h defines -38°C to -36°C
MOD output, and so on. Values recalled from this EEPROM memory table are written into the MOD DAC location which holds the
value until the next temperature conversion. The part can be placed into a manual mode (Mod_En bit, Table 02h, Register 80h),
where MOD DAC can be directly controlled for calibration. If the temperature compensation functionality is not required, then
program the entire Table 04h, to the desired modulation setting.
60
____________________________________________________________________
Burst-Mode PON Controller
With Integrated Monitoring
DS1863
Table 05h, Register Descriptions
Table 05h, Register 80h to C7h: APC Tracking Error LUT
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (EE)
7
80h-A3h
2
26
25
24
23
22
21
bit7
20
bit0
The Tracking Error LUT is set of registers assigned to hold the temperature profile for the APC reference DAC. The values in this
table combined with the APC bits in the Comp Ranging register (Table 02h, Register 8Dh) determine the set point for the APC loop.
The on board temperature measurement is used to index the LUT (T INDEX, Table 02h, Register 81h) in 4°C increments from -40°C
to +100°C, starting at register 80h in Table 05h. Register 80h defines the -40°C to -36°C APC reference value, register 81h defines
-36°C to -32°C APC reference value, and so on. Values recalled from this EEPROM memory table are written into the APC DAC
location, which holds the value until the next temperature conversion. The part can be placed into a manual mode (Apc_En bit,
Table 02h, Register 80h), where APC DAC can be directly controlled for calibration. If tracking error temperature compensation is
not required by the application, program the entire LUT to the APC set-point.
Table 05h, Register A3h to A7h: Reserved
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
These registers are reserved.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
16 TSSOP
U16+1
21-0066
____________________________________________________________________
61
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/06
1
2
12/06
8/09
DESCRIPTION
PAGES
CHANGED
Initial release.
—
Changed “triplexer” to “transceiver” in the General Description.
1
Added “Turn-Off Delay” and “Turn-On Delay” to the t OFF and tON PARAMETER specs
in the Control Loop and Quick-Trip Timing Characteristics table.
3
Corrected reference of “312-5mV” in Note 6 to “312.5mV.”
4
Changed IINIT to t ON in Figure 1.
9
Corrected reference of “BIAS MAX” to MAX IBIAS” in the BIAS and MOD Output
During Initial Power-Up section.
9
Corrected reference of “MAX IBIAS” to “BIAS MAX” in the BIAS-EN (Table 02h) bit
description.
43
Corrected reference of “Factory Default” to “Power-On Value” in the register
descriptions for Tindex, MOD DAC, and APC DAC.
44
Replaced all instances of 5.5V with 3.9V.
Added the Analog Voltage Monitoring table.
1–5
5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
62 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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