Rev 0; 4/06
SFP Laser Controller and
Diagnostic IC
Features
The DS1864 is an SFF-8472 multisource agreement
(MSA)-compliant laser controller/monitor that is ideal for
SFP optical-transceiver module designs. It controls laser
driver bias and modulation currents through a pair of temperature-controlled current-sink DACs. System diagnostics are provided by monitoring three analog inputs, VCC,
and temperature through the internal temperature sensor.
The device also contains all EEPROM required by the
SFF-8472 MSA, including all A0h and A2h EEPROM. The
DS1864’s memory map can be configured to be compatible with both the DS1852/DS1856 and the DS1859 memory maps. Additionally, memory is secured with customerconfigurable two-level password protection.
Eye-safety features are integrated by three fast-trip
comparators that monitor transmit-power high, transmitpower low, and bias current. The fast-trip comparators
drive a FET driver output to disable the laser in the case
of eye safety violation.
♦ SFF-8472 MSA Compatible
♦ Five Monitored Channels (Temperature, VCC,
MON1, MON2, MON3)
Three External Analog Inputs (MON1, MON2,
MON3) Support Internal and External
Calibration
Enhanced RSSI Monitoring (26dB Range, 0.5dB
Accuracy)
Scalable Dynamic Range for External Analog
Inputs
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored
Channels
♦ Two Linear 8-Bit Current-Sink DACs
Two User-Selectable Full-Scale Ranges (0.5mA
or 1.5mA)
Values Changeable Every 2°C
♦ Three Fast-Trip Comparators (Tx Power High,
Tx Power Low, and Bias Current) for Eye Safety
♦ Flexible, Two Level Password Scheme Provides
Three Levels of Security
♦ Provides All Optional and Required SFF-8472
MSA EEPROM (Both A0h and A2h Memory)
♦ I2C-Compatible Serial Interface
♦ Operates from a 3.3V or 5V Supply
♦ -40°C to +95°C Operating Temperature Range
♦ 28-Pin TQFN Package (5mm x 5mm)
With its integrated laser driver control, system diagnostics, eye-safety features, and internal temperature sensor, the DS1864 provides an ideal solution for SFP
optical transceiver modules by improving system performance, reducing board space, and simplifying design.
Applications
SFP Optical Transceiver Modules
Laser Control and Monitoring
Pin Configuration
FETG
GND
N.C.
27
RX-LOS
OUT1
28
PART
TX-F
VCC
TOP VIEW
Ordering Information
26
25
24
23
22
TEMP RANGE
PIN-PACKAGE
DS1864T
-40°C to +95°C
28 TQFN (5mm x 5mm)
DS1864T+
-40°C to +95°C
28 TQFN (5mm x 5mm)
+Denotes lead-free only package.
RSELOUT
1
21
VCC
SDA
2
20
DAC0
SCL
3
19
GND
INTX-F
4
18
DAC1
INLOS
5
17
MON1P
IN1
6
16
MON1N
N.C.
7
15
N.C.
12
13
MON3P
14
Typical Operating Circuit appears at end of data sheet.
MON2
11
RSEL
GND
10
MON3N
9
TX-D
8
N.C.
DS1864
TQFN
5mm x 5mm
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS1864
General Description
DS1864
SFP Laser Controller and
Diagnostic IC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to Ground ...........-0.5V to +6.0V
Voltage Range on Inputs Relative to Ground* .................-0.5V to
(VCC + 0.5V)
Voltage Range on DAC Pins Relative to Ground*............-0.5V to
(VCC + 0.5V)
Current into DAC Pins ...........................................................5mA
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature............See IPC/J-STD-020 Specification
*Not to exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +95°C)
PARAMETER
Supply Voltage
SYMBOL
VCC
CONDITIONS
(Note 1)
MIN
TYP
MAX
UNITS
2.97
5.50
V
V
V
Input Logic 0 (SDA, SCL)
VIL
IIL(max) = -10µA
-0.3
+0.3 x
VCC
Input Logic 1 (SDA, SCL)
VIH
IIH(max) = 10µA
0.7 x
VCC
VCC +
0.3
VIL
Input Logic 0
-0.3
0.9
1.5
VCC +
0.3
V
MAX
UNITS
5
mA
+1
µA
Input Logic Levels (TX-D, INLOS,
RSEL, IN1)
VIH
Input Logic 1
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
Supply Current
ICC
Input Leakage (SDA, SCL)
IIL
CONDITIONS
MIN
(Notes 2 and 3)
TYP
3
-1
VOL1
3mA sink current
0.4
VOL2
6mA sink current
0.6
I/O Capacitance
CI/O
For SDA/SCL
TX-D Pullup Resistor
RPU
TA = +25°C
Low-Level Output Voltage (SDA)
14
20
V
10
pF
24
kΩ
Digital Power-On Reset
VPOD
1.0
2.2
V
Analog Power-On Reset
VPOA
2.00
2.97
V
High-Level Output Voltage
(FETG)
VOH
4mA source current
VCC 0.4
VCC +
0.3
V
Low-Level Output Voltage (TX-F,
LOS Voltage, FETG)
VOL
4mA sink current
0.0
0.4
V
0.4 < VI/O < 0.9VCC
-10
+10
µA
Input Current Each I/O Pin
2
_____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
ANALOG OUTPUT CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
IDAC0 and IDAC1
DESCRIPTION
Range 1
Range 2
IDAC0 and IDAC1 (Off State Current)
CONDITIONS
MIN
TYP
Position FFh (Note 6)
nA
VCC
V
IDAC < 50µA
±10
µA
IDAC > 50µA
±4
%
IDAC < 50µA
±10
µA
0.7
Range 1
Range 2
mA
100
Voltage at IDAC0 and IDAC1
10
UNITS
mA
1.5
Shutdown or Position 00h
IDAC0 and IDAC1 Accuracy
(Note 6)
MAX
0.5
IDAC > 50µA
±4
Resolution
0.4
%
%FS
ANALOG VOLTAGE MONITORING CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Full-Scale Monitor Input
At factory setting (Note 4)
2.4875
2.5000
2.5125
V
Full-Scale VCC Monitor
At factory setting (Note 5)
6.5208
6.5536
6.5864
V
Monitor Resolution
(VCC, IBI, TXP, RIN)
0.024
MON1P to MON1N FS
MON1 (Note 7)
MON1P, MON1N Common-Mode
Voltage
%FS
0
2.5
V
0
VCC
V
2.5
V
MON1P (Single-Ended)
(Notes 7 and 8)
MON1 FS (Factory)
(Note 7)
2.5
MON2 FS (Factory)
(Note 7)
2.5
V
MON3 FS (Factory)
VMON3 = 2.5V (Note 7)
2.5
V
V
Supply Accuracy
VCCacc
(Note 7)
0.5
%FS
MON1 Accuracy
MON1acc
(Note 7)
0.5
%FS
MON2 Accuracy
MON2acc
(Note 7)
0.5
%FS
MON3 Accuracy
MON3acc
(Notes 7 and 9)
0.5
%FS
Monitoring Update Rate
tframe
Fast-Trip Comparator Accuracy
FCacc
Dual range disabled
21.5
26.0
Dual range enabled
57
70
±4
ms
%FS
_____________________________________________________________________
3
DIGITAL THERMOMETER CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
Thermometer Error
TERR
Update Rate
tframe
CONDITIONS
-40°C to +95°C
(Notes 10, 17)
MIN
TYP
-3
MAX
UNITS
+3
°C
Dual range disabled
57
70
Dual range enabled
67
80
TYP
MAX
ms
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
UNITS
➜
SHUTDOWN AND FAULTS (SEE FAULT AND SHUTDOWN TIMING DIAGRAMS FIGURES 1 TO 10), FOR FAST ALARMS AND
SFP MANAGEMENT
TX-D (to DACs Off-State
Currents)
tOFF
Figure 4
From
TX-D
(Notes 11, 17)
Recovery from Normal Disable
(to DACs Set Values)
tON
Figure 4
From
TX-D
(Notes 12, 17)
Recovery After Power-Up (to
DACs Set Values)
tINIT_DACs
Figure 9
Shutdown Response Time (to
DACs Off-State Current)
µs
0.8
ms
From
VCC = 2.97V
(Notes 11, 17)
100
ms
tFAULT
Figure 5
IBMD > TripHi
or IBIAS > Trip
IBMD < TripLo
(Notes 11, 17)
50
µs
Recovery from Safety Fault
Shutdown (to DACs Set Values)
tINITSF
Figures 6
and 10
From
TX-D
(Notes 11, 17)
50
ms
Fault Reset Time (to TX-F = 0)
tINITR1
Figure 2
From
TX-D
100
200
ms
100
200
ms
➜
➜
➜
Fault Reset Time (to TX-F = 0)
➜
5
tINITR2
From
Figures 1,
VCC = 2.97V
2, 3, and 6
➜
DS1864
SFP Laser Controller and
Diagnostic IC
Fault Assert Time (to TX-F = 1)
tFAULT
Figure 5
IBMD > TripHi
or IBIAS > Trip
IBMD < TripLo
(Note 11)
50
µs
LOS Assert Time
tLOSS_ON
Figure 8
RSSI < Trip
(Note 12)
50
µs
LOS Deassert Time
tLOSS_OFF
Figure 8
RSSI > Trip
(Note 12)
50
µs
4
_____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING FOR SOFT CONTROL AND STATUS FUNCTIONS
TX-D Assert Time
tOFF
Time from TX-D set until DACs fall below
10% of nominal (Notes 13, 17)
10
ms
TX-D Deassert time
tON
Time from TX-D cleared until DACs rise
above 90% of nominal (Notes 13, 17)
50
ms
Time to Initialize, Including
Reset of TX-F
tINIT
Time from power-on or negation of TX-F
using TX-D;
serial communication possible
200
ms
Time from fault to TX-F set (Note 17)
50
ms
TX-F Assert Time
tFAULT
RX-LOS Assert Time
tLOS_ON
Time from occurrence of loss of signal to
RX-LOS set
50
ms
RX-LOS Deassert Time
tLOS_OFF
Time from occurrence of presence of signal
to RX-LOS cleared
50
ms
Rate-Select Change Time
tRATE_SEL
Time from change of state of rate-select bit
to rate-select output (RSELOUT) pin change
50
ms
MAX
UNITS
400
kHz
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 5.5V; TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 19)
PARAMETER
SYMBOL
CONDITIONS
TYP
SCL Clock Frequency
fSCL
Bus Free Time Between Stop and
Start Conditions
tBUF
1.3
µs
tHD:STA
0.6
µs
tLOW
1.3
µs
Hold Time (Repeated) Start
Condition
Low Period of SCL
High Period of SCL
(Note 14)
MIN
0
tHIGH
0.6
Data Hold Time
tHD:DAT
0
µs
Data Setup Time
tSU:DAT
100
ns
Start Setup Time
tSU:STA
0.6
µs
0.9
µs
SDA and SCL Rise Time
tR
(Note 15)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 15)
20 +
0.1CB
300
ns
Stop Setup Time
tSU:STO
0.6
SDA and SCL Capacitive
Loading
CB
(Note 15)
EEPROM Write Time
tW
(Note 16)
µs
10
400
pF
20
ms
_____________________________________________________________________
5
DS1864
AC ELECTRICAL CHARACTERISTICS (continued)
DS1864
SFP Laser Controller and
Diagnostic IC
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40°C to +95°C.)
PARAMETER
EEPROM Writes
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
6
SYMBOL
CONDITIONS
+70°C (Note 17)
MIN
50,000
TYP
MAX
UNITS
Writes
All voltages are referenced to ground. Currents into the IC are positive, and currents out of the IC are negative.
Supply current is measured with all logic inputs at their inactive state (SDA = SCL = VCC) and driven to well-defined logic
levels. All outputs are disconnected.
DAC0/DAC1 positions programmed to FFh and with outputs floating.
Full-scale is user programmable. The maximum voltage that the MON inputs read is approximately full-scale, even if the
voltage on the inputs is greater than full-scale.
This voltage defines the maximum range of the analog-to-digital (ADC) converter voltage, not the maximum VCC voltage.
Accuracy specification includes supply and temperature variations. Measured at 1.2V.
%FS refers to calibrated full scale in the case of internal calibration, and uncalibrated full scale in the case of external calibration. Uncalibrated full scale is set at the factory and is specified in this data sheet as V CC FS (Factory), MON1 FS
(Factory), MON2 FS (Factory), and MON3 FS (Factory). Calibrated full scale is set by the user, allowing him to change any
of these scales for his instrumentation.
When used single-ended, MON1N must be connected to GND.
0.5%FS with 0.5dB (~11%) accuracy results in 16.4dB range. Assuming some overlap of the ranges, this scheme should
cover the required 26dB range.
See Figure 14 for thermometer error.
When the DACs are re-enabled, they ramp up to their final values. The ramp up starts from 0 and should not exceed its
final value at any point during its initial transient.
This spec is the time it takes, from RSSI voltage below the RSSI voltage trip threshold, to LOS asserted high.
Measured from the falling clock edge after the stop bit of the write transaction.
I2C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing.
CB⎯total capacitance of one bus line in picofarads.
EEPROM write begins after a stop condition occurs.
This parameter is guaranteed by design.
_____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
VCC > 2.97V
TX-F
TX-D
DAC0, DAC1
tINIT
Figure 1. Power-On Initialization with TX-D Low
VCC > 2.97V
TX-F
TX-D
DAC0, DAC1
tINIT
Figure 2. Power-On Initialization with TX-D Asserted
VCC > 2.97V
TX-F
TX-D
DAC0, DAC1
tINIT
INSERTION
Figure 3. Example of Initialization with TX-D Low (Hot-Plug)
_____________________________________________________________________
7
DS1864
Timing Diagrams
SFP Laser Controller and
Diagnostic IC
DS1864
Timing Diagrams (continued)
TX-F
TX-D
DAC0, DAC1
tOFF
tON
Figure 4. TX-D Timing During Normal Operation
OCCURRENCE
OF FAULT
TX-F
TX-D
DAC0, DAC1
tFAULT
Figure 5. Detection of Transmitter Safety Fault Operation
OCCURRENCE
OF FAULT
TX-F
TX-D
DAC0, DAC1
tRESET
tINIT
NOTE: TX-F IS ALSO DEPENDENT ON INTX-F.
Figure 6. Successful Recovery from Transient Safety Fault Condition
8
_____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
OCCURRENCE
OF FAULT
TX-F
TX-D
DAC0, DAC1
tRESET
tFAULT
tINIT
NOTE: TX-F IS ALSO DEPENDENT ON INTX-F.
Figure 7. Unsuccessful Recovery from a Transient Safety Fault Condition
OCCURRENCE
OF LOS
LOS
tLOSS_ON
tLOSS_OFF
Figure 8. Timing of LOS Detection
TX-D
DAC0, DAC1
tINIT_DACs
Figure 9. Output Enable/Power-Up
TX-D
DAC0, DAC1
tINITSF
Figure 10. Output Enable/Recovery from Safety Fault Shutdown
_____________________________________________________________________
9
DS1864
Timing Diagrams (continued)
Typical Operating Characteristics
(VCC = +3.3V, TA = 25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
SDA = SCL = VCC
1.70
2.3
2.2
2.1
DACS IN 1.5mA MODE
1.60
0.5mA MODE
0.5
OUTPUT CURRENT (mA)
SUPPLY CURRENT (µA)
2.4
OUTPUT CURRENT vs. DAC 0 SETTING
0.6
DS1864a toc02
DS1864a toc01
SDA = SCL = VCC
SUPPLY CURRENT (mA)
1.80
1.50
1.40
DACS IN 0.5mA MODE
1.30
1.20
DS1864a toc03
SUPPLY CURRENT vs. VOLTAGE
2.5
DAC VOLTAGES = 0.7V
0.4
0.3
0.2
0.1
1.10
DAC SETTINGS AT FFh
1.00
4.0
4.5
VOLTAGE (V)
5.0
5.5
0
-40
OUTPUT CURRENT vs. DAC 0 SETTING
0.5mA MODE
0.5
1.2
0.8
0.4
100
0
1.5mA MODE
1.6
0.4
0.3
0.2
100
150
200
DAC 0 SETTING (DEC)
250
100
150
200
DAC 1 SETTING (DEC)
0.8
250
0
DAC 0 DNL (LSB)
0.6
DAC 0 DNL (LSB)
0.4
0.2
0
-0.2
-0.4
0.5mA MODE
0.8
0.8
1.5mA MODE
0.6
0.4
250
0.4
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
100
150
200
DAC 1 SETTING (DEC)
DAC 0 INL (LSB)
-0.6
0
50
1.0
DAC 0 INL (LSB)
0.6
50
1.0
DS1864a toc07
0.5mA MODE
0.8
1.2
0
0
DAC 0 INL (LSB)
1.0
250
0.4
DS1864a toc08
50
100
150
200
DAC 0 SETTING (DEC)
OUTPUT CURRENT vs. DAC 1 SETTING
0
0
50
2.0
0.1
0
10
80
OUTPUT CURRENT vs. DAC 1 SETTING
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
1.6
20
40
60
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
1.5mA MODE
0
0.6
DS1864a toc04
2.0
-20
DS1864a toc06
3.5
DS1864a toc05
3.0
DS1864a toc09
2.0
DAC 0 INL (LSB)
DS1864
SFP Laser Controller and
Diagnostic IC
-1.0
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
____________________________________________________________________
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
SFP Laser Controller and
Diagnostic IC
DAC 1 INL (LSB)
0.5mA MODE
0.8
0.6
0.4
-0.2
0.2
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
-1.0
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
DAC 1 INL (LSB)
0.6
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
DAC 0, 0.5mA
0.40
DAC CURRENT (mA)
DAC 1 DNL (LSB)
0.4
0.2
1.5mA MODE
0.8
0.50
DS1864a toc14
0.6
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
DAC 0 CURRENT vs. SUPPLY VOLTAGE
0.60
0.40
0.20
1.2
PROGRAMMED DAC
SETTING (FFh)
0.8
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
5
DAC 1, 0.5mA
0.80
PROGRAMMED DAC
SETTING (FFh)
0.60
0.40
0.20
0
3.5
2
3
4
POWER-UP VOLTAGE (V)
DAC 1 CURRENT vs. SUPPLY VOLTAGE
0.4
0.00
1
1.00
DAC CURRENT (mA)
DAC 0, 1.5mA
1.6
DAC CURRENT (mA)
PROGRAMMED DAC
SETTING (FFh)
3.0
0
DS1864a toc17
0.80
0.20
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
2.0
DS1864a toc16
DAC 0, 0.5mA
0.30
0
0
DAC 0 CURRENT vs. SUPPLY VOLTAGE
1.00
PROGRAMMED DAC
SETTING (80h)
0.10
-1.0
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
DAC SETTING vs. POWER-UP VOLTAGE
1.0
DS1864a toc13
1.5mA MODE
0.8
0
DAC 1 DNL (LSB)
1.0
DAC 1 INL (LSB)
0.2
-0.4
0
DAC CURRENT (mA)
0.4
DS1864a toc15
0
0.6
DS1864a toc18
0.2
0.5mA MODE
0.8
DAC 1 DNL (LSB)
0.4
DAC 1 INL (LSB)
DAC 0 DNL (LSB)
0.6
1.0
DS1864a toc11
DS1864a toc10
1.5mA MODE
0.8
DAC 1 DNL (LSB)
1.0
DS1864a toc12
DAC 0 DNL (LSB)
1.0
0.00
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
____________________________________________________________________
5.5
11
DS1864
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = 25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = 25°C, unless otherwise noted.)
DAC 0 CURRENT
vs. FUNCTION OF THE VOLTAGE ON THE DAC
0.80
0.8
1.5
0.60
0.40
PROGRAMMED DAC
SETTING (FFh)
0
0
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
0.80
1.7
2.2
2.7
DAC 0 VOLTAGE (V)
3.2
0.7
2.00
DS1864a toc22
DAC 1, 0.5mA
1.2
DAC 1 CURRENT
vs. FUNCTION OF THE VOLTAGE ON THE DAC
DAC 1 CURRENT
vs. FUNCTION OF THE VOLTAGE ON THE DAC
1.00
0
0.7
5.5
DAC 1, 1.5mA
PROGRAMMED DAC
SETTING (FFh)
0.50
1.2
1.7
2.2
2.7
DAC 1 VOLTAGE (V)
12
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
1.2
1.7
2.2
2.7
DAC 1 VOLTAGE (V)
3.2
-40
3.0
2.5
2.0
1.5
1.0
0.5
0
-20
0
20
40
60
TEMPERATURE (°C)
80
100
LSB ERROR vs. FULL-SCALE INPUT
6
LSB ERROR
DS1864a toc26
MONITOR QUICK TRIP DNL (LSB)
DS1864a toc25
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
DACS 0 AND 1 IN 0.5mA MODE
MONITOR FAST-TRIP
DNL (LSB)
MONITOR FAST-TRIP
INL (LSB)
3.0
2.5
2.0
1.5
1.0
0.5
0
0.40
0.00
0.7
3.2
0.60
0.20
0
0.7
DACS 0 AND 1 IN 1.5mA MODE
0.80
0.20
0
3.2
1.00
DAC CURRENT (mA)
DAC 1 CURRENT (mA)
0.40
PROGRAMMED DAC
SETTING (FFh)
1.00
1.7
2.2
2.7
DAC 0 VOLTAGE (V)
DAC CURRENT AT SETTING 7Fh
vs. TEMPERATURE
1.50
0.60
1.2
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
DS1864a toc27
3.5
DS1864a toc23
3.0
PROGRAMMED DAC
SETTING (FFh)
1.0
0.5
0.20
0.4
DAC 1 CURRENT (mA)
DAC 0, 1.5mA
DAC 0 CURRENT (mA)
PROGRAMMED DAC
SETTING (FFh)
DS1864a toc21
DAC 0, 0.5mA
DAC 0 CURRENT (mA)
DAC CURRENT (mA)
1.6
2.0
DS1864a toc20
DAC 1, 1.5mA
1.2
1.00
DS1864a toc19
2.0
DAC 0 CURRENT
vs. FUNCTION OF THE VOLTAGE ON THE DAC
DS1864a toc24
DAC 1 CURRENT vs. SUPPLY VOLTAGE
MONITOR QUICK TRIP INL (LSB)
DS1864
SFP Laser Controller and
Diagnostic IC
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
____________________________________________________________________
0
10 20 30 40 50 60 70 80 90 100
NORMALIZED FULL-SCALE (%)
SFP Laser Controller and
Diagnostic IC
PIN
PIN NAME
DESCRIPTION
1
RSELOUT
2
SDA
I2C Serial Data Input/Output
3
SCL
I2C Serial Clock Input
4
INTX-F
5
INLOS
6
IN1
Digital Input
7
N.C.
No Connection
8
N.C.
No Connection
9
GND
Ground. All GND pins must be connected.
10
TX-D
Transmit Disable Input. Places DAC0 and DAC1 in high-impedance state.
11
RSEL
Rate Select Logic Input
12
MON3N
13
MON3P
Voltage Monitor Input, High Side. Used typically for RSSI.
14
MON2
Voltage Monitor Input. Used typically for Transmit Power (TXP).
15
N.C.
16
MON1N
Voltage Monitor Input, Low Side. Used typically for Bias Sense Current (IBIAS).
17
MON1P
Voltage Monitor Input, High Side. Used typically for Bias Sense Current (IBIAS).
18
DAC1
Open-Drain Rate-Select Output
TX-F Input from External Device
Loss of Signal Input from External Device
Voltage Monitor Input, Low Side. Used typically for RSSI.
No Connection
Lookup Table-Controlled Current Sink
19
GND
Ground. All GND pins must be connected.
20
DAC0
Lookup Table-Controlled Current Sink
21
VCC
Power Supply. All VCC pins must be connected.
22
N.C.
No Connection
23
GND
Ground. All GND pins must be connected.
24
FETG
Logic Output Driving External FET
25
TX-F
Open-Drain Fault Output
26
RX-LOS
27
OUT1
28
VCC
Open-Drain Loss of Signal Output
Open-Drain Digital Output
Power Supply. All VCC pins must be connected.
____________________________________________________________________
13
DS1864
Pin Description
SFP Laser Controller and
Diagnostic IC
DS1864
Functional Diagrams
ADDRESS
SDA
AD
I2 C
INTERFACE
SCL
DATA BUS
PASSWORD
PROTECTION
R/W
ADDRESS
EEPROM
256 BYTES
R/W
MD (MAIN DEVICE
ENABLE)
EEPROM
96 BYTES
00h–5Fh
PASSWORD
PROTECTION
AUXILIARY DEVICE
GBIC MEMORY
ADDRESS
AD (AUXILIARY DEVICE
ENABLE A0h)
DEVICE
ADDRESS
LOWER MEMORY
MD
ALARM AND
WARNING LIMITS
R/W
DATA BUS
DATA BUS
SRAM
32 BYTES
60h–7Fh
ADFIX
PASSWORD
PROTECTION
PASSWORD
PROTECTION
MD
TABLE 01h (DS1852)
TABLE 00h (DS1859)
MODE SELECT
TABLE SELECT
LOGIC
CONTROL
SIGNALS
TABLE 04h (DS1852)
TABLE 01h (DS1859)
MODE SELECT
TABLE SELECT
EEPROM
120 BYTES
ADDRESS
MD
TABLE SELECT
ADDRESS
R/W
R/W
DATA BUS
EEPROM
8 BYTES
88h–DFh
DATA BUS
EEPROM
8 BYTES
PASSWORD
PROTECTION
MD
DS1864
SRAM
8 BYTES
80h–87h
ADDRESS
TABLE SELECT
R/W
DAC RANGE SELECT
DATA BUS
LOGIC CONTROL SIGNALS
EEPROM
59 BYTES
C0h–FBh
TABLE 05h
CONFIGURATION
AND CONTROL
NON LUT CONTROL
AND CONFIGURATION
REGISTGERS
FAST ALARMS
AND WARNING
LIMITS
MASK
VCC
MASK
PASSWORD
PROTECTION
VCC
GND
MD
SELC
TABLE SELECT
RSEL
RSEL LOGIC*
LOSC
DATA BUS
RX-LOS
LOS LOGIC*
FAST ALARMS AND
WARNING FLAGS
ADDRESS
TABLE 02h
DAC0
LOOKUP TABLE
R/W
INVL
TABLE SELECT
EEPROM
72 BYTES
80h–C7h
RSELOUT
ADDRESS
INLOS
PASSWORD
PROTECTION
MD
R/W
DATA BUS
EEPROM
72 BYTES
80h–C7h
TABLE 03h
DAC1
LOOKUP TABLE
POWERON RESET
TEMP INDEX
TEMP INDEX
LOS FLAG
TX-D
IN1C
INV1
IN1 LOGIC*
IN1
STARTUP/SHUTDOWN
LOGIC*
INTX-F
OUT1
INTERNAL
TEMP
DAC DISABLE
ADC
CONTROL
INTERNAL
CALIBRATION
TX-F
DAC0
FETG
DAC0 LOOKUP
TABLE REGISTER
LOGIC CONTROL
SIGNALS
MONITOR LIMITS
DAC RANGE
SELECT
DATA BUS
DAC
DISABLE
MON3P
MON3N
MON2
MON1P
MUX
13-BIT DAC
MON1N
VCC
MEASUREMENT
ALARM AND
WARNING FLAGS
DAC1 LOOKUP
TABLE REGISTER
CONVERSION
VALUES
MASK
FAST ALARMS AND
WARNING LIMITS
DAC1
COMPARATOR
FAST-TRIP
COMPARATORS
INTERRUPT
MINT
FAST ALARMS AND
WARNING FLAGS
*SEE FIGURES 12 AND 13.
Figure 11. Block Diagram, Main
14
____________________________________________________________________
DAC RANGE
SELECT
DAC
DISABLE
SFP Laser Controller and
Diagnostic IC
VCC
RPU
TXDS
TX-D
VCC
TXDC
R
C
DISABLE DACs
Q
HTXP flag
C
HTXP ENABLE
D
FPOL
FETG
Q
S
HBAL flag
INV
HBAL ENABLE
TX-F
MINT
HBAL flag
LTXP flag
HTXP flag
HBWA flag
LTXP flag
INTX-F
LTXP ENABLE
FAULT RESET TIMER
(130ms)
IN
OUT
IN
OUT
POWER-ON RESET
Figure 12. Block Diagram, Shutdown
INV1
OUT1
IN1C
IN1
IN1S
RSELOUT
SELC
RSEL
SELS
LOSC
INVL
INLOS
1
LOS flag
0
RX-LOS
MUX
Figure 13. Block Diagram, Outputs
____________________________________________________________________
15
DS1864
Functional Diagrams (continued)
Detailed Description
The DS1864 manages all system monitoring functions
in a fiber-optic data transceiver module in accordance
with SFF-8472 MSA. The IC communicates with a host
system through a I2C bus, and can be programmed
with a unique I2C address.
The IC offers temperature-controlled lookup tables for
its two current-sink DACs. Monitoring and calibration
functions for supply voltage, temperature and three
analog signals are available, as well as programmable
alarm and warning flags for these signals which can be
used to trigger interrupts based on user-specified limits.
The IC also possesses laser shutdown (eye safety) features such as programmable fast-trip alarms and interrupts, in addition to signals such as FETG for laser
safety disconnect.
The memory is protected by a customizable two-layer
password scheme. Furthermore, the memory layout
can be configured to be compatible with the
DS1852/DS1856 or the DS1859.
An overview of the DS1864’s functions is shown in the
block diagram in Figure 11. Additional DS1864 functions are shown in Figures 12 and 13.
Control Features
The DS1864 contains two current-sink DACs, DAC0 and
DAC1. Normally, each DAC is controlled by a temperature-indexed lookup table (LUT), which can change the
DAC settings based on the temperature measured by
the internal temperature sensor. However, each DAC
can also be manually programmed by the user.
DAC0 and DAC1
The current-sink DACs are linear and have two userselectable ranges, 1.5mA and 0.5mA. The range is
selected by the DAC0R and DAC1R bits located in
address 88h in Table 04h (Table 01h in DS1859 configuration). The 1.5mA range is selected when the corresponding bit is set to a 1, and the 0.5mA range is
selected when the corresponding bit is set to a 0. The
temperature-indexed LUT for each DAC determines the
value to be loaded in to the DAC0 and DAC1 registers
(bytes 82h and 83h respectively in Table 04h (Table 01h
in DS1859 configuration)). The DACs can be disabled
(placed in a high-impedance mode) by pulling the TX-D
pin high. The TXDC control bit (Lower Memory Register,
byte 6Eh, bit 6) can also be used to disable the DAC
outputs by placing them in a high-impedance state.
To determine the DAC position to produce a desired
current, the following equation can be used:
⎛ DESIRED CURRENT ⎞
DESIRED POSITION = ⎜
⎟ × 255
⎝ FULL SCALE CURRENT ⎠
Update bits are provided to indicate when an A/D conversion has completed for each monitored value. These
bits are located in Lower Memory, byte 77h.
DAC Lookup Table (LUT) Operation
The current-sink DAC settings are determined by temperature-controlled Lookup Tables (LUTs). The LUTs
are located in Table 02h for DAC0 and Table 03h for
DAC1. The lookup tables are 72 bytes each and allow
the biasing to be adjusted every 2°C between -40°C
and +102°C. Temperatures less than -40°C or greater
than +102°C use the -40°C or +102°C values, respectively. The values programmed into the LUTs are 8-bit
unsigned values that represent the desired DAC setting
for each 2°C temperature window. The LUTs have 1°C
hysteresis (see Figure 14) to prevent the DAC’s setting
from chattering in the event the temperature remains
near a LUT switching point. Table 1 shows which register corresponds to which temperature in the LUTs.
Figure 14 shows how the LUT chooses which memory
location to use for the DACs depending on the temperature read from the internal temperature sensor.
The Temperature Index Byte (address 81h, Table 04h
(Table 01h in DS1859 configuration)) is automatically
calculated following each temperature conversion and
points to the corresponding location in the LUTs for the
9Ah
DECREASING
TEMPERATURE
99h
MEMORY LOCATION
DS1864
SFP Laser Controller and
Diagnostic IC
98h
97h
INCREASING
TEMPERATURE
96h
95h
2
4
Figure 14. LUT Hysteresis
16
____________________________________________________________________
6
8
10
TEMPERATURE (°C)
12
SFP Laser Controller and
Diagnostic IC
80
CORRESPONDING
TEMPERATURE (°C)
≤ -40°C
81
82
-38°C
-36°C
ADDRESS (hex)
⎯
⎯
C6
C7
+100°C
≥ +102°C
current temperature. The DAC value referenced in the
LUT is then loaded into address 82h of Table 04h
(Table 01h in DS1859 configuration) for DAC0 and into
address 83h of Table 04h (Table 01h in DS1859 configuration) for DAC1.
DAC Manual Mode
During normal operation, the DAC setting is automatically modified once per conversion cycle based on the
ADC results. However, if the TEN bit (bit 1, address
80h, Table 04h (Table 01h in DS1859 configuration)) is
set to 0, the DACs are placed in a manual mode and
temperature indexing is disabled. Once in manual
mode, the user programs the current-sink DACs by
writing the desired positions to addresses 82h and 83h
in Table 04h (Table 01h in DS1859 configuration) to
control DAC0 and DAC1, respectively.
RSEL Operation
The rate select pin (RSEL) along with the SELC rate
select bit (Lower Memory Register, byte 6Eh, bit 3)
determine the state of the RSELOUT pin, which is
intended to be used to control receiver multirate performance. The RSEL pin state is OR’ed with the state of the
SELC bit to determine the RSELOUT pin state. Bit SELS
(Lower Memory Register, byte 6Eh, bit 4) indicates the
state of the RSEL pin. See Figure 13 for more details.
Monitoring Features
The DS1864 incorporates five basic monitor channels,
which include temperature, supply voltage (VCC), and
three external channels (MON1, MON2, and MON3).
These analog signals are sampled and converted into
digital measurements and compared to threshold limits
to determine alarm and warning signals and fault states.
These five signals can be calibrated externally, using
reserved registers for calibration values, or internally,
using built-in gain, offset, and right-shifting functions.
Digital Diagnostics
In optical transceiver applications, the external monitor
channels are typically used for Bias Current (IBI)
through pins MON1P and MON1N, Transmitted Power
(TXP) through a MON2 pin, and Received Power (RIN)
through pins MON3P and MON3N. While MON2 is a
single-ended monitor, MON1 and 3 have the option of
being used as differential or single-ended monitors. To
use these channels single-ended, connect the ‘N’ side
to ground. A 13-bit ADC samples and digitizes the five
analog signals and the results are stored in registers
60h through 69h in the Lower Memory. The representative digital values are 13-bits wide (left justified), and
are stored in successive register pairs. The temperature value is stored in a 2’s complement format, while
VCC and the three analog inputs are stored in an unsigned format. The digital values are updated every
tFRAME. From these measurements, alarms and warnings are generated after a digital comparison with high
and low set limits. A maskable interrupt, MINT, asserted
through TX-Fault, can be enabled based on any combination of alarms and warnings.
Alarm and Warning Flags
Alarm and warning flags are generated by comparing
the digitally converted values of the measured temperature, supply voltage, and three MON inputs with userprogrammed upper and lower limits. These limits are
stored in EEPROM locations 00h through 27h in the
Lower Memory. The two types of flags, alarm and warning, are also stored in the Lower Memory. Addresses
70h and 71h contain the alarm flags, while addresses
74h and 75h contain the warning flags. The Alarms and
Warnings section under Fault Management describe
how to program the alarm and warning thresholds, and
how to use them to generate interrupts.
Calibration Overview
Calibration is provided internally or externally. External
calibration makes use of a range of registers, reserved
for this purpose according to SFF-8472 standard. This
range is 38h to 5F in the Lower Memory Registers. The
calibration constants are loaded in the registers during
system test. In external calibration mode, a host
processor retrieves the constants and computes the
calibrated data.
The DS1864 features internal calibration for the five
analog channels. Internal calibration makes use of two
registers for four of the five monitored analog channels:
VCC, MON1 (Bias Current (IBI)), MON2 (Transmitted
Power (TXP)) and MON3 (Received Power (RIN)). One
register is for offset calibration, the other for gain calibration. Both registers are loaded during system test.
Only the offset scaling register is used for temperature.
____________________________________________________________________
17
DS1864
Table 1. LUT Addresses For
Corresponding Temperature Values
DS1864
SFP Laser Controller and
Diagnostic IC
Internal calibration applies to measured values acquired
by the ADC, and does not apply to the fast alarms. If internal calibration is desired, each analog channel requires
that registers 8Eh through AFh in Table 04h (Table 01h in
DS1859 configuration) are loaded with the appropriate values to calibrate for gain and offset. Every gain and offset
register is 2-bytes wide. Both gain and offset calibration
are independently capable of converting input variables
into a digital output range spanning 0000h to FFFFh.
The last adjustment is made by using right-shifting.
Right-shifting registers are located in registers A2h
through ABh and AEh to AFh, and store a 3-bit value
used to shift each MON value from 0 to 7 spaces to the
right. The effect of this is to make better use of the ADC
range and increase the accuracy of the readings. Rightshifting is the last function performed on the MON signal before the digital value is sent to the MON register.
Temperature Monitor Operation
The internal temperature monitor values are stored in
16-bit 2’s complement format, and located in memory
addresses 60h and 61h of the Lower Memory. The temperature conversions are updated every tFRAME, and
do not occur during an active read or write to memory.
The factory default calibration values for the temperature monitor are shown in Table 2.
Table 2. Internal Temperature Monitor
Factory Default Calibration
SIGNAL
+FS
SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)
Temperature
+127.96875°C
7FF8
-128.00°C
8000
To convert the 2s complement register value to the temperature it represents, first convert the 2-byte hexadecimal value to a decimal value as if it is an unsigned value,
then divide the result by 256. Finally, subtract 256 if the
result of the division is greater than or equal to +128.
Example converted values are shown in Table 3 below.
Table 3. Temperature Conversion Values
18
MSB
(bin)
LSB
(bin)
TEMPERATURE
(°C)
01000000
00000000
64
01000000
00001111
64.059
01011111
00000000
95
11110110
00000000
-10
11011000
00000000
-40
The offset of the temperature sensor can be adjusted
using the internal calibration registers to account for
differences between the ambient temperature at the
location of the DS1864 and the temperature of the
device it is biasing. When offsets are applied to the
temperature measurement, the value converted is offset by a fixed value from the DS1864’s ambient temperature. For more information, see the following
Temperature Monitor Offset Calibration section.
Temperature Monitor Offset Calibration
The DS1864’s temperature sensor comes precalibrated
and requires no further adjustment by the customer for
proper operation. However, it is possible to characterize
a system and add a fixed offset to the DS1864’s temperature reading so it is representative of another location’s
temperature. This is not required for biasing because
the temperature offset can be accounted for by adjusting the data’s location in the LUTs, but this feature is
available for customers that see application benefits.
To change the temperature sensor’s offset: write the
temperature offset register to 0000h, measure the
source reference temperature (TREF, °C), and read the
temperature from the DS1864 (TDS1864, °C). Then, the
following formula can be used to calculate the value for
the temperature offset register.
TEMP OFFSET = (64 × (−275 + TREF − TDS1864 ))
XORBITWISE BB40h
Once the value is calculated, write it to the temperature
offset register.
Voltage Monitor Operation
In addition to monitoring temperature, the DS1864 monitors VCC and the three MON inputs in a round-robin
fashion using its 13-bit A/D converter. The converted
values are stored in memory addresses 62h to 69h as
16-bit unsigned numbers with the ADC results left justified in the register. The round-robin update time is
specified by tFRAME in the analog voltage monitoring
characteristics.
The default factory-calibrated values for the voltage
monitors are shown in Table 4.
By using the internal gain and offset calibration registers the +FS and -FS signal values shown in Table 4
can be modified to meet customer needs. For more
information on calibration, see the following Voltage
Monitor Calibration section.
Note: ±FS voltages shown in Table 4 were calculated
assuming factory-programmed gain and offset values
in addition to right shifting set to 0.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
SIGNAL
+FS
(V)
+FS
(hex)
-FS
(V)
-FS
(hex)
VCC
6.5528V
FFF8
0V
0000
MON1
2.4997V
FFF8
0V
0000
MON2
2.4997V
FFF8
0V
0000
MON3
2.4997V
FFF8
0V
0000
To calculate the voltage measured from the register
value, first calculate the LSB weight of the 16-bit register.
The LSB weight is equal to the full-scale voltage span
divided 65528. Next, convert the hexadecimal register
value to decimal and multiply it times the LSB weight.
Example: Using the factory default VCC trim, what voltage is measured if the VCC register value is C340h?
The LSB for VCC is equal to (6.5528V - 0V) / 65528 =
100.00µV. C340h is equal to 49984 decimal, which
yields a supply voltage equal to 49984 x 100.00µV =
4.9984V. Table 5 shows more conversion examples
based on the factory trimmed A/D settings.
The factory-programmed LSB for VCC is 100µV. The
factory-programmed LSB weight for the MON channels
is 38.147µV.
Table 5. Voltage Monitor Conversion
Examples
REGISTER
VALUE (HEX)
INPUT
VOLTAGE
(V)
SIGNAL
LSB
WEIGHT µV)
VCC
100.00
8080
3.2896
VCC
100.00
C0F0
4.9392
MON1
38.147
AA00
1.6601
MON2
38.147
1880
0.2392
MON3
38.147
9CF0
1.5326
Voltage Monitor Calibration
(Gain, Offset, and Right Shifting)
The DS1864 has the ability to scale each analog voltage’s gain and offset to produce the desired digital
result. Each of the inputs (VCC, MON1, MON2, MON3)
has specific registers for the gain, offset, and right shifting (in memory Table 04h (Table 01h in DS1859 configuration)) allowing them to be individually calibrated.
To scale the gain and offset of the converter for a specific input, one must first know the relationship between
the analog input and the expected digital result. The
input that would produce a digital result of all zeros is
the null value (normally this input is GND). The input
that would produce a digital result of all ones (FFF8h) is
the full-scale (FS) value. The expected FS value is also
found by multiplying FFF8h by the LSB weight.
The right-shifting operation on the A/D converter output
is carried out based on the contents of Registers Right
Shift1 and Right Shift2 in EEPROM. Each of the three
analog channels (MON1 (Bias Current (IBI)), MON2
(Transmitted Power (TXP)), and MON3 (Received Power
(RIN)) is allocated 3 bits to set the number of right shifts.
Up to 7 right-shift operations are allowed and will be
executed as a part of every conversion before the result
is loaded in the corresponding measurement registers
62h to 69h. This is true during the setup of internal calibration as well as during subsequent data conversions.
Example: Since the FS digital reading is 65528 (FFF8h)
LSBs, if the LSB’s weight is 50µV, then the FS value is
65528 x 50µV = 3.2764V.
A binary search is used to calibrate the gain of the converter. This requires forcing two known voltages on the
input pin. It is preferred that one of the forced voltages is
the null input and the other is 90% of FS. Since the LSB
of the least significant bit in the digital reading register is
known, the expected digital results can be calculated
for both the null input and the 90% of full-scale value.
An explanation of the binary search used to scale the gain
is best served with the following example pseudo-code:
/* Assume that the null input is 0.5V */
/* Assume that the requirement for the LSB is 50µV */
FS = 65528 * 50e-6;
/*3.2764V */
CNT1 = 0.5 / 50e-6;
/* 1000 */
CNT2 = 0.9 X FS / 50e-6;
/* 58968 */
/* So the null input is 0.5V and 90% of FS is 2.94876V */
Set the input's offset register to zero
gain_result = 0h;
/* Working register for gain calculation */
CLAMP = FFF0h;
/* This is the max A/D value*/
For n = 15 down to 0
begin
gain_result = gain_result + 2^n;
Write gain_result to the input's gain register;
Force the 90% FS input (2.94876V);
Meas2
= A/D result from DS1864;
If Meas2 >= CLAMP
Then
gain_result = gain_result - 2^n;
Else
Force the null input (0.5V)
Meas1 = A/D result from DS1864
If [(Meas2-Meas1)>(CNT2-CNT1)]
Then
gain_result = gain_result - 2^n;
end;
Write gain_result to the input's gain register;
____________________________________________________________________
19
DS1864
Table 4. Voltage Monitor Factory Default
Calibration
DS1864
SFP Laser Controller and
Diagnostic IC
The gain register is now set and the resolution of the
conversion will match the expected LSB. Customers
requiring nonzero null values (e.g., 0.5V as the example
shows) must next calibrate the input’s offset. If the
desired null value is 0V, leave the offset register programmed to 0000h and skip this step.
To calibrate the offset register, program the gain register with the gain_result value determined above. Next,
force the null input voltage (0.5V for the example) and
read the digital result from the part (Meas1). The offset
value can be calculated using the following formula:
⎛ Meas1⎞
OFFSET = −1 × ⎜
⎟
⎝ 4 ⎠
This value is then programmed into the corresponding
offset register.
Enhanced RSSI Monitoring
(Dual-Range Functionality)
The DS1864 offers a brand new feature to improve the
accuracy and range of MON3, which is most commonly
used for monitoring RSSI. Predecessors of the DS1864,
namely the DS1859 and the DS1856, feature programmable gain, offset, and right shifting (Scalable Dynamic
Ranging) on each of the MON channels. These three
elements are extremely beneficial when monitoring lowamplitude signals such as RSSI. The accuracy of the
RSSI measurements is increased at the small cost of
reduced range (of input signal swing). The DS1864
eliminates this tradeoff by offering “dual-range” calibration on the MON3 channel. This feature enables right
shifting (along with its gain and offset settings) when
the input signal is below a set threshold (within the
range that benefits using right shifting) and then automatically disables right shifting (recalling different gain
and offset settings) when the input signal exceeds the
threshold. Also, to prevent “chattering,” hysteresis prevents excessive switching between modes in addition
to ensuring that continuity is maintained. Dual-range
operation is enabled by default (factory programmed in
EEPROM). However, it can easily be disabled by the
RSSIF and RSSIC bits, which are described later in this
section. When dual-range operation is disabled, MON3
operates identically to the other MON channels,
although featuring a differential input.
Dual-range functionality consists of two modes of operation: fine mode and course mode. Each mode is calibrated for a unique transfer function, hence the term
“dual range.” Table 7 highlights the registers related to
MON3. Fine mode is equivalent to the other MON channels and is similar to the DS1859 and DS1856. Fine
mode is calibrated using the gain, offset, and right
20
shifting registers at locations shown in Table 7 and is
ideal for relatively small analog input voltages. Course
mode is automatically switched to when the input
exceeds the threshold (to be discussed in a subsequent paragraph). Course mode is calibrated using different gain and offset registers, but lacks right shifting
(since course mode is only used on large input signals). The gain and offset registers for course mode are
also shown in Table 7. Additional information for each
of the registers can be found in the memory map.
Dual-range operation is transparent to the end user.
The results of MON3 analog-to-digital conversions are
still stored/reported in the same memory locations (68
to 69h, Lower Memory) regardless of whether the conversion was performed in fine mode or course mode.
The only way to tell which mode generated the digital
result is by reading the RSSIS bit.
When the DS1864 is powered up, analog-to-digital conversions begin in a round-robin fashion. Every MON3
timeslice begins with a fine mode analog to digital conversion (using fine mode’s gain, offset, and right-shifting settings). See the flowchart in Figure 15. Then,
depending on whether the last MON3 timeslice resulted
in a course mode conversion and also depending on
the value of the current fine conversion, decisions are
made whether to use the current fine mode conversion
result or to make an additional conversion (within the
same MON3 timeslice), using course mode (using
course mode’s gain and offset settings⎯and remember, no right shifting) and reporting the course mode
result. The flowchart also illustrates how hysteresis is
implemented. The fine mode conversion is compared
to one of two thresholds. The actual threshold values
are a function of the number of right shifts being used.
Table 6 shows the threshold values for each possible
number of right shifts.
The RSSIF and RSSIC bits are used to force fine mode
or course mode conversions, or to disable the dualrange functionality. Dual-range functionality is enabled
by default (both RSSIC and RSSIF are factory programmed to “0” in EEPROM). It can be disabled by setting RSSIC to 0 and RSSIF to 1. These bits are also
useful when calibrating MON3. For additional information, see the Memory Map.
Fault Management
The DS1864 provides a variety of system alerts to help
automate laser control. These alerts are in the form of
fast-trip comparators, fast-trip alarm and warning
thresholds, diagnostic alarm and warning thresholds,
and configurable laser eye safety and shutdown logic.
Fast-trip comparator values are measured against fasttrip thresholds to set alarms and to enable fault and
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
# OF RIGHT
SHIFTS
FINE MODE MAX
(HEX)
COURSE MODE
MIN* (HEX)
0
FFF8
F000
1
7FFC
7800
2
3FFE
3C00
3
1FFF
1E00
4
0FFF
0F00
5
07FF
0780
6
03FF
03C0
7
01FF
01E0
DS1864
Table 6. MON3 Hysteresis Threshold
Values
MON3
TIMESLICE
PERFORM FINE
MODE CONVERSION
DID PRIOR MON3
TIMESLICE RESULT IN A
COURSE CONV.?
(RSSIS = 1?)
Y
N
WAS CURRENT FINE
MODE CONV. <
COURSE MIN?
*This is the minimum reported course mode conversion.
Table 7. MON3 Configuration Registers
DID CURRENT FINE
MODE CONV.
REACH MAX?
Y
Y
FINE MODE
COURSE
GAIN REGISTER
98 to 99h,
Table 04h*
9A to 9Bh,
Table 04h*
OFFSET REGISTER
A8 to A9h,
Table 04h*
AA to ABh,
Table 04h*
RSSIS BIT = 0
RSSIS BIT = 1
RIGHT SHIFT REGISTER
8Fh,
Table 04h*
N/A
REPORT FINE
CONVERSION RESULT
REPORT COURSE
CONVERSION RESULT
RSSIC AND RSSIF BITS
RSSIS BIT
MON3 MEASUREMENT
N
PERFORM COURSE
MODE CONVERSION
N
8Ah, Table 04h*
77h, Lower Memory
68 to 69h, Lower Memory
*Table 04h in DS1852 configuration or Table 01h in DS1859
configuration.
shutdown signals. Alarm and warning thresholds keep
the system functioning within user-programmed parameters. All alarm and warning flags are active high.
Fast-trip alarms and warnings can be configured to
overwrite the diagnostic flags for the same function.
Laser safety features are also implemented to accept
and send alarm signals to control laser activity.
Fast-Trips
The three monitor channels (MON1, MON2, and MON3)
have associated fast channels. A sequencer with fast-trip
comparators monitors the three voltage channels: MON1
(Bias Current (IBI)), MON2 (Transmitted Power (TXP)),
and MON3 (Received Power (RIN)). These signals are the
same raw (uncalibrated) signals used for the diagnostic
circuits. Five fast-trip flags (alarms and warnings) are
generated: high-bias alarm (HBAL), high-bias warning
(HBWA), high transmitted power (HTXP), low transmitted
power (LTXP), and loss of received signal (LOS), see
END OF MON3
TIMESLICE
Figure 15. Dual-Range Functionality Flowchart
Figure 12. These flags are located in Lower Memory, byte
73h. These flags are latched temporarily by design as
required by the sequencer. In order to disable a comparator, set its threshold to 00h for low flags and FFh for
high flags. The FT_enable bit (bit 3, byte 80h, Table 04h
(Table 01h in DS1859 configuration)) determines if fasttrip alarms are enabled or disabled.
The thresholds for HBAL and HBWA can be programmed to be temperature compensated. Registers
B0h to B7h for HBAL and B8h to BFh for HBWA of
Table 04h (Table 01h in DS1859 configuration) are
where the temperature-compensated alarm and warning thresholds are stored. Register DBh of Table 04h
(Table 01h in DS1859 configuration) is the location of
the HTXP programmable threshold. Register DCh of
____________________________________________________________________
21
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 configuration) is the
location of the LTXP programmable threshold. Register
DDh of Table 04h (Table 01h in DS1859 configuration)
is the location of the LOS programmable threshold.
Alarms and Warnings
There are ten comparators for alarms and ten comparators for warnings for the five analog channels: VCC,
Temperature, MON1, MON2, and MON3. These comparators have high and low threshold limits, which are
used to determine when alarm and warning flags are
triggered. A high alarm flag occurs when a comparator
determines if the monitored analog value is above a
programmable threshold. A low alarm flag occurs when
a comparator determines if the monitored analog value
is below a programmable threshold. The same applies
for high and low warning flags, though warning flags
are typically set to trip prior to the alarm flags. The programmable thresholds have a 2-byte set point in the
same format as the ADC values stored in Lower
Memory bytes 60h through 69h. The programmable
high and low thresholds for both alarms and warnings
are located in Lower Memory bytes 00h through 27h.
The status bits for the alarm flags are located in Lower
Memory bytes 70h and 71h. The status bits for the
warning flags are located in Lower Memory bytes 74h
and 75h. A high alarm or warning flag is set to a 1 when
the corresponding digital value exceeds the user programmed high threshold. A low alarm or warning flag
is set to a 1 when the corresponding digital value
goes below the user-programmed low threshold.
Comparisons of all measured values with high and low
alarm and warning limits are done automatically.
The MASK bits control which flags can assert the maskable interrupt bit, MINT (bit 0, address 71h of the Lower
Memory). The MASK bits are located in Table 01h,
bytes F8h through FBh, or Table 05h, bytes F8h
through FBh, depending on the state of the MASK bit
(Table 04h (Table 01h in DS1859 configuration), byte
DAh, bit 0). If the MASK bit is 0, then the values in
addresses F8h through FBh in Table 05h will determine
which flags will assert MINT. If the MASK bit is 1, then
the values in addresses F8h through FBh in Table 01h
(Table 00h in DS1859 configuration) will determine
which flags will assert MINT.
TX-F, INTX-F, and TX-D
The TX-F pin is used to indicate a DAC shutdown and/or
laser fault. See the logic diagram in Figure 12. The
TXDC control bit (bit 6, byte 6Eh of the Lower Memory)
is a software-controllable shutdown feature. It not only
triggers TX-F to go active when set to a 1, but will also
disable the DACs, shutting down the laser. The TX-D pin
acts like a hardware version of the TXDC bit, triggering
22
the TX-F pin and disabling the DACs when set high. The
MINT interrupt bit discussed earlier also can trigger the
TX-F pin if configured to enable when one of its alarm or
warning flags goes high. Four fast-trip flags also can
trigger TX-F to go active. The INTX-F pin, used for triggering from an externally generated transmit fault signal, can also be used to trigger the TX-F pin. The INV bit
(bit 2, byte 89h, Table 04h (Table 01h in DS1859 configuration)) is used to invert the polarity of the TX-F pin.
TXF bit (bit 2, byte 6Eh, Lower Memory) is a status bit
that indicates the state of the output pin TX-F. The TX-F
pin is not latched, except in the case of a shutdown
fault. The status of TX-F will reset to inactive upon
removal of the causes of the alarms, or upon resetting of
the shutdown fault. The TX-F pin is open drain.
RX-LOS and INLOS
The RX-LOS pin is used to indicate a loss of received
signal on the MON3 (Received Power) input. RX-LOS
can be triggered by either the external signal, INLOS,
or the internal alarm, LOS flag. INLOS is an input pin
that can be used to indicate a loss of signal generated
from an external source. LOS flag (bit 2, byte 73h of
Lower Memory) can also be used to indicate a loss of
signal. LOS flag is active high when the value of MON3
goes below its threshold, set by programming byte
DDh of Table 04h (Table 01h in DS1859 configuration)
to the desired limit. To configure which signal triggers
RX-LOS, the LOSC bit (bit 6, byte 89h, Table 04h
(Table 01h in DS1859 configuration)) is used. If LOSC
= 1, INLOS is used to trigger the RX-LOS indicator. If
LOSC = 0, then the LOSC flag is used. The final control
bit for this logic is the INVL bit. The INVL bit (bit 0, byte
89h, Table 04h (Table 01h in DS1859 configuration)) is
used to invert the polarity of the RX-LOS pin. The RXLOS pin is open drain. See Figure 13 for details.
FETG Laser Safety Features
An auxiliary shutdown signal FETG can be asserted
during a safety fault to disconnect the laser from its
supply as a laser safety disconnect. The polarity of this
signal is determined by the FPOL bit (bit 7, byte DAh in
Table 04h (Table 01h in DS1859 configuration)). If
FPOL is 1, then FETG is high in a shutdown condition. If
FPOL is 0, then FETG is low in a shutdown condition.
A safety fault is a latched event that is generated from
the fast-trip flags (LTXP, HBAL, and HTXP). These flags
can be independently configured to initiate a safety
fault using the enable bits (bits 4, 5, and 6 in byte DAh
of Table 04h (Table 01h in DS1859 configuration)). A 1
for these bits enables that specific flag to generate a
safety fault, while a 0 masks the flag. When a safety
fault is generated, the DACs are disabled (forced to a
high-impedance state), FETG is disabled (driven low),
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
Power-Up and Low-Voltage Operation
During power-up, the device is inactive until V CC
exceeds the analog power-on-reset (VPOA), at which
time the device becomes fully functional. Once V CC
exceeds VPOA, the RDYB bit (address byte 6Eh, bit 0)
is timed to go from a 1 to a 0 and indicates when A/D
conversions begin. If VCC ever dips below VPOA, the
RDYB bit reads as a 1 again. Once a device exceeds
VPOA and the EEPROM is recalled, the values remain
active (recalled) until VCC falls below VPOD.
As the device powers up, the V CC low alarm flag
defaults to a 1 until the first VCC A/D conversion occurs
and sets or clears the flag accordingly.
Memory Organization
The DS1864 memory map is divided into seven sections that include Auxiliary Memory, Lower Memory,
and five Upper Memory tables. The Upper Memory
tables are addressed by setting the Table Select Byte
(7Fh in the Lower Memory) to the desired table number
and accessing the upper memory locations (80h to
FFh). The Lower Memory and Auxiliary Device can be
addressed at any time regardless of the state of the
Table Select Byte. The Lower Memory and Table 04h
(Table 01h in DS1859 configuration) are used to configure the DS1864 and read the status of the monitors.
Memory Tables 02h and 03h contain the temperature
indexed DAC Lookup Tables. Memory Tables 05h and
01h (Table 00h in DS1859 configuration) contain masks
for alarm and warning flags. Table 01h (Table 00h in
DS1859 configuration) also contains password settings.
The Mode bit (bit 3, byte 89h in Table 04h (Table 01h in
DS1859 configuration)) selects between DS1852/
DS1856-compatible memory configuration or the
DS1859-compatible memory configuration. See Figures
16 and 17 for more information.
Die Identification
DS1864 has an ID hard coded in its die. Three registers
(Table 05h, bytes C0h to C2h) are assigned for this feature. Two registers are for the device ID, and a third
register is for the version number. ID registers are hard-
wired at the time of manufacture and are globally readable through the I2C interface.
Memory Map Configurations
The default DS1864 memory configuration is compatible with the DS1852 memory map. The Mode bit (bit 3,
register 89h of Table 04h (Table 01h in DS1859 configuration)) can be selected to make the DS1864 memory
map compatible with the DS1859 memory map. Figure
16 shows the DS1852/DS1856 compatible configuration
(default), and Figure 17 shows the DS1859-compatible
configuration.
When the DS1864 is in the DS1852-compatible configuration, user memory is in Table 01h. In contrast, when
the DS1864 is in the DS1859-compatible configuration
(having set Mode to 1), user memory is in Table 00h. In
addition, Table 04h in the DS1852 configuration will be
reassigned as Table 01h in the DS1859 configuration.
Memory Protection and Passwords
The memory of the DS1864 is protected by two passwords, PW1 (user password) and a PW2 (vendor password). The password entry location for both passwords
is in 7Bh-7Eh of Lower Memory and resides in SRAM.
The PW2 password setting locations are in Table 04h
(Table 01h in DS1859 configuration), registers C1h to
C6h. The PW1 password settings are in Table 05h, registers D1h to D6h. Password setting and password
entry bytes are write only (read as 0s).
Furthermore, the Auxiliary Memory and Main Device
Memory are divided into eight blocks; see Table 9. The
read and write protection for each block is activated by
an enable bit. Two sets of enable bytes are used for
both PW1 and PW2 level access, one byte to allow read
access to the memory blocks and one byte for write
access to the memory blocks. The two PW2 password
enable bytes are located in Table 04h (Table 01h in
DS1859 configuration), registers C1h and C2h. The
PW1 password enable bytes are located in Table 05h,
registers D1h and D2h. Table 8 shows how the password enable bytes can be configured to protect the
memory blocks. Table 9 shows the bit assignments for
each of the eight blocks of DS1864 memory. See the
registers mentioned above in the Memory Map section
for more details.
Note that regardless of read/write permissions for a
given table, password settings and password entry are
unconditionally read protected. They are write protected if the proper write enable bit is set to 1. Bytes 78h to
7Fh in Lower Memory are unprotected.
____________________________________________________________________
23
DS1864
and TX-F is set active. A falling edge of transmit disable
(the logic OR of TX-D/TXDC) will initiate a safety fault
recovery. At this point, the FETG output and the DACs
are enabled. The TX-F output will not be disabled until a
tINITR1 time later. LTXP is masked during this time period to allow for system recovery. HBAL and HTXP flags
are not masked and will generate another safety fault
if their appropriate limit is exceeded. A safety fault is not
generated on standard shutdowns (the logic OR of
TX-D/TXDC).
DS1864
SFP Laser Controller and
Diagnostic IC
I2C ADDRESS A0h
I2C ADDRESS A2h (DEFAULT)
00h
NOTE 1:
WHEN MODE BIT (TABLE 04h BYTE 89h BIT 3) = 0,
THE DS1864 IS IN DS1852/DS1856-COMPATIBLE CONFIGURATION (DEFAULT).
00h
NOTE 2:
IF ADFIX = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h.
F ADFIX = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS
DETERMINED BY THE VALUE IN 8Ch TABLE 04h (IN DS1852 CONFIGURATION).
LOWER MEMORY
GBIC EEPROM
(256 BYTES)
PASSWORD ENTRY (PWE)
(4 BYTES)
MAIN DEVICE
AUXILIARY DEVICE
NOTE 3:
TABLE 00h DOES NOT EXIST IN DS1852/DS1856 CONFIGURATION.
TABLE SELECT BYTE 7Fh
80h
80h
80h
TABLE 01h
TABLE 02h
TABLE 03h
TABLE 04h
TABLE 05h
EEPROM
(120 BYTES)
DAC0
LOOKUP TABLE
(72 BYTES)
DAC1
LOOKUP TABLE
(72 BYTES)
NON LOOKUP
TABLE CONTROL
AND CONFIGURATION
REGISTERS
CONTROL
AND CONFIGURATION
F7h
F8h
FFh
C7h
C7h
DFh
EEPROM
(8 BYTES)
FFh
Figure 16. DS1852/DS1856-Compatible Configuration (Mode Bit = 0, Default)
EEPROM Write Disable
The SEE control bit resides in Table 04h (Table 01h in
DS1859 configuration), register 80h, bit 2. By default
(SEE bit = 0) these locations act as ordinary EEPROM.
By setting SEE = 1, these locations function as SRAM
memory allowing an infinite number of write cycles. This
also eliminates the requirement for the EEPROM write
time. Because changes made with SEE = 1 do not
effect the EEPROM, these changes will not be retained
through power cycles. The power-up value will be the
last value written with SEE = 0.
24
C0h
80h
____________________________________________________________________
FBh
SFP Laser Controller and
Diagnostic IC
DS1864
I2C ADDRESS A0h
I2C ADDRESS A2h (DEFAULT)
00h
NOTE 1:
WHEN MODE BIT (TABLE 04h BYTE 89h BIT 3) = 1,
THE DS1864 IS IN DS1859-COMPATIBLE CONFIGURATION.
00h
NOTE 2:
IF ADFIX = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h.
F ADFIX = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS
DETERMINED BY THE VALUE IN 8Ch TABLE 01h (IN DS1859 CONFIGURATION).
LOWER MEMORY
GBIC EEPROM
(256 BYTES)
PASSWORD ENTRY (PWE)
(4 BYTES)
MAIN DEVICE
AUXILIARY DEVICE
NOTE 3:
TABLE 04h DOES NOT EXIST IN DS1859 CONFIGURATION.
TABLE SELECT BYTE 7Fh
80h
80h
80h
FFh
C0h
TABLE 00h
TABLE 01h
TABLE 02h
TABLE 03h
TABLE 05h
EEPROM
(120 BYTES)
NON LOOKUP
TABLE CONTROL
AND CONFIGURATION
REGISTERS
DAC0
LOOKUP TABLE
(72 BYTES)
DAC1
LOOKUP TABLE
(72 BYTES)
CONTROL
AND CONFIGURATION
FBh
C7h
F7h
F8h
80h
C7h
DFh
EEPROM
(8 BYTES)
FFh
Figure 17. DS1859-Compatible Configuration (Mode Bit = 1)
____________________________________________________________________
25
DS1864
SFP Laser Controller and
Diagnostic IC
Table 8. Password-Enable Chart
ENABLE BIT
ENABLE BIT
STATUS
PW2 (C1h, C2h)
TABLE 04h
(TABLE 01h IN
DS1859
CONFIGURATION)
PW1 (D1h, D2h),
TABLE 05h
⎯
0
0
UNPROTECTED
0
1
PW1 PASSWORD
PROTECTED
1
X
PW2 PASSWORD
PROTECTED
Table 9. Memory Block Assignments
MEMORY
BLOCK
(RANGE)
A0h
(00h TO 7Fh)
AUXILIARY
DEVICE
LOWER
MEMORY
A0h
(80h TO FFh)
AUXILIARY
DEVICE
UPPER
MEMORY
A2h
(00h TO 7Ah)
MAIN
DEVICE
LOWER
MEMORY
A2h
(80h TO F7h)
TABLE 01h*
A2h
(F8h TO FFh)
TABLE 01h*
A2h
(80h TO C7h)
TABLE 04h
AND
TABLES*
02h, 03h
ENABLE BIT
LOCATIONS
0
1
2
3
4
5
*Table 01h becomes Table 00h in DS1859 configuration.
Table 04h becomes Table 01h in DS1859 configuration.
26
____________________________________________________________________
A2h
(F8h TO FFh)
TABLE 05h
A2h
(D0h TO D6h)
TABLE 05h
6
7
SFP Laser Controller and
Diagnostic IC
A0h Auxiliary Device Memory Register Descriptions
Auxiliary Registers 00h To FFh: GBIC Memory
FACTORY DEFAULT:
00h
MEMORY TYPE:
EEPROM
These registers are used to store GBIC data as called out by the SFF-8472 specification. This block of EEPROM is accessed
through I2C slave address A0h.
A2h Main Device, Lower Memory Register Descriptions
Lower Memory Register 00h to 01h: High Temperature Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
00h
01h
S
-1
2
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
2-8
2
2
2
2
2
2
bit7
bit0
Temperature measurements above this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 7).
Measurements below this threshold will automatically clear its alarm bit.
Lower Memory Register 02h to 03h: Low Temperature Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
02h
S
26
25
24
23
22
21
20
03h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
bit7
bit0
Temperature measurements below this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 6).
Measurements above this threshold will automatically clear its alarm bit.
Lower Memory Register 04h to 05h: High Temperature Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
04h
S
26
25
24
23
22
21
20
05h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
bit7
bit0
Temperature measurements above this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 7).
Measurements below this threshold will automatically clear its warning bit.
____________________________________________________________________
27
DS1864
Memory Map
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 06h to 07h: Low Temperature Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
06h
S
26
25
24
23
22
21
20
07h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
bit7
bit0
Temperature measurements below this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 6).
Measurements above this threshold will automatically clear its warning bit.
Lower Memory Register 08h to 09h: High VCC Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
08h
09h
Shadowed Memory (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the VCC input above this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 5).
Measurements below this threshold will automatically clear its alarm bit.
Lower Memory Register 0Ah to 0Bh: Low VCC Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
0Ah
0Bh
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the VCC input below this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 4).
Measurements above this threshold will automatically clear its alarm bit.
Lower Memory Register 0Ch to 0Dh: High VCC Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
0Ch
0Dh
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
bit7
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the VCC input above this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit
5). Measurements below this threshold will automatically clear its warning bit.
28
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Lower Memory Register 0Eh to 0Fh: Low VCC Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
15
0Eh
2
214
213
212
211
210
29
28
0Fh
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurements of the VCC input below this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 4).
Measurements above this threshold will automatically clear its warning bit.
Lower Memory Register 10h to 11h: High MON1 Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
10h
11h
Shadowed Memory (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON1 input above this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 3).
Measurements below this threshold will automatically clear its alarm bit.
Lower Memory Register 12h to 13h: Low MON1 Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
12h
13h
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON1 input below this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 2).
Measurements above this threshold will automatically clear its alarm bit.
Lower Memory Register 14h to 15h: High MON1 Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
14h
15h
215
7
2
bit7
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the MON1 input above this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 3).
Measurements below this threshold will automatically clear its warning bit.
____________________________________________________________________
29
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 16h to 17h: Low MON1 Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
15
16h
2
214
213
212
211
210
29
28
17h
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurements of the MON1 input below this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 2).
Measurements above this threshold will automatically clear its warning bit.
Lower Memory Register 18h to 19h: High MON2 Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
18h
19h
Shadowed Memory (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON2 input above this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 1).
Measurements below this threshold will automatically clear its alarm bit.
Lower Memory Register 1Ah to 1Bh: Low MON2 Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
1Ah
1Bh
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON2 input below this threshold will set its corresponding alarm bit (Lower Memory Register 70h, bit 0).
Measurements above this threshold will automatically clear its alarm bit.
Lower Memory Register 1Ch to 1Dh: High MON2 Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
1Ch
1Dh
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
bit7
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the MON2 input above this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 1).
Measurements below this threshold will automatically clear its warning bit.
30
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Lower Memory Register 1Eh to 1Fh: Low MON2 Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
15
1Eh
2
214
213
212
211
210
29
28
1Fh
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurements of the MON2 input below this threshold will set its corresponding warning bit (Lower Memory Register 74h, bit 0).
Measurements above this threshold will automatically clear its warning bit.
Lower Memory Register 20h to 21h: High MON3 Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
20h
21h
Shadowed Memory (SEE)
15
2
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON3 input above this threshold will set its corresponding alarm bit (Lower Memory Register 71h, bit 7).
Measurements below this threshold will automatically clear its alarm bit.
Lower Memory Register 22h to 23h: Low MON3 Alarm Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
22h
23h
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
bit0
Voltage measurements of the MON3 input below this threshold will set its corresponding alarm bit (Lower Memory Register 71h, bit 6).
Measurements above this threshold will automatically clear its alarm bit.
Lower Memory Register 24h to 25h: High MON3 Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
24h
25h
215
7
2
bit7
214
6
2
213
5
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit0
Voltage measurements of the MON3 input above this threshold will set its corresponding warning bit (Lower Memory Register 75h, bit 7).
Measurements below this threshold will automatically clear its warning bit.
____________________________________________________________________
31
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 26h to 27h: Low MON3 Warning Limit
FACTORY DEFAULT:
0000h
MEMORY TYPE:
Shadowed Memory (SEE)
15
26h
2
214
213
212
211
210
29
28
27h
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurements of the MON3 input below this threshold will set its corresponding warning bit (Lower Memory Register 75h, bit 6).
Measurements above this threshold will automatically clear its warning bit.
Lower Memory Register 28h to 37h: Reserved Memory
28h to 37h
RESERVED
Lower Memory Register 38h to 5Fh: External Calibration Constants
FACTORY DEFAULT:
00h
MEMORY TYPE:
Nonvolatile (EEPROM)
38h TO 5Fh
EEPROM
If external calibration constants are used for calibrating the transceiver module, they can be stored in this section of memory,
reserved for such use under SFF-8472.
Lower Memory Register 60h to 61h: Measured Temperature
FACTORY DEFAULT:
N/A
MEMORY TYPE:
Volatile (SRAM)
60h
S
26
25
24
23
22
21
20
61h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
bit7
bit0
Signed 2’s complement direct-to-digital temperature measurement.
Lower Memory Register 62h to 63h: Measured VCC
FACTORY DEFAULT:
N/A
MEMORY TYPE:
Volatile (SRAM)
62h
63h
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
bit7
Unsigned voltage measurement of VCC.
32
____________________________________________________________________
210
2
2
29
28
1
20
2
bit0
SFP Laser Controller and
Diagnostic IC
DS1864
Lower Memory Register 64h to 65h: Measured MON1
FACTORY DEFAULT:
N/A
MEMORY TYPE:
Volatile (SRAM)
15
64h
2
214
213
212
211
210
29
28
65h
27
26
25
24
23
22
21
20
bit7
bit0
Unsigned voltage measurement of MON1 signal.
Lower Memory Register 66h to 67h: Measured MON2
FACTORY DEFAULT:
N/A
MEMORY TYPE:
Volatile (SRAM)
15
66h
2
214
213
212
211
210
29
28
67h
27
26
25
24
23
22
21
20
bit7
bit0
Unsigned voltage measurement of MON2 signal.
Lower Memory Register 68h to 69h: Measured MON3
FACTORY DEFAULT:
N/A
MEMORY TYPE:
68h
69h
Volatile (SRAM)
15
2
7
2
214
213
6
5
2
2
212
211
4
3
2
2
bit7
210
2
2
29
28
1
20
2
bit0
Unsigned voltage measurement of MON3 signal.
Lower Memory Register 6Ah to 6Dh: Reserved Memory
6Ah to 6Dh
RESERVED
____________________________________________________________________
33
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 6Eh: Logic States
POWER-ON VALUE:
x0xx0xxx b
MEMORY TYPE:
Volatile (SRAM)
WRITE
ACCESS
6Eh
N/A
ALL
N/A
N/A
ALL
N/A
N/A
N/A
TXDS
TXDC
IN1S
SELS
SELC
TXF
RXL
RDYB
bit7
bit0
bit7
TXDS: TX-Disable Status bit. Indicates the state of the TX-D pin.
0 = TX-D pin is low.
1 = TX-D pin is high.
bit6
TXDC: Soft TX-Disable bit. A control bit set by the user in order to control the On/Off state of both
DAC outputs.
0 = DACs enabled (Default).
1 = Forces the DAC0 and DAC1 outputs to a high-impedance (off) mode.
bit5
IN1S: A status bit reflecting the state of the IN1 input pin.
bit4
SELS: A status bit reflecting the state of the RSEL input pin.
bit3
SELC: Soft Rate Select. A control bit that set by the user and OR’d with SELS to set the state of the
RESELOUT pin. Used for bandwidth selection.
0 = (Default)
1 = This bit allows software control over the state of the RESELOUT pin.
bit2
TXF: A status bit that indicates the state of TX-F output pin.
0 = TX-F pin is at logic 0
1 = TX-F pin is at logic 1
bit1
RXL: A status bit that indicates the state of RX-LOS input pin.
0 = RX-LOS pin is at logic 0
1 = RX-LOS pin is at logic 1
bit0
RDBY: Ready Bar.
0 = VCC is above POA.
1 = VCC is below POA.
Lower Memory Register 6Fh: Reserved Memory
6Fh
34
RESERVED FOR SFF-8079
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Lower Memory Register 70h: Alarm Flags
POWER-ON VALUE:
Determined after each channel’s first analog-to-digital conversion.
MEMORY TYPE:
Volatile (SRAM)
70h
TMPhi
TMPlo
VCChi
VCClo
MON1hi
bit7
MON1lo
MON2hi
MON2lo
bit0
bit7
TMPalmhi: High Alarm Status for Temperature measurement.
0 = Temperature measurement is below set limit.
1 = Temperature measurement is above set limit.
bit6
TMPalmlo: Low Alarm Status for Temperature measurement.
0 = Temperature measurement is above set limit.
1 = Temperature measurement is below set limit.
bit5
VCCalmhi: High Alarm Status for VCC measurement.
0 = VCC measurement is below set limit.
1 = VCC measurement is above set limit.
bit4
VCCalmlo: Low Alarm Status for VCC measurement.
0 = VCC measurement is above set limit.
1 = VCC measurement is below set limit.
bit3
MON1almhi: High Alarm Status for MON1 measurement.
0 = MON1 measurement is below set limit.
1 = MON1 measurement is above set limit.
bit2
MON1almlo: Low Alarm Status for MON1 measurement.
0 = MON1 measurement is above set limit.
1 = MON1 measurement is below set limit.
bit1
MON2almhi: High Alarm Status for MON2 measurement.
0 = MON2 measurement is below set limit.
1 = MON2 measurement is above set limit.
bit0
MON2almlo: Low Alarm Status for MON2 measurement.
0 = MON2 measurement is above set limit.
1 = MON2 measurement is below set limit.
____________________________________________________________________
35
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 71h: Alarm Flags
POWER-ON VALUE:
Determined after each channel’s first analog-to-digital conversion.
MEMORY TYPE:
Volatile (SRAM)
71h
MON3hi
MON3lo
RESERVED
bit7
bit0
bit7
MON3almhi: High Alarm Status for MON3 measurement.
0 = MON3 measurement is below set limit.
1 = MON3 measurement is above set limit.
bit6
MON3almlo: Low Alarm Status for MON3 measurement.
0 = MON3 measurement is above set limit.
1 = MON3 measurement is below set limit.
bit5:1
bit0
Reserved
MINT: Maskable Interrupt. An interrupt output signal that is determined by unmasked alarm and
warning flags. Masks of alarm and warning flags are located in Table 01h (Table 00h in DS1859
configuration), bytes F8h through FBh, or Table 05h, bytes F8h through FBh, depending on the state
of the MASK bit (Table 04h (Table 01h in DS1859 configuration), byte DAh, bit 0), and determine the
state of MINT. MINT is maskable to 0 if no interrupt is desired by setting bytes F8h through FBh to a
value of 00h.
Lower Memory Register 72h: Reserved Memory
72h
36
MINT
RESERVED
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
POWER-ON VALUE:
00h
MEMORY TYPE:
Volatile (SRAM)
73h
0
0
0
HBWA flag
HBAL flag
LOS flag
LTXP flag
HTXP flag
bit7
bit0
These are the results from the fast-trip comparators. If these flags are latched, they can be cleared by writing the flags to 0.
bit7:5
These bits are set to 0.
bit4
HBWA flag: Fast-trip flag indicating the High Bias Warning Limit has been exceeded.
0 = Bias measurement is below set limit.
1 = Bias measurement is above set limit.
bit3
HBAL flag: Fast-trip flag indicating the High Bias Alarm Limit has been exceeded.
0 = Bias measurement is below set limit.
1 = Bias measurement is above set limit.
bit2
LOS flag: Fast-trip flag indicating the Loss of Signal Limit has been exceeded.
0 = LOS measurement is above set limit.
1 = LOS measurement is below set limit.
bit1
LTXP flag: Fast-trip flag indicating the Low Transmit Power Limit has been exceeded.
0 = RSSI measurement is above set limit.
1 = RSSI measurement is below set limit.
bit0
HTXP flag: Fast-trip flag indicating the High Transmit Power Limit has been exceeded.
0 = RSSI measurement is below set limit.
1 = RSSI measurement is above set limit.
____________________________________________________________________
37
DS1864
Lower Memory Register 73h: Fast-Trip Flags
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 74h: Warning Flags
POWER-ON VALUE:
Determined after each channel’s first analog-to-digital conversion.
MEMORY TYPE:
Volatile (SRAM)
74h
TMPhi
TMPlo
VCChi
VCClo
MON1hi
MON1lo
bit7
38
MON2hi
MON2lo
bit0
bit7
TMPwrnhi: High Warning Status for Temperature measurement.
0 = Temperature measurement is below set limit.
1 = Temperature measurement is above set limit.
bit6
TMPwrnlo: Low Warning Status for Temperature measurement.
0 = Temperature measurement is above set limit.
1 = Temperature measurement is below set limit.
bit5
VCCwrnhi: High Warning Status for VCC measurement.
0 = VCC measurement is below set limit.
1 = VCC measurement is above set limit.
bit4
VCCwrnlo: Low Warning Status for VCC measurement.
0 = VCC measurement is above set limit.
1 = VCC measurement is below set limit.
bit3
MON1wrnhi: High Warning Status for MON1 measurement.
0 = MON1 measurement is below set limit.
1 = MON1 measurement is above set limit.
bit2
MON1wrnlo: Low Warning Status for MON1 measurement.
0 = MON1 measurement is above set limit.
1 = MON1 measurement is below set limit.
bit1
MON2wrnhi: High Warning Status for MON2 measurement.
0 = MON2 measurement is below set limit.
1 = MON2 measurement is above set limit.
bit0
MON2wrnlo: Low Warning Status for MON2 measurement.
0 = MON2 measurement is above set limit.
1 = MON2 measurement is below set limit.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Lower Memory Register 75h: Warning Flags
POWER-ON VALUE:
Determined after each channel’s first analog-to-digital conversion.
MEMORY TYPE:
Volatile (SRAM)
75h
MON3hi
MON3lo
RESERVED
bit7
bit0
bit7
MONwrn3hi: High Warning Status for MON3 measurement.
0 = MON3 measurement is below set limit.
1 = MON3 measurement is above set limit.
bit6
MON3wrnlo: Low Warning Status for MON3 measurement.
0 = MON3 measurement is above set limit.
1 = MON3 measurement is below set limit.
bit5:0
Reserved
Lower Memory Register 76h: Reserved Memory
76h
RESERVED
____________________________________________________________________
39
DS1864
SFP Laser Controller and
Diagnostic IC
Lower Memory Register 77h: Conversion Updates
POWER-ON VALUE:
00h
MEMORY TYPE:
Volatile (SRAM)
77h
TAU
VCCU
MON1U
MON2U
MON3U
0
bit7
0
RSSIS
bit0
Each of the status bits becomes a 1 after an update has occurred for the corresponding measurement. The user can write any of
the status bits to a 0 and monitor for a transition to a 1 to verify that a measurement has occurred.
bit7
TAU: Temperature measurement update status bit.
0 = Temperature measurement has not yet been updated.
1 = Temperature measurement has been updated.
bit6
VCCU: VCC measurement update status bit.
0 = VCC measurement has not yet been updated.
1 = VCC measurement has been updated.
bit5
MON1U: MON1 measurement update status bit
0 = MON1 measurement has not yet been updated.
1 = MON1 measurement has been updated.
bit4
MON2U: MON2 measurement update status bit.
0 = MON2 measurement has not yet been updated.
1 = MON2 measurement has been updated.
bit3
MON3U: MON3 measurement update status bit.
0 = MON3 measurement has not yet been updated.
1 = MON3 measurement has been updated.
bit2
This status bit is set to 0.
bit1
This bit is reserved and reads as 0.
bit0
RSSIS: Indicates which range is being reported for MON3 internal calibration.
0 = Fine range is being reported.
1 = Coarse range is being reported.
Lower Memory Register 78h to 7Ah: Reserved Memory
78h to 7Ah
40
RESERVED
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Lower Memory Register 7Bh to 7Eh: Password Entry Bytes
POWER-ON VALUE:
0000 0000h
MEMORY TYPE:
Volatile (SRAM)
7Bh
31
2
230
229
228
227
226
225
224
7Ch
223
222
221
220
219
218
217
216
7Dh
15
14
13
12
11
10
2
7
7Eh
2
2
2
6
5
2
2
2
2
4
3
2
2
2
2
2
9
28
1
20
2
2
bit7
bit0
The password is entered into the four bytes to gain PW1 or PW2 level access. There are two levels of passwords for the DS1864.
The lower level password (PW1) will have access to unprotected areas plus those made available with PW1. The higher level
password (PW2) will have all of the access of PW1 plus those made available with PW2. See the Memory Protection section for
details on password access.
Lower Memory Register 7Fh: Table Select Byte
POWER-ON VALUE:
See below
MEMORY TYPE:
Volatile (SRAM)
7Fh
0
0
0
0
0
22
21
bit7
20
bit0
The upper memory tables of the DS1864 are selected by writing the desired Table value in this register. For example, if Table 04h is
to be selected, the value 04h will be written to register 7Fh. The Power On value of the Table Select Byte is determined by the value
written in Table 04h (Table 01h in DS1859 configuration), register C7h.
Table 01h In Default DS1852 Configuration, (Table 00h in DS1859 Configuration)
Register Descriptions
Table 01h (Table 00h in DS1859 Configuration), 80h to F7h: User Memory
FACTORY DEFAULT:
00h
MEMORY TYPE:
Nonvolatile (EEPROM)
80h to F7h
EEPROM
bit7
bit0
This is general use EEPROM.
____________________________________________________________________
41
DS1864
SFP Laser Controller and
Diagnostic IC
Table 01h (Table 00h in DS1859 Configuration), F8h: Alarm Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
F8h
TMPhi
TMPlo
VCChi
VCClo
MON1hi
MON1lo
MON2hi
bit7
MON2lo
bit0
Bytes F8h and F9h configure a maskable interrupt, determining which alarm flags assert the MINT bit (Lower Memory, byte 71h, bit
0). If one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
These bit locations do not match the register locations as called out in the SFF-8472, therefore another four byte set is also stored in
Table 05h, registers F8h to FBh. The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration), register DAh, bit 0)
determines which of these mask sets is used to generate the MINT interrupt.
42
bit7
TMPalmhimask: Determines if an interrupt is generated for a High Temperature Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
TMPalmlomask: Determines if an interrupt is generated for a Low Temperature Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5
VCCalmhimask: Determines if an interrupt is generated for a High VCC Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit4
VCCalmlomask: Determines if an interrupt is generated for a Low VCC Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit3
MON1almhimask: Determines if an interrupt is generated for a High MON1 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit2
MONalmlomask: Determines if an interrupt is generated for a Low MON1 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit1
MON2almhimask: Determines if an interrupt is generated for a High MON2 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit0
MON2almlomask: Determines if an interrupt is generated for a Low MON2 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 01h (Table 00h in DS1859 Configuration), F9h: Alarm Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
F9h
MON3hi
MON3lo
RESERVED
bit7
bit0
These bytes configure a maskable interrupt, determining which alarm flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
These bit locations do not match the register locations as called out in the SFF-8472, therefore another four byte set is also stored in
another location (Table 05h, registers F8h to FBh). The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration),
register DAh, bit 0) determines which mask sets is used to generate the MINT interrupt.
bit7
MONalm3himask: Determines if an interrupt is generated for a High MON3 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
MON3almlomask: Determines if an interrupt is generated for a Low MON3 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5:0
Reserved.
____________________________________________________________________
43
DS1864
SFP Laser Controller and
Diagnostic IC
Table 01h (Table 00h in DS1859 Configuration), FAh: Warning Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
FAh
TMPhi
TMPlo
VCChi
VCClo
MON1hi
MON1lo
MON2hi
MON2lo
bit7
bit0
These bytes configure a maskable interrupt, determining which warning flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
These bit locations do not match the register locations as called out in the SFF-8472, therefore another four byte set is also stored in
another location (Table 05h, registers F8h to FBh). The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration),
register DAh, bit 0) determines which of these mask sets is used to generate the MINT interrupt.
44
bit7
TMPwrnhimask: Determines if an interrupt is generated for a High Temperature Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
TMPwrnlomask: Determines if an interrupt is generated for a Low Temperature Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5
VCCwrnhimask: Determines if an interrupt is generated for a High VCC Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit4
VCCwrnlomask: Determines if an interrupt is generated for a Low VCC Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit3
MON1wrnhimask: Determines if an interrupt is generated for a High MON1 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit2
MONwrnlomask: Determines if an interrupt is generated for a Low MON1 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit1
MON2wrnhimask: Determines if an interrupt is generated for a High MON2 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit0
MON2wrnlomask: Determines if an interrupt is generated for a Low MON2 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 01h (Table 00h in DS1859 Configuration), FBh: Warning Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
FBh
MON3hi
MON3lo
RESERVED
bit7
bit0
These bytes configure a maskable interrupt, determining which warning flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
These bit locations do not match the register locations as called out in the SFF-8472, therefore another four byte set is also stored in
another location (Table 05h, registers F8h to FBh). The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration),
register DAh, bit 0) determines which mask sets is used to generate the MINT interrupt.
bit7
MON3wrnhimask: Determines if an interrupt is generated for a High MON3 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
MON3wrnlomask: Determines if an interrupt is generated for a Low MON3 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5:0
Reserved.
Table 01h (Table 00h in DS1859 Configuration), FCh to FFh: General Memory
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
FCh to FFh
EEPROM
bit7
bit0
This is memory reserved for general use.
Table 02h Register Descriptions
Table 02h, 80h to C7h: Temperature Lookup Table For DAC0
FACTORY DEFAULT:
00h
MEMORY TYPE:
Nonvolatile (EEPROM)
80h to C7h
EEPROM
bit7
bit0
This is the lookup table (LUT) for the DAC0 settings.
____________________________________________________________________
45
DS1864
SFP Laser Controller and
Diagnostic IC
Table 03h Register Descriptions
Table 03h, 80h to C7h: Temperature Lookup Table For DAC1
FACTORY DEFAULT:
00h
MEMORY TYPE:
Nonvolatile (EEPROM)
80h to C7h
EEPROM
bit7
bit0
This is the lookup table (LUT) for the DAC1 settings.
Table 04h In Default DS1852 Configuration, (Table 01h in DS1859 Configuration)
Register Descriptions
Table 04h (Table 01h in DS1859 Configuration), 80h: Mode
POWER-ON VALUE:
0Bh
MEMORY TYPE:
Volatile (SRAM)
80h
0
0
0
0
FT_enable
SEE
TEN
bit7
AEN
bit0
This byte controls the different modes of the DS1864. It controls the analog-to-digital updates, the shadowed EEPROM functionality
and the fast-trip comparators.
bit7:4
bit3
bit2
bit1
bit0
Value is 0.
FT_enable: Determines if the fast-trip comparators used to set fast-trip alarms are enabled or
disabled.
0 = Fast-trips are disabled.
1 = Fast-trips are enabled.
SEE: Determines if the Shadowed EEPROM acts like SRAM or EEPROM.
0 = Acts like EEPROM (Nonvolatile).
1 = Acts like SRAM (Volatile).
TEN: Determines if the temperature conversions are enabled or disabled.
0 = Temperature conversions disabled. DAC0 and DAC1 settings can be controlled manually by
writing to registers 82h and 83h in Table 04h (Table 01h in DS1859 configuration).
1 = Temperature conversions enabled. Lookup tables in automatic control mode. (default)
AEN: Determines if the address calculations from the LUT are enabled or disabled. This bit controls a
test mode setting that can allow manual control over the temperature index, Table 04h (Table 01h in
DS1859 configuration), Register 81h.
0 = Test mode. Manual control over Temperature Index enabled.
1 = Normal operation. Temperature index calculations automatically carried out.
Table 04h (Table 01h in DS1859 Configuration), 81h: Temperature Index Byte
FACTORY DEFAULT:
00h until first temperature conversion.
MEMORY TYPE:
81h
Volatile (SRAM)
7
2
26
25
24
23
22
bit7
This byte is the temperature calculated index used to select the address of DAC settings in the lookup tables.
46
____________________________________________________________________
21
20
bit0
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), 82h: DAC0 Value
DAC0 value is high-impedance (Hi-Z) until programmed value is recalled from
FACTORY DEFAULT:
MEMORY TYPE:
82h
Volatile (SRAM)
7
2
26
25
24
23
22
21
bit7
20
bit0
DAC values from 00h to FFh for DAC0 are stored here. Under normal operation, the LUTs automatically select the DAC setting
according to the values programmed into the corresponding LUT. This byte is updated automatically based on the current
temperature and is corresponding setting in the LUT.
Table 04h (Table 01h in DS1859 Configuration), 83h: DAC1 Value
DAC1 value is high-impedance (Hi-Z) until programmed value is recalled from
FACTORY DEFAULT:
MEMORY TYPE:
83h
Volatile (SRAM)
7
2
26
25
24
23
bit7
22
21
20
bit0
DAC values from 00h to FFh for DAC1 are stored here. Under normal operation, the LUTs automatically select the DAC setting
according to the values programmed into the corresponding LUT. This byte is updated automatically based on the current
temperature and is corresponding setting in the LUT.
Table 04h (Table 01h in DS1859 Configuration), 84h to 87h: Reserved Memory
84h to 87h
RESERVED
____________________________________________________________________
47
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), 88h: Configuration And Status
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
88h
IN1C
X
INV1
FT_latch
DAC1R
DAC0R
bit7
bit7
48
Alatch
Wlatch
bit0
IN1C: Software control bit for IN1 value.
0 = No interrupt is generated on OUT1.
1 = An interrupt is generated on OUT1.
bit6
No function.
bit5
INV1: Allows inversion of OUT1 pin value. OUT1=INV1[(IN1C)OR(IN1S)], where IN1S is from register 6Eh.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit4
FT_latch: Configures fast-trip flags to be latched or unlatched.
0 = Fast-trip flags unlatched.
1 = Fast-trip flags latched. They will clear when written to 0’s.
bit3
DAC1R: Range select for DAC1.
0 = The 0.5mA range is selected.
1 = The 1.5mA range is selected.
bit2
DAC0R: Range select for DAC0.
0 = The 0.5mA range is selected.
1 = The 1.5mA range is selected.
bit1
Alatch: Alarm Latch. Configures alarm flags to be latched or unlatched.
0 = Alarm flags unlatched.
1 = Alarm flags latched. They will clear when written to 0s.
bit0
Wlatch: Warning Latch. Configures warning flags to be latched or unlatched.
0 = Warning flags unlatched.
1 = Warning flags latched. They will clear when written to 0s.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), 89h: Logic Configuration
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
89h
X
LOSC
X
ADFIX
Mode
INV
X
bit7
Logic control bits for alarm and warning flags, as well as internal and external signals.
INVL
bit0
bit7
This bit is not used.
bit6
LOSC: A LOS channel configuration bit.
0 = The analog signal MON3, resulting from RSSI, is compared to a threshold, asserting LOS if it is
lower than the threshold.
1 = A digital input signal, INLOS, is used as the source for the LOS signal.
bit5
This bit is not used.
bit4
ADFIX: Determines which I2C slave address is used.
0 = A2h I2C address selected (default).
1 = I2C address determined by value in Table 04h (Table 01h in DS1859 configuration), register 8Ch.
bit3
Mode: Selects between DS1852/DS1856 memory configuration or DS1859 memory configuration. The
next I2C command will be to the selected configuration if a change is made. Does not require a power
cycle.
0 = DS1852 configuration selected (default).
1 = DS1859 configuration selected.
bit2
INV: Used for polarity inversion or non-inversion if an externally generated TXF is used. See Figure 12.
TX-F=[INV[XOR]INTXF]
bit1
This bit is not used.
bit0
INVL: Used for polarity inversion or non-inversion if an externally generated INLOS signal is used.
RXLOS=[INVL[XOR]INLOS]
Table 04h (Table 01h in DS1859 Configuration), 8Ah: Configuration
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
8Ah
X
X
X
X
X
X
RSSIC
RSSIF
bit7
bit0
Forces coarse or fine measurement for MON3 (RSSI) input. Note: Dual-range functionality can be disabled by writing this register to 01h.
bit7:2
No function.
bit1
RSSIC: Force the dual range conversion to use Coarse measurement only. This is used for calibration
of MON3.
0 = Coarse measurement not forced.
1 = Coarse measurement forced. If both RSSIC and RSSIF are 1, then the Coarse measurement is used.
bit0
RSSIF: Force the dual range conversion to use Fine measurement only. This is used for calibration of
MON3.
0 = Fine measurement not forced.
1 = Fine measurement forced. If both RSSIC and RSSIF are 1, then the Coarse measurement is used.
____________________________________________________________________
49
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), 8Bh: Reserved Memory
8Bh
RESERVED
Table 04h (Table 01h in DS1859 Configuration), 8Ch: Main Device Address
FACTORY DEFAULT:
A2h
MEMORY TYPE:
Shadowed Memory (SEE)
7
8Ch
2
26
25
24
23
22
21
bit7
20
bit0
2
Contains the Main Device address. If ADFIX = 1, then the value in this register determines the I C slave address for the Main
Device memory. If ADFIX = 0, the slave address is A2h. There are 128 possible addresses that can be programmed. If ADFIX = 1
and this register was changed to A0h, GBIC memory will not be addressed.
Table 04h (Table 01h in DS1859 Configuration), 8Dh: Reserved Memory
8Dh
RESERVED
Table 04h (Table 01h in DS1859 Configuration), 8Eh: Right-Shift Control
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
8Eh
Reserved
MON12
MON11
MON10
Reserved
bit7
Control right shifts for the monitor channels.
50
MON22
MON21
MON20
bit0
bit7
Reserved
bit6:4
MON12-MON10: Allows for right-shifting the final answer of MON1 voltage measurements. Allows for
scaling the measurements to the smallest full-scale voltage and then right-shifting the result so the
reading is weighted to the correct lsb.
bit3
Reserved
bit2:0
MON22-MON20: Allows for right-shifting the final answer of MON2 voltage measurements. Allows for
scaling the measurements to the smallest full-scale voltage and then right-shifting the result so the
reading is weighted to the correct lsb.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), 8Fh: Right-Shift Control
FACTORY DEFAULT:
30h
MEMORY TYPE:
Shadowed Memory (SEE)
8Fh
RESERVED
MON32
MON31
MON30
RESERVED
bit7
Control right shifts for the monitor channels.
bit7
bit0
Reserved
bit6:4
MON32-MON30: Allows for right-shifting the final answer of MON3 voltage measurements. Allows for
scaling the measurements to the smallest full-scale voltage and then right-shifting the result so the
reading is weighted to the correct lsb. This only applies to “Fine” conversions.
bit3:0
Reserved
Table 04h (Table 01h in DS1859 Configuration), 90h to 91h: Reserved Memory
90h to 91h
RESERVED
Table 04h (Table 01h in DS1859 Configuration), 92h to 93h: Gain Calibration For VCC
FACTORY DEFAULT:
####h
MEMORY TYPE:
92h
93h
Shadowed Memory (SEE)
15
2
7
2
214
213
6
5
2
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
Controls gain of the VCC measurements.
bit0
Table 04h (Table 01h in DS1859 Configuration), 94h to 95h: Gain Calibration For MON1
FACTORY DEFAULT:
####h
MEMORY TYPE:
94h
95h
Shadowed Memory (SEE)
15
2
7
2
214
213
6
5
2
2
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit7
Controls gain of the MON1 measurements. Refer to the Temperature Monitor Offset Calibration section
bit0
Table 04h (Table 01h in DS1859 Configuration), 96h to 97h: Gain Calibration For MON2
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
96h
97h
215
7
2
214
213
6
5
2
2
bit7
Controls gain of the MON2 measurements.
212
4
2
211
3
2
210
2
2
29
28
1
20
2
bit0
____________________________________________________________________
51
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), 98h to 99h: Gain Calibration For MON3 (Fine)
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
15
98h
2
214
213
212
211
210
29
28
99h
27
26
25
24
23
22
21
20
bit7
Controls gain of the MON3 Fine measurements.
bit0
Table 04h (Table 01h in DS1859 Configuration), 9Ah to 9Bh: Gain Calibration For MON3 (Coarse)
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
15
9Ah
2
214
213
212
211
210
29
28
9Bh
27
26
25
24
23
22
21
20
bit7
Controls gain of the MON3 Coarse measurements.
bit0
Table 04h (Table 01h in DS1859 Configuration), A2h to A3h: Offset Calibration For VCC
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
A2h
S
S
215
214
213
212
211
210
A3h
29
28
27
26
25
24
23
22
bit7
Controls offset of the VCC measurements.
bit0
Table 04h (Table 01h in DS1859 Configuration), A4h to A5h: Offset Calibration For MON1
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
A4h
S
S
A5h
9
8
2
2
215
7
2
214
6
2
213
5
2
212
4
2
211
3
2
bit7
Controls offset of the MON1 measurements.
210
22
bit0
Table 04h (Table 01h in DS1859 Configuration), A6h to A7h: Offset Calibration For MON2
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
A6h
S
S
215
214
213
212
211
210
A7h
29
28
27
26
25
24
23
22
bit7
Controls offset of the MON2 measurements.
52
____________________________________________________________________
bit0
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), A8h to A9h: Offset Calibration For MON3 (Fine)
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
A8h
S
S
215
214
213
212
211
210
A9h
29
28
27
26
25
24
23
22
bit7
Controls offset of the MON3 Fine measurements.
bit0
Table 04h (Table 01h in DS1859 Configuration), AAh To ABh: Offset Calibration For MON3 (Coarse)
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
AAh
S
S
ABh
9
8
2
215
7
2
2
214
213
6
5
2
2
212
4
2
211
3
2
bit7
Controls offset of the MON3 Coarse measurements.
210
22
bit0
Table 04h (Table 01h in DS1859 Configuration), ACh To ADh: Reserved Memory
ACh to ADh
RESERVED
Table 04h (Table 01h in DS1859 Configuration), AEh To AFh: Offset Calibration For Temperature
FACTORY DEFAULT:
####h
MEMORY TYPE:
Shadowed Memory (SEE)
AEh
S
28
27
26
25
24
23
22
AFh
1
0
-1
-2
-3
-4
-5
2-6
2
2
2
bit7
Controls offset of the temperature measurements.
2
2
2
2
bit0
____________________________________________________________________
53
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), B0h to B7h: Thresholds For High-Bias Alarm Flags (HBAL)
FACTORY DEFAULT:
FFh
MEMORY TYPE:
Shadowed Memory (SEE)
B0h
7
2
26
25
24
23
22
21
20
B1h
27
26
25
24
23
22
21
20
B2h
7
6
5
4
3
2
1
20
1
2
7
2
2
2
2
2
2
20
B4h
27
26
25
24
23
22
21
20
B5h
7
6
5
4
3
2
1
20
1
2
5
2
4
2
3
2
2
2
6
3
2
2
2
4
2
2
7
5
2
B3h
2
6
2
2
2
B6h
2
2
2
2
2
2
2
20
B7h
27
26
25
24
23
22
21
20
bit7
bit0
These represent the high thresholds for comparing bias levels. Each alarm byte contains the value for the threshold corresponding
to the temperature range indicated below. Only the upper 8 bits of the 16 bit measurement are compared here.
B0h
54
Alarm byte location when temperature is less than -8°C.
B1h
Alarm byte location when temperature in the range of -8°C to +8°C.
B2h
Alarm byte location when temperature in the range of +8°C to +24°C.
B3h
Alarm byte location when temperature in the range of +24°C to +40°C.
B4h
Alarm byte location when temperature in the range of +40°C to +56°C.
B5h
Alarm byte location when temperature in the range of +56°C to +72°C.
B6h
Alarm byte location when temperature in the range of +72°C to +88°C.
B7h
Alarm byte location when temperature is greater than +88°C.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), B8h to BFh: Thresholds For High-Bias Warning Flags (HBWA)
FACTORY DEFAULT:
FFh
MEMORY TYPE:
Shadowed Memory (SEE)
B8h
7
2
26
25
24
23
22
21
20
B9h
27
26
25
24
23
22
21
20
BAh
7
6
5
4
3
2
1
20
1
2
7
2
2
2
2
2
2
2
2
20
BCh
27
26
25
24
23
22
21
20
BDh
7
6
5
4
3
2
1
20
1
6
2
5
3
2
2
4
3
2
2
2
2
4
2
2
7
5
2
BBh
2
6
2
2
2
BEh
2
2
2
2
2
2
2
20
BFh
27
26
25
24
23
22
21
20
bit7
bit0
These represent the high thresholds for comparing bias levels. Each warning byte contains the value for the threshold
corresponding to the temperature range indicated below. Only the upper 8 bits of the 16 bit measurement are compared here.
B8h
Warning byte location when temperature is less than -8°C.
B9h
Warning byte location when temperature in the range of -8°C to +8°C.
BAh
Warning byte location when temperature in the range of +8°C to +24°C.
BBh
Warning byte location when temperature in the range of +24°C to +40°C.
BCh
Warning byte location when temperature in the range of +40°C to +56°C.
BDh
Warning byte location when temperature in the range of +56°C to +72°C.
BEh
Warning byte location when temperature in the range of +72°C to +88°C.
BFh
Warning byte location when temperature is greater than +88°C.
Table 04h (Table 01h in DS1859 Configuration), C0h: Reserved Memory
C0h
RESERVED
____________________________________________________________________
55
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), C1h: PW2 Password Write-Enable Byte
FACTORY DEFAULT:
00h
MEMORY TYPE:
C1h
Shadowed Memory (SEE)
7
2
26
25
24
23
bit7
22
21
20
bit0
This byte configures the Write protection of PW2. This is discussed in more detail in the Memory Protection and Password section.
56
bit7
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers D0h
through D6h in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit6
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit5
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers 80h
through C7h in the Main Device memory, Table 04h (Table 01h in DS1859 configuration), Table 02h,
and Table 03h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit4
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit3
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers 80h
through F7h in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit2
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers 00h
through 7Ah in the Main Device memory.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit1
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers 80h
through FFh in the Auxiliary Device memory of I2C slave address A0h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit0
When this bit is set, PW2 Write protection is enabled for the memory block consisting of registers 00h
through 7Fh in the Auxiliary Device memory of I2C slave address A0h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), C2h: PW2 Password Read-Enable Byte
FACTORY DEFAULT:
00h
MEMORY TYPE:
C2h
Shadowed Memory (SEE)
7
2
bit7
26
25
24
23
22
21
20
bit0
This byte configures the Read protection of PW2. This is discussed in more detail in the Memory Protection and Password section.
bit7
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers D0h
through D6h in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit6
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit5
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers 80h
through C7h in the Main Device memory, Table 04h (Table 01h in DS1859 configuration), Table 02h,
and Table 03h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit4
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit3
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers 80h
through F7h in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit2
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers 00h
through 7Ah in the Main Device memory.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit1
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers 80h
through FFh in the Auxiliary Device memory of I2C slave address A0h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
bit0
When this bit is set, PW2 Read protection is enabled for the memory block consisting of registers 00h
through 7Fh in the Auxiliary Device memory of I2C slave address A0h.
0 = Memory is unprotected (PW2 level).
1 = Memory is protected (PW2 level).
____________________________________________________________________
57
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), C3h to C6h: PW2 Password Setting
FACTORY DEFAULT:
0000 0000h
MEMORY TYPE:
Shadowed Memory (SEE)
C3h
31
2
230
229
228
227
226
225
224
C4h
223
222
221
220
219
218
217
216
C5h
15
14
13
12
11
10
C6h
2
7
2
2
6
2
2
5
2
2
4
2
2
3
2
2
2
2
9
28
1
20
2
2
bit7
bit0
These four bytes contain the password for access to memory space that is protected per Password Enable Bytes C1h and C2h of
Table 04h (Table 01h in DS1859 Configuration). (see Memory Protection and Password section).
Table 04h (Table 01h in DS1859 Configuration), C7h: Table Select Power-Up Default
FACTORY DEFAULT:
01h
MEMORY TYPE:
C7h
Shadowed Memory (SEE)
7
2
26
25
24
23
22
bit7
This byte is automatically loaded into the Table Select SRAM byte 7Fh (Lower Memory) on power up.
58
____________________________________________________________________
21
20
bit0
SFP Laser Controller and
Diagnostic IC
DS1864
Table 04h (Table 01h in DS1859 Configuration), DAh: Control And Shutdown Configuration And Status
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
DAh
FPOL
HTXP enable HBAL enable LTXP enable
X
X
X
bit7
MASK
bit0
This byte contains bits for shutdown configuration and status control.
bit7
FPOL: Configures the polarity of the auxiliary shutdown (FETG output).
0 = FETG is asserted low under a shutdown condition.
1 = FETG is asserted high under a shutdown condition.
bit6
HTXP enable: Configures a shutdown in response to a HTXP alarm.
0 = Shutdown will not respond to a trip of HTXP alarm.
1 = Shutdown will respond to a trip of HTXP alarm.
bit5
HBAL enable: Configures a shutdown in response to a HBAL alarm.
0 = Shutdown will not respond to a trip of HBAL alarm.
1 = Shutdown will respond to a trip of HBAL alarm.
bit4
LTXP enable: Configures a shutdown in response to a LTXP alarm.
0 = Shutdown will not respond to a trip of LTXP alarm.
1 = Shutdown will respond to a trip of LTXP alarm.
bit3:1
Not used.
bit0
MASK: Configures locations of alarms and warning interrupt masks to be either in Table 05h or in Table
01h (Table 00h in DS1859 configuration).
0 = Interrupt masks are located in Table 05h, bytes F8h through FBh.
1 = Interrupt masks are located in Table 01h (Table 00h in DS1859 configuration), bytes F8h through FBh.
Table 04h (Table 01h in DS1859 Configuration), DBh: High Transmitted Power Threshold (HTXP)
FACTORY DEFAULT:
FFh
MEMORY TYPE:
Shadowed Memory (SEE)
DBh
27
26
25
24
23
22
21
bit7
20
bit0
This byte sets a high D/A threshold for comparing transmitted power level. Only the upper 8 bits of the 16 bit value are compared.
Table 04h (Table 01h in DS1859 Configuration), DCh: Low Transmitted Power Threshold (LTXP)
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
DCh
27
bit7
26
25
24
23
22
21
20
bit0
This byte sets a low D/A threshold for comparing transmitted power level. Only the upper 8 bits of the 16 bit value are compared.
____________________________________________________________________
59
DS1864
SFP Laser Controller and
Diagnostic IC
Table 04h (Table 01h in DS1859 Configuration), DDh: LOS Threshold (LOS)
FACTORY DEFAULT:
00h
MEMORY TYPE:
DDh
Shadowed Memory (SEE)
7
26
2
25
24
23
22
21
bit7
20
bit0
This byte sets a low D/A threshold for comparing received power (RSSI) level. Only the upper 8 bits of the 16 bit value are
compared.
Table 05h Register Descriptions
Table 05h, C0h to C1h: Device ID
FACTORY DEFAULT:
18 64h
MEMORY TYPE:
Hardwired
C0h
C1h
0
0
0
1
1
0
0
0
1
1
0
0
1
0
bit7
0
0
bit0
These bytes identify the device as a DS1864.
Table 05h, C2h: Device Revision
FACTORY DEFAULT:
##h
MEMORY TYPE:
C2h
Hardwired
7
2
26
25
24
23
bit7
This byte indicates revision of the design.
60
____________________________________________________________________
22
21
20
bit0
SFP Laser Controller and
Diagnostic IC
DS1864
Table 05h, D1h: PW1 Password Write-Enable Byte
FACTORY DEFAULT:
00h
MEMORY TYPE:
D1h
Shadowed Memory (SEE)
7
2
bit7
26
25
24
23
22
21
20
bit0
This byte configures the Write protection of PW1. This is discussed in more detail in the Memory Protection and Password section.
bit7
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers D0h
through D6h in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit6
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit5
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers 80h
through C7h in the Main Device memory, Table 04h (Table 01h in DS1859 configuration), Table 02h,
and Table 03h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit4
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit3
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers 80h
through F7h in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit2
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers 00h
through 7Ah in the Main Device memory.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit1
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers 80h
through FFh in the Auxiliary Device memory on I2C slave address A0h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit0
When this bit is set, PW1 Write protection is enabled for the memory block consisting of registers 00h
through 7Fh in the Auxiliary Device memory of I2C slave ddress A0h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
____________________________________________________________________
61
DS1864
SFP Laser Controller and
Diagnostic IC
Table 05h, D2h: PW1 Password Read-Enable Byte
FACTORY DEFAULT:
00h
MEMORY TYPE:
D2h
Shadowed Memory (SEE)
7
2
26
25
24
23
bit7
22
21
20
bit0
This byte configures the Read protection of PW1. This is discussed in more detail in the Memory Protection and Password section.
62
bit7
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers D0h
through D6h in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit6
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 05h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit5
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers 80h
through C7h in the Main Device memory, Table 04h (Table 01h in DS1859 configuration), Table 02h,
and Table 03h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit4
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers F8h
through FFh in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit3
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers 80h
through F7h in the Main Device memory, Table 01h (Table 00h in DS1859 configuration).
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit2
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers 00h
through 7Ah in the Main Device memory.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit1
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers 80h
through FFh in the Auxiliary Device memory of I2C slave address A0h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
bit0
When this bit is set, PW1 Read protection is enabled for the memory block consisting of registers 00h
through 7Fh in the Auxiliary Device memory of I2C slave address A0h.
0 = Memory is unprotected (PW1 level).
1 = Memory is protected (PW1 level).
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 05h, D3h to D6h: PW1 Password Setting
FACTORY DEFAULT:
0000 0000h
MEMORY TYPE:
Shadowed Memory (SEE)
D3h
31
2
230
229
228
227
226
225
224
D4h
223
222
221
220
219
218
217
216
D5h
15
14
13
12
11
10
D6h
2
7
2
2
6
2
2
5
2
2
4
2
2
3
2
2
2
2
9
28
1
20
2
2
bit7
bit0
These four bytes contain the password for access to memory space that is protected per Password Enable Byte D1 and D2h of
Table 05h (see Memory Protection and Password section).
____________________________________________________________________
63
DS1864
SFP Laser Controller and
Diagnostic IC
Table 05h, F8h: Alarm Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
F8h
TMPhi
TMPlo
VCChi
VCClo
MON1hi
MON1lo
MON2hi
MON2lo
bit7
bit0
These bytes configure a maskable interrupt, determining which alarm flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration), register DAh, bit 0) determines which of these mask
sets are used to generate the MINT interrupt.
64
bit7
TMPalmhimask: Determines if an interrupt is generated for a High-Temperature Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
TMPalmlomask: Determines if an interrupt is generated for a Low-Temperature Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5
VCCalmhimask: Determines if an interrupt is generated for a High VCC Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit4
VCCalmlomask: Determines if an interrupt is generated for a Low VCC Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit3
MON1almhimask: Determines if an interrupt is generated for a High MON1 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit2
MONalmlomask: Determines if an interrupt is generated for a Low MON1 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit1
MON2almhimask: Determines if an interrupt is generated for a High MON2 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit0
MON2almlomask: Determines if an interrupt is generated for a Low MON2 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 05h, F9h: Alarm Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
F9h
MON3hi
MON3lo
RESERVED
bit7
bit0
These bytes configure a maskable interrupt, determining which alarm flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration), register DAh, bit 0) determines which mask sets are
used to generate the MINT interrupt.
bit7
MON3almhimask: Determines if an interrupt is generated for a High MON3 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
MON3almlomask: Determines if an interrupt is generated for a Low MON3 Alarm Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5:0
Reserved.
____________________________________________________________________
65
DS1864
SFP Laser Controller and
Diagnostic IC
Table 05h, FAh: Warning Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
FAh
TMPhi
TMPlo
VCChi
VCClo
MON1hi
MON1lo
MON2hi
MON2lo
bit7
bit0
These bytes configure a maskable interrupt, determining which warning flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
The MASK configuration bit (Table 04h (Table 01h in DS1859 configuration), register DAh, bit 0) determines which mask sets are
used to generate the MINT interrupt.
66
bit7
TMPwrnhimask: Determines if an interrupt is generated for a High-Temperature Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
TMPwrnlomask: Determines if an interrupt is generated for a Low-Temperature Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5
VCCwrnhimask: Determines if an interrupt is generated for a High VCC Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit4
VCCwrnlomask: Determines if an interrupt is generated for a Low VCC Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit3
MON1wrnhimask: Determines if an interrupt is generated for a High MON1 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit2
MONwrnlomask: Determines if an interrupt is generated for a Low MON1 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit1
MON2wrnhimask: Determines if an interrupt is generated for a High MON2 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit0
MON2wrnlomask: Determines if an interrupt is generated for a Low MON2 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
DS1864
Table 05h, FBh: Warning Masks
FACTORY DEFAULT:
00h
MEMORY TYPE:
Shadowed Memory (SEE)
FBh
MON3hi
MON3lo
RESERVED
bit7
bit0
These bytes configure a maskable interrupt, determining which warning flags assert the MINT bit (Lower Memory, byte 71h, bit 0). If
one of the interrupts is desired, its bit must be written to a 1 here. If no interrupt is desired, the bit should be written to a 0.
A mask configuration bit (Table 04h (Table 01h in DS1859 configuration), register DAh, bit 0) determines which mask sets are used
to generate the MINT interrupt.
bit7
MON3wrnhimask: Determines if an interrupt is generated for a High MON3 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit6
MON3wrnlomask: Determines if an interrupt is generated for a Low MON3 Warning Flag.
0 = No interrupt is generated.
1 = An interrupt is generated.
bit5:0
Reserved.
____________________________________________________________________
67
DS1864
SFP Laser Controller and
Diagnostic IC
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, and start and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it often initiates a low-power (or idle) mode for slave devices.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the Timing
Diagrams for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates a stop condition. See the Timing Diagrams for
applicable timing.
Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer
following the current one. Repeated starts are commonly
used during read operations to identify a specific memory
address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See
the Timing Diagrams for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (Figure 19). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (Figure 19) before the next rising edge of SCL during
a bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always the 9th
bit transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a write
operation) performs an ACK by transmitting a zero during
the 9th bit. A device performs a NACK by transmitting a 1
68
during the 9th bit. Timing (Figure 19) for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or as
an indication that the device is not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to terminate communication so the slave will return control of
SDA to the master.
Slave Address Byte: Each slave on the I 2 C bus
responds to a slave addressing byte sent immediately
following a start condition. The slave address byte contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit. The DS1864
(and some of its predecessors) is unique in that it actually responds to two slave addresses. The slave
address for the Auxiliary Device memory is A0h. The
slave address for the Main Device memory is A2h by
default, although it can be programmed to something
different by writing byte 8Ch in Table 04h (Table 01h in
DS1859 configuration) along with the corresponding
configuration bit. By writing the correct slave address
with R/W = 0, the master indicates it will write data to
the slave. If R/W = 1, the master will read data from the
slave. If an incorrect slave address is written, the
DS1864 assumes the master is communicating with
another I2C device and ignores the communications
until the next start condition is sent. If both the Auxiliary
Device and the Main Device addresses are set to A0h,
only the Main Device will respond.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte transmitted during a write operation following the slave
address byte.
____________________________________________________________________
SFP Laser Controller and
Diagnostic IC
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and generates a stop condition. The DS1864 writes 1 to 8 bytes (1
page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte
is sent. The address counter limits the write to one 8byte page (one row of the memory map). The first page
begins at address 00h and subsequent pages begin at
multiples of 8 (08h, 10h, 18h, etc). Attempts to write to
additional pages of memory without sending a stop
condition between pages results in the address counter
wrapping around to the beginning of the present row.
To prevent address wrapping from occurring, the master must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new start condition, and write the slave address byte (R/W = 0) and
the first memory address of the next memory row
before continuing to write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS1864 requires the EEPROM write time
(tW) after the stop condition to write the contents of the
page to EEPROM. During the EEPROM write time, the
DS1864 will not acknowledge either of its slave
addresses because it is busy. It is possible to take
advantage of that phenomenon by repeatedly addressing the DS1864, which allows the next page to be written as soon as the DS1864 is ready to receive the data.
The alternative to acknowledge polling is to wait for
maximum period of tW to elapse before attempting to
write again to the DS1864.
EEPROM Write Cycles: When EEPROM writes occur,
the DS1864 writes the whole EEPROM memory page (8
bytes), even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page
are allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This
can result in a whole page being worn out over time by
writing a single byte repeatedly. Writing a page one
byte at a time wears the EEPROM out eight times faster
than writing the entire page at once. The DS1864’s
EEPROM write cycles are specified in the Nonvolatile
Memory Characteristics table. The specification shown
is at the worst-case temperature. Writing to SRAMshadowed EEPROM memory with SEE = 1 does not
count as an EEPROM write.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation occurs
at the present value of the memory address counter. To
read a single byte from the slave, the master generates a
start condition, writes the slave address byte with R/W =
1, reads the data byte with a NACK to indicate the end of
the transfer, and generates a stop condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular address. To do this, the master
generates a start condition, writes the slave address byte
(R/W = 0), writes the memory address where it desires to
read, generates a repeated start condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte it NACKs to indicate the end of the
transfer and generates a stop condition. This can be
done with or without modifying the address counter’s
location before the read cycle. The DS1864’s address
counter does not wrap on page boundaries during read
operations, but the counter will roll from its uppermost
memory address FFh to 00h if the last memory location
is read during the read transaction.
See Figure 20 for a read example using the repeated
start condition to specify the starting memory location.
Application Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors, and
mount the capacitors as close as possible to the VCC and
GND pins to minimize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open collector output on the DS1864 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be utilized
____________________________________________________________________
69
DS1864
I2C Communication
DS1864
SFP Laser Controller and
Diagnostic IC
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
ACK
START
CONDITION
9
ACK
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 18. I2C Data Transfer Protocol
SDA
tBUF
tHD:STA
tLOW
tR
tSP
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tHD:DAT
Figure 19. I2C AC Characteristics
for SCL. Pullup resistor values should be chosen to
ensure that the rise and fall times listed in the AC
Electrical Characteristics table are within specification.
70
____________________________________________________________________
tSU:STO
SFP Laser Controller and
Diagnostic IC
DS1864
COMMUNICATIONS KEY
S
START
A
ACK
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
P
STOP
N
NOT
ACK
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
SR
REPEATED
START
X
X
X
X
X
X
X
X
NOTE:
ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
8-BITS ADDRESS OR DATA
WRITE A SINGLE BYTE TO 2-WIRE ADDRESS A0h
S
1 0
1
0 0
0
0
0
A
MEMORY ADDRESS
A
DATA
A
A
DATA
A
P
WRITE UP TO A 8-BYTE PAGE WITH A SINGLE TRANSACTION I2C ADDRESS A2h
S
1 0
1
0 0
0
1
0
A
MEMORY ADDRESS
A
DATA
P
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER FROM I2C ADDRESS A0h
S
1 0
1
0 0
0
0
0
MEMORY ADDRESS
A
A
SR
1 0
1
0 0
0
0
1
A
DATA
N
1
1
A
DATA
A
P
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER FROM I2C ADDRESS A2h
S
1 0
1
0 0
0
DATA
1
0
A
MEMORY ADDRESS
A
A
DATA
SR
1 0
1
A
0 0
0
DATA
N
P
Figure 20. I2C Communications Examples
____________________________________________________________________
71
SFP Laser Controller and
Diagnostic IC
DS1864
Typical Operating Circuit
3.3V
HOST
3.3V
4.7kΩ
3.3V
0.1µF
4.7kΩ
VCC
FETG
SDA
10nF
SCL
TX-DISABLE
TX-D
MON3P
RECEIVER SIGNAL +
ROSA
INTX-F
MON3N
10Ω
IN1
3.3V
3.3V
3.3V
(IF SINGLE ENDED)
3.3V
RSEL
10kΩ
10kΩ
10kΩ
10kΩ
DS1864
INLOS
OUT+ BIAS MD
DAC0
APCSET
TX_DISABLE
TX-DISABLE
RX-LOS
DAC1
MON1P
RSELOUT
MODSET
BC_MON
PC_MON
MAX3975
LASER DRIVER
TX-FAULT
1kΩ
OUT1
1kΩ
TX-F
MON1N
INTX-F
GND
MON2
Package Information
Chip Topology
TRANSISTOR COUNT: 52353
SUBSTRATE CONNECTED TO GROUND
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
72 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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