DS2155DK/DS2156DK
T1/E1/J1 Single-Chip Transceiver
Design Kit Daughter Cards
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS2155/DS2156 design kits are evaluation
boards for the DS2155 and DS2156. The
DS2155/DS2156 design kits are intended to be used
as daughter cards with either the DK2000 or the
DK101 motherboards. The boards are complete with
a single-chip transceiver (SCT), transformers,
termination resistors, configuration switches, line
protection circuitry, network connectors, and an
interface to the motherboard.
Expedites New Designs by Eliminating FirstPass Prototyping
Interfaces Directly to the DK101 or DK2000
Motherboards
Demonstrates Key Functions of the DS2156
and DS2155
High-Level Software Provides Visual Access
to Registers
Software-Controlled (Register Mapped)
Configuration Switches to Facilitate Clock
and Signal Routing
BNC Connections for 75Ω E1
Bantam and RJ48 Connectors for 120Ω E1
and 100Ω T1
Multitap Transformer to Facilitate True
Impedance Matching for 75Ω and 120Ω/100Ω
Paths
Network Interface Protection for Overvoltage
and Overcurrent Events
UTOPIA II Bus Connection for MPC8260
(DS2156 Only)
UTOPIA II Prototype Connectors (DS2156
Only)
Test Points and Prototype Area Available for
Further Customization
ORDERING INFORMATION
PART
DESCRIPTION
DS2155DK
DS2155 Design Kit Daughter Card
DS2156DK
DS2156 Design Kit Daughter Card
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
TABLE OF CONTENTS
COMPONENT LIST.....................................................................................................................3
BASIC OPERATION....................................................................................................................4
HARDWARE CONFIGURATION .................................................................................................................. 4
QUICK SETUP (DEMO MODE) .................................................................................................................. 4
QUICK SETUP (REGISTER VIEW ) ............................................................................................................. 4
SAMPLE UTOPIA II CONFIGURATION (DS2156 ONLY)............................................................................. 5
REGISTER MAP..........................................................................................................................5
CPLD REGISTER MAP ........................................................................................................................... 6
DS2155/DS2156 INFORMATION................................................................................................8
DS2155DK/DS2156DK INFORMATION......................................................................................8
TECHNICAL SUPPORT ..............................................................................................................8
SCHEMATICS .............................................................................................................................8
LIST OF TABLES
Table 1. Daughter Card Address Map .........................................................................................5
Table 2. CPLD Register Map .......................................................................................................6
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
COMPONENT LIST
DESIGNATION
C1–C5, C8–C12,
C15–C19, C21,
C22, C29–C34
C7, C36
QTY
DESCRIPTION
23
0.1mF 10%, 16V ceramic capacitors (0603)
SUPPLIER
Digi-Key
PART
311-1088-1-ND
2
1mF 10%, 16V ceramic capacitors (1206)
Digi-Key
PCC1882CT-ND
C13, C14
2
0.1mF 10%, 16V ceramic capacitors (0805)
Digi-Key
311-1142-1-ND
C23
1
0.1mF 10%, 25V ceramic capacitor (1206)
Digi-Key
PCC1883CT-ND
C24–C27
4
0.22mF, 50V ceramic capacitors
Digi-Key
UNK
C35
DS1, DS4–DS18
DS2, DS3
F1–F6
J1, J2
J3, J4
J5, J6
1
16
2
6
2
2
2
10mF 20%, 16V tantalum capacitor (B case)
LED, green, SMD
LED, red, SMD
250V, 1.25A fuse, SMT
Male 0.1, SMD, 50-pin, dual-row vertical
Bantam connectors
Connector BNC RA 5-pin
Digi-Key
Digi-Key
Digi-Key
Teccor Electronics
Samtec
SWK
Kruvand
J7–J9
3
Socket, SMD, 50-pin, dual-row vertical
Samtec
JT10
L1
R1, R14, R21
R2, R3, R58, R59
R4, R5, R60
R6, R9, R10, R13,
R15–R19, R22,
R23, R25–R29,
R32, R37, R38,
R44, R47–R49, R61
R7, R8, R11, R12,
R30, R31, R35,
R36, R39–R43,
R45, R50–R53
R24
R33, R34
1
1
3
4
3
Connector, 10-pin, dual-row vertical
Choke, dual 4-line 24mH, 8-pin SO
51.1W 1%, 1/8W resistors (1206)
0W 5%, 1/8W resistors (1206)
51.1W 1%, 1/10W resistors (0805)
Digi-Key
Pulse Engineering
Digi-Key
Digi-Key
Digi-Key
PCS3106CT-ND
P501CT-ND
P500CT-ND
F1250T
TSM-125-01-T-DV
RTT34B02
UCBJR220
TFM-125-02-S-DLC
S2012-05-ND
PE-65857
P51.1FCT-ND
P0.0ETR-ND
P51.1CCT-ND
24
10kW 1%, 1/10W resistors (0805)
Digi-Key
P10.0KCCT-ND
18
330W 0.1%, 1/10W MF resistors (0805)
Digi-Key
P330ZCT-ND
1
2
1.0kW 1%, 1/10W resistor (0805)
NOPOP
Digi-Key
—
R46
1
4.7kW 1%, 1/8W resistor (0805)
Digi-Key
R54, R55
R56, R57
RJ1
SW1
T1
U11
U1–U4, U6
2
2
1
1
1
1
5
61.9W 1%, 1/8W resistors (1206)
49.9W 1%, 1/8W resistors (1206)
RJ48 connector
Switch DPDT slide 6-pin TH
XFMR 16-pin SMT
T1/E1/J1 XCVR 100-pin QFP, 0°C to +70°C
BBUS switch 10-bit CMOS, 150-mil, 24-pin SO
Digi-Key
Digi-Key
Molex
Avnet
Pulse Engineering
Dallas Semiconductor
IDT
U5
1
144-pin macrocell CPLD
Avnet
U7–U10
Z1, Z6–Z8
Z2, Z3
Z4, Z5
Z9, Z10
4
4
2
2
2
Quad bus switch, 150-mil, 16-pin SO
160V, 500A Sidactor
58V, 500A Sidactor
6V, 50A Sidactor
25V, 500A Sidactor
IDT
Teccor Electronics
Teccor Electronics
Teccor Electronics
Teccor Electronics
P1.00KCCT-ND
NOPOP
9C08052A4701FK
HFT
P61.9FCT-ND
P49.9FCT-ND
43223
SSA22
TX1099
DS2156L
IDTQS3R861Q
XC95144XL10TQ100C
IDTQS3125Q
P1800SCMC
P0640SCMC
P0080SAMC
P0300SCMC
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
BASIC OPERATION
This design kit relies upon several supporting files, which can be downloaded from our website at www.maximic.com/DS2155DK.
Hardware Configuration
Using the DK101 processor board:
· Connect the daughter card to the DK101 processor board.
· Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector and the
TIM 5V supply headers are unused.)
· All processor board DIP switch settings should be in the ON position with exception for the flash programming
switch, which should be OFF.
· From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select
Programs®ChipView®ChipView.
Using the DK2000 processor board:
· Connect the daughter card to the DK2000 processor board.
· Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected
to connector J2.
· From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select
Programs®ChipView®ChipView.
General:
· Upon power-up the RLOS LED is lit, as well as the MCLK-2.048MHz and TCLK-2.048MHz LEDs.
· Due to the dual winding transformer, only the 120W line build-out configuration setting is needed to cover 75W
E1 and 120W E1.
Quick Setup (Demo Mode)
·
·
·
The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select
Demo Mode.
The program requests a configuration file, then select between the displayed files.
(DS2155_E1_DSNCOM_DRVR.cfg or DS2155_T1_DSNCOM_DRVR.cfg).
The Demo Mode screen appears. Upon external loopback, the LOS and OOF indicators extinguish.
Quick Setup (Register View)
·
·
·
·
The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select
Register View.
The program requests a definition file, then select DS2155.def.
The Register View screen appears, showing the register names, acronyms, and values.
Predefined register settings for several functions are available as initialization files.
¾ INI files are loaded by selecting the menu File®Reg Ini File®Load Ini File.
¾ Load the INI file DS2155_T1_BERT_ESF.ini.
¾ After loading the INI file the following may be observed:
The RLOS LED extinguishes upon external loopback.
The DS2155/DS2156 begins transmitting a Daly pattern. When external loopback is applied, the BERT
bit-count registers BBC1–3 and BEC1–3 may be updated by clearing and setting BC1.LC and
clicking the Read All button.
Miscellaneous:
· Clock frequencies and certain pin bias levels are provided by a register-mapped CPLD, which is on the
DS2155/DS2156 daughter card.
· The definition file for this CPLD is named DS215x_35x_CPLD_V2.def. See the CPLD Register Map section for
definitions.
· All files referenced above are available for download at www.maxim-ic.com/DS2155DK.
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
Sample UTOPIA II Configuration (DS2156 Only)
The following register settings configure the DS2156 daughter card for UTOPIA II, single CLAV, 8-bit mode on PHY
port 0. UTOPIA II bus connection is provided by header J1 (Tx) and header J2 (Rx).
After configuring the following registers toggle the MSTREG.URST bit to reset the UTOPIA II core.
UTOPIA II Setup, Register Settings for daughter card CPLD
NAME
SWITCH 1
SWITCH 2
SWITCH 3
VALUE
0x0F
0x03
0x0F
NAME
SWITCH 4
LEVELS
VALUE
0x0F
0x07
UTOPIA II Setup, Register Settings for DS2156 E1 Configuration
NAME
MSTREG
E1RCR1
E1RCR2
E1TCR1
E1TCR2
CCR1
CCR4
IOCR1
IOCR2
VALUE
0x02
0x68
0x00
0x15
0x00
0x00
0x00
0x00
0x00
NAME
LBCR
TAF
TNAF
LIC1
LIC2
LIC3
LIC4
VALUE
0x00
0x9B
0xC0
0x11
0x90
0x00
0x00
UTOPIA II Setup, Register Settings for DS2156 UTOPIA II Configuration
NAME
U_TCFR
U_TCR1
U_TCR2
U_RCFR
U_RCR1
VALUE
0x01
0x05
0x00
0x01
0x01
NAME
U_RCR2
U_TIUPB
PCPR
PCDR1, 2, 3, 4
VALUE
0x0
0x0
0x22
0x0
REGISTER MAP
The DK101 daughter card address space begins at 0x81000000.
The DK2000 daughter card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets given in Table 1 are relative to the beginning of the daughter card address space.
Table 1. Daughter Card Address Map
OFFSET
0X0000
to
0X0015
DEVICE
DESCRIPTION
CPLD
Board identification and clock/signal routing
0X1000
to 0X10ff
Single-Chip
Transceiver
Board is populated with one of the following:
DS2156, DS2155, DS21352, or DS21354.
Please see data sheet for details.
Registers in the CPLD can be easily modified using the ChipView.exe, a host-based user interface software along
with the definition file named DS215x_35x_CPLD_V2.def. Definition files for the SCT are named DS2155.def,
DS21352.def, or DS21354.def, depending on the board population option.
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
CPLD Register Map
Table 2. CPLD Register Map
OFFSET
NAME
TYPE
DESCRIPTION
0X0000
0X0002
0X0003
0X0004
0X0005
0X0006
0X0007
0X0011
0X0012
0X0013
0X0014
BID
XBIDH
XBIDM
XBIDL
BREV
AREV
PREV
SWITCH1
SWITCH2
SWITCH3
SWITCH4
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Write
Read-Write
Read-Write
Read-Write
Board ID
High-Nibble Extended Board ID
Middle-Nibble Extended Board ID
Low-Nibble Extended Board ID
Board FAB Revision
Board Assembly Revision
PLD Revision
Pin to 1.544MHz
Pin to 2.048MHz
Pin-to-Pin Connect
Pin-to-Pin Connect
0X0015
LEVELS
Read-Write
Set Level On Pin 1 = 3.3V
ID Registers
OFFSET
NAME
TYPE
VALUE
0X0000
0X0002
0X0003
0X0004
BID
XBIDH
XBIDM
XBIDL
Read-Only
Read-Only
Read-Only
Read-Only
0X0005
BREV
Read-Only
0X0006
AREV
Read-Only
0X0007
PREV
Read-Only
0xD
0x0
0x0
0x5
Displays current
FAB revision
Displays current
assembly revision
Displays current
PLD firmware
revision
DESCRIPTION
Board ID
High-Nibble Extended Board ID
Middle-Nibble Extended Board ID
Low-Nibble Extended Board ID
Board FAB Revision
Board Assembly Revision
PLD Revision
Control Registers
The control registers are used primarily to control several banks of FET switches that route clocks and backplane
signals. Please note that certain register settings cause line contention, e.g., setting SWITCH1.4 and SWITCH2.4
both to 0 would drive MCLK with both 1.544MHz and 2.048MHz.
SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF
(MSB)
—
—
—
NAME
POSITION
MCLK
SWITCH1.3
TCLK
SWITCH1.2
RSYSCLK
SWITCH1.1
TSYSCLK
SWITCH1.0
—
MCLK
TCLK
RSYSCLK
FUNCTION
0 = Connect MCLK to the 1.544MHz clock
1 = Open Switch 1.4
0 = Connect TCLK to the 1.544MHz clock
1 = Open Switch 1.3
0 = Connect RSYSCLK to the 1.544MHz clock
1 = Open Switch 1.2
0 = Connect TSYSCLK to the 1.544MHz clock
1 = Open Switch 1.1
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(LSB)
TSYSCLK
DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
SWITCH2: PIN TO 2.048MHz (Offset = 0X0012) INITIAL VALUE = 0x3
(MSB)
—
—
—
NAME
POSITION
MCLK
SWITCH2.3
TCLK
SWITCH2.2
RSYSCLK
SWITCH2.1
TSYSCLK
SWITCH2.0
—
MCLK
TCLK
RSYSCLK
(LSB)
TSYSCLK
FUNCTION
0 = Connect MCLK to the 2.048MHz clock
1 = Open Switch 2.4
0 = Connect TCLK to the 2.048MHz clock
1 = Open Switch 2.3
0 = Connect RSYSCLK to the 2.048MHz clock
1 = Open Switch 2.2
0 = Connect TSYSCLK to the 2.048MHz clock
1 = Open Switch 2.1
SWITCH3: PIN-TO-PIN CONNECT (Offset = 0X0013) INITIAL VALUE = 0xF
(MSB)
—
—
—
NAME
POSITION
TSS_RS
SWITCH3.3
TCL_RC
SWITCH3.2
RSY_RC
SWITCH3.1
TSY_RC
SWITCH3.0
—
TSS_RS
TCL_RC
RSY_RC
(LSB)
TSY_RC
FUNCTION
0 = Connect TSSYNC to RSYNC
1 = Open Switch 3.4
0 = Connect TCLK to RCLK
1 = Open Switch 3.3
0 = Connect RSYSCLK to RCLK
1 = Open Switch 3.2
0 = Connect TSYSCLK to RCLK
1 = Open Switch 3.1
SWITCH4: PIN-TO-PIN CONNECT (Offset = 0X0014) INITIAL VALUE = 0x3
(MSB)
—
(LSB)
—
—
—
NAME
POSITION
URCLK_2048
SWITCH4.3
UTCLK_2048
SWITCH4.2
RSER_TSER
SWITCH4.1
RSYNC_TSYNC
SWITCH4.0
UTCLK_2048 UT_CLK_2048 RSER_TSER RSYNC_TSYNC
FUNCTION
0 = Connect UR_CLK (TSSYNC) to 2.048MHz
1 = Open Switch 4.4
0 = Connect UT_CLK (TCHCLK) to 2.048MHz
1 = Open Switch 4.3
0 = Connect RER to TSER
1 = Open Switch 4.2
0 = Connect RSYNC to TSYNC
1 = Open Switch 4.1
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
LEVELS: SET LEVEL ON PIN (Offset = 0X0015) INITIAL VALUE = 0x6
(MSB)
—
—
—
—
—
BP_EN
PPCTDM_EN
(LSB)
TUSEL
NAME
POSITION
FUNCTION
—
LEVELS1.3
—
BP_EN
LEVELS1.2
0 = Enable IDT switches that connect the UTOPIA bus to
daughter card header
PPCTDM_EN
LEVELS1.1
0 = Enable IDT switches that connect the TDM bus to the
daughter card header
TUSEL
LEVELS1.0
0 = Set DS2156.TUSEL to enable TDM backplane
1 = Set DS2156.TUSEL to enable UTOPIA backplane
Note: When the UTOPIA backplane is enabled (LEVELS.TUSEL = 1) there is a possibility for contention between
the UTOPIA bus master and TSYSCLK, TSER, and RSER. To avoid this, the following switches should be opened
when the UTOPIA backplane is enabled: SWITCH1.0, SWITCH2.0, SWITCH3.0, and SWITCH4.1
DS2155/DS2156 INFORMATION
For more information about the DS2155 and DS2156, please consult the DS2155 and DS2156 data sheets
available on our website at www.maxim-ic.com/DS2155 and www.maxim-ic.comDS2156. Software downloads are
also available for this design kit.
DS2155DK/DS2156DK INFORMATION
For more information about the DS2155DK and DS2156DK, including software downloads, please consult the
DS2155DK/DS2156DK data sheet available on our website at www.maxim-ic.com/DS2155DK.
TECHNICAL SUPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS2155DK/DS2156DK schematics are featured in the following 13 pages.
DOCUMENT REVISION HISTORY
REVISION
DATE
032503
060303
012705
110106
DESCRIPTION
Initial DS2155DK/DS2156DK data sheet release.
Updated the Title, General Description, Features, and Basic Operation
sections; “TIM” replaced with “daughter card.”
Updated schematics (removed component values for Fuse and Sidactor; see
Component List).
Updated schematics.
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
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CONTENTS
1. COVER PAGE
2. SCT POPULATION OPTION (DS2155, DS2156, DS21352 OR DS21354)
3. TX AND RX ANALOG PATHS
4. TIM ADDRESS AND DATA BUS
5. CPLD ADDRESS DATA CONNECTIONS, BIAS LEVELS FOR SCT
6. UTOPIA: TIM HEADER AND BUS SWITCHES
7. TESTPOINTS FOR UTOPIA 2
8. UTOPIA: NETLIST ASSOCIATIONS
9. SWITCHING FOR CLOCKS AND TDM
10. SUPPLY DECOUPLING
11. SCT TESTPOINTS
12. NETLIST CROSS-REFERENCE
13. PART CROSS-REFERENCE
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DS2156DK02A0
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DS2156, DS2155, DS2135Y DESIGN KIT
7
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8
JTMS
JTRST
JTDI
JTCLK
JTDO
TTIP
TRING
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
8XCLK
RCL
LIUC
RTIP
RRING
RPOSI
RNEGI
RCLKI
RPOSO
RNEGO
RCLKO
10
4
7
5
2
41
42
43
40
39
38
32
29
12
6
13
89
90
91
88
87
86
17
16
U11
DS2156L
7
JTMS
JTRST
JTDI
JTCLK
JTDO
TTIP
TRING
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
8XCLK
RCL
LIUC
RTIP
RRING
RPOSI
RNEGI
RCLKI
RPOSO
RNEGO
RCLKO
7
V3_3
18
31
44
61
81
83
D
8
6
5
6
DS2156
TQFP
5
NC3
BTS
MUX
RD/DS*
WR/RW*
ALE/AS/A
A
A
A
A
A
A
A
D/AD
D/AD
D/AD
D/AD
D/AD
D/AD
D/AD
D/AD
TCHBLK
RCHBLK
RLOS/LOTC
INT*
CS*
UOP0
UOP1
UOP2
UOP3
UOP0
UOP1
UOP2
UOP3
RVDD
TVDD
DVDD1
DVDD2
DVDD3
DVDD4
30
19
20
24
45
60
80
84
TVSS
RVSS1
RVSS2
RVSS3
DVSS1
DVSS2
DVSS3
DVSS4
82 RCLK
78 RLINK
98 RSYNC
92 RCHCLK
100RSYSCLK
79 RLCLK
85 RDATA
97 RFSYNC
RCLK
RLINK
RSYNC
RCHCLK
RSYSCLK
RLCLK
RDATA
RFSYNC
ESIBS0 36
ESIBS1 54
TCLK
TLINK
TSYNC
TCHCLK
TSYSCLK
TLCLK
TDATA
TSSYNC
TSIG
RSER
MCLK
RMSYNC
RSIG
BPCLK
TSTRST
RSIGF
XTALD
ESIBRD
TSER
RSER 95
MCLK 21
RMSYNC 96
RSIG 94
BPCLK 3
TSTRST 14
RSIGF 93
XTALD 22
ESIBRD 76
TSER 47
8
9
15
23
ESIBS
ESIBS
46
35
37
53
51
34
50
52
48
49
TCLK
TLINK
TSYNC
TCHCLK
TSYSCLK
TLCLK
TDATA
TSSYNC
TSIG
TESO
NC1
NC2
TUSEL 26
N_P27 27
28
77
74
55
11
66
67
68
69
70
71
72
N_P28
BTS
MUX
RD_DS
WR_RW
A7
A6
A5
A4
A3
A2
A1
A0
73
56
57
58
59
62
63
64
D_AD7
D_AD6
D_AD5
D_AD4
D_AD3
D_AD2
D_AD1
D_AD0
TCHBLK
RCHBLK
RLOS_LOTC
INT
CS
65
75
25
99
1
33
4
4
3
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ENGINEER:
TITLE:
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DS2156DK02A0
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DATE:
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1
1
RTIP
RRING
0
R2
0
R3
1
TRING
0
R59
0
R58
2
2
2
2
2
6
1UF
C7
1
Z
2
1
1
1
SW1
DPDT
1
2
Z4
2
1:0.8
1:1
16
14
1:1
15
5
1:0.8
11
10
9
Z
2
1
TTIP
6
5
4
3
2
1
5
6
7
8
2
2
2
2
2
1
0.22UF
C26
0.22UF
C25
0.22UF
C24
0.22UF
C27
Z2
Z
2
1
1
1
6
3
8
7
5
24 UH
L1
24 UH
L1
4
1
2
Z
2
D
1
2
2
1
C23
7
R60
1
2
2
1
3
6
4
5
61.9
1
8
51.1
Z1
Z6
1
Z3
4
Z
Z
4
Z7
Z8
2
1
2
1
Z
Z
Z9
Z10
Z
2
1
Z
2
1
2
1
2
1
R55
1
R54 61.9
0.1UF
T1
Z5
R57
1
1
1
1
1
1
F1
F2
F4
F3
F5
F6
2
2
2
2
2
2
3
1
3
5
7
ENGINEER:
1
2
1
CONN_BNC_5PIN
J6
2
CONN_BNC_5PIN
J5
1
3
5
7
RJ1
RJ48
2
4
6
8
TITLE:
2
4
6
8
3
2
STEVE SCULLY
DS2156DK02A0
2
T1
R56
49.9
49.9
2
5
T
CONN_BANTAM_IPC
2
J3
PAGE:
1
3 / 13
10/04/02
DATE:
T
CONN_BANTAM_IPC
R
J4
R
5
1
A
B
C
D
A
B
C
D
8
8
INT
CS_T
PPC_RXD
PPC_TXD
PPC_RSYNC
PPC_TSYNC
PPC_TXCLK
PPC_RXCLK
TIM5V
7
9
7
5
3
1
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
7
12
10
8
6
4
2
JX
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
J9
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
4
25
6
D_AD0
D_AD1
D_AD2
D_AD3
D_AD4
D_AD5
D_AD6
D_AD7
A15
3
12
10
8
6
4
2
ENGINEER:
J1X
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
TITLE:
49
47
45
43
41
39
37
35
33
31
29
A14
CLK16384_T
21
A13
23
19
17
A11
A12
15
A10
13
11
9
7
5
3
1
TIM5V J8
V3_3
3
RESET_OUT
5
4
27
(TIM LSB)
5
WE_T
RW_T
A9
A8
A0
A1
A2
A3
A4
A5
A6
A7
6
1
51.1
R1
2
NIMD8
NIMD9
NIMD10
NIMD11
NIMD12
NIMD13
NIMD14
NIMD15
SNIM_B7
SNIM_B6
SNIM_B5
SNIM_B4
SNIM_B3
SNIM_B2
2
STEVE SCULLY
DS2156DK02A0
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
2
CLK1544_T
UNUSED
PAGE:
1
4 / 13
10/04/02
DATE:
1
A
B
C
D
A
B
C
10K
9
7
5
3
R26
R24
1
2
10K
R27
10
8
6
4
1
1
1
1
1
1
R16
R47
R28
R44
R61
2
2
2
2
2
1
2
2
R49
1
R23
2
R9
2
1
2
R22
1
R6
2
1
2
R10
1
2
R38
R46 4.7K
1
10
8
6
4
2
8
7
ALL UNMARKED BIAS RESISTORS ARE 10K
JTRST
ESIBRD
RPOSI
RNEGI
RCLKI
TPOSI
TNEGI
TCLKI
TSYSCLK
TSTRST
MUX
RSYSCLK
TSER
9
7
5
3
2
GND2
1
1
GND3
1
2
TDO
TDI
TMS
TCK
1
R25
CONN_10P
NC
TMS
TDO
TDI
TCK
98
57
5
88
51
38
6
R13
R17
R15
R18
R29
R19
R37
R48
R32
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
TP
TP
TP
V3_3
V3_3
TP18 TP15 TP14
TSSYNC
TLINK
TSIG
LIUC
BTS
INT
RSYNC
TSYNC
TCLK
3.3V3
3.3V2
3.3V1
2.5V_3.3V4
2.5V_3.3V3
2.5V_3.3V2
26
5
DS16
V3_3
DS17
R52
330
R51
330
CS
SW4_B0EN
SW4_B1EN
SW4_B2EN
SW4_B3EN
BTS
MUX
WR_RW
RD_DS
A0
A1
A2
A3
A4
A5
A6
A7
4
IO55
IO56
IO57
IO58
IO59
IO60
IO61
IO62
IO63
IO64
IO65
IO66
IO67
IO68
IO69
IO70
IO71
IO72
TP
2
TP
TP
3
ENGINEER:
TITLE:
1
330
R11
330
2
STEVE SCULLY
DS2156DK02A0
DS7 ..TO.. DS18
1
R8
2
2
A12
37
39
1
RED
53
52
50
49
42
41
40
DS3
2
1
1
PAGE:
1
5 / 13
10/04/02
DATE:
V3_3
RESET_OUT
RW_T
CS_T
WE_T
PPC_TDM_EN
BP_EN
A11
36
35
33
32
30
29
28
27
D_AD7
D_AD6
D_AD5
D_AD4
D_AD3
D_AD2
D_AD1
D_AD0
25
DS2
RED
2
IO36
IO35
IO34
IO33
IO32
IO31
IO30
IO29
IO28
IO27
IO26
IO25
IO24
IO23
IO22
IO21
GCK3 IO20
IO19
TP17
TP12
TP13
XILINX_XC9572XL
GREEN LEDS
V3_3
77
78
79
81
82
85
86
87
89
90
91
92
93
94
95
96
97
99
IO1
IO54
10K
JT10
47
83
45
48
2.5V_3.3V1
IO3
IO52
U5
IO5
IO50
2
TCK
TDI
TDO
TMS
GND4
CLK2048
IO7
IO48
XILINX_XC9572XL
IO9
IO46
U5
IO11
IO44
D
GND5
3
IO42
4
IO13
IO14
IO41
V3_3
GND6
CLK16384_T
IO2
IO53
R40
R42330
5
IO4
IO51
R36330
R31330
1.0K
IO6
IO49
R39330
R41330
1
2
IO8
IO47
R35330
R30330
GND1
IO10
IO45
R45330
R50330
GND7
IO12
IO43
SW1_B0EN
SW1_B1EN
SW1_B2EN
SW1_B3EN
SW2_B0EN
SW2_B1EN
SW2_B2EN
SW2_B3EN
SW3_B0EN
SW3_B1EN
SW3_B2EN
SW3_B3EN
R43330
R53330
330
1
1
1
1
1
1
1
1
1
1
1
1
GND8
21
31
44
62
69
75
84
100
TUSEL
IO15
IO40
6
1
1
IO16
IO39
7
1
1
GCK1 IO17
IO38
8
1
1
1
3
4
6
8
9
10
11
12
13
14
15
16
17
18
20
22
23
GCK2 IO18
IO37
76
74
72
71
70
68
67
66
65
64
63
61
60
59
58
56
55
54
RLOS_LOTC_INDICATOR
INT_INDICATOR
INT
RLOS_LOTC
A
B
C
D
A
B
C
D
8
8
7
11
10
9
8
7
6
5
4
3
2
1
12
11
10
9
8
7
6
5
4
3
2
1
12
B9
B8
B7
B6
B5
B4
B3
B2
B1
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC1
GND
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BE*
VCC
U3
IDTQS3R861
A9
A8
A7
A6
A5
A4
A3
A2
A1
B0
BE*
NC1
A0
VCC
GND
U4
IDTQS3R861
6
6
5
GND
7
5
3
1
19
13
14
15
16
17
GND
49
47
45
43
RXPRTY 41
19
18
39
20
35
33
31
29
27
25
23
21
37
BP_EN
GND
GND
GND
17
TXPRTY 15
21
22
23
24
13
14
15
13
2
16
R12
330
11
1
17
2
9
V3_3
BP_EN
1
GREEN
DS4
5
18
19
20
21
22
23
24
V3_3
BP_EN IS BIT MAPPED TO
PLD ADDRESS 0X15 BIT 2
LOGIC 0 CLOSES SWITCHES
RXA_1
RXDATA_6
RXDATA_4
RXDATA_2
RXDATA_0
RXSOC
RXA_3_RXCLAV_2
RXCLAV_0
RXA_2_RXCLAV_1
RXA_4_RXCLAV_3
TXA_3_TXCLAV_2
TXA_1
TXDATA_6
TXDATA_4
TXDATA_2
TXDATA_0
TXSOC
TXA_3_TXCLAV_2
TXCLAV_0
RXA_3_RXCLAV_2
7
12
10
8
6
4
2
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
4
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
TIM J2X
J7
4
GND
GND
GND
3
3
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BE*
VCC
13
14
15
16
17
18
19
20
21
22
23
24
13
14
15
16
17
18
19
20
21
22
23
24
2
STEVE SCULLY
DS2156DK02A0
NC1
GND
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BE*
VCC
U1
IDTQS3R861
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC1
GND
ENGINEER:
TITLE:
11
10
9
8
7
6
5
4
3
2
1
12
11
10
9
8
7
6
5
4
3
2
1
12
U2
IDTQS3R861
2
51.1
PAGE:
1
6 / 13
10/04/02
DATE:
BP_EN
TXA_2_TXCLAV_1
RXA_4_RXCLAV_3
RXA_2_RXCLAV_1
RXA_0
RXDATA_7
RXDATA_5
RXDATA_3
RXDATA_1
RXENA R4
1
2
UR_CLK
V3_3
BP_EN
TXA_4_TXCLAV_3
TXA_2_TXCLAV_1
TXA_0
TXDATA_7
TXDATA_5
TXDATA_3
TXDATA_1
TXENA R5
1
2 UT_CLK
TXA_4_TXCLAV_3
51.1
V3_3
1
A
B
C
D
A
B
C
D
8
UR_CLK 1
R21
51.1
RXADDR0
RXADDR2
RXADDR3
RXCLAV0
GND
RXDATA_0
RXDATA_2
GND
RXDATA_5
RXDATA_7
2
12
10
8
6
4
2
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
7
ADTECH RX
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
CONN_50P1
J2
RXENB
RXADDR1
GND
RXADDR4
GND
RXSOC
RXDATA_1
RXDATA_3
RXDATA_4
RXDATA_6
GND
6
6
TXADDR0
GND
TXADDR3
TXCLAV0
TXDATA_0
TXDATA_2
GND
TXDATA_5
TXDATA_7
5
5
12
10
8
6
4
2
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
ADTECH TX
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
CONN_50P1
J1
4
TXENABLE
2 R14 1 UT_CLK
GND
TXSOC
TXADDR1
TXADDR2
TXADDR4
GND
TXDATA_1
TXDATA_3
TXDATA_4
TXDATA_6
GND
4
3
3
ENGINEER:
TITLE:
1
1
1
1
1
1
1
2
STEVE SCULLY
TP
TP
TP
PAGE:
1
7 / 13
10/04/02
DATE:
GND
TP22
RESET_OUT
1
1
1
1
A8
A9
RW_T
WE_T
1
1
TP20 TP21
TP6
TP1
TP16
TP7
TP11
TP10
TP9
TP8
TP4
TP5
TP3
TP2
2
DS2156DK02A0
CS_T
CLK16384_T
CLK1544_T
A10
A11
A12
A13
TP
TP
TP
TP
7
1
TP
TP
TP
TP
TP
TP
1
8
1
TP
TP
A
B
C
D
A
B
C
D
RXA_3_RXCLAV_2
RMSYNC
RXA_4_RXCLAV_3
RFSYNC
RXCLAV_0
RSER
RXDATA_0
RLINK
RXADDR3
UR_ADDR3
RXADDR4
UR_ADDR4
RXCLAV0
UR_CLAV
RXDATA_0
UR_DATA0
8
RXDATA_7
RPOSO
RXDATA_7
UR_DATA7
RXDATA_5
RCLKO
RXDATA_5
UR_DATA5
RXDATA_6
RNEGO
RXDATA_4
RCLKI
RXDATA_4
UR_DATA4
RXDATA_6
UR_DATA6
RXDATA_3
RNEGI
7
RXDATA_2
RPOSI
RXDATA_3
UR_DATA3
RXDATA_2
UR_DATA2
RXDATA_1
RLCLK
RXA_2_RXCLAV_1
RSIG
RXADDR2
UR_ADDR2
RXDATA_1
UR_DATA1
RXA_1
RSIGF
RXA_0
RCHCLK
RXADDR1
UR_ADDR1
RXADDR0
UR_ADDR0
6
6
5
TXDATA_5
UT_DATA5
TXDATA_4
UT_DATA4
TXDATA_3
UT_DATA3
TXDATA_2
UT_DATA2
TXDATA_1
UT_DATA1
TXDATA_0
UT_DATA0
4
TXDATA_5
TSER
TXDATA_4
TPOSO
TXDATA_3
TNEGO
TXDATA_2
TCLKO
TXDATA_1
TCLKI
TXDATA_0
TNEGI
UT_CLAV
LIUC
TXA_4_TXCLAV_3
TPOSI
TXADDR4
UT_ADDR4
TXCLAV0
TXCLAV_0
TXA_3_TXCLAV_2
TLINK
TXA_2_TXCLAV_1
TLCLK
TXA_1
TCHBLK
TXA_0
UOP3
RXSOC
RCHBLK
RXENA
BPCLK
4
TXADDR3
UT_ADDR3
TXADDR2
UT_ADDR2
TXADDR1
UT_ADDR1
TXADDR0
UT_ADDR0
RXSOC
UR_SOC
RXENB
UR_ENB
5
3
3
ENGINEER:
TITLE:
2
STEVE SCULLY
DS2156DK02A0
TXSOC
UT_SOC
TXDATA_6
TSIG
UR_CLK
1
TCHCLK
TSSYNC
TXSOC
UOP0
TXENA
UOP1
TXDATA_7
TSYSCLK
UT_CLK
TXENABLE
UT_ENB
TXDATA_7
UT_DATA7
TXDATA_6
UT_DATA6
2
PAGE:
1
8 / 13
10/04/02
DATE:
0.1UF NOPOP
R34
C14
7
R33
C13
2
1 1
2
2
1 1
2
8
0.1UF NOPOP
A
B
C
D
A
B
C
D
8
8
GND
4A
3A
NC2
4Y
3Y
2Y
9
13
10
7
4
15
12
16
SW1_B2EN
SW1_B3EN
TSYSCLK
RSYSCLK
TCLK
MCLK
V3_3
1A
3
8
14
11
GND
4A
3A
2A
2OE*
5
6
1OE*
2
NC1
NC2
4Y
3Y
2Y
1Y
4OE*
3OE*
VCC
9
13
10
7
4
15
12
16
SW2_B2EN
SW2_B3EN
TSYSCLK
RSYSCLK
TCLK
MCLK
V3_3
7
SWITCH 2 IS MEMORY MAPPED
TO PLD REGISTER 0X12
LOGIC 0 CLOSES SWITCH
LOGIC 1 OPENS SWITCH
SW2_B0EN
SW2_B1EN
CLK2048
1
U10
IDTQS3125
SWITCH 1 IS MEMORY MAPPED
TO PLD REGISTER 0X11
LOGIC 0 CLOSES SWITCH
LOGIC 1 OPENS SWITCH
8
14
11
2A
6
4OE*
2OE*
1Y
3OE*
VCC
1OE*
1A
NC1
SW1_B0EN 2
SW1_B1EN 5
CLK1544_T 3
1
U8
IDTQS3125
7
6
6
TSER
RSER
TCLK
RCLK
TSYNC
RSYNC
VCC
A9
B9
B8
B7
A7
A8
B6
B5
B4
B3
A6
A5
A4
A3
B2
B1
A1
A2
B0
BE*
A0
NC1
GND
13
14
15
16
17
18
19
20
21
22
23
24
2
5
1
PPC_TDM_EN
PPC_TXD
PPC_RXD
PPC_TXCLK
PPC_RXCLK
PPC_TSYNC
PPC_RSYNC
1
V3_3
4
R7
330
GREEN DS1
4
PPC_TDM_EN IS BIT MAPPED TO
PLD ADDRESS 0X15 BIT 1
LOGIC 0 CLOSES SWITCHES
11
10
9
8
7
6
5
4
3
2
1
12
U6
IDTQS3R861
5
2
1
1
NC2
4Y
3Y
2Y
1Y
4OE*
3OE*
VCC
9
13
10
7
4
15
12
16
V3_3
SW3_B2EN
SW3_B3EN
RCLK
RCLK
RCLK
RSYNC
GND
4A
3A
2A
1A
2OE*
1OE*
NC1
NC2
4Y
3Y
2Y
1Y
4OE*
3OE*
VCC
U9
IDTQS3125
9
13
10
7
4
15
12
16
SW4_B2EN
SW4_B3EN
TSYNC
TSER
UT_CLK
UR_CLK
V3_3
ENGINEER:
TITLE:
2
STEVE SCULLY
DS2156DK02A0
SWITCH 4 IS MEMORY MAPPED
TO PLD REGISTER 0X14
LOGIC 0 CLOSES SWITCH
LOGIC 1 OPENS SWITCH
8
14
SW4_B0EN 2
SW4_B1EN 5
3
RSYNC
6
RSER
CLK2048 11
3
GND
4A
3A
2A
1A
2OE*
1OE*
NC1
U7
IDTQS3125
2
SWITCH 3 IS MEMORY MAPPED
TO PLD REGISTER 0X13
LOGIC 0 CLOSES SWITCH
LOGIC 1 OPENS SWITCH
8
SW3_B0EN 2
SW3_B1EN 5
3
TSYSCLK
6
RSYSCLK
11
TCLK
14
TSSYNC
3
PAGE:
1
9 / 13
10/04/02
DATE:
1
A
B
C
D
8
7
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP33 TP38 TP37 TP36 TP35 TP34 TP32 TP31
1
TP
1
1
TP24 TP25 TP26 TP27 TP28 TP29 TP23 TP30
1
1
A
1
1
B
1
1
C
1
1
D
1
1
7
1
1
8
1
C35
2
1
6
6
V3_3
10UF
C36
1
2
1UF
C31
2
2
2
1
C32
0.1UF
C33
0.1UF
1
1
0.1UF
C34
2
1
5
5
0.1UF
C1
2
1
0.1UF
C22
2
1
0.1UF
C29
2
2
1
C30
0.1UF
1
0.1UF
C11
4
1
4
2
0.1UF
C10
2
2
1
C9
0.1UF
1
0.1UF
C8
2
2
1
C16
0.1UF
1
0.1UF
C15
2
1
3
3
ENGINEER:
TITLE:
0.1UF
C18
2
2
1
C19
0.1UF
1
0.1UF
C2
1
C4
0.1UF
1
1
C3
0.1UF
1
2
2
STEVE SCULLY
DS2156DK02A0
2
2
0.1UF
C5
2
2
0.1UF
C17
2
2
2
1
C12
0.1UF
C21
0.1UF
1
1
0.1UF
PAGE:
1
10 / 13
VCC
10/04/02
DATE:
V3_3
1
A
B
C
D
A
B
C
D
8
7
JTMS
JTRST
JTDI
JTCLK
JTDO
TTIP
TRING
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
8XCLK
RCL
LIUC
RTIP
RRING
RPOSI
RNEGI
RCLKI
RPOSO
RNEGO
RCLKO
1
JTMS
JTRST
JTDI
JTCLK
JTDO
2
10
4
7
5
41
42
43
40
39
38
32
TTIP
TRING
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
8XCLK
RCL
LIUC
RTIP
RRING
RPOSI
RNEGI
RCLKI
RPOSO
RNEGO
RCLKO
29
12
6
13
89
90
91
88
87
86
17
16
VALUE=NA
6
V3_3
18
31
44
61
81
83
TVSS
RVSS1
RVSS2
RVSS3
DVSS1
DVSS2
DVSS3
DVSS4
6
30
19
20
24
45
60
80
84
ESIBS
ESIBS
ESIBS0 36
ESIBS154
7
5
4
DS2156
TQFP
5
4
NC3
BTS
MUX
RD/DS*
WR/RW*
ALE/AS/A
A
A
A
A
A
A
A
D/AD
D/AD
D/AD
D/AD
D/AD
D/AD
D/AD
D/AD
TCHBLK
RCHBLK
RLOS/LOTC
INT*
CS*
UOP0
UOP1
UOP2
UOP3
UOP0
UOP1
UOP2
UOP3
8
9
15
23
8
RSER
MCLK
RMSYNC
RSIG
BPCLK
TSTRST
RSIGF
XTALD
ESIBRD
TSER
RSER 95
MCLK 21
RMSYNC 96
RSIG 94
BPCLK 3
TSTRST 14
RSIGF 93
XTALD 22
ESIBRD 76
TSER 47
RVDD
TVDD
DVDD1
DVDD2
DVDD3
DVDD4
RCLK
RLINK
RSYNC
RCHCLK
RSYSCLK
RLCLK
RDATA
RFSYNC
82
78
98
92
100
79
85
97
RCLK
RLINK
RSYNC
RCHCLK
RSYSCLK
RLCLK
RDATA
RFSYNC
TCLK
TLINK
TSYNC
TCHCLK
TSYSCLK
TLCLK
TDATA
TSSYNC
TSIG
46
35
37
53
51
34
50
52
48
49
TCLK
TLINK
TSYNC
TCHCLK
TSYSCLK
TLCLK
TDATA
TSSYNC
TSIG
TESO
NC1
NC2
TUSEL 26
N_P27 27
33
BTS
MUX
RD_DS
WR_RW
11
28
77
74
55
66
67
68
69
70
71
72
3
ENGINEER:
TITLE:
N_P28
A7
A6
A5
A4
A3
A2
A1
A0
73
56
57
58
59
62
63
64
D_AD7
D_AD6
D_AD5
D_AD4
D_AD3
D_AD2
D_AD1
D_AD0
TCHBLK
RCHBLK
RLOS_LOTC
INT
CS
65
75
25
99
1
3
2
STEVE SCULLY
DS2156DK02A0
2
PAGE:
1
11 / 13
10/04/02
DATE:
1
A
B
C
D
A
B
C
D
7
7
8A7> 2C8< 5A8< 11C7<
2C8> 8A7> 11C7>
2D6> 11D5>
5C4 2A3< 11A3<
4B6 5B1 7B1
2D6> 8C7> 11D5>
2D6> 8B7> 11D5>
RCLKI
RCLKO
RDATA
RD_DS
RESET_OUT
RFSYNC
RLCLK
8
2C8> 11C7>
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 5C4 2B3< 11B3<
4C6 7B1
4B6 7B1
4C3 7C3
4C3 5C1 7C3
4C3 5C1 7B3
4B3 7B3
4B3
4B3
2A5> 8D4> 11A4>
5C1 6B2< 6B6< 6C2< 6C6<
5D4 2B3< 5A6< 11A3<
7B3 9D8 4B2<
5D3 9B3 9B8
4B4 5D3 7B3
5B4 2C3< 11C3<
4B8 5B1 7B3
2B3 4B6 5C1 11B3
2C3 4B6 5C1 11B3
2C3 4B6 5C1 11C3
2C3 4B6 5C1 11C3
2C3 4B6 5C1 11C3
2C3 4B6 5C1 11C3
2C3 4A6 5C1 11C3
2C3 4A6 5D1 11C3
2A5 11A4 5A8<
2A6 11A6
2A6 11A5
2C3> 4A8 5A2 11C3> 5A6<
5A2
2A8< 11A7<
2A8< 11A7<
2A8> 11A7>
2B8< 11B7<
2B8< 5A8< 11A7<
8B4> 2C8< 5A6< 11B7<
9B6 9C6 2A5< 11A5<
5C4 2A3< 5A8< 11A3<
4B2
4B2
4B2
4B2
4B2
4B2
4B2
4C2
2A4< 11A4<
2A3< 11A3<
4C8 9A4
4C8 9A4
4C8 9A4
5C1 9A4<
4B8 9A4
4C8 9A4
4C8 9A4
2C3> 8D4> 11C3>
2D6> 8D7> 11D5>
2C8> 11C7>
2D6> 9A6 9C1 9C1 9D1 11D6>
8XCLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BPCLK
BP_EN
BTS
CLK1544_T
CLK2048
CLK16384_T
CS
CS_T
D_AD0
D_AD1
D_AD2
D_AD3
D_AD4
D_AD5
D_AD6
D_AD7
ESIBRD
ESIBS0
ESIBS1
INT
INT_INDICATOR
JTCLK
JTDI
JTDO
JTMS
JTRST
LIUC
MCLK
MUX
NIMD8
NIMD9
NIMD10
NIMD11
NIMD12
NIMD13
NIMD14
NIMD15
N_P27
N_P28
PPC_RSYNC
PPC_RXCLK
PPC_RXD
PPC_TDM_EN
PPC_TSYNC
PPC_TXCLK
PPC_TXD
RCHBLK
RCHCLK
RCL
RCLK
*** Signal Cross-Reference for the entire design ***
8
6
RLINK
2D6> 8B7> 11D6>
RLOS_LOTC
2C3> 5B2 11C3>
RLOS_LOTC_INDICATOR 5A2
RMSYNC
2A5> 8C7> 11A5>
RNEGI
8B7> 2C8< 5A8< 11C7<
RNEGO
2C8> 8A7> 11C7>
RPOSI
8B7> 2C8< 5A8< 11C7<
RPOSO
2C8> 8A7> 11C7>
RRING
2C8< 3B8< 11C7<
RSER
2A5> 8C7> 9A6 9B3 11A5>
RSIG
2A5> 8D7> 11A5>
RSIGF
2A5> 8D7> 11A4>
RSYNC
2D6 9A6 9B3 9C1 11D5
5A6<
RSYSCLK
9B6 9C3 9D6 2D6< 5A8< 11D5<
RTIP
2C8< 3B8< 11C7<
RW_T
4B6 5B1 7B1
RXADDR0
7B8 8D8
RXADDR1
7B6 8D8
RXADDR2
7B8 8D8
RXADDR3
7B8 8C8
RXADDR4
7B6 8C8
RXA_0
6B2 8D7>
RXA_1
6B7 8D7>
RXA_2_RXCLAV_1
6A7 6B2 8D7>
RXA_3_RXCLAV_2
6A7 6C7 8C7>
RXA_4_RXCLAV_3
6A7 6B2 8C7>
RXCLAV0
7A8 8C8
RXCLAV_0
6A7 8C7>
RXDATA_0
6B7 7C8 8B7> 8B8
RXDATA_1
6A2 7C6 8B7> 8B8
RXDATA_2
6B7 7C8 8B7> 8B8
RXDATA_3
6B2 7C6 8B7> 8B8
RXDATA_4
6B7 7C6 8A7> 8A8
RXDATA_5
6B2 7C8 8A7> 8A8
RXDATA_6
6B7 7C6 8A7> 8A8
RXDATA_7
6B2 7C8 8A7> 8A8
RXENA
6A2 8D4>
RXENB
7A6 8D5
RXPRTY
6B5
RXSOC
6B7 7B6 8D4> 8D5
SNIM_B2
4C2
SNIM_B3
4C2
SNIM_B4
4C2
SNIM_B5
4C2
SNIM_B6
4C2
SNIM_B7
4C2
SW1_B0EN
5A4 9D8<
SW1_B1EN
5A4 9D8<
SW1_B2EN
5A3 9D6<
SW1_B3EN
5A3 9D6<
SW2_B0EN
5A3 9B8<
SW2_B1EN
5A3 9B8<
SW2_B2EN
5A3 9B6<
SW2_B3EN
5A3 9B6<
SW3_B0EN
5A3 9D3<
SW3_B1EN
5A3 9D3<
SW3_B2EN
5A3 9D1<
SW3_B3EN
5A3 9D1<
SW4_B0EN
5B4 9B3<
SW4_B1EN
5B4 9B3<
SW4_B2EN
5B4 9B2<
SW4_B3EN
5B4 9B2<
TCHBLK
2D3> 8C4> 11C3>
TCHCLK
2D5> 11D4> 8A1<
TCK
5B8 5D8<
TCLK
9A6 9B6 9C3 9C6 2D5< 5A6<
11D5<
TCLKI
8B4> 2B8< 5A8< 11B7<
TCLKO
2B8> 8A4> 11B7>
TDATA
2D5 11D4
TDI
5B8 5D7<
TDO
5B8 5C7<
TIM5V
4D3 4D8
TLCLK
2D5> 8C4> 11D4>
TLINK
8C4> 2D5< 5B6< 11D5<
TMS
5B8 5C7<
6
5
5
4
8B4> 2B8< 5A8< 11B7<
2B8> 8A4> 11B7>
8C4> 2B8< 5A8< 11B7<
2B8> 8A4> 11B7>
2B8> 11B7> 3C8<
8A4> 9A6 9B2 2A5< 5A8< 11A4<
8D1> 2D5< 5B6< 11D4<
9C3 2D5< 5B6< 8A1< 11D4<
2A5< 5A8< 11A4<
2D5 9A6 9B2 11D5 5A6<
8D1> 9B6 9D3 9D6 2D5< 5A8<
11D4<
TTIP
2B8> 11B7> 3C8<
TUSEL
5D2 2A4< 11A4<
TXADDR0
7B5 8D5
TXADDR1
7B4 8C5
TXADDR2
7B4 8C5
TXADDR3
7B5 8C5
TXADDR4
7B4 8C5
TXA_0
6C2 8D4>
TXA_1
6C7 8C4>
TXA_2_TXCLAV_1
6B2 6C2 8C4>
TXA_3_TXCLAV_2
6C7 6C7 8C4>
TXA_4_TXCLAV_3
6C2 6C2 8C4>
TXCLAV0
7B5 8B5
TXCLAV_0
6C7 8B5
TXDATA_0
6C7 7C5 8B4> 8B5
TXDATA_1
6C2 7C4 8B4> 8B5
TXDATA_2
6C7 7C5 8A4> 8A5
TXDATA_3
6C2 7C4 8A4> 8A5
TXDATA_4
6C7 7C4 8A4> 8A5
TXDATA_5
6C2 7C5 8A4> 8A5
TXDATA_6
6C7 7C4 8D1> 8D2
TXDATA_7
6C2 7C5 8D1> 8D2
TXENA
6C2 8C1>
TXENABLE
7B4 8C2
TXPRTY
6C5
TXSOC
6C7 7B4 8B1> 8B2
UOP0
2A6> 8B1> 11A5>
UOP1
2A6> 8C1> 11A5>
UOP2
2A6> 11A5>
UOP3
2A6> 8D4> 11A5>
UR_ADDR0
8D8
UR_ADDR1
8D8
UR_ADDR2
8D8
UR_ADDR3
8C8
UR_ADDR4
8C8
UR_CLAV
8C8
UR_CLK
9B2 6A1< 7A8< 8A2<
UR_DATA0
8B8
UR_DATA1
8B8
UR_DATA2
8B8
UR_DATA3
8B8
UR_DATA4
8A8
UR_DATA5
8A8
UR_DATA6
8A8
UR_DATA7
8A8
UR_ENB
8D5
UR_SOC
8D5
UT_ADDR0
8D5
UT_ADDR1
8C5
UT_ADDR2
8C5
UT_ADDR3
8C5
UT_ADDR4
8C5
UT_CLAV
8B4>
UT_CLK
9B2 6C1< 7B4< 8A2<
UT_DATA0
8B5
UT_DATA1
8B5
UT_DATA2
8A5
UT_DATA3
8A5
UT_DATA4
8A5
UT_DATA5
8A5
UT_DATA6
8D2
UT_DATA7
8D2
UT_ENB
8C2
UT_SOC
8B2
WE_T
4B6 5B1 7B1
TNEGI
TNEGO
TPOSI
TPOSO
TRING
TSER
TSIG
TSSYNC
TSTRST
TSYNC
TSYSCLK
4
3
3
ENGINEER:
TITLE:
WR_RW
XTALD
2
STEVE SCULLY
DS2156DK02A0
5C4 2A3< 11A3<
2A5> 11A4>
2
PAGE:
1
12 / 13
10/04/02
DATE:
1
A
B
C
D
A
B
C
D
7
1
C1
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C21
C22
C23
C24
C25
C26
C27
C29
C30
C31
C32
C33
C34
C35
C36
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DS17
DS18
F1
F2
F3
F4
F5
F6
J1
J2
J3
J4
J5
J6
J7
J8
J9
JT10
L1
R1
R2
R3
R4
R5
R6
8
DS2156_TQFP 11D7
CAP
10B5
CAP
10B3
CAP
10B2
CAP
10B2
CAP
10B2
CAP
3D6
CAP
10B4
CAP
10B4
CAP
10B4
CAP
10B4
CAP
10B2
CAP
8A1
CAP
8A1
CAP
10B3
CAP
10B3
CAP
10B2
CAP
10B3
CAP
10B3
CAP
10B2
CAP
10B5
CAP
3A6
CAP
3C5
CAP
3B5
CAP
3A5
CAP
3D5
CAP
10B4
CAP
10B4
CAP
10B6
CAP
10B5
CAP
10B5
CAP
10B5
CAP
10B6
CAP
10B6
LED
9B4
LED
5A2
LED
5A2
LED
6D5
LED
5A3
LED
5A4
LED
5A3
LED
5A4
LED
5A4
LED
5A3
LED
5A4
LED
5A3
LED
5A3
LED
5A3
LED
5A3
LED
5B5
LED
5B5
LED
5A3
FUSE
3B4
FUSE
3B4
FUSE
3D4
FUSE
3C4
FUSE
3D4
FUSE
3A3
CONN_50P1 7D5
CONN_50P1 7D7
CONN_BANTAM_IPC 3B1
CONN_BANTAM_IPC 3C1
CONN_BNC_5PIN 3A3
CONN_BNC_5PIN 3D2
CONN_50P2 6D4
CONN_50P2 4D3
CONN_50P2 4D7
CONN_10P 5C8
CHOKE_DUAL_T1 3B4 3C4
RES1
4B2
RES
3B7
RES
3B7
RES
6A2
RES
6C2
RES1
5A7
7
*** Part Cross-Reference for the entire design ***
8
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
RJ1
SW1
T1
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP20
TP21
6
RES
9B4
RES1
5A2
RES1
5A7
RES1
5A7
RES1
5A2
RES
6D5
RES1
5B6
RES1
7B4
RES1
5B6
RES1
5A7
RES1
5B6
RES1
5A6
RES1
5A6
RES1
7A8
RES1
5A7
RES1
5A7
RES1
5B8
RES1
5D7
RES1
5D8
RES1
5D8
RES1
5A7
RES1
5A6
RES
5A3
RES
5A3
RES1
5A6
RES1
8A1
RES1
8A1
RES
5A3
RES
5A3
RES1
5A6
RES
5A7
RES
5A3
RES
5A4
RES
5A3
RES
5A4
RES
5A3
RES1
5A7
RES
5A3
RES1
5B7
RES1
5A7
RES1
5A6
RES1
5A7
RES
5A3
RES
5B4
RES
5B4
RES
5A3
RES1
3B6
RES1
3B6
RES
3B5
RES
3B6
RES
3D7
RES
3C7
RES
3A5
RES1
5A7
RJ48_CON 3C3
SWITCH_DPDT_SLIDE_6P 3A6
XFMR_2IN_4OUT_U 3B5 3D5
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 7C2
TSTPNT_SNG 7C2
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 7B2
TSTPNT_SNG 5D2
TSTPNT_SNG 5D2
TSTPNT_SNG 5A6
TSTPNT_SNG 5A6
TSTPNT_SNG 7B2
TSTPNT_SNG 5D2
TSTPNT_SNG 5A6
TSTPNT_SNG 7B2
TSTPNT_SNG 7B1
6
5
5
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
4
TSTPNT_SNG 7B1
TSTPNT_SNG 10A7
TSTPNT_SNG 10A8
TSTPNT_SNG 10A7
TSTPNT_SNG 10A7
TSTPNT_SNG 10A7
TSTPNT_SNG 10A7
TSTPNT_SNG 10A7
TSTPNT_SNG 10A7
TSTPNT_SNG 10A4
TSTPNT_SNG 10A4
TSTPNT_SNG 10A5
TSTPNT_SNG 10A5
TSTPNT_SNG 10A5
TSTPNT_SNG 10A5
TSTPNT_SNG 10A5
TSTPNT_SNG 10A5
IDTQS3R861_U 6B3
IDTQS3R861_U 6D3
IDTQS3R861_U 6B6
IDTQS3R861_U 6D6
XILINX_XC9572XL 5D4 5D7
IDTQS3R861_U 9B5
IDTQS3125_U 9D3
IDTQS3125_U 9D7
IDTQS3125_U 9B3
IDTQS3125_U 9B7
DS2156_TQFP 2D7
SIDACTOR_2 3C4
SIDACTOR_2 3D5
SIDACTOR_2 3A5
SIDACTOR_2 3B5
SIDACTOR_2 3C6
SIDACTOR_2 3A4
SIDACTOR_2 3C4
SIDACTOR_2 3A4
SIDACTOR_2 3C4
SIDACTOR_2 3B4
4
3
3
ENGINEER:
TITLE:
2
STEVE SCULLY
DS2156DK02A0
2
PAGE:
1
13 / 13
10/04/02
DATE:
1
A
B
C
D
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