DS21Q55DK
Quad T1/E1/J1 Transceiver Design Kit
Daughter Card
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS21Q55DK is an easy-to-use evaluation board
for the DS21Q55 quad T1/E1/J1 transceiver. The
DS21Q55DK is intended to be used as a daughter
card with the DK101 motherboard or the DK2000
motherboard. The DS21Q55DK comes complete with
a DS21Q55 quad SCT, transformers, termination
resistors, configuration switches, line-protection
circuitry, network connectors, and motherboard
connectors. The DK101/DK2000 motherboard and
Dallas’ ChipView software give point-and-click
access to configuration and status registers from a
Windows®-based PC. On-board LEDs indicate
receive loss-of-signal and interrupt status. An onboard FPGA contains mux logic to connect framer
ports to one another or to the DK2000 in a variety of
configurations.
Demonstrates Key Functions of DS21Q55
Quad T1/E1/J1 Transceiver
Includes DS21Q55 Quad LIU, Transformers,
BNC, and RJ45 Network Connectors and
Termination Passives
Compatible with DK101 and DK2000 Demo Kit
Motherboards
DK101/DK2000 and ChipView Software
Provide Point-and-Click Access to the
DS21Q55 Register Set
All Equipment-Side Framer Pins are Easily
Accessible for External Data Source/Sink
Memory-Mapped FPGA Provides Flexible
Clock/Data/Sync Connections Among Framer
Ports and DK2000 Motherboard
LEDs for Loss-of-Signal and Interrupt Status
Easy-to-Read Silk-Screen Labels Identify the
Signals Associated with All Connectors,
Jumpers and LEDs
Network Interface Protection for Overvoltage
and Overcurrent Events
Each DS21Q55DK is shipped with a free DK101
motherboard. For complex applications, the DK2000
high-performance demo kit motherboard can be
purchased separately.
Windows is a registered trademark of Microsoft Corp.
DESIGN KIT CONTENTS
ORDERING INFORMATION
PART
DS21Q55DK
DS21Q55DK Design Kit Daughter Card
DK101 Low-Cost Motherboard
CD-ROM
ChipView Software
DS21Q55DK Data Sheet
DK101 Data Sheet
DS21Q55 Data Sheet
DS21Q55 Errata Sheet
DESCRIPTION
DS21Q55 Demo Kit Daughter Card
(with included DK101 Motherboard)
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
TABLE OF CONTENTS
COMPONENT LIST .....................................................................................................................3
BOARD FLOORPLAN.................................................................................................................4
ERRATA ......................................................................................................................................4
BASIC OPERATION....................................................................................................................4
HARDWARE CONFIGURATION .....................................................................................................................4
Using the DK101 Processor Board: ..................................................................................................................... 4
Using the DK2000 Processor Board: ................................................................................................................... 4
General ................................................................................................................................................................. 5
Miscellaneous ....................................................................................................................................................... 5
QUICK SETUP (DEMO MODE).....................................................................................................................5
QUICK SETUP (REGISTER VIEW) ........................................................................................................5
ADDRESS MAP ..........................................................................................................................6
FPGA REGISTER MAP ........................................................................................................................7
ID REGISTERS............................................................................................................................7
CONTROL REGISTERS..............................................................................................................8
FPGA CONTROL EXAMPLES..................................................................................................15
DS21Q55 INFORMATION .........................................................................................................17
DS21Q55DK INFORMATION....................................................................................................17
TECHNICAL SUPPORT ............................................................................................................17
SCHEMATICS ...........................................................................................................................17
DOCUMENT REVISION HISTORY ...........................................................................................17
LIST OF TABLES
Table 1. Daughter Card Address Map........................................................................................................ 6
Table 2. FPGA Register Map ..................................................................................................................... 7
Table 3. TCLKx Source Definition .............................................................................................................. 8
Table 4. TSYSCLKx Source Definition ....................................................................................................... 9
Table 5. RSYSCLKx Source Definition....................................................................................................... 9
Table 6. RSYNCx Function Definition ...................................................................................................... 11
Table 7. TSERx Source Definition............................................................................................................ 12
Table 8. FPGA Configuration for Scenario #1 (Port 1, T1 Mode) .............................................................15
Table 9. FPGA Configuration for Scenario #2 (Port 1, T1 Mode) .............................................................16
Table 10. DS21Q55 Partial Configuration for Scenario #2 (Port 1, T1 Mode)..........................................16
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
COMPONENT LIST
DESIGNATION
QTY
C1–C8
8
0.22μF, 50V capacitors
Phycomp
PCF1150CT-ND
23
0.1μF 10%, 16V ceramic capacitors (0603)
Phycomp
06032R104K7B20D
4
0.1μF 10%, 25V ceramic capacitors (1206)
Panasonic
ECJ-3VB1E104K
8
1μF 10%, 16V ceramic capacitors (1206)
Panasonic
ECJ-3YB1C105K
2
1
1
5
16
1
8
1
2
1
3
10μF 20%, 10V ceramic capacitors (1206)
Quad port choke
LED, red, SMD
LED, green, SMD
1.25A, 250V fuse, SMT
10-pin, dual row, vertical jumper
5-pin connectors, BNC right-angle vertical
8-pin 4-port jack, right-angle RJ45
50-pin socket, SMD, dual row, vertical
12-pin connector, dual row, vertical
10kΩ 1%, 1/10W resistors (0805)
Panasonic
Pulse
Panasonic
Panasonic
Teccor
Digi-Key
Cambridge
Molex
Samtec
Digi-Key
Panasonic
ECJ-3YB1A106M
T8132
LN1251C
LN1351C
F1250T
S2012-05-ND
CP-BNCPC-004
43223-8140
TFM-125-02-S-D-LC
S2012-06-ND
ERJ-6ENF1002V
5
10kΩ 5%, 1/10W resistors (0805)
Panasonic
ERJ-6GEYJ103V
17
0Ω 5%, 1/8W resistors (1206)
Panasonic
ERJ-8GEYJ0R00V
R13
1
470Ω 5%, 1/10W resistor (0805)
Panasonic
ERJ-6GEYJ471V
R22–R25
4
51.1Ω 1%, 1/10W resistors (0805)
Panasonic
ERJ-6ENF51R1V
R27, R28, R38
3
1.0kΩ 1%, 1/10W resistors (0805)
Panasonic
ERJ-6ENF1001V
R29–R36
8
61.9Ω 1%, 1/8W resistors (1206)
Panasonic
ERJ-8ENF61R9V
R37, R47
2
Not populated
Panasonic
Not populated
R40, R42–R44,
R46, R49
6
330Ω 0.1%, 1/10W MF resistors (0805)
Panasonic
ERA-6YEB331V
SW1–SW4
4
6-PIN TH Switch DPDT
Tyco
SSA22
T1
1
XFMR, XMIT/RCV, 1 to 2, SMT 32-pin
Pulse
TX1473
U1
1
XILINX spartan 2.5V FPGA
144-pin, 20 x 20 TQFP
Xilinx
XC2S50-5TQ144C
U2
1
Quad T1/E1/J1 transceiver
256-pin BGA, 0°C to +70°C
multichip module
Dallas
Semiconductor
DS21Q55
U3
1
1M PROM for FPGA 44-pin TQFP
Xilinx
XC18V01VQ44C_U
U4
1
8-pin μMAX, SO
2.5V or ADJ
Maxim
MAX1792EUA25
U20
1
Serial configuration EEPROM for XILINX
65kb, 8-DIP
Atmel
AT17LV65EUA-NOPOP
Z1–Z8
8
50A, 6V Sidactor, DO214 SMD
Teccor
P0080SAMC
Z9–Z16
8
500A, 25V Sidactor, DO214 SMD
Teccor
P0300SCMC
Z17–Z32
16
500A, 170V Sidactor, DO214 SMD
Teccor
P1800SCMC
C9, C10, C12, C18,
C22–C33, C35,
C38–C43
C11, C13–C15
C16, C17, C19–C21,
C34, C36, C45
C37, C44
CH1
DS1
DS2–DS6
F1–F16
J1
J2–J9
J10
J11, J12
J13
R1, R2, R4
R3, R26, R39, R41,
R45
R5–R12, R14–R21,
R48
DESCRIPTION
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SUPPLIER
PART
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
FPGA
RLOS 1-4 LEDs
FPGA
STATUS
LED
JTAG
FPGA
CONFIG
PROM
QUAD PORT
CHOKE
QUAD PORT
TRANSFORMER
CPU INTERFACE
INT LED
CPU INTERFACE
DS21Q55
PCM BUS
TEST POINTS
IMPEDANCE
MATCHING/
LINE
PROTECTION
LINE
PROTECTION
PORT 4
BNC
PORT
4
LINE
PROTECTION
PORT 3
BNC
PORT
3
LINE
PROTECTION
PORT 2
BNC
PORT
2
LINE
PROTECTION
PORT 1
BNC
PORT
1
2.5V FPGA
SUPPLY
ERRATA
•
•
Connector J1 has silk-screen mislabeled such that the text TMS and TCK should be swapped. Worded
differently, TCK belongs to pin 7 and TMS belongs to pin 9.
Switches SW1 to SW4 are missing silk screen to indicate which side is grounded. Sliding the switch toward the
BNC grounds the BNC shell (E1 mode). For T1 mode the switch should be slid away from the BNC.
BASIC OPERATION
This design kit relies upon several supporting files, which are available for downloading on our website at
www.maxim-ic.com/telecom. See the DS21Q55DK QuickView data sheet for these files.
Hardware Configuration
Using the DK101 Processor Board:
•
•
•
•
Connect the daughter card to the DK101 processor board.
Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is
unused. Additionally, the ‘TIM 5V supply’ headers are unused.)
All processor board DIP-switch settings should be in the ON position with exception of the flash-programming
switch, which should be OFF.
From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs →
ChipView → ChipView.
Using the DK2000 Processor Board:
•
•
•
Connect the daughter card to the DK2000 processor board.
Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply may be connected
to connector J2.
From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs →
ChipView → ChipView.
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RJ45 x 4
BOARD FLOORPLAN
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
General
•
•
Upon power-up, the RLOS LEDs (green) will not be lit, the INT LED (red) will not be lit, but the FPGA status
LED (green) will be lit.
When operating in E1 mode, slide SW1–SW4 such that the BNC shell is grounded (to the left, as shown in the
board floorplan). When operating in T1 mode, ensure that SW1–SW4 are slid to the right as shown in the
board floorplan.
Miscellaneous
•
•
•
Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA, which is on the
DS21Q55 daughter card.
The definition file for this FPGA is named DS21Q55DC_FPGA.def. The definitions are located on page 7. A
drop-down menu on the top of the screen allows for switching between definition files.
All files referenced above are available for download as described in the section marked “BASIC OPERATION”
Quick Setup (Demo Mode)
•
•
•
•
The PC will load ChipView offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Demo Mode.
The program will request a configuration file, select among the displayed files
(DS2155_E1_DSNCOM_DRVR.cfg or DS2155_T1_DSNCOM_DRVR.cfg).
The Demo Mode screen will appear. Upon external loopback, the LOS and OOF indicators will extinguish.
Note: Demo Mode interacts with the device driver, which is resident in the DK101/DK2000 firmware. The
current implementation of this driver is for one device. As such, the demo mode will only interact with Port 1.
With minor changes, the device driver is extendible to N devices.
Quick Setup (Register View)
•
•
•
•
The PC will load ChipView offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View.
The program will request a definition file. Select DS21Q55DC_FPGA.def; through the ‘links’ section this will
also load DS21Q55DC.def.
The Register View Screen will appear, showing the register names, acronyms, and values for the DS21Q55
Predefined register settings for several functions are available as initialization files.
• INI files are loaded by selecting the menu File→Reg Ini File→Load Ini File
• Load the INI file DS21Q55_T1_BERT_ESF.ini
• After loading the INI file, the following may be observed:
− The RLOS LEDs (green) light upon external loopback.
− All four ports of the DS2Q155 begin transmitting a Daly pattern. When external loopback is applied, the
BERT bit count registers BBC1–3 and BEC1–3 may be updated by clearing and setting BC1.LC and
clicking the ‘Read All’ button.
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
ADDRESS MAP
DK101 Daughter Card address space begins at 0x81000000.
DK2000 Daughter Card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets given below are relative to the beginning of the daughter card address space (shown above).
Table 1. Daughter Card Address Map
OFFSET
0X0000
to
0X0015
0X1000
to
0X10ff
0X2000
to
0X20ff
0X3000
to
0X30ff
0X4000
to
0X40ff
DEVICE
FPGA
DESCRIPTION
Board identification and clock/signal routing
T1/E1/J1
Transceiver #1
DS21Q55 T1/E1/J1 transceiver, port 1
T1/E1/J1
Transceiver #2
DS21Q55 T1/E1/J1 transceiver, port 2
T1/E1/J1
Transceiver #3
DS21Q55 T1/E1/J1 transceiver, port 3
T1/E1/J1
Transceiver #4
DS21Q55 T1/E1/J1 transceiver, port 4
Registers in the FPGA may be easily modified using the ChipView host-based user-interface software along with
the definition file named “DS21Q55DC_FPGA.def.”
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
FPGA Register Map
Table 2. FPGA Register Map
OFFSET
0X0000
0X0002
0X0003
0X0004
0X0005
0X0006
0X0007
0X0011
0X0012
0X0013
0X0014
0X0015
0X0016
0X0017
0X0018
0X0019
0X001A
0X001B
REGISTER
NAME
BID
XBIDH
XBIDM
XBIDL
BREV
AREV
PREV
MCSR
TCSR
SYSCLKT
SYSCLKR
SYNC1
SYNC2
SYNC3
TSERS
PRSER
PSYNC
PCLK
TYPE
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
DESCRIPTION
Board ID
High-Nibble Extended Board ID
Middle-Nibble Extended Board ID
Low-Nibble Extended Board ID
Board FAB Revision
Board Assembly Revision
PLD Revision
DS21Q55 MCLK Pin Source
DS21Q55 TCLK Pin Source
DS21Q55 TSYSCLK Pin Setting
DS21Q55 RSYSCLK Pin Setting
DS21Q55 TSYNC Source
DS21Q55 TSSYNC Source
DS21Q55 RSYNC Source
TSER Source
PCM RSER Source
PCM RSYNC/TSYNC Source
PCM RCLK/TCLK Source
ID REGISTERS
BID: BOARD ID (Offset=0X0000)
BID is read only with a value of 0xD
XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset=0X0002)
XBIDH is read only with a value of 0x0
XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset=0X0003)
XBIDM is read only with a value of 0x1
XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset=0X0004)
XBIDL is read only with a value of 0x6
BREV: BOARD FAB REVISION (Offset=0X0005)
BREV is read only and displays the current fab revision
AREV: BOARD ASSEMBLY REVISION (Offset=0X0006)
AREV is read only and displays the current assembly revision
PREV: PLD REVISION (Offset=0X0007)
PREV is read only and displays the current PLD firmware revision
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
CONTROL REGISTERS
Register Name: MCSR
Register Description: DS21Q55 MCLK Pin Source
Register Offset: 0x0011
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
MSRCB
1
0
MSRCA
1
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
Bit 0: DS21Q55 Port 1 and 3 MCLK Source (MSRCA)
0 = Connect MCLK 1 (controls port 1 and 3) to the 1.544MHz clock
1 = Connect MCLK 1 (controls port 1 and 3) to the 2.048MHz clock
Bit 1: DS21Q55 Port 2 and 4 MCLK Source (MSRCA)
0 = Connect MCLK 2 (controls port 2 and 4) to the 1.544MHz clock
1 = Connect MCLK 2 (controls port 2 and 4) to the 2.048MHz clock
Register Name: TCSR
Register Description: DS21Q55 TCLK Pin Source
Register Offset: 0x0012
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
Bit 0 to 1: DS21Q55 Port 1 TCLK Source (T1S0, T1S1)
The source for TCLK 1 is Defined as shown in Table 3.
Bit 2 to 3: DS21Q55 Port 2 TCLK Source (T2S0, T2S1)
The source for TCLK 2 is Defined as shown in Table 3.
Bit 4 to 5: DS21Q55 Port 3 TCLK Source (T3S0, T3S1)
The source for TCLK 3 is Defined as shown in Table 3.
Bit 6 to 7: DS21Q55 Port 4 TCLK Source (T4S0, T4S1)
The source for TCLK 3 is Defined as shown in Table 3.
Table 3. TCLKx Source Definition
TxS1, TxS0
00
01
10
11
TCLK CONNECTION
Drive TCLKX with the 1.544MHz clock
Drive TCLKX with the 2.048MHz clock
Drive TCLKX with RCLKX
N/A
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYSCLKT
Register Description: DS21Q55 TSYSCLK Pin Setting
Register Offset: 0x0013
Bit #
Name
Default
7
R4S1
0
6
R4S0
0
5
R3S1
0
4
R3S0
0
3
R2S1
0
2
R2S0
0
1
R1S1
0
0
R1S0
0
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
Bit 0 to 1: DS21Q55 Port 1 TSYSCLK Source (R1S0, R1S1)
The source for TSYSCLK 1 is Defined as shown in Table 4.
Bit 2 to 3: DS21Q55 Port 2 TSYSCLK Source (R2S0, R2S1)
The source for TSYSCLK 2 is Defined as shown in Table 4.
Bit 4 to 5: DS21Q55 Port 3 TSYSCLK Source (R3S0, R3S1)
The source for TSYSCLK 3 is Defined as shown in Table 4.
Bit 6 to 7: DS21Q55 Port 4 TSYSCLK Source (R4S0, R4S1)
The source for TSYSCLK 4 is Defined as shown in Table 4.
Table 4. TSYSCLKx Source Definition
RxS1, RxS0
00
01
10
11
TSYSCLKX CONNECTION
Drive TSYSCLKX with the 1.544MHz clock
Drive TSYSCLKX with the 2.048MHz clock
Drive TSYSCLK X with 8.192MHz clock
Drive TSYSCLKX with DS21Q55 PortX BPCLK
Register Name: SYSCLKR
Register Description: DS21Q55 RSYSCLK Pin Setting
Register Offset: 0x0014
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
Bit 0 to 1: DS21Q55 Port 1 RSYSCLK Source (T1S0, T1S1)
The source for RSYSCLK 1 is Defined as shown in Table 5.
Bit 2 to 3: DS21Q55 Port 2 RSYSCLK Source (T2S0, T2S1)
The source for RSYSCLK 2 is Defined as shown in Table 5.
Bit 4 to 5: DS21Q55 Port 3 RSYSCLK Source (T3S0, T3S1)
The source for RSYSCLK 3 is Defined as shown in Table 5.
Bit 6 to 7: DS21Q55 Port 4 RSYSCLK Source (T4S0, T4S1)
The source for RSYSCLK 4 is Defined as shown in Table 5.
Table 5. RSYSCLKx Source Definition
TxS1, TxS0
00
01
10
11
RSYSCLKX CONNECTION
Drive RSYSCLKX with the 1.544MHz clock
Drive RSYSCLKX with the 2.048MHz clock
Drive RSYSCLK X with 8.192MHz clock
Drive RSYSCLKX with DS21Q55 PortX BPCLK
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYNC1
Register Description: DS21Q55 TSYNC Pin Source
Register Offset: 0x0015
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21Q55 Port 1 TSYNC Source (T1SRC)
0 = TSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TSYNC Source (T2SRC)
0 = TSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TSYNC Source (T3SRC)
0 = TSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSYNC Source (T4SRC)
0 = TSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 4 with RSYNC 4
Note: When driving TSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
TSYNCx is an input (IOCR1.1 = 0) and RSYNCx is an output (IOCR1.4 = 0).
Register Name: SYNC2
Register Description: DS21Q55 TSSYNC Pin Source
Register Offset: 0x0016
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21Q55 Port 1 TSSYNC Source (T1SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TSSYNC Source (T2SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TSSYNC Source (T3SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSSYNC Source (T4Source)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 4 with RSYNC 4
Note: When driving TSSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
RSYNCx is an output (IOCR1.4 = 0).
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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYNC3
Register Description: DS21Q55 RSYNC Pin Setting
Register Offset: 0x0017
Bit #
Name
Default
7
RSOR1
0
6
RSOR0
0
5
—
—
4
—
—
3
R4IO
0
2
R3IO
0
1
R2IO
0
0
R1IO
0
Bit 0: DS21Q55 Port 1 RSYNC Setting (R1IO)
0 = RSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 1 with RSYNCX as shown in Table 6
Bit 1: DS21Q55 Port 2 RSYNC Setting (R2IO)
0 = RSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 2 with RSYNCX as shown in Table 6
Bit 2: DS21Q55 Port 3 RSYNC Setting (R3IO)
0 = RSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 4 with RSYNCX as shown in Table 6
Bit 3: DS21Q55 Port 4 RSYNC Setting (R4IO)
0 = RSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive RSYNC 4 with RSYNCX as shown in Table 6
Note: When driving RSYNCy with RSYNCx the corresponding DS21Q55 port should be configured such that
RSYNCx is an output (IOCR1.4 = 0) and RSYNCy is an input (IOCR1.4 = 1).
Table 6. RSYNCx Function Definition
RSOR1, RSOR0
00
01
10
11
MASTER RSYNC DESIGNATION
RSYNC 1 is used to drive other RSYNC pins (providing RXIO = 1)
RSYNC 2 is used to drive other RSYNC pins (providing RXIO = 1)
RSYNC 3 is used to drive other RSYNC pins (providing RXIO = 1)
RSYNC 4 is used to drive other RSYNC pins (providing RXIO = 1)
11 of 32
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: TSERS
Register Description: DS21Q55 TSER Pin Source
Register Offset: 0x0018
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
3
R1EN
0
2
R1EN
0
1
R1EN
0
0
R1EN
0
Bit 0 to 1: DS21Q55 Port 1 TSER Source (T1S0, T1S1)
The source for TSER 1 is Defined as shown in Table 7.
Bit 2 to 3: DS21Q55 Port 2 TSER Source (T2S0, T2S1)
The source for TSER 2 is Defined as shown in Table 7.
Bit 4 to 5: DS21Q55 Port 3 TSER Source (T3S0, T3S1)
The source for TSER 3 is Defined as shown in Table 7.
Bit 6 to 7: DS21Q55 Port 4 TSER Source (T4S0, T4S1)
The source for TSER 4 is Defined as shown in Table 7.
Table 7. TSERx Source Definition
TxS1, TxS0
00
01
10
11
TSERX CONNECTION
Tri-state TSERX (weak pulldown)
Drive TSERX with RSERX
Drive TSERX with PCM_TXD bus (DK2000 only)
N/A
Register Name: PRSER
Register Description: PCM RSER Source
Register Offset: 0x0019
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
Bit 0 to 1: PCM RSER Source (R1EN)
0 = Do not drive DS21Q55 Port 1 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 1 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 2 to 3: DS21Q55 Port 2 TSER Source (T2S0, T2S1)
0 = Do not drive DS21Q55 Port 2 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 2 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 4 to 5: DS21Q55 Port 3 TSER Source (T3S0, T3S1)
0 = Do not drive DS21Q55 Port 3 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 3 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 6 to 7: DS21Q55 Port 4 TSER Source (T4S0, T4S1)
0 = Do not drive DS21Q55 Port 4 RSER onto PCM_RSER
1 = Logically OR DS21Q55 Port 4 RSER with selected other RSER pins and drive onto PCM_RSER
Note: PRSER register is for use with the DK2000 only.
12 of 32
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: PSYNC
Register Description: PCM RSYNC/TSYNC Source
Register Offset: 0x001A
Bit #
Name
Default
7
—
—
6
—
—
5
T2SR
0
4
T1SR
0
3
—
—
Bit 0 to 1: PCM_RSYNC Source
R2SR, R1SR
PCM_RSYNC Source
00
PCM_RSYNC is driven by DS21Q55 port 1 RSYNC.
01
PCM_RSYNC is driven by DS21Q55 port 2 RSYNC.
10
PCM_RSYNC is driven by DS21Q55 port 3 RSYNC.
11
PCM_RSYNC is driven by DS21Q55 port 4 RSYNC.
Bit 4 to 5: PCM_TSYNC Source
T2SR, T1SR
PCM_TSYNC Source
00
PCM_TSYNC is driven by DS21Q55 port 1 TSYNC.
01
PCM_TSYNC is driven by DS21Q55 port 2 TSYNC.
10
PCM_TSYNC is driven by DS21Q55 port 3 TSYNC.
11
PCM_TSYNC is driven by DS21Q55 port 4 TSYNC.
Note: PSYNC register is for use with the DK2000 only.
13 of 32
2
—
—
1
R2SR
0
0
R1SR
0
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: PCLK
Register Description: PCM RCLK/TCLK Source
Register Offset: 0x001B
Bit #
Name
Default
7
—
—
6
TCM
0
5
T2SR
0
4
T1SR
0
3
—
—
2
RCM
0
Bit 0 to 2: PCM_RCLK Source
RCM, R2SR, R1SR
PCM_RCLK Source
000
PCM_RCLK is driven by DS21Q55 port 1 RCLK.
001
PCM_RCLK is driven by DS21Q55 port 2 RCLK.
010
PCM_RCLK is driven by DS21Q55 port 3 RCLK.
011
PCM_RCLK is driven by DS21Q55 port 4 RCLK.
100
PCM_RCLK is driven by DS21Q55 port 1 BPCLK.
101
PCM_RCLK is driven by DS21Q55 port 2 BPCLK.
110
PCM_RCLK is driven by DS21Q55 port 3 BPCLK.
111
PCM_RCLK is driven by DS21Q55 port 4 BPCLK.
Bit 4 to 5: PCM_TCLK Source
TCM, T2SR, T1SR
PCM_TCLK Source
000
PCM_TCLK is driven by source used for DS21Q55 port 1 TCLK.
001
PCM_TCLK is driven by source used for DS21Q55 port 2 TCLK.
010
PCM_TCLK is driven by source used for DS21Q55 port 3 TCLK.
011
PCM_TCLK is driven by source used for DS21Q55 port 4 TCLK.
100
PCM_TCLK is driven by DS21Q55 port 1 BPCLK.
101
PCM_TCLK is driven by DS21Q55 port 2 BPCLK.
110
PCM_TCLK is driven by DS21Q55 port 3 BPCLK.
111
PCM_TCLK is driven by DS21Q55 port 4 BPCLK.
Note: PCLK register is for use with the DK2000 only.
14 of 32
1
R2SR
0
0
R1SR
0
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
FPGA CONTROL EXAMPLES
SCENARIO #1: DS21Q55 TO/FROM DK2000
DS21Q55
DK2000
XO
TSER
TCLK
BPCLK
TSYNC
PCM_TXD
RSER
RCLK
BPCLK
RSYNC
PCM_RXD
PCM_TCLK
PCM_TSYNC
PCM_RCLK
PCM_RSYNC
Table 8. FPGA Configuration for Scenario #1 (Port 1, T1 Mode)
REGISTER
SETTING
FUNCTION
MCSR
0X01
Drive DS21Q55 ports 1 and 3 MCLK with 2.048MHz
TCSR
0X00
Drive TCLK with 1.544MHz
SYSCLKT
0X00
Drive TSYSCLK with 1.544MHz
SYSCLKR
0X00
Drive RSYSCLK with 1.544MHz
SYNC1
0X00
Tri-state FPGA driver pin for DS21Q55 TSYNC1
SYNC2
0X01
Drive TSSYNC1 with RSYNC1
SYNC3
0X00
Tri-state FPGA driver pin for DS21Q55 RSYNC
TSERS
0X02
Drive DS21Q55 TSER1 with data from PCM bus
PRSER
0X01
Drive DS21Q55 RSER1 onto PCM bus
PSYNC
0X00
PCM RSYNC and PCM TSYNC are provided by DS21Q55 port 1 RSYNC and
TSYNC (respectively)
PCLK
0X44
PCM RCLK and TCLK are driven by port 1 BPCLK
15 of 32
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
SCENARIO #2: EXTERNAL REMOTE LOOPBACK
(FULL BANDWIDTH, NOT JUST PAYLOAD)
DS21Q55
TSER
TCLK
BPCLK
TSYNC
RSER
RCLK
BPCLK
RSYNC
Table 9. FPGA Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER
SETTING
FUNCTION
MCSR
0X01
Drive DS21Q55 ports 1 and 3 MCLK with 2.048MHz
TCSR
0X02
Drive TCLK1 with RCLK1
SYSCLKT
0X00
Drive TSYSCLK with 1.544MHz
SYSCLKR
0X00
Drive RSYSCLK with 1.544MHz
SYNC1
0X01
Drive TSYNC1 with RSYNC1
SYNC2
0X01
Drive TSSYNC1 with RSYNC1
SYNC3
0X00
Tri-state FPGA driver pin for DS21Q55 RSYNC
TSERS
0X01
Drive DS21Q55 TSER1 with data from RSER1
PRSER
N/A
Unused
PSYNC
N/A
Unused
PCLK
N/A
Unused
Table 10. DS21Q55 Partial Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER
IOCR1
ESCR
CCR1
SETTING
TSIO = 0;
RSIO = 0
TESE = 0;
RESE = 0
TCSS1 = 0;
TCSS2 = 0
FUNCTION
TSYNc is an input, RSYNC is an output
Bypass Rx and Tx elastic stores
TCLK is driven by TCLK pin
16 of 32
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
DS21Q55 INFORMATION
For more information about the DS21Q55, please consult the DS21Q55 data sheet available on our website at
www.maxm-ic.com/DS21Q55. Software downloads are also available for this demo kit.
DS21Q55DK INFORMATION
For more information about the DS21Q55DK, including software downloads, please consult the DS21Q55DK data
sheet available on our website at www.maxim-ic.com/telecom.
TECHNICAL SUPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS21Q55DK schematics are featured in the following pages.
DOCUMENT REVISION HISTORY
REVISION
DATE
121903
DESCRIPTION
Initial DS21Q55DK data sheet release.
012506
Changed part number for CH1 in Component List from “TX1473” to “T8132.”
110106
Updated schematics.
17 of 32
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
6
5
4
3
2
A
8
7
CONTENTS
1.
COVER PAGE
2.
DS21Q55 CONTROL AND BACKPLANE
3.
PORT 1 AND 2 TX / RX SYSTEM SIDE
4.
PORT 3 AND 4 TX / RX SYSTEM SIDE
5.
PORT 1 TX / RX ANALOG PATHS
6.
PORT 2 TX / RX ANALOG PATHS
7.
PORT 3 TX / RX ANALOG PATHS
8.
PORT 4 TX / RX ANALOG PATHS
9.
TIM ADDRESS DATA BUS CONNECTION
10. FPGA CROSS CONNECT FOR RX / TX SIGNALS
11. FPGA AND CONFIG PROM CONTROL
12. FPGA CLOCK AND DATABUS
13. SUPPLY DECOUPLING
14. SIGNAL CROSS-REFERENCE
15. COMPONENT CROSS-REFERENCE
6
5
4
3
ENGINEER:
TITLE:
2
STEVE SCULLY
DS21Q55DK02A1
PAGE:
1
1 / 15
2/24/03
DATE:
A1: 3/7/2003 - REPLACED THE SYMBOL XC2S50E_U WITH SYMBOL XC2S50_U.
REVISIONS:
A
B
D
B
1
C
DS21Q55 DESIGN KIT
7
C
D
8
A
B
C
D
8
TP3
8
1
JTRST
JTMS
JTCLK
JTDI_CON2SCT
R48
JTD_SCT2PROM 1
TP2
1
A0
A1
A2
A3
A4
A5
A6
A7
7
0
WR_RW
RD_DS
CS1
CS2
CS3
CS4
7
A0
A1
A2
A3
A4
A5
A6
A7
L17
V2
T4
V8
H4
U8
P4
JTDO
JTDI
JTCLK
JTMS
JTRST*
RD*
WR*
CS4*
CS3*
CS2*
CS1*
U3
2 V19
N1
Y15
W13
V18
N2
K3
K17
B5
A14
P3
6
DVDD1
CONTROL
5
DS21Q55_U
5
4
4
J3
N4
U2
V5
B12
C12
C16
D18
A9
B3
B6
C4
G20
M17
M20
P18
P1
J17
E4
W18
W2
G19
D11
U19
V3_3
DVDD2
DVDD3
DVDD3
DVDD3
DVDD4
DVDD4
DVDD4
DVDD4
RVDD1
RVDD3
RVDD4
U2
DVDD1
TVSS1
DVDD1
TVSS2
DVDD1
TVSS3
TVSS4
DVDD2
DVSS1
DVDD2
DVSS1
DVSS1
DVDD2
DVSS2
DVDD3
DVSS2
DVSS2
DVSS3
DVSS3
DVSS3
DVSS4
DVSS4
DVSS4
RVSS1
RVDD2
RVSS1
RVSS2
RVSS2
TVDD1
RVSS3
TVDD2
RVSS3
TVDD3
RVSS4
TVDD4
RVSS4
6
W4
G18
C5
U18
H3
U6
W8
A17
A20
B11
A5
B7
B9
H20
L20
N17
R2
T2
H19
J18
D4
D5
V20
W19
NC2
NC1
D7
D6
D5
D4
D3
D2
D1
D0
MUX
LIUC
BTS
INT*
TSTRST
MCLK2
MCLK1
V17
H18
U4
V4
U5
U9
U7
W15
J19
U11
U10
K2
P2
U1
U16
W20
T1
3
3
ENGINEER:
TITLE:
D_AD0
D_AD1
D_AD2
D_AD3
D_AD4
D_AD5
D_AD6
D_AD7
MCLK1
MCLK2
TSTRST
INT
BTS
LIUC
MUX
2
STEVE SCULLY
DS21Q55DK02A1
2
PAGE:
1
2 / 15
2/24/03
DATE:
1
A
B
C
D
A
B
C
D
8
8
ESIBRD
ESIBR0
ESIBR1
TTIP1
TRING1
TCLK1
RTIP1
RRING1
RCLK1
V9
W6
J4
V7
T3
W7
W3
R1
V6
M3
L3
L4
M4
R3
R4
N3
Y11
Y10
Y9
Y2
Y1
ESIBR1
ESIBR0
ESIBRD
TPOSO
TNEGO
TCLKO
TPOSI
TNEGI
TCLKI
RCLKO
RNEGO
RPOSO
RCLKI
RNEGI
RPOSI
RCLK
RRING
RTIP
TCLK
TRING
TTIP
7
TLCLK
TLINK
TSIG
TCHCLK
TCHBLK
TSER
TSYSCLK
TSSYNC
TSYNC
RFSYNC
RSIGF
RSIG
RMSYNC
RSYNC
RSYSCLK
RSER
RCHCLK
RCHBLK
RLCLK
RLINK
BPCLK
RLOS/LOTC
DS21Q55_U
PORT
U2
7
RSER1
RSYSCLK1
RSYNC1
RLOS1
BPCLK1
V3
W5
W10
V10
W1
6
TSYNC1
W12 TSSYNC1
W11 TSYSCLK1
W9
TSER1
V1
K4
K1
L2
L1
G1
H1
J2
J1
M2
F1
G2
M1
H2
6
5
5
4
4
ESIBRD
ESIBR0
ESIBR1
TTIP2
TRING2
TCLK2
RTIP2
RRING2
RCLK2
B17
F18
C13
C19
B20
E18
C20
F19
D19
C14
B15
A16
A15
D13
B14
B13
Y14
Y13
B19
Y4
Y3
3
ENGINEER:
TITLE:
ESIBR1
ESIBR0
2
E20
E19
C18
A18
F20
C17
D20
TSER2
TSYNC2
B18 TSSYNC2
A19 TSYSCLK2
D17
C15
B16
D16
2
STEVE SCULLY
RLOS2
BPCLK2
RSER2
RSYSCLK2
RSYNC2
D12
F17
D15
D14
G17
A12
A13
H17
E17
DS21Q55DK02A1
TLCLK
TLINK
TSIG
TCHCLK
TCHBLK
TSER
TSYSCLK
TSSYNC
TSYNC
RFSYNC
RSIGF
RSIG
RMSYNC
RSYNC
RSYSCLK
RSER
RCHCLK
RCHBLK
RLCLK
RLINK
BPCLK
RLOS/LOTC
DS21Q55_U
PORT
U2
ESIBRD
TPOSO
TNEGO
TCLKO
TPOSI
TNEGI
TCLKI
RCLKO
RNEGO
RPOSO
RCLKI
RNEGI
RPOSI
RCLK
RRING
RTIP
TCLK
TRING
TTIP
3
PAGE:
1
3 / 15
2/24/03
DATE:
1
A
B
C
D
A
B
C
D
8
8
ESIBRD
ESIBR0
ESIBR1
TTIP3
TRING3
TCLK3
RTIP3
RRING3
RCLK3
A6
D7
C3
C9
D9
A7
A8
D8
C8
B4
C2
B1
A4
A1
B2
E3
Y17
Y16
B10
Y6
Y5
7
ESIBR1
ESIBR0
TLCLK
TLINK
TSIG
TCHCLK
TCHBLK
TSER
TSYSCLK
TSSYNC
TSYNC
RFSYNC
RSIGF
RSIG
RMSYNC
RSYNC
RSYSCLK
RSER
RCHCLK
RCHBLK
RLCLK
RLINK
BPCLK
RLOS/LOTC
DS21Q55_U
PORT
U2
ESIBRD
TPOSO
TNEGO
TCLKO
TPOSI
TNEGI
TCLKI
RCLKO
RNEGO
RPOSO
RCLKI
RNEGI
RPOSI
RCLK
RRING
RTIP
TCLK
TRING
TTIP
7
4
R17
P17
V15
M18
Y20
Y19
M19
Y8
Y7
P19
N20
TSER3
6
D6
C6
A10
B8
C11
C10
J20
T20
U13
N19
R19
R20
TSYNC3
D10 TSSYNC3
A11 TSYSCLK3
C7
P20
T17
A2
D2
U17
ESIBRD
ESIBR0
ESIBR1
TTIP4
TRING4
TCLK4
RTIP4
RRING4
RCLK4
C1
5
4
U15
RSER3
RSYSCLK3
RSYNC3
RLOS3
BPCLK3
5
F2
D1
G3
E2
F3
G4
D3
A3
F4
E1
6
3
3
2
STEVE SCULLY
DS21Q55DK02A1
TLCLK
TLINK
TSIG
TCHCLK
TCHBLK
TSER
TSYSCLK
TSSYNC
TSYNC
RFSYNC
RSIGF
RSIG
RMSYNC
RSYNC
RSYSCLK
RSER
RCHCLK
RCHBLK
RLCLK
RLINK
BPCLK
RLOS/LOTC
DS21Q55_U
PORT
ENGINEER:
TITLE:
ESIBR1
ESIBR0
ESIBRD
TPOSO
TNEGO
TCLKO
TPOSI
TNEGI
TCLKI
RCLKO
RNEGO
RPOSO
RCLKI
RNEGI
RPOSI
RCLK
RRING
RTIP
TCLK
TRING
TTIP
U2
2
RLOS4
BPCLK4
TSYNC4
TSSYNC4
T18
T19
L19
L18
U20
N18
TSYSCLK4
K20
TSER4
K19
R18
V14
V16
Y18
W16
RSER4
W14 RSYSCLK4
V12
RSYNC4
W17
U14
Y12
K18
U12
V13
V11
PAGE:
1
4 / 15
2/24/03
DATE:
1
A
B
C
D
A
B
C
8
1
1
RRING1
1
TRING1
RTIP1
1
TTIP1
0
7
R18
0
R19
0
R20
0
2
2
2
2
1
2
2
1UF
C16
2
1
50A
6
6
50A
Z
2
1
R21
R30
1
1
2
0.1UF
Z
16
15
14
13
T1
RCV
T1
XMIT
17
18
20
19
5
5
2
2
0.22UF
C6
0.22UF
C7
1
1
18
15
500A
17
CH1
500A
CH1
20
19
16
13
14
4
Z
Z
4
500A
Z
Z
Z
1
1
Z
500A
1
1
500A
500A
1
Z8
Z7
2
1
Z29
Z24
2
1
1
2
Z15
Z16
Z27
Z20
2
1
61.9
2
2
1
1
2
2
2
2
2
1.25 AMP
F7
1.25 AMP
F8
1.25 AMP
F16
1.25 AMP
F15
3
1
3
5
7
RJ45
2
4
6
8
J10
ENGINEER:
1
CONN_BNC_5PIN
J9
2
STEVE SCULLY
1
1
51.1
R23
CONN_BNC_5PIN
J5
2
DS21Q55DK02A1
A1
A3
A5
A7
RJ45_4PORT
TITLE:
A2
A4
A6
A8
3
2
2
D
7
61.9
C14
8
R31
2
5
2
4
6
3
1
PAGE:
1
5 / 15
2/24/03
DATE:
SW4
DPDT
1
A
B
C
D
A
B
C
8
2
1
RRING2
1
TRING2
RTIP2
1
TTIP2
7
0
R7
0
R8
0
R11
0
2
1
2
2
1
2
R12
2
1UF
C19
2
1
50A
6
6
50A
Z
2
1
D
R29
1
1
2
0.1UF
Z
12
11
9
10
T1
RCV
T1
XMIT
21
22
24
23
5
5
2
2
0.22UF
C5
0.22UF
C8
1
1
22
11
500A
21
CH1
500A
CH1
24
23
12
9
10
4
4
Z
Z
500A
Z
Z
Z
1
1
Z
500A
1
1
500A
500A
2
Z4
Z2
2
1
Z26
Z22
2
1
2
1
Z13
Z14
Z30
Z18
1
2
61.9
1
1
2
1
2
2
2
2
2
1.25 AMP
F5
1.25 AMP
F6
1.25 AMP
F14
1.25 AMP
F13
3
3
2
4
6
8
1
3
5
7
RJ45
ENGINEER:
TITLE:
B2
B4
B6
B8
B1
B3
B5
B7
2
STEVE SCULLY
1
CONN_BNC_5PIN
J8
1
1
51.1
R24
CONN_BNC_5PIN
J4
DS21Q55DK02A1
J10
RJ45_4PORT
2
2
2
7
61.9
C13
8
R34
2
5
2
4
6
3
1
PAGE:
1
6 / 15
2/24/03
DATE:
SW2
DPDT
1
A
B
C
D
A
B
C
8
1
1
RRING3
1
TRING3
RTIP3
1
TTIP3
0
7
R16
0
R17
0
R14
0
2
2
2
2
1
2
R15
2
1UF
C17
2
1
50A
6
6
50A
Z
2
1
D
7
R33
1
1
2
0.1UF
Z
8
7
5
6
T1
RCV
T1
XMIT
25
26
28
27
5
5
2
2
0.22UF
C4
0.22UF
C3
1
1
5
6
26
7
500A
25
8
CH1
500A
CH1
28
27
4
Z
Z
4
500A
Z
500A
Z
1
Z6
Z5
2
1
Z31
Z23
2
1
1
2
Z
1
1
1
Z
500A
1
1
500A
Z11
Z12
2
2
2
2
1.25 AMP
F4
1.25 AMP
F3
1.25 AMP
F12
1.25 AMP
F11
J10
3
1
3
5
7
RJ45
2
4
6
8
ENGINEER:
TITLE:
C2
C4
C6
C8
1
CONN_BNC_5PIN
J7
2
STEVE SCULLY
1
1
51.1
R22
CONN_BNC_5PIN
J3
2
DS21Q55DK02A1
C1
C3
C5
C7
RJ45_4PORT
3
2
2
2
1
2
Z25
Z19
2
1
61.9
2
61.9
C15
8
R32
2
5
2
4
6
3
1
PAGE:
1
7
/15
2/24/03
DATE:
SW3
DPDT
1
A
B
C
D
A
B
C
8
1
1
RRING4
1
TRING4
RTIP4
1
TTIP4
0
R5
0
R6
0
R9
0
7
2
2
2
2
2
1UF
C20
2
1
50A
6
50A
Z
2
1
6
Z3
Z1
R10
2
1
1
2
1
0.1UF
Z
4
3
1
2
T1
RCV
T1
XMIT
29
30
32
31
5
5
2
2
0.22UF
C1
0.22UF
C2
1
1
1
2
30
3
500A
29
4
CH1
500A
CH1
32
31
4
Z
1
2
Z
4
500A
Z
1
Z
1
1
500A
500A
Z
Z
1
500A
Z10
Z9
2
1
2
2
1
Z28
Z17
Z32
Z21
1
2
R36
1
2
1
1
2
2
2
2
2
1.25 AMP
F2
1.25 AMP
F1
1.25 AMP
F10
1.25 AMP
F9
3
1
3
5
7
RJ45
2
4
6
ENGINEER:
TITLE:
D2
D4
D6
8
J10
1
CONN_BNC_5PIN
J6
2
STEVE SCULLY
1
1
51.1
R25
CONN_BNC_5PIN
J2
2
DS21Q55DK02A1
D1
D3
D5
D7
RJ45_4PORT
D8
3
2
2
D
7
61.9
C11
8
R35
61.9
2
5
2
4
6
3
1
PAGE:
1
8 / 15
2/24/03
DATE:
SW1
DPDT
1
A
B
C
D
A
B
C
D
12
11
8
10
9
6
5
8
4
3
7
2
1
CON12P
J13
8
INT
AUX_CLK
CS_T
PCM_RXD
PCM_TXD
PCM_RSYNC
PCM_TSYNC
PCM_TXCLK
PCM_RXCLK
TIM5V
7
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
7
12
10
8
6
4
2
JX
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
J11
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
(TIM LSB)
6
D_AD0
D_AD1
D_AD2
D_AD3
D_AD4
D_AD5
D_AD6
D_AD7
WE_T
CPU_RESET
RW_T
A9
A8
A0
A1
A2
A3
A4
A5
A6
A7
6
5
5
4
4
A15
A14
CLK16384_T
3
12
10
8
6
4
2
J1X
49 50
47 48
45 46
43 44
41 42
39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11
9
7
5
3
1
ENGINEER:
TITLE:
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
A12
A13
17
15
A11
A10
13
11
9
7
5
3
1
J12
TIM5V
V3_3
3
CLK1544_T
2
STEVE SCULLY
DS21Q55DK02A1
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
2
PAGE:
1
9 / 15
2/24/03
DATE:
1
A
B
C
D
A
8
7
6
IO12_4
IO8_4
IO9_4/VREF1_4
IO10_4
IO11_4
124
95
85
74
101
IO1_4
IO2_4
IO3_4/VREF2_4
IO4_4
IO5_4
116 IO7_4
79 IO6_4
75
77
76
78
IO7_5
BANK 7
U1
XC2S50_U
I/O PORT
IO3_5
IO9_7/VREF2_7
113
BANK 5
IO4_5
IO8_7
GCK0
IO8_5/VREF2_5
IO4_7
88
5
IO5_5
IO7_7
B
AUX_CLK
RSER1
TSER1
RCLK1
TCLK1
BPCLK1
RSYSCLK1
TSYSCLK1
RSYNC1
TSYNC1
TSSYNC1
PCM_RXD
PCM_TXD
6
IO6_5
IO6_7
BANK 4
IO12_7/IRDY_7
RSER2
TSER2
RCLK2
TCLK2
BPCLK2
RSYSCLK2
TSYSCLK2
TSYNC2
RSYNC2
IO9_5
IO3_7/VREF1_7
C
7
IO2_7
IO2_5/VREF1_5
IO10_7
IO1_5
IO11_7
D
8
GCK1
134
102
131
140
100
93
96
94
121
91
IO5_7
5
IO3_6/D3
IO2_6
IO1_6/TRDY_6
4
4
IO13_6
IO12_6
IO11_6
IO10_6/VREF2_6
IO9_6
IO8_6
IO7_6
IO6_6
IO5_6
IO4_6/VREF1_6
BANK 6
IO1_7
129
141
136
132
83
84
87
80
86
139
130
133
RSER4
TSER4
RCLK4
TCLK4
BPCLK4
RSYSCLK4
TSYSCLK4
RSYNC4
TSYNC4
TSSYNC4
PCM_RSYNC
PCM_TSYNC
138
99
118
115
137
120
114
103
117
122
123
112
126
3
ENGINEER:
TITLE:
TSSYNC2
RSER3
TSER3
RCLK3
TCLK3
BPCLK3
RSYSCLK3
TSYSCLK3
RSYNC3
TSYNC3
TSSYNC3
PCM_RXCLK
PCM_TXCLK
3
2
STEVE SCULLY
DS21Q55DK02A1
2
PAGE:
1
10/ 15
2/24/03
DATE:
1
A
B
C
D
A
B
10
8
6
4
2
8
10
8
6
4
2
9
7
5
3
1
CONN_10P
J1
4
3
2
V3_3
CE
RESET
CLK
3
VCC
7
GND
CEO
SER_EN
1
DATA
1.0K
1
JTDO_SPART2CON
5 JTDI_CON2SCT
7 JTCLK
9 JTMS
1
CFG_DIN
CCLK
XRST
DONE
U20
AT17LV65
5
6
7
8
1
1
NOPOP
R47
2
NOPOP
R37
2
6
X_INIT
XRST
CCLK
DONE
43
10
13
21
15
5
7
CLK
CF*
5
XC18V02
VQ44C
OE_RESET*
CEO*
CE*
TMS
TCK
TDO
TDI
U3
3
JTD_SCT2PROM
JTD_PROM2SPART 31
V3_3
VCC1
SERIAL EEPROM OPTION - UNPOPULATED
6
VCC2
V3_3
5
D0
D1
D2
D3
D4
D5
D6
D7
V3_3
40
29
42
27
9
25
14
19
1
16
35
36
53
70
71
90
107
108
4
CFG_DIN
VCCO1
VCCO2
VCCO3
VCCO4
VCCO5
VCCO6
VCCO7
VCCO8
VCCO9
VCCO10
VCCO11
V2_5
GND13
3
U1
XC2S50_U
CONTROL
VCCINT2
GND6
127
VCCINT3
GND7
VCCO12
VCCINT4
GND8
144
VCCINT5
GND9
4
VCCINT6
GND10
VCCINT1
GND5
7
VCC3
GND1
C
1.0K
VCCO1
GND2
VCCINT7
GND11
9
14
24
55
82
92
97
125
VCCINT8
GND12
D
1.0K
VCCO2
GND3
8
2
R28
1
2
R27
1
VCCO3
GND4
6
18
28
41
R38
2
17
35
38
8
16
26
36
VCCO4
J2.TDI
GND15
GND14
3
104
105
109
111
106
72
69
37
34
2
32
142
2
XRST
2
470
R13
2
STEVE SCULLY
DS21Q55DK02A1
CONFIG
PROM
TDO
TDI
DONE
1
CCLK
1
J2.TDO
PAGE:
1
11 / 15
2/24/03
DATE:
FPGA
CPU_RESET
JTMS
JTD_PROM2SPART
JTCLK
JTDO_SPART2CON
JTAG CONFIGURATION
NC1
NC2
M0
M1
M2
DONE
TESTPOINT
TDO
TDI
ENGINEER:
TITLE:
DS21Q55
CCLK
TDO
TCK
TDI
TMS
PROGRAM*
GND16
GND4
GND3
GND2
GND1
8
17
25
33
45
52
61
73
81
89
98
110
119
128
135
143
A
B
C
D
A
B
C
8
2
TSTRST
R2
1
1
7
1
2
6
1
1
1
330
R44
330
R43
330
R40
330
R42
330
R46
2
ESIBR1
V3_3
R39
2
ESIBR0
2
2
2
2
R41
2 R45
ESIBRD
R4
R1
1
1
INT
LIUC
1
1
1
1
2
2
RED
2
2
2
1
DS2
2
DS3
RED
1
DS4
RED
1
RED
1
RLOS3_IND
RLOS2_IND
RLOS1_IND
INT_IND
5
RLOS4_IND
DS5
2
DS1
RED
1
CLK1544_T
A0
A1
A2
A3
A4
A5
A6
A7
INT
66
12
42
20
43
56
5
13
63
15
4
IO1_0
IO2_0/VREF1_0
IO3_0
IO4_0
IO5_0
IO6_0
IO7_0/VREF2_0
IO8_0
IO9_0
GCK3
IO1_1/CS*
R3
3
BANK 1
BANK 3
U1
XC2S50_U
I/O PORT
IO9_3
2
IO5_1
IO8_3/D5
JTRST
IO2_1/WRITE*
IO12_3
IO6_1
IO7_3/D6
IO3_1
IO11_3/D4
IO7_1
IO6_3
4
IO4_1/VREF1_1
IO10_3/VREF2_3
IO8_1
IO5_3
BANK 0
IO13_3/TRDY_3
IO9_1/VREF2_1
IO4_3/VREF1_3
ALL UNMARKED BIAS RESISTORS ARE 10K
V3_3
5
D_AD7
D_AD6
D_AD5
D_AD4
D_AD3
D_AD2
D_AD1
D_AD0
INT_IND
MCLK1
MCLK2
IO10_1
IO3_3
6
CLK16384_T
IO11_1
31
30
50
28
47
26
11
27
21
64
23
18
GCK2
IO12_2/DIN/D0
3
ENGINEER:
TITLE:
IO11_2
IO10_2/VREF2_2
IO9_2
IO8_2
IO7_2/D1
IO6_2/D2
IO5_2
IO4_2/VREF1_2
IO3_2/D3
IO2_2
IO1_2/IRDY_2
IO13_2/DOUT/BUSY
IO2_3/D7
A12
A13
A14
A15
RLOS1
RLOS2
RLOS3
RLOS4
RLOS1_IND
RLOS2_IND
RLOS3_IND
RLOS4_IND
7
38
39
19
41
10
59
44
46
40
48
49
3
51
2
STEVE SCULLY
DS21Q55DK02A1
2
R49
BANK 2
IO1_3/INIT*
54
4
57
58
22
60
62
29
7
65
6
67
68
X_INIT
2
1
D
8
RED
2
DS6
1
WE_T
RW_T
CS_T
BTS
MUX
WR_RW
RD_DS
CS1
CS2
CS3
CS4
CFG_DIN
CPU_RESET
330
/
PAGE:
1
12 / 15
2/24/03
DATE:
V3_3
1
A
B
C
D
A
B
C
D
C44
2
1
10UF
C45
8
8
2
1
1UF
C43
2
1
0.1UF
C31
1
2
0.1UF
7
7
C9
1
2
0.1UF
C18
1
2
0.1UF
C40
1
2
6
6
0.1UF
1
C25
2
0.1UF
C22
1
2
0.1UF
5
5
C10
2
1
0.1UF
C30
1
10K
2
1
2
V2_5
0.1UF
R26
1
4
TP
TP
4
3
TP
2
1
2
TP
C21
1
1UF
C39
2
1
1
V3_3
1
4
1
X_INIT
C27
2
0.1UF
1
0.1UF
SHDN
RST
IN
IN
1
GND
SET
OUT
OUT
5
7
6
8
2
U4
MAX1792
C12
2
0.1UF
C32
1
3
3
ENGINEER:
TITLE:
0.1UF
C37
1
C38
2
C29
1
1
2
10UF
2
0.1UF
0.1UF
C33
1
2
1
1UF
1
0.1UF
0.1UF
2
1
1UF
2
2
V2_5
1
C24
1
0.1UF
0.1UF
1
1
0.1UF
0.1UF
1
1
13 / 15
VCC
2/24/03
1
V3_3
PAGE:
2
0.1UF
V3_3
DATE:
1
2
STEVE SCULLY
DS21Q55DK02A1
C34
2
C23
2
C36
2
C28
2
C42
C41
2
C26
C35
2
0.1UF
A
B
C
D
A
B
C
D
7
8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
AUX_CLK
BPCLK1
BPCLK2
BPCLK3
BPCLK4
BTS
CCLK
CFG_DIN
CLK1544_T
CLK16384_T
CPU_RESET
CS1
CS2
CS3
CS4
CS_T
DONE
D_AD0
D_AD1
D_AD2
D_AD3
D_AD4
D_AD5
D_AD6
D_AD7
ESIBR0
ESIBR1
ESIBRD
INT
INT_IND
JTCLK
JTDI_CON2SCT
JTDO_SPART2CON
JTD_PROM2SPART
JTD_SCT2PROM
JTMS
JTRST
LIUC
MCLK1
MCLK2
MUX
PCM_RSYNC
PCM_RXCLK
PCM_RXD
PCM_TSYNC
PCM_TXCLK
PCM_TXD
RCLK1
RCLK2
RCLK3
RCLK4
RD_DS
RLOS1
RLOS1_IND
RLOS2
RLOS2_IND
RLOS3
RLOS3_IND
RLOS4
7
9D6 12C5 2B7<
9C6 12C5 2B7<
9C6 12C5 2B7<
9C6 12C5 2B7<
9C6 12C5 2B7<
9C6 12B5 2A7<
9C6 12B5 2A7<
9C6 12B5 2A7<
9C6
9C6
9C3
9C3
9C3 12A4
9C3 12A4
9B3 12A4
9B3 12A3
9B8 10C7<
3C6> 10C6
3C1> 10D5
4C6> 10C3
4C1> 10A5
12C1 2C3<
11A6< 11B8< 11C1<
11A4> 11B8 12B1
9B2 12C5<
9C4 12D3<
9B6 12B1 11C1<
12B1 2C7<
12B1 2C7<
12B1 2C7<
12B1 2C7<
9B8 12C1
11B8 11A6< 11C1<
2B3 9B6 12D3
2B3 9B6 12D3
2B3 9B6 12D3
2B3 9B6 12D3
2B3 9B6 12D3
2B3 9B6 12D3
2B3 9B6 12D4
2B3 9B6 12D4
3A4 3A8 4A4 4A8 12C6<
3A4 3A8 4A4 4A8 12C6<
3B4 3B8 4A4 4A8 12D6<
2C3> 9B8 12B5 12D6<
12B5 12D3
11A8 2B7< 11C1<
11A8 2B8<
11A7 11C1>
11A6 11D1<
2B8 11A6<
11A8 2B7< 11D1<
2B7 12D8<
2C3< 12D6<
12D3 2C3<
12D3 2C3<
12C1 2B3<
9C8 10A4
9C8 10B3
9C8 10B7
9C8 10A4
9C8 10B3
9C8 10B7
3C8> 10C6
3C4> 10D5
4C8> 10C3
4C4> 10A5
12C1 2C7<
3C6> 12A3
12A3 12A5
3C1> 12A3
12A3 12A5
4C6> 12A3
12A3 12A5
4C1> 12A3
*** Signal Cross-Reference for the entire design ***
8
RLOS4_IND
RRING1
RRING2
RRING3
RRING4
RSER1
RSER2
RSER3
RSER4
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RTIP1
RTIP2
RTIP3
RTIP4
RW_T
TCLK1
TCLK2
TCLK3
TCLK4
TIM5V
TRING1
TRING2
TRING3
TRING4
TSER1
TSER2
TSER3
TSER4
TSSYNC1
TSSYNC2
TSSYNC3
TSSYNC4
TSTRST
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYSCLK1
TSYSCLK2
TSYSCLK3
TSYSCLK4
TTIP1
TTIP2
TTIP3
TTIP4
WE_T
WR_RW
XRST
X_INIT
6
12A3 12A5
3C8< 5B8<
3C4< 6B8<
4C8< 7B8<
4C4< 8B8<
3C6> 10C6
3C1> 10D5
4B6> 10C3
4B1> 10A5
3B6 10B6
3B1 10D4
4B6 10B3
4B1 10A5
10B6 3B6<
10D5 3B1<
10B3 4B6<
10A5 4B1<
3C8< 5B8<
3C4< 6B8<
4C8< 7B8<
4C4< 8B8<
9C6 12C1
10C6 3C8<
10D5 3C4<
10C3 4C8<
10A5 4C4<
9D3 9D8
3C8> 5C8<
3C4> 6C8<
4C8> 7C8<
4C4> 8C8<
10C6 3B6<
10D5 3B1<
10C3 4B6<
10A5 4B1<
10B6 3B6<
10C3 3B1<
10B3 4B6<
10A4 4B1<
2C3< 12D8<
3B6 10B6
3B1 10D5
4B6 10B3
4B1 10A5
10B6 3B6<
10D5 3B1<
10B3 4B6<
10A5 4B1<
3C8> 5C8<
3C4> 6C8<
4C8> 7C8<
4C4> 8C8<
9B6 12C1
12C1 2C7<
11A6> 11B8> 11C2<
11A6 12A3 13D4
6
5
5
4
4
3
PAGE:
ENGINEER:
3
DATE:
TITLE:
2
2
1
1
A
B
C
D
A
B
C
D
7
DS1
DS2
DS3
DS4
DS5
DS6
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
J1
J2
J3
J4
J5
J6
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
CH1
8
7
CAP
8B5
CAP
8C5
CAP
7C5
CAP
7B5
CAP
6B5
CAP
5B5
CAP
5C5
CAP
6C5
CAP
13B7
CAP
13B5
CAP
8A6
CAP
13B4
CAP
6A6
CAP
5A6
CAP
7A6
CAP
5D6
CAP
7D6
CAP
13B7
CAP
6C6
CAP
8C6
CAP
13C4
CAP
13B5
CAP
13B2
CAP
13B2
CAP
13B6
CAP
13B1
CAP
13B4
CAP
13B2
CAP
13B3
CAP
13B5
CAP
13B7
CAP
13B3
CAP
13B2
CAP
13D3
CAP
13B1
CAP
13D2
CAP
13D3
CAP
13B3
CAP
13B4
CAP
13B6
CAP
13B2
CAP
13B2
CAP
13B8
CAP
13B8
CAP
13B8
CHOKE_QUADPORT_T1 5B4 5C4 6B4 6C4 7B4 7C4 8B4
8C4
LED
12B5
LED
12A5
LED
12A5
LED
12A5
LED
12B5
LED
12B2
FUSE
8B4
FUSE
8B4
FUSE
7B4
FUSE
7B4
FUSE
6B3
FUSE
6B3
FUSE
5B4
FUSE
5B4
FUSE
8D4
FUSE
8C4
FUSE
7D4
FUSE
7C4
FUSE
6D3
FUSE
6C3
FUSE
5D4
FUSE
5C4
CONN_10P 11B8
CONN_BNC_5PIN 8B2
CONN_BNC_5PIN 7B2
CONN_BNC_5PIN 6B2
CONN_BNC_5PIN 5B2
CONN_BNC_5PIN 8D2
*** Part Cross-Reference for the entire design ***
8
TP1
TP2
TP3
TP24
TP25
TP26
U1
U2
U3
U4
U20
Z1
Z2
Z3
Z4
J7
J8
J9
J10
J11
J12
J13
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
SW1
SW2
SW3
SW4
T1
6
CONN_BNC_5PIN 7D2
CONN_BNC_5PIN 6D2
CONN_BNC_5PIN 5D2
RJ45_8
5C3 6C3 7C3 8C3
CONN_50P2 9D7
CONN_50P2 9D3
CON12P
9D8
RES1
12D6
RES1
12D7
RES
12D7
RES1
12D6
RES
8B7
RES
8B7
RES
6B7
RES
6B7
RES
8C7
RES
8D7
RES
6C7
RES
6D7
RES
11C2
RES
7C7
RES
7D7
RES
7B7
RES
7B7
RES
5B7
RES
5B7
RES
5C7
RES
5D7
RES
7B2
RES
5B2
RES
6B2
RES
8B2
RES
13D4
RES1
11A7
RES1
11A8
RES1
6A6
RES1
5A6
RES1
5A6
RES1
7A6
RES1
7A6
RES1
6A6
RES1
8A6
RES1
8A6
RES1
11B7
RES1
11A7
RES
12C6
RES1
12A6
RES
12C6
RES1
12A6
RES1
12A6
RES1
12A6
RES
12D6
RES1
12B6
RES1
11A7
RES
2B7
RES1
12B2
SWITCH_DPDT_SLIDE_6P 8C1
SWITCH_DPDT_SLIDE_6P 6C1
SWITCH_DPDT_SLIDE_6P 7C1
SWITCH_DPDT_SLIDE_6P 5C1
XFMR_QUADPORT_T1 5B5 5C5 6B5 6C5 7B5 7C5 8B5
8C5
TSTPNT_SNG 13B3
TESTPOINT 2B8
TESTPOINT 2B8
TSTPNT_SNG 13B4
TSTPNT_SNG 13B4
TSTPNT_SNG 13B4
XC2S50_U 10C5 11C3 12C3
DS21Q55_U 2D7 3C3 3C7 4C3 4C7
XC18V02VQ44C_U 11A6
MAX1792
13D4
AT17LV65 11C7
SIDACTOR_2 8B6
SIDACTOR_2 6B6
SIDACTOR_2 8C6
SIDACTOR_2 6C6
6
5
5
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
Z16
Z17
Z18
Z19
Z20
Z21
Z22
Z23
Z24
Z25
Z26
Z27
Z28
Z29
Z30
Z31
Z32
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
SIDACTOR_2
7B6
7C6
5B6
5C6
8B4
8C4
7C4
7B4
6C4
6B4
5C4
5B4
8A4
6A4
7A4
5A4
8A4
6A4
7A4
5A4
7C4
6C4
5C4
8C4
5C4
6C4
7C4
8C4
4
4
3
PAGE:
ENGINEER:
3
DATE:
TITLE:
2
2
1
1
A
B
C
D
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