DS21Q59
E1 Quad Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS21Q59 E1 quad transceiver contains all the
necessary functions for connecting to four E1 lines.
The DS21Q59 is a direct replacement for the
DS21Q50, with the addition of signaling access and
improved interrupt handling. It is composed of a line
interface unit (LIU), framer, and a TDM backplane
interface, and is controlled through an 8-bit parallel
port configured for Intel or Motorola bus operations or
serial port operation.
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APPLICATIONS
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DSLAMs
Routers
IMA and WAN Equipment
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PIN CONFIGURATION
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TOP VIEW
Dallas
Semiconductor
DS21Q59
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100
Four Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceivers
Pin Compatible with the DS21Q50
Long-Haul and Short-Haul Line Interfaces
32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Frames to FAS, CAS, and CRC4 Formats
CAS/CCS Signaling Support
4MHz/8MHz/16MHz Clock Synthesizer
Flexible System Clock with Automatic Source
Switching on Loss-of-Clock Source
Two-Frame Elastic-Store Slip Buffer on the
Receive Side
Interleaving PCM Bus Operation Up to
16.384MHz
Configurable Parallel and Serial Port Operation
Detects and Generates Remote and AIS Alarms
Fully Independent Transmit and Receive
Functionality
Four Separate Loopback Functions
PRBS Generation/Detection/Error Counting
3.3V Low-Power CMOS
Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits
Eight Additional User-Configurable Output Pins
100-Pin (14mm) LQFP Package
1
LQFP
ORDERING INFORMATION
PART
DS21Q59L
DS21Q59LN
TEMP RANGE
PIN-PACKAGE
0°C to +70°C
100 LQFP
-40°C to +85°C
100 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 76
REV: 090104
DS21Q59 Quad E1 Transceiver
TABLE OF CONTENTS
1.
ACRONYMS .......................................................................................................................6
2.
DETAILED DESCRIPTION.................................................................................................6
3.
BLOCK DIAGRAM .............................................................................................................7
4.
PIN DESCRIPTION.............................................................................................................8
4.1
PIN FUNCTION DESCRIPTIONS ......................................................................................................12
5.
FUNCTIONAL DESCRIPTION .........................................................................................13
6.
HOST INTERFACE PORT................................................................................................14
6.1
PARALLEL PORT OPERATION .......................................................................................................14
6.2
SERIAL PORT OPERATION ............................................................................................................14
7.
REGISTER MAP...............................................................................................................16
8.
CONTROL, ID, AND TEST REGISTERS .........................................................................17
8.1
POWER-UP SEQUENCE ................................................................................................................18
8.2
FRAMER LOOPBACK ....................................................................................................................21
8.3
AUTOMATIC ALARM GENERATION .................................................................................................22
8.4
REMOTE LOOPBACK ....................................................................................................................22
8.5
LOCAL LOOPBACK .......................................................................................................................23
9.
STATUS AND INFORMATION REGISTERS ...................................................................27
9.1
INTERRUPT HANDLING .................................................................................................................28
9.2
CRC4 SYNC COUNTER................................................................................................................29
10.
ERROR COUNT REGISTERS..........................................................................................34
10.1
BPV OR CV COUNTER .............................................................................................................34
10.2
CRC4 ERROR COUNTER ..........................................................................................................34
10.3
E-BIT/PRBS BIT-ERROR COUNTER ..........................................................................................35
10.4
FAS ERROR COUNTER .............................................................................................................35
11.
SIGNALING OPERATION................................................................................................36
11.1
RECEIVE SIGNALING .................................................................................................................36
11.2
TRANSMIT SIGNALING ...............................................................................................................36
11.3
CAS OPERATION .....................................................................................................................36
12.
DS0 MONITORING FUNCTION .......................................................................................37
13.
PRBS GENERATION AND DETECTION.........................................................................39
14.
SYSTEM CLOCK INTERFACE ........................................................................................40
15.
TRANSMIT CLOCK SOURCE..........................................................................................41
16.
IDLE CODE INSERTION ..................................................................................................41
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DS21Q59 Quad E1 Transceiver
17.
PER-CHANNEL LOOPBACK ..........................................................................................42
18.
ELASTIC STORE OPERATION .......................................................................................42
19.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..................................43
20.
USER-CONFIGURABLE OUTPUTS ................................................................................45
21.
LINE INTERFACE UNIT ...................................................................................................47
21.1
21.1.1
RECEIVE CLOCK AND DATA RECOVERY .....................................................................................47
Termination ...........................................................................................................................................47
21.2
TRANSMIT W AVESHAPING AND LINE DRIVING .............................................................................48
21.3
JITTER ATTENUATORS ..............................................................................................................50
21.3.1
Clock and Data Jitter Attenuators .........................................................................................................50
21.3.2
Undedicated Clock Jitter Attenuator .....................................................................................................51
22.
CODE MARK INVERSION (CMI) .....................................................................................52
23.
INTERLEAVED PCM BUS OPERATION .........................................................................54
24.
FUNCTIONAL TIMING DIAGRAMS.................................................................................56
24.1
RECEIVE ..................................................................................................................................56
24.2
TRANSMIT ................................................................................................................................58
25.
OPERATING PARAMETERS...........................................................................................62
26.
AC TIMING PARAMETERS AND DIAGRAMS ................................................................63
26.1
MULTIPLEXED BUS AC CHARACTERISTICS .................................................................................63
26.2
NONMULTIPLEXED BUS AC CHARACTERISTICS ..........................................................................66
26.3
SERIAL PORT ...........................................................................................................................68
26.4
RECEIVE AC CHARACTERISTICS ...............................................................................................69
26.5
TRANSMIT AC CHARACTERISTICS .............................................................................................72
26.6
SPECIAL MODES AC CHARACTERISTICS ....................................................................................74
27.
PACKAGE INFORMATION..............................................................................................75
28.
REVISION HISTORY ........................................................................................................76
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DS21Q59 Quad E1 Transceiver
LIST OF FIGURES
Figure 3-1. Block Diagram ....................................................................................................................... 7
Figure 6-1. Serial Port Operation Mode 1 ...............................................................................................14
Figure 6-2. Serial Port Operation Mode 2 ...............................................................................................15
Figure 6-3. Serial Port Operation Mode 3 ...............................................................................................15
Figure 6-4. Serial Port Operation Mode 4 ...............................................................................................15
Figure 21-1. External Analog Connections (Basic Configuration) ...........................................................48
Figure 21-2. External Analog Connections (Protected Interface) ............................................................49
Figure 21-3. Transmit Waveform Template ............................................................................................50
Figure 21-4. Jitter Tolerance...................................................................................................................51
Figure 21-5. Jitter Attenuation ................................................................................................................51
Figure 22-1. CMI Coding ........................................................................................................................52
Figure 22-2. Example of CMI Code Violation (CV)..................................................................................53
Figure 23-1. IBO Configuration Using Two DS21Q59 Transceivers (Eight E1 Lines)..............................55
Figure 24-1. Receive Frame and Multiframe Timing ...............................................................................56
Figure 24-2. Receive Boundary Timing (With Elastic Store Disabled).....................................................56
Figure 24-3. Receive Boundary Timing (With Elastic Store Enabled) .....................................................56
Figure 24-4. Receive Interleave Bus Operation ......................................................................................57
Figure 24-5. Transmit Frame and Multiframe Timing ..............................................................................58
Figure 24-6. Transmit Boundary Timing..................................................................................................58
Figure 24-7. Transmit Interleave Bus Operation .....................................................................................59
Figure 24-8. Framer Synchronization Flowchart .....................................................................................60
Figure 24-9. Transmit Data Flow ............................................................................................................61
Figure 26-1. Intel Bus Read AC Timing (PBTS = 0)................................................................................64
Figure 26-2. Intel Bus Write Timing (PBTS = 0)......................................................................................64
Figure 26-3. Motorola Bus AC Timing (PBTS = 1) ..................................................................................65
Figure 26-4. Intel Bus Read Timing (PBTS = 0)......................................................................................66
Figure 26-5. Intel Bus Write Timing (PBTS = 0)......................................................................................67
Figure 26-6. Motorola Bus Read Timing (PBTS = 1)...............................................................................67
Figure 26-7. Motorola Bus Write Timing (PBTS = 1)...............................................................................67
Figure 26-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0) ............................................................................68
Figure 26-9. Receive AC Timing (Receive Elastic Store Disabled) .........................................................70
Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled) ........................................................71
Figure 22-11. Transmit AC Timing (IBO Disabled)..................................................................................73
Figure 22-12. Transmit AC Timing (IBO Enabled) ..................................................................................74
Figure 26-13. NRZ Input AC Timing .......................................................................................................74
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DS21Q59 Quad E1 Transceiver
LIST OF TABLES
Table 4-A. Pin Description (Sorted by Function) ...................................................................................... 8
Table 4-B. Pin Assignments (Sorted by Number) ...................................................................................10
Table 4-C. System (Backplane) Interface Pins .......................................................................................12
Table 4-D. Alternate Jitter Attenuator .....................................................................................................12
Table 4-E. Clock Synthesizer .................................................................................................................12
Table 4-F. Parallel Port Control Pins ......................................................................................................12
Table 4-G. Serial Port Control Pins.........................................................................................................13
Table 4-H. Line Interface Pins ................................................................................................................13
Table 4-I. Supply Pins ............................................................................................................................13
Table 6-A. Bus Mode Select ...................................................................................................................14
Table 7-A. Register Map (Sorted by Address) ........................................................................................16
Table 8-A. Sync/Resync Criteria.............................................................................................................19
Table 8-B. G.703 Function......................................................................................................................24
Table 8-C. Output Modes .......................................................................................................................25
Table 9-A. Alarm Criteria ........................................................................................................................29
Table 13-A. Transmit PRBS Mode Select...............................................................................................39
Table 13-B. Receive PRBS Mode Select................................................................................................39
Table 14-A. Synthesizer Output Select ...................................................................................................40
Table 14-B. System Clock Selection.......................................................................................................40
Table 20-A. OUTA and OUTB Function Select .......................................................................................46
Table 21-A. Line Build-Out Select in LICR..............................................................................................48
Table 21-B. Transformer Specifications..................................................................................................48
Table 23-A. IBO System Clock Select ....................................................................................................54
Table 23-B. IBO Device Assignment ......................................................................................................54
Table 26-A. AC Characteristics—Multiplexed Parallel Port .....................................................................63
Table 26-B. AC Characteristics—Nonmultiplexed Parallel Port ..............................................................66
Table 26-C. AC Characteristics—Serial Port (BTS1 = 1, BTS0 = 0) .......................................................68
Table 26-D. AC Characteristics—Receiver.............................................................................................69
Table 26-E. AC Characteristics—Transmit .............................................................................................72
Table 26-F. AC Characteristics—Special Modes ....................................................................................74
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DS21Q59 Quad E1 Transceiver
1. ACRONYMS
The following abbreviations are used throughout this data sheet:
FAS
CAS
MF
Si
CRC4
CCS
Sa
E-Bit
LOC
TCLK
RCLK
Frame Alignment Signal
Channel Associated Signaling
Multiframe
International Bits
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error Bits
Loss of Clock
This generally refers to the transmit rate clock and can reference an actual input signal to the
device (TCLK) or an internally derived signal used for transmission.
This generally refers to the recovered network clock and can be a reference to an actual output
signal from the device or an internal signal.
2. DETAILED DESCRIPTION
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface
generates the necessary waveshapes for driving the network, depending on the type of media used. E1 waveform
generation includes G.703 waveshapes for both 75W coax and 120W twisted cables. The receive interface recovers
clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal. The jitter
attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator only
requires a 2.048MHz MCLK and can be placed in either the transmit or receive data paths. An additional feature of
the LIU is a code mark inversion (CMI) coder/decoder for interfacing to optical networks.
On the transmit side, the backplane interface section provides clock/data and frame-sync signals to the framer. The
framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC
codes, and provides the HDB3 (zero code suppression) and alternate mark inversion (AMI) line coding. The
receive-side framer decodes AMI and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.
The backplane interface provides a versatile method of sending and receiving data from the host system. The
receive elastic store provides a method for interfacing to asynchronous systems. The elastic store also manages
slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow multiple E1 lines to
share a high-speed backplane.
The parallel port provides access for control and configuration of all the DS21Q59’s features. Diagnostic
capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code
generation and detection. The device fully meets all the latest E1 specifications, including ITU-T G.703, G.704,
G.706, G.823, G.732 and I.431 ETS 300 011, ETS 300 233, and ETS 300 166 as well as CTR12 and CTR4.
The DS21Q59 is optimized for high-density termination of E1 lines. Two significant features are included for this
type of application: the IBO and a system clock synthesizer feature. The IBO allows up to eight E1 data streams to
be multiplexed onto a single high-speed PCM bus without additional external logic. The system clock synthesizer
allows any of the E1 lines to be selected as the master source of the clock for the system and for all the
transmitters. This is also accomplished without the need of external logic. Each of the four transceivers has a clock
and data jitter attenuator that can be assigned to either the transmit or receive path. In addition there is a single,
undedicated clock jitter attenuator that can be hardware configured as needed by the user. Each transceiver also
contains a PRBS pattern generator and detector. Figure 23-1 shows a simplified typical application that terminates
eight E1 lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The
16.384MHz system clock is derived and phase-locked to one of the eight E1 lines. On the receive side of each port,
an elastic store provides logical management of any slip conditions due to the asynchronous relationship of the
eight E1 lines. In this application all eight transmitters are timed to the selected E1 line.
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DS21Q59 Quad E1 Transceiver
3. BLOCK DIAGRAM
Figure 3-1. Block Diagram
MCLK
OUTA1
OUTB1
USER OUTPUT
SELECT
VCO/PLL
REMOTE LOOPBACK
RECEIVE-SIDE
FRAMER
SYNC
CONTROL
DATA
CLOCK
SYNC
TRANSMITSIDE
FORMATTER
DIVIDEBY-2/4/8
A
B
TCLK1
LOTC
TRANSMIT
CLOCK SOURCE
BACKUP CLOCK MUX
TRANSCEIVERS 2, 3, 4
SYSTEM CLOCK
INTERFACE
RCLK TRANSCEIVER 2
RCLK TRANSCEIVER 3
RCLK TRANSCEIVER 4
MUX
PARALLEL AND TEST CONTROL PORT
(ROUTED TO ALL BLOCKS)
ALTERNATE
JITTER
ATTENUATOR
REFCLK
4/8/16MHz
AJACKI
AJACOI
INT
D0–D7/
AD0–AD7
SYNTHESIZER
BTS0
TS1
TS0
WR(R/W)
RD(DS)
ALE(AS)/A5
A0–A4
Tx Ck
MUX
DETECT
TRANSCEIVER 1 OF 4
CS
PBTS
BTS1
TSER1
IBO
BUFFER
A
BU Ck
B
MUX
C
Dallas
Semiconductor
DS21Q59
TSYNC1
7 of 76
2.048MHz
TTIP1
RSER1
SYSCLK1
RSYNC1
ELASTIC
STORE AND
IBO BUFFER
DATA
CLOCK
SYNC
FRAMER LOOPBACK
TRING1
LINE I/F
TRANSMIT
TRANSMIT
SIDE
EITHER TRANSMIT OR RECEIVE PATH
JITTER ATTENUATOR
RTIP1
LOCAL LOOPBACK
RRING1
RECOVERY
CLOCK/DATA
LINE I/F
RECEIVE
RECEIVE
SIDE
4/8/16MCK
DS21Q59 Quad E1 Transceiver
4. PIN DESCRIPTION
Table 4-A. Pin Description (Sorted by Function)
NAME
PIN
71
45
46
47
48
49
70
69
50
96
97
98
19
20
21
22
23
24
25
44
84
59
34
9
83
58
33
8
94
73
61
36
11
86
60
35
10
85
95
75
72
67
42
17
92
63
38
13
88
64
39
14
PARALLEL
PORT ENABLED
4/8/16MCK
A0
A1
A2
A3
A4
AJACKI
AJACKO
ALE (AS)/A5
BTS0
BTS1
CS
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
DVDD1
DVDD2
DVDD3
DVDD4
DVSS1
DVSS2
DVSS3
DVSS4
INT
MCLK
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
PBTS
RD (DS)
REFCLK
RRING1
RRING2
RRING3
RRING4
RSER1
RSER2
RSER3
RSER4
RSYNC1
RSYNC2
RSYNC3
SERIAL PORT
ENABLED
—
ICES
OCES
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLK
—
—
—
—
—
—
—
—
—
—
—
—
FUNCTION
[SERIAL PORT MODE IN BRACKETS]
TYPE
O
I
I
I
I
I
I
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
O
I
O
O
O
O
O
O
O
O
I
I
I/O
I
I
I
I
O
O
O
O
I/O
I/O
I/O
4.096MHz, 8.192MHz, or 16.384MHz Clock
Address Bus Bit 0/Serial Port [Input-Clock Edge Select]
Address Bus Bit 1/Serial Port [Output-Clock Edge Select]
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Alternate Jitter Attenuator Clock Input
Alternate Jitter Attenuator Clock Output
Address Latch Enable/Address Bus Bit 5
Bus Type Select 0
Bus Type Select 1
Chip Select
Data Bus Bit 0/Address/Data Bus Bit 0
Data Bus Bit 1/Address/Data Bus Bit 1
Data Bus Bit 2/Address/Data Bus Bit 2
Data Bus Bit 3/Address/Data Bus Bit 3
Data Bus Bit 4/Address/Data Bus Bit 4
Data Bus Bit 5/Address/Data Bus Bit 5
Data Bus Bit 6/Address/Data Bus Bit 6
Data Bus Bit 7/Address/Data Bus Bit 7 [Serial Data Output]
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Interrupt
Master Clock Input
User-Selectable Output A
User-Selectable Output A
User-Selectable Output A
User-Selectable Output A
User-Selectable Output B
User-Selectable Output B
User-Selectable Output B
User-Selectable Output B
Parallel Bus Type Select
Read Input (Data Strobe) [Serial Port Clock]
Reference Clock
Receive Analog Ring Input
Receive Analog Ring Input
Receive Analog Ring Input
Receive Analog Ring Input
Receive Serial Data
Receive Serial Data
Receive Serial Data
Receive Serial Data
Receive Sync
Receive Sync
Receive Sync
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DS21Q59 Quad E1 Transceiver
NAME
PIN
89
66
41
16
91
93
68
43
18
90
65
40
15
62
37
12
87
80
55
30
5
79
54
29
4
99
100
81
56
31
6
82
57
32
7
76
51
26
1
78
53
28
3
77
52
27
2
74
PARALLEL
PORT ENABLED
RSYNC4
RTIP1
RTIP2
RTIP3
RTIP4
RVDD1
RVDD2
RVDD3
RVDD4
RVSS1
RVSS2
RVSS3
RVSS4
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
TCLK1
TCLK2
TCLK3
TCLK4
TRING1
TRING2
TRING3
TRING4
TS0
TS1
TSER1
TSER2
TSER3
TSER4
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TTIP1
TTIP2
TTIP3
TTIP4
TVDD1
TVDD2
TVDD3
TVDD4
TVSS1
TVSS2
TVSS3
TVSS4
WR (R/W)
SERIAL PORT
ENABLED
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI
FUNCTION
[SERIAL PORT MODE IN BRACKETS]
TYPE
I/O
I
I
I
I
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
O
O
O
O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
O
O
O
O
—
—
—
—
—
—
—
—
I
Receive Sync
Receive Analog Tip Input
Receive Analog Tip Input
Receive Analog Tip Input
Receive Analog Tip Input
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Transmit/Receive System Clock
Transmit/Receive System Clock
Transmit/Receive System Clock
Transmit/Receive System Clock
Transmit Clock
Transmit Clock
Transmit Clock
Transmit Clock
Transmit Analog Ring Output
Transmit Analog Ring Output
Transmit Analog Ring Output
Transmit Analog Ring Output
Transceiver Select 0
Transceiver Select 1
Transmit Serial Data
Transmit Serial Data
Transmit Serial Data
Transmit Serial Data
Transmit Sync
Transmit Sync
Transmit Sync
Transmit Sync
Transmit Analog Tip Output
Transmit Analog Tip Output
Transmit Analog Tip Output
Transmit Analog Tip Output
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Write Input (Read/Write) [Serial Data Input]
Note: EQVSS lines are wired to RVSS lines.
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DS21Q59 Quad E1 Transceiver
Table 4-B. Pin Assignments (Sorted by Number)
NAME
PIN
PARALLEL
PORT ENABLED
SERIAL PORT
ENABLED
TYPE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
TTIP4
TVSS4
TVDD4
TRING4
TCLK4
TSER4
TSYNC4
DVSS4
DVDD4
OUTB3
OUTA3
SYSCLK3
RSER3
RSYNC3
RVSS4
RTIP3
RRING3
RVDD4
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
TTIP3
TVSS3
TVDD3
TRING3
TCLK3
TSER3
TSYNC3
DVSS3
DVDD3
OUTB2
OUTA2
SYSCLK2
RSER2
RSYNC2
RVSS3
RTIP2
RRING2
RVDD3
D7/AD7
A0
A1
A2
A3
A4
ALE (AS)/A5
TTIP2
TVSS2
TVDD2
TRING2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDO
ICES
OCES
—
—
—
—
—
—
—
—
O
—
—
O
I
I
I/O
—
—
O
O
I
O
I/O
—
I
I
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
—
—
O
I
I
I/O
—
—
O
O
I
O
I/O
—
I
I
—
I/O
I
I
I
I
I
I
O
—
—
O
FUNCTION
[Serial Port Mode in Brackets]
Transmit Analog Tip Output
Transmit Analog Signal Ground
Transmit Analog Positive Supply
Transmit Analog Ring Output
Transmit Clock
Transmit Serial Data
Transmit Sync
Digital Signal Ground
Digital Positive Supply
User-Selectable Output B
User-Selectable Output A
Transmit/Receive System Clock
Receive Serial Data
Receive Sync
Receive Analog Signal Ground
Receive Analog Tip Input
Receive Analog Ring Input
Receive Analog Positive Supply
Data Bus Bit 0/Address/Data Bus Bit 0
Data Bus Bit 1/Address/Data Bus Bit 1
Data Bus Bit 2/Address/Data Bus Bit 2
Data Bus Bit 3/Address/Data Bus Bit 3
Data Bus Bit 4/Address/Data Bus Bit 4
Data Bus Bit 5/Address/Data Bus Bit 5
Data Bus Bit 6/Address/Data Bus Bit 6
Transmit Analog Tip Output
Transmit Analog Signal Ground
Transmit Analog Positive Supply
Transmit Analog Ring Output
Transmit Clock
Transmit Serial Data
Transmit Sync
Digital Signal Ground
Digital Positive Supply
User-Selectable Output B
User-Selectable Output A
Transmit/Receive System Clock
Receive Serial Data
Receive Sync
Receive Analog Signal Ground
Receive Analog Tip Input
Receive Analog Ring Input
Receive Analog Positive Supply
Data Bus Bit 7/Address/Data Bus Bit 7 [Serial Data Output]
Address Bus Bit 0/Serial Port [Input-Clock Edge Select]
Address Bus Bit 1/Serial Port [Output-Clock Edge Select]
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Address Latch Enable/Address Bus Bit 5
Transmit Analog Tip Output
Transmit Analog Signal Ground
Transmit Analog Positive Supply
Transmit Analog Ring Output
10 of 76
DS21Q59 Quad E1 Transceiver
NAME
PIN
PARALLEL
PORT ENABLED
SERIAL PORT
ENABLED
TYPE
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TCLK2
TSER2
TSYNC2
DVSS2
DVDD2
OUTB1
OUTA1
SYSCLK1
RSER1
RSYNC1
RVSS2
RTIP1
RRING1
RVDD2
AJACKO
AJACKI
4/8/16MCK
REFCLK
MCLK
WR (R/W)
RD (DS)
TTIP1
TVSS1
TVDD1
TRING1
TCLK1
TSER1
TSYNC1
DVSS1
DVDD1
OUTB4
OUTA4
SYSCLK4
RSER4
RSYNC4
RVSS1
RTIP4
RRING4
RVDD1
INT
PBTS
BTS0
BTS1
CS
TS0
TS1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI
SCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I/O
—
—
O
O
I
O
I/O
—
I
I
—
O
I
O
I/O
I
I
I
O
—
—
O
I
I
I/O
—
—
O
O
I
O
I/O
—
I
I
—
O
I
—
—
I
I
I
FUNCTION
[Serial Port Mode in Brackets]
Transmit Clock
Transmit Serial Data
Transmit Sync
Digital Signal Ground
Digital Positive Supply
User-Selectable Output B
User-Selectable Output A
Transmit/Receive System Clock
Receive Serial Data
Receive Sync
Receive Analog Signal Ground
Receive Analog Tip Input
Receive Analog Ring Input
Receive Analog Positive Supply
Alternate Jitter Attenuator Clock Output
Alternate Jitter Attenuator Clock Input
4.096MHz, 8.192MHz, or 16.384MHz Clock
Reference Clock
Master Clock Input
Write Input (Read/Write) [Serial Data Input]
Read Input (Data Strobe) [Serial Port Clock]
Transmit Analog Tip Output
Transmit Analog Signal Ground
Transmit Analog Positive Supply
Transmit Analog Ring Output
Transmit Clock
Transmit Serial Data
Transmit Sync
Digital Signal Ground
Digital Positive Supply
User-Selectable Output B
User-Selectable Output A
Transmit/Receive System Clock
Receive Serial Data
Receive Sync
Receive Analog Signal Ground
Receive Analog Tip Input
Receive Analog Ring Input
Receive Analog Positive Supply
Interrupt
Parallel Bus Type Select
Bus Type Select 0
Bus Type Select 1
Chip Select
Transceiver Select 0
Transceiver Select 1
Note: EQVSS lines are wired to RVSS.
11 of 76
DS21Q59 Quad E1 Transceiver
4.1
Pin Function Descriptions
Table 4-C. System (Backplane) Interface Pins
NAME
TYPE
TCLK
I
TSER
I
TSYNC
I/O
RSER
O
RSYNC
I/O
SYSCLK
I
OUTA
O
OUTB
O
FUNCTION
Transmit Clock. TCLK is a 2.048MHz primary clock that is used to clock data through the transmit
formatter.
Transmit Serial Data. Transmit NRZ serial data. TSER is sampled on the falling edge of TCLK when
IBO disabled. It is sampled on the falling edge of SYSCLK when the IBO function is enabled.
Transmit Sync. As an input, pulse at this pin establishes either frame or multiframe boundaries for the
transmitter. As an output, it can be programmed to output either a frame or multiframe pulse.
Receive Serial Data. RSER is the received NRZ serial data. RSER is updated on the rising edges of
RCLK when the receive elastic store is disabled. It is updated on the rising edges of SYSCLK when the
receive elastic store is enabled.
Receive Sync. An extracted pulse one RCLK wide is output at this pin that identifies either frame or
CAS/CRC4 multiframe boundaries. If the receive elastic store is enabled, this pin can be enabled to be
an input at which a frame-boundary pulse synchronous with SYSCLK is applied.
System Clock. SYSCLK is a 2.048MHz clock used to clock data out of the receive elastic store. When
the IBO is enabled SYSCLK can be a 4.096MHz, 8.192MHz, or 16.384MHz clock.
User-Selectable Output A. OUTA is a multifunction pin the host can program to output various alarms,
clocks, or data, or be used to control external circuitry.
User-Selectable Output B. OUTB is a multifunction pin the host can program to output various alarms,
clocks, or data, or be used to control external circuitry.
Table 4-D. Alternate Jitter Attenuator
NAME
TYPE
AJACKI
AJACKO
I
O
FUNCTION
Alternate Jitter Attenuator Clock Input. AJACKI is clock input to the alternate jitter attenuator.
Alternate Jitter Attenuator Clock Output. AJACKO is clock output of the alternate jitter attenuator.
Table 4-E. Clock Synthesizer
NAME
TYPE
4/8/16MCK
O
REFCLK
I/O
FUNCTION
4.096MHz/8.192MHz/16.384MHz Clock Output. 4/8/16MCK is a 4.096MHz, 8.192MHz, or 16.384MHz
clock output that is referenced to one of the four recovered line clocks (RCLKs) or to an external
2.048MHz reference.
Reference Clock. REFCLK can be configured as an output to source a 2.048MHz reference clock or as
an input to supply a 2.048MHz reference clock from an external source to the clock synthesizer.
Table 4-F. Parallel Port Control Pins
NAME
TYPE
INT
O
BTS0
I
BTS1
I
TS0
TS1
PBTS
I
I
I
AD0 to
AD7/SDO
I/O
A0 to A4
I
RD (DS)/SCLK
I
CS
I
ALE (AS)/A5
I
WR (R/W)/SDI
I
FUNCTION
Interrupt. INT flags the host controller during conditions and change of conditions defined in status
registers 1 and 2 and the HDLC status register. It is an active-low, open-drain output.
Bus Type Select Bit 0. BTS0 is used with BTS1 to select between muxed, nonmuxed, serial bus
operation, and output high-Z mode.
Bus Type Select Bit 1. BTS1 is used with BTS0 to select between muxed, nonmuxed, serial bus
operation, and output high-Z mode.
Transceiver Select Bit 0. TS0 is used with TS1 to select one of four transceivers.
Transceiver Select Bit 1. TS1 is used with TS0 to select one of four transceivers.
Parallel Bus Type Select. PBTS is used to select between Motorola and Intel parallel bus types.
Data Bus or Address/Data Bus [D0 to D6], Data Bus or Address/Data Bus [D7]/Serial Port Output.
In nonmultiplexed bus operation (MUX = 0), these pins serve as the data bus. In multiplexed bus
operation (MUX = 1), they serve as an 8-bit multiplexed address/data bus.
Address Bus. In nonmultiplexed bus operation, these pins serve as the address bus. In multiplexed bus
operation, these pins are not used and should be wired low.
Read Input—Data Strobe/Serial Port Clock. RD and DS are active-low signals. DS is active high when
in multiplexed mode (Section 26).
Chip Select. CS must be low to read or write to the device. It is an active-low signal.
Address Latch Enable (Address Strobe) or A6. In nonmultiplexed bus operation, this pin serves as the
upper address bit. In multiplexed bus operation, it demultiplexes the bus on a positive-going edge.
Write Input (Read/Write)/Serial Port Data Input, Active Low
12 of 76
DS21Q59 Quad E1 Transceiver
Table 4-G. Serial Port Control Pins
NAME
TYPE
SDO
O
Serial Port Data Output. Data at this output can be updated on the rising or falling edge of SCLK.
FUNCTION
SDI
ICES
OCES
SCLK
I
I
I
I
Serial Port Data Input. Data at this input can be sampled on the rising or falling edge of SCLK.
Input Clock-Edge Select. ICES is used to select which SCLK clock edge samples data at SDI.
Output Clock-Edge Select. OCES is used to select which SCLK clock edge updates data at SDO.
Serial Port Clock. SCLK is used to clock data into and out of the serial port.
Table 4-H. Line Interface Pins
NAME
TYPE
MCLK
I
RTIP and
RRING
TTIP and
TRING
I
O
FUNCTION
Master Clock Input. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is
used internally for both clock/data recovery and for jitter attenuation.
Receive Tip and Ring. RTIP and RRING are analog inputs for clock recovery circuitry. These pins connect
through a 1:1 step-up transformer to the E1 line. See Section 21 for details.
Transmit Tip and Ring. TTIP and TRING are analog line-driver outputs. These pins connect through a 1:2
step-up transformer to the E1 line. See Section 21 for details.
Table 4-I. Supply Pins
NAME
TYPE
DVDD
RVDD
TVDD
DVSS
RVSS
TVSS
Supply
Supply
Supply
Supply
Supply
Supply
FUNCTION
Digital Positive Supply. 3.3V ±5%. Should be wired to the RVDD and TVDD pins.
Receive Analog Positive Supply. 3.3V ±5%. Should be wired to the DVDD and TVDD pins.
Transmit Analog Positive Supply. 3.3V ±5%. Should be wired to the RVDD and DVDD pins.
Digital Signal Ground. 0V. Should be wired to the RVSS and TVSS pins.
Receive Analog Signal Ground. 0V. Should be wired to DVSS and TVSS.
Transmit Analog Signal Ground. 0V. Should be wired to DVSS and RVSS.
5. FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the DS21Q59’s RRING and RTIP pins.
The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the
receive framer, where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS21Q59
contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in
transmission. The device has a usable receive sensitivity of 0dB to -43dB, which allows the device to operate on
cables over 2km in length. The receive framer locates FAS frame and CRC and CAS multiframe boundaries as well
as detects incoming alarms including carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the
receive elastic store can be enabled to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock, which is provided at the SYSCLK input. The clock applied at
the SYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The transmit framer is
independent of the receive framer in both the clock requirements and characteristics. The transmit formatter
provides the necessary frame/multiframe data overhead for E1 transmission.
Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125ms frame,
there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots
are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1, time slot
1 is identical to channel 2, and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8.
Bit number 1, MSB, is transmitted first. Bit number 8, the LSB, is transmitted last. The term “locked” is used to refer
to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., an 8.192MHz
clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
13 of 76
DS21Q59 Quad E1 Transceiver
6. HOST INTERFACE PORT
The DS21Q59 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an
external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing
configurations. See Table 6-A for a description of the bus configurations. Motorola bus signals are listed in
parentheses (). See the timing diagrams in the AC Electrical Characteristics in Section 26 for more details.
Table 6-A. Bus Mode Select
PBTS
0
0
1
1
X
X
6.1
BTS1
0
0
0
0
1
1
BTS0
0
1
0
1
0
1
PARALLEL PORT MODE
Intel Multiplexed
Intel Nonmultiplexed
Motorola Multiplexed
Motorola Nonmultiplexed
Serial
TEST (Outputs High-Z)
Parallel Port Operation
When using the parallel interface on the DS21Q59 (BTS1 = 0) the user has the option for either multiplexed bus
operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q59 can operate
with either Intel or Motorola bus timing configurations. If the PBTS pin is wired low, Intel timing is selected; if wired
high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
Section 26 for more details.
6.2
Serial Port Operation
Setting the BTS1 pin = 1 and BTS0 pin = 0 enables the serial bus interface on the DS21Q59. Port read/write timing
is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See
Section 26 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 6-1, Figure 6-2,
Figure 6-3, and Figure 6-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next five bits identify the register address. The next bit is reserved and must be set to 0 for proper
operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The burst mode
causes all registers to be consecutively written or read.
All data transfers are initiated by driving the CS input low. When input-clock edge select (ICES) is low, input data is
latched on the rising edge of SCLK; when ICES is high, input data is latched on the falling edge of SCLK. When
output-clock edge select (OCES) is low, data is output on the falling edge of SCLK; when OCES is high, data is
output on the rising edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated
if the CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Figure 6-1. Serial Port Operation Mode 1
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)
OCES = 1 (UPDATE SDO ON THE RISING EDGE OF SCLK)
SCLK
1
2
3
4
5
6
7
A0
A1
A2
A3
A4
A5
8
9
10
11
12
13
14
15
D0
D1
D2
D3
D4
D5
D6
16
CS
SDI
R/W
LSB
SDO
B
MSB
LSB
14 of 76
D7
MSB
DS21Q59 Quad E1 Transceiver
Figure 6-2. Serial Port Operation Mode 2
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)
OCES = 0 (UPDATE SDO ON THE FALLING EDGE OF SCLK)
SCLK
1
2
3
4
5
6
7
8
A0
A1
A2
A3
A4
A5
9
10
11
12
13
14
15
16
CS
SDI
R/W
B
LSB
MSB
SDO
D0
D1
D2
D3
D4
D5
D6
D7
LSB
MSB
Figure 6-3. Serial Port Operation Mode 3
ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK)
OCES = 0 (UPDATE SDO ON THE FALLING EDGE OF SCLK)
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SDI
A0
R/W
A1
A2
A3
A4
B
A5
LSB
MSB
SDO
D0
D1
D2
D3
D4
D5
D6
D7
MSB
LSB
Figure 6-4. Serial Port Operation Mode 4
ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK)
OCES = 1 (UPDATE SDO ON THE RISING EDGE OF SCLK)
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D0
D1
D2
D3
D4
D5
D6
16
CS
SDI
R/W
LSB
SDO
A0
A1
A2
A3
A4
A5
B
MSB
LSB
15 of 76
D7
MSB
DS21Q59 Quad E1 Transceiver
7. REGISTER MAP
Table 7-A. Register Map (Sorted by Address)
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
R/W
R
R
R
R
R
R
R
R
R/W
R
R/W
R/W
—
—
—
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NAME
VCR1
VCR2
CRCCR1
CRCCR2
EBCR1
EBCR2
FASCR1
FASCR2
RIR
SSR
SR1
SR2
—
—
—
IDR
RCR
TCR
CCR1
CCR2
CCR3
CCR4
CCR5
LICR
IMR1
IMR2
OUTAC
OUTBC
IBO
SCICR
TEST3 (set to 00h)
CCR7
TAF
TNAF
TDS0M
TIDR
TIR1
TIR2
TIR3
TIR4
RAF
RNAF
RDS0M
PCLB1
PCLB2
PCLB3
PCLB4
CCR6
SA1
SA2
SA3
SA4
SA5
SA6
SA7
FUNCTION
BPV or Code Violation Count 1
BPV or Code Violation Count 2
CRC4 Error Count 1
CRC4 Error Count 2
E-Bit Count 1/PRBS Error Count 1
E-Bit Count 2/PRBS Error Count 2
FAS Error Count 1
FAS Error Count 2
Receive Information
Synchronizer Status
Status 1
Status 2
Unused
Unused
Unused
Device ID (Note 1)
Receive Control
Transmit Control 1
Common Control 1
Common Control 2
Common Control 3
Common Control 4
Common Control 5
Line Interface Control Register
Interrupt Mask 1
Interrupt Mask 2
Output A Control
Output B Control
Interleave Bus Operation Register
System Clock-Interface Control Register (Note 1)
Test 2 (Note 2)
Common Control 7
Transmit Align Frame
Transmit Nonalign Frame
Transmit DS0 Monitor
Transmit Idle Definition
Transmit Idle 1
Transmit Idle 2
Transmit Idle 3
Transmit Idle 4
Receive Align Frame
Receive Nonalign Frame
Receive DS0 Monitor
Per-Channel Loopback Control 1
Per-Channel Loopback Control 2
Per-Channel Loopback Control 3
Per-Channel Loopback Control 4
Common Control 6
Signaling Access Register 1
Signaling Access Register 2
Signaling Access Register 3
Signaling Access Register 4
Signaling Access Register 5
Signaling Access Register 6
Signaling Access Register 7
16 of 76
DS21Q59 Quad E1 Transceiver
ADDRESS
37
38
39
3A
3B
3C
3D
3E
3F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NAME
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
FUNCTION
Signaling Access Register 8
Signaling Access Register 9
Signaling Access Register 10
Signaling Access Register 11
Signaling Access Register 12
Signaling Access Register 13
Signaling Access Register 14
Signaling Access Register 15
Signaling Access Register 16
Note 1: The device ID register and the system clock-interface control register exist in Transceiver 1 only (TS0, TS1 = 0).
Note 2: Only the factory uses the test register; this register must be cleared (set to all zeros) on power-up initialization to ensure proper
operation.
8. CONTROL, ID, AND TEST REGISTERS
The DS21Q59 operation is configured through a set of nine control registers. Typically, registers are only accessed
when the system is first powered up. Once the device has been initialized, the control registers only need to be
accessed when there is a change in the system configuration. There is one receive control register (RCR), one
transmit control register (TCR), and seven common control registers (CCR1 to CCR7). Each of these registers is
described in this section.
Address 0Fh has a device identification register (IDR). The four MSBs of this read-only register are fixed to 1 0 0 1,
indicating that a DS21Q59 E1 quad transceiver is present. The lower 4 bits of the IDR are used to identify the
revision of the device. This register exists in Transceiver 1 only (TS0, TS1 = 0).
The factory in testing the DS21Q59 uses the test register at addresses 1E. On power-up, the test register should
be set to 00h for the DS21Q59 to properly operate.
Register Name:
Register Description:
Register Address:
Bit #
Name
NAME
1
0
0
1
ID3
ID2
ID1
ID0
7
1
IDR
Device Identification Register
0F Hex
6
0
BIT
7
6
5
4
3
1
2
0
5
0
4
1
3
ID3
2
ID2
1
ID1
0
ID0
FUNCTION
Bit 7
Bit 6
Bit 5
Bit 4
Chip Revision Bit 3. MSB of a decimal code that represents the chip revision.
Chip Revision Bit 2
Chip Revision Bit 1
Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
17 of 76
DS21Q59 Quad E1 Transceiver
8.1
Power-Up Sequence
On power-up and after the supplies are stable, the DS21Q59 should be configured for operation by writing to all the
internal registers (this includes setting the test register to 00h) since the contents of the internal registers cannot be
predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry. (It
takes the device about 40ms to recover from the LIRST bit being toggled.) After the SYSCLK input is stable, the
ESR bits (CCR4.5 and CCR4.6) should be toggled from 0 to 1 (this step can be skipped if the elastic store is
disabled).
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RSMF
NAME
BIT
RSMF
7
RSM
6
RSIO
5
RESE
4
—
3
FRC
2
SYNCE
1
RESYNC
0
RCR
Receive Control Register
10 Hex
6
RSM
5
RSIO
4
RESE
3
—
2
FRC
1
SYNCE
0
RESYNC
FUNCTION
RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the
multiframe mode (RCR.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries.
1 = RSYNC outputs CRC4 multiframe boundaries.
RSYNC Mode Select
0 = frame mode (see the timing diagrams in Section 24.1)
1 = multiframe mode (see the timing diagrams in Section 24.1)
RSYNC I/O Select. (Note: This bit must be set to 0 when RCR .4 = 0.)
0 = RSYNC is an output (depends on RCR.6)
1 = RSYNC is an input (only valid if elastic store enabled)
Receive Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
Unused. Should be set = 0 for proper operation.
Frame Resync Criteria
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
Sync Enable
0 = auto resync enabled
1 = auto resync disabled
Resync. When toggled from low to high, a resync is initiated. Must be cleared and
set again for a subsequent resync.
18 of 76
DS21Q59 Quad E1 Transceiver
Table 8-A. Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
FAS
CRC4
CAS
SYNC CRITERIA
FAS present in frame N and N + 2,
and FAS not present in frame N + 1
Two valid MF alignment words found
within 8ms
Valid MF alignment word found and
previous time slot 16 contains code
other than all zeros
Register Name:
Register Description:
Register Address:
Bit #
Name
RESYNC CRITERIA
7
IFSS
NAME
BIT
IFSS
7
TFPT
6
AEBE
5
TUA1
4
TSiS
3
TSA1
2
TSM
1
TSIO
0
ITU SPEC.
Three consecutive incorrect FAS received;
alternate (RCR1.2 = 1): if the above criteria
is met or three consecutive incorrect bit 2 of
non-FAS received
915 or more CRC4 codewords out of 1000
received in error
Two consecutive MF alignment words
received in error
G.706
4.1.1
4.1.2
G.706
4.2 and 4.3.2
G.732 5.2
TCR
Transmit Control Register
11 Hex
6
TFPT
5
AEBE
4
TUA1
3
TSiS
2
TSA1
1
TSM
0
TSIO
FUNCTION
Internal Frame-Sync Select
0 = TSYNC normal
1 = if TSYNC is in the INPUT mode (TSIO = 0), then TSYNC is internally
replaced by the recovered receive frame sync. The TSYNC pin is ignored
1 = if TSYNC is in the OUTPUT mode (TSIO = 1), then TSYNC outputs the
recovered multiframe frame sync
Transmit Time Slot 0 Pass Through
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF
registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
Automatic E-Bit Enable
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
Transmit Unframed All Ones
0 = transmit data normally
1 = transmit an unframed all-ones code
Transmit International Bit Select
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (In this mode, TCR.6 must be
set to 0)
Transmit Signaling All Ones
0 = normal operation
1 = force time slot 16 in every frame to all ones
TSYNC Mode Select
0 = frame mode (see the timing diagrams in Section 24.2)
1 = CAS and CRC4 multiframe mode (see the timing diagrams in Section 24.2)
TSYNC I/O Select
0 = TSYNC is an input
1 = TSYNC is an output
Note: See Figure 24-9 for more details about how the transmit control register affects DS21Q59 operation.
19 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
FLB
CCR1
Common Control Register 1
12 Hex
6
THDB3
NAME
BIT
FLB
7
THDB3
6
TIBE
5
TCRC4
4
RSMS
3
RHDB3
2
PCLMS
1
RCRC4
0
5
TIBE
4
TCRC4
3
RSMS
2
RHDB3
1
PCLMS
0
RCRC4
FUNCTION
Framer Loopback. See Section 8.2 for details.
0 = loopback disabled
1 = loopback enabled
Transmit HDB3 Enable
0 = HDB3 disabled
1 = HDB3 enabled
Transmit Insert Bit Error. A 0-to-1 transition causes a single bit error to be
inserted in the transmit path.
Transmit CRC4 Enable
0 = CRC4 disabled
1 = CRC4 enabled
Receive Signaling Mode Select
0 = CAS signaling mode. Receiver searches for the CAS MF alignment
signal.
1 = CCS signaling mode. Receiver does not search for the CAS MF
alignment signal.
Receive HDB3 Enable
0 = HDB3 disabled
1 = HDB3 enabled
Per-Channel Loopback Mode Select. See Section 17 for details.
0 = remote per-channel loopback
1 = local per-channel loopback
Receive CRC4 Enable
0 = CRC4 disabled
1 = CRC4 enabled
20 of 76
DS21Q59 Quad E1 Transceiver
8.2
Framer Loopback
When CCR1.7 is set to 1, the DS21Q59 enters a framer loopback (FLB) mode (Figure 3-1). This loopback is useful
in testing and debugging applications. In FLB mode, the SCT loops data from the transmitter back to the receiver.
When FLB is enabled, the following occurs:
1) Data is transmitted as normal at TPOSO and TNEGO.
2) Data input through RPOSI and RNEGI is ignored.
3) The RCLK output is replaced with the TCLK input.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
ECUS
NAME
BIT
ECUS
7
VCRFS
6
AAIS
5
ARA
4
RSERC
3
LOTCMC
2
RCLA
1
TCSS
0
CCR2
Common Control Register 2
13 Hex
6
VCRFS
5
AAIS
4
ARA
3
RSERC
2
LOTCMC
1
RCLA
0
TCSS
FUNCTION
Error Counter Update Select. See Section 10 for details.
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
VCR Function Select. See Section 10 for details.
0 = count bipolar violations (BPVs)
1 = count code violations (CVs)
Automatic AIS Generation
0 = disabled
1 = enabled
Automatic Remote Alarm Generation
0 = disabled
1 = enabled
RSER Control
0 = allow RSER to output data as received under all conditions
1 = force RSER to 1 under loss-of-frame alignment conditions
Loss-of-Transmit Clock Mux Control. Determines whether the transmit
formatter should switch to the ever present RCLK if the TCLK should fail to
transition.
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
Receive Carrier Loss (RCL) Alternate Criteria
0 = RCL declared upon 255 consecutive 0s (125ms)
1 = RCL declared upon 2048 consecutive 0s (1ms)
Transmit Clock Source Select. This function allows the user to internally
select RCLK as the clock source for the transmit formatter.
0 = source of transmit clock is determined by CCR2.2 (LOTCMC)
1 = forces transmitter to internally switch to RCLK as source of transmit clock;
signal at TCLK pin is ignored
21 of 76
DS21Q59 Quad E1 Transceiver
8.3
Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is
enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are
present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal).
If one (or more) of these conditions is present, the framer forces an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the receiver is monitored to determine if any of the
following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-ofreceive carrier (or signal), or if CRC4 multiframe synchronization cannot be found within 128ms of FAS
synchronization (if CRC4 is enabled). If one (or more) of these conditions is present, the device transmits an RAI
alarm. RAI generation conforms to ETS 300 011 specifications, and a constant remote alarm is transmitted if the
DS21Q59 cannot find CRC4 multiframe synchronization within 400ms as per G.706.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RLB
6
LLB
NAME
BIT
RLB
7
LLB
6
LIAIS
5
TCM4
4
TCM3
TCM2
TCM1
TCM0
3
2
1
0
8.4
CCR3
Common Control Register
14 Hex
5
LIAIS
4
TCM4
3
TCM3
2
TCM2
1
TCM1
0
TCM0
FUNCTION
Remote Loopback. See Section 8.4 for details.
0 = loopback disabled
1 = loopback enabled
Local Loopback. See Section 8.5 for details.
0 = loopback disabled
1 = loopback enabled
Line Interface AIS-Generation Enable
0 = allow normal data to be transmitted at TTIP and TRING
1 = force unframed all ones to be transmitted at TTIP and TRING at the
MCLK rate
Transmit Channel Monitor Bit 4. MSB of a channel decode that
determines which transmit channel data appears in the TDS0M register.
See Section 10 or details.
Transmit Channel Monitor Bit 3
Transmit Channel Monitor Bit 2
Transmit Channel Monitor Bit 1
Transmit Channel Monitor Bit 0. LSB of the channel decode.
Remote Loopback
When CCR4.7 is set to 1, the DS21Q59 is forced into remote loopback (RLB) mode. In this loopback, data input
through the RPOSI and RNEGI pins is transmitted back to the TPOSO and TNEGO pins. Data continues to pass
through the DS21Q59’s receive framer as it would normally and the data from the transmit formatter is ignored
(Figure 3-1).
22 of 76
DS21Q59 Quad E1 Transceiver
8.5
Local Loopback
When CCR4.6 is set to 1, the DS21Q59 is forced into local loopback (LLB) mode. In this loopback, data continues
to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data being transmitted.
Data in this loopback passes through the jitter attenuator (Figure 3-1).
Register Name:
Register Description:
Register Address:
Bit #
Name
7
LIRST
NAME
BIT
LIRST
7
RESA
6
RESR
5
RCM4
4
RCM3
RCM2
RCM1
RCM0
3
2
1
0
CCR4
Common Control Register 4
15 Hex
6
RESA
5
RESR
4
RCM4
3
RCM3
2
RCM2
1
RCM1
0
RCM0
FUNCTION
Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset
that affects the clock recovery state machine and jitter attenuator.
Normally this bit is only toggled on power-up. It must be cleared and set
again for a subsequent reset.
Receive Elastic Store Align. Setting this bit from 0 to 1 may force the
receive elastic store’s write/read pointers to a minimum separation of half
a frame. No action is taken if the pointer separation is already greater
than or equal to half a frame. If pointer separation is less than half a
frame, the command is executed and data is disrupted. This bit should be
toggled after SYSCLK has been applied and is stable. It must be cleared
and set again for a subsequent align. See Section 18 for details.
Receive Elastic Store Reset. Setting this bit from 0 to 1 forces the
receive elastic store to a depth of one frame. Receive data is lost during
the reset. The bit should be toggled after SYSCLK has been applied and
is stable. It must be cleared and set again for a subsequent reset. See
Section 18 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data appears in the RDS0M register.
See Section 10 for details.
Receive Channel Monitor Bit 3
Receive Channel Monitor Bit 2
Receive Channel Monitor Bit 1
Receive Channel Monitor Bit 0. LSB of the channel decode.
23 of 76
DS21Q59 Quad E1 Transceiver
CCR5
Common Control Register 5
16 Hex
Register Name:
Register Description:
Register Address:
Bit #
Name
7
LIUODO
NAME
BIT
LIUODO
7
CDIG
6
LIUSI
5
IRTSEL
4
TPRBS1
TPRBS0
RPRBS1
RPRBS0
3
2
1
0
6
CDIG
5
LIUSI
4
IRTSEL
3
TPRBS1
2
TPRBS0
1
RPRBS1
0
RPRBS0
FUNCTION
Line Interface Open-Drain Option. This control bit determines whether or not the
TTIP and TRING outputs are open drain. The line driver outputs can be forced
open drain to allow 6VPEAK pulses to be generated or to allow the creation of a very
low power interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
Customer Disconnect Indication Generator. This control bit determines whether
the line interface generates an unframed ...1010... pattern at TTIP and TRING
instead of the normal data pattern.
0 = generate normal data at TTIP and TRING
1 = generate a ...1010... pattern at TTIP and TRING
Line Interface G.703 Synchronization Interface Enable. This control bit works
with CCR7.0 to select G.703 functionality on the transmitter and receiver (Table
8-B). These bits determine whether the line receiver and transmitter should
receive/transmit a normal E1 signal (Section 6 of G.703) or a 2.048MHz
synchronization signal (Section 10 of G.703).
Receive Termination Select. This function applies internal parallel resistance to
the normal 120W external termination to create a 75W termination.
0 = normal 120W external termination
1 = internally adjust receive termination to 75W
Transmit PRBS Mode Bit 1
Transmit PRBS Mode Bit 0
Receive PRBS Mode Bit 1
Receive PRBS Mode Bit 0
Table 8-B. G.703 Function
LIUSI
(CCR5.5)
TG703
(CCR7.0)
0
0
Transmit and receive function normally
0
1
Transmit G.703 signal, receiver functions normally
1
0
Transmit and receive G.703 signal
1
1
Receive G.703, transmitter functions normally
FUNCTION
24 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
OTM1
CCR6
Common Control Register 6
2F Hex
6
OTM0
5
SRAS
4
LTC/SC
3
T16S
2
—
1
—
0
RESET
NAME
OTM1
OTM0
BIT
7
6
SRAS
5
LTC/SC
4
T16S
3
—
2
FUNCTION
Output Test Mode 1 (Table 8-C)
Output Test Mode 0 (Table 8-C)
Signaling Read Access Select. This bit controls the function of registers
SA1 through SA16 when reading.
0 = reading SA1–SA16 accesses receive signaling data
1 = reading SA1–SA16 accesses transmit signaling data
Loss-of-Transmit Clock/Signaling Change-of-State Select. This bit
determines how the status register bit at SR2.2 operates.
0 = SR2.2 indicates loss-of-transmit clock
1 = SR2.2 indicates signaling data has changed states since the last
multiframe
Time Slot 16 Select. Transmit signaling insertion enable.
0 = signaling is not inserted into the transmit path from SA1–SA16
1 = signaling is inserted into the transmit path from SA1–SA16
Unused. Should be set = 0 for proper operation.
—
1
Unused. Should be set = 0 for proper operation.
RESET
0
Reset. A low-to-high transition of this bit resets all register bits to 0.
Table 8-C. Output Modes
OTM1
OTM0
OUTPUTS
0
0
Normal Operation
0
1
Outputs in Tri-State
1
0
Outputs Low
1
1
Outputs High
25 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit:
Name:
7
—
CCR7
Common Control Register 7
1F Hex
6
—
NAME
—
—
—
—
BIT
7
6
5
4
136S
3
ALB
2
—
1
TG703
0
5
—
4
—
3
136S
2
ALB
1
—
0
TG703
FUNCTION
Unused. Should be set = 0 for proper operation.
Unused. Should be set = 0 for proper operation.
Unused. Should be set = 0 for proper operation.
Unused. Should be set = 0 for proper operation.
1:1.36 Transformer Select
0 = 1:2 transmit transformer
1 = 1:1.36 or 1:1.6 transmit transformer (see table below for details)
Analog Loopback. Setting this bit internally connects TTIP and TRING to
RTIP and RRING. The external signal at the RTIP and RRING pins is
ignored.
Unused. Should be set = 0 for proper operation.
Transmit G.703. This control bit works with CCR5.5 to select G.703
functionality on the transmitter and receiver (Table 8-B). These bits
determine whether the line receiver and transmitter should receive/
transmit a normal E1 signal (Section 6 of G.703) or a 2.048MHz
synchronization signal (Section 10 of G.703).
136S
L2
L1
L0
APPLICATION
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75W
120W
75W
120W
N.M.
N.M.
N.M.
N.M.
TRANSFORMER
1:1.6
Rt = 0W
Rt = 0W
Rt = 2.7W
Rt = 3.3W
N.M.
N.M.
N.M.
N.M.
N.M. = Not meaningful
26 of 76
TRANSFORMER
1:1.36
N.M.
N.M.
Rt = 0W
Rt = 0W
N.M.
N.M.
N.M.
N.M.
DS21Q59 Quad E1 Transceiver
9. STATUS AND INFORMATION REGISTERS
The DS21Q59 has a set of four registers that contain information about a framer’s real-time status. The registers
include status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status
register (SSR).
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers is set to 1.
All the bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are not latched,
which means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, the bit remains set until
the user reads that bit. The bit is cleared when it is read and is not set again until the event has occurred again (or,
in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit remains set if the alarm is still present).
The user always precedes a read of the SR1, SR2, and RIR registers with a write. The byte written to the register
informs the framer which bits the user wishes to read and have cleared. The user writes a byte to one of these
registers with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to
obtain the latest information on. When a 1 is written to a bit location, the read register updates with the latest
information. When a 0 is written to a bit position, the read register does not update and the previous value is held.
A write to the status and information registers is immediately followed by a read of the same register. The read
result should be logically ANDed with the mask byte that was just written, and this value should be written back into
the same register to ensure the bit clears. This second write step is necessary because the alarms and events in
the status registers occur asynchronously in respect to their access through the parallel port. This write-read-write
scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the
other bits in the register. This operation is key in controlling the DS21Q59 with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and reports the status of the
synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a
write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt through the INT output pin. Each
of the alarms and events in SR1 and SR2 can be either masked or unmasked from the interrupt pin through
interrupt mask register 1 (IMR1) and interrupt mask register 2 (IMR2).
The interrupts caused by alarms in SR1 (RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused
by events in SR1 and SR2 (RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, and RCMF). The alarmcaused interrupts force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 9-A). The INT pin is allowed to return high (if no other interrupts are
present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present.
The event-based interrupts force the INT pin low when the event occurs. The INT pin returns high () when the user
reads the event bit that caused the interrupt to occur. Furthermore, some event-based interrupts occur continuously
as long as the event is occurring (RSLIP, SEC, TMF, RMF, TAF, RAF, RCMF). Other event-based interrupts force
the INT pin low only once when the event is first detected (LOTC, PRSBD, RDMA, RSA1, RSA0), that is, the
PRBSD interrupt fires once when the receiver detects the PRBS pattern. If the receiver continues to receive the
PRBS pattern, no more interrupts are fired. If the receiver then detects that PRBS is no longer being sent, it resets
and, when it receives the PRBS pattern again, another interrupt is fired.
27 of 76
DS21Q59 Quad E1 Transceiver
9.1
Interrupt Handling
The host can quickly determine which status registers in the four ports are causing an interrupt by reading one of
the unused addresses such as 0Ch, 0Dh, or 0Eh in any port.
Bit #
Name
7
SR2P4
NAME
BIT
SR2P4
7
SR1P4
6
SR2P3
5
SR1P3
4
SR2P2
3
SR1P2
2
SR2P1
1
SR1P1
0
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RGM1
NAME
RGM1
RGM0
BIT
7
6
JALT
5
RESF
4
RESE
3
CRCRC
2
FASRC
1
CASRC
0
6
SR1P4
5
SR2P3
4
SR1P3
3
SR2P2
RGM0
0
1
0
1
1
SR2P1
0
SR1P1
FUNCTION
Status Register 2, Port 4. A 1 in this bit position indicates that status register 2
in port 4 is asserting an interrupt.
Status Register 1, Port 4. A 1 in this bit position indicates that status register 1
in port 4 is asserting an interrupt.
Status Register 2, Port 3. A 1 in this bit position indicates that status register 2
in port 3 is asserting an interrupt.
Status Register 1, Port 3. A 1 in this bit position indicates that status register 1
in port 3 is asserting an interrupt.
Status Register 2, Port 2. A 1 in this bit position indicates that status register 2
in port 2 is asserting an interrupt.
Status Register 1, Port 2. A 1 in this bit position indicates that status register 1
in port 2 is asserting an interrupt.
Status Register 2, Port 1. A 1 in this bit position indicates that status register 2
in port 1 is asserting an interrupt.
Status Register 1, Port 1. A 1 in this bit position indicates that status register 1
in port 1 is asserting an interrupt.
RIR
Receive Information Register
08 Hex
6
RGM0
5
JALT
4
RESF
3
RESE
2
CRCRC
1
FASRC
0
CASRC
FUNCTION
Receive Gain Monitor Bit 1. See table below for level indication.
Receive Gain Monitor Bit 0. See table below for level indication.
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to
within 4 bits of its limit; useful for debugging jitter attenuation operation.
Receive Elastic Store Full. Set when the receive elastic store buffer fills and a
frame is deleted.
Receive Elastic Store Empty. Set when the receive elastic store buffer
empties and a frame is repeated.
CRC Resync Criteria Met. Set when 915/1000 codewords are received in
error.
FAS Resync Criteria Met. Set when three consecutive FAS words are
received in error.
CAS Resync Criteria Met. Set when two consecutive CAS MF alignment
words are received in error.
Level Indication
RGM1
0
0
1
1
2
SR1P2
LEVEL (dB)
0 to 10
10 to 20
20 to 30
>30
28 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
CSC5
NAME
CSC5
CSC4
CSC3
CSC2
BIT
7
6
5
4
CSC0
3
FASSA
2
CASSA
1
CRC4SA
0
9.2
SSR
Synchronizer Status Register
09 Hex
6
CSC4
5
CSC3
4
CSC2
3
CSC0
2
FASSA
1
CASSA
0
CRC4SA
FUNCTION
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CRC4 Sync Counter Bit 4
CRC4 Sync Counter Bit 3
CRC4 Sync Counter Bit 2
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter bit 1 is not
accessible.
FAS Sync Active. Set while the synchronizer is searching for alignment at the
FAS level.
CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF
alignment word.
CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4
MF alignment word.
CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared
when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by
disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4
level cannot be obtained within 400ms, the search should be abandoned and proper action taken. The CRC4 sync
counter rolls over.
Table 9-A. Alarm Criteria
ALARM
RSA1
(Receive Signaling
All Ones)
RSA0
(Receive Signaling
All Zeros)
RDMA
(Receive Distant
Multiframe Alarm)
RUA1
(Receive Unframed
All Ones)
RRA
(Receive Remote
Alarm)
RCL
(Receive Carrier
Loss)
SET CRITERIA
Over 16 consecutive frames (one full
MF) time slot 16 contains less than three
zeros
Over 16 consecutive frames (one full
MF) time slot 16 contains all zeros
CLEAR CRITERIA
Over 16 consecutive frames (one full
MF) time slot 16 contains three or more
zeros
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single one
ITU SPEC
G.732
4.2
G.732
5.2
Bit 6 in time slot 16 of frame 0 set to one
for two consecutive MF
Bit 6 in time slot 16 of frame 0 set to
zero for two consecutive MF
O.162
2.1.5
Fewer than three zeros in two frames
(512 bits)
More than two zeros in two frames (512
bits)
O.162
1.6.1.2
Bit 3 of nonalign frame set to one for
three consecutive occasions
Bit 3 of nonalign frame set to zero for
three consecutive occasions
O.162
2.1.4
255 (or 2048) consecutive zeros
received
In 255-bit times at least 32 ones are
received
G.775/
G.962
29 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RSA1
NAME
BIT
RSA1
7
RDMA
6
RSA0
5
RSLIP
4
RUA1
3
RRA
2
RCL
1
RLOS
0
SR1
Status Register 1
0A Hex
6
RDMA
5
RSA0
4
RSLIP
3
RUA1
2
RRA
1
RCL
0
RLOS
FUNCTION
Receive Signaling All Ones. Set when the contents of time slot 16 contains fewer
than three zeros over 16 consecutive frames. This alarm is not disabled in the
CCS signaling mode. Both RSA1 and RSA0 are set if a change in signaling is
detected.
Receive Distant MF Alarm. Set when bit 6 of time slot 16 in frame 0 has been set
for two consecutive multiframes. This alarm is not disabled in the CCS signaling
mode.
Receive Signaling All Zeros. Set when over a full MF, time slot 16 contains all
zeros. Both RSA1 and RSA0 are set if a change in signaling is detected.
Receive Elastic Store Slip. Set when the elastic store has either repeated or
deleted a frame of data.
Receive Unframed All Ones. Set when an unframed all-ones code is received at
RPOSI and RNEGI.
Receive Remote Alarm. Set when a remote alarm is received at RPOSI and
RNEGI.
Receive Carrier Loss. Set when 255 (or 2048 if CCR2.1 = 1) consecutive zeros
have been detected at RTIP and RRING. (Note: A receiver carrier loss based on
data received at RPOSI and RNEGI is available in the HSR register.)
Receive Loss of Sync. Set when the device is not synchronized to the receive E1
stream.
30 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RSA1
NAME
BIT
RSA1
7
RDMA
6
RSA0
5
RSLIP
4
RUA1
3
RRA
2
RCL
1
RLOS
0
IMR1
Interrupt Mask Register 1
18 Hex
6
RDMA
5
RSA0
4
RSLIP
3
RUA1
FUNCTION
Receive Signaling All Ones
0 = interrupt masked
1 = interrupt enabled
Receive Distant MF Alarm
0 = interrupt masked
1 = interrupt enabled
Receive Signaling All Zeros
0 = interrupt masked
1 = interrupt enabled
Receive Elastic Store Slip Occurrence
0 = interrupt masked
1 = interrupt enabled
Receive Unframed All Ones
0 = interrupt masked
1 = interrupt enabled
Receive Remote Alarm
0 = interrupt masked
1 = interrupt enabled
Receive Carrier Loss
0 = interrupt masked
1 = interrupt enabled
Receive Loss of Sync
0 = interrupt masked
1 = interrupt enabled
31 of 76
2
RRA
1
RCL
0
RLOS
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RMF
NAME
BIT
RMF
7
RAF
6
TMF
5
SEC
4
TAF
3
LOTC
2
RCMF
1
PRBSD
0
SR2
Status Register 2
0B Hex
6
RAF
5
TMF
4
SEC
3
TAF
2
LOTC
1
RCMF
0
PRBSD
FUNCTION
Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is
enabled or not) on receive multiframe boundaries.
Receive Align Frame. Set every 250µs at the beginning of align frames.
Used to alert the host that Si and Sa bits are available in the RAF and
RNAF registers.
Transmit Multiframe. Set every 2ms (regardless if CRC4 is enabled) on
transmit multiframe boundaries.
One-Second Timer. Set on increments of one second based on RCLK. If
CCR2.7 = 1, this bit is set every 62.5ms instead of once a second.
Transmit Align Frame. Set every 250µs at the beginning of align frames.
Used to alert the host that the TAF and TNAF registers need to be
updated.
Loss-of-Transmit Clock. Set when the TCLK pin has not transitioned for
one channel time (or 3.9ms).
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries;
continues to be set every 2ms on an arbitrary boundary if CRC4 is
disabled.
Pseudorandom Bit-Sequence Detect. When receive PRBS is enabled,
15
this bit is set when the 2 - 1 PRBS pattern is detected at RPOS and
RNEG. The PRBS pattern can be framed, unframed, or in a specific time
slot.
32 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RMF
IMR2
Interrupt Mask Register 2
19 Hex
6
RAF
NAME
BIT
RMF
7
RAF
6
TMF
5
SEC
4
TAF
3
LOTC
2
RCMF
1
PRBSD
0
5
TMF
4
SEC
3
TAF
FUNCTION
Receive CAS Multiframe
0 = interrupt masked
1 = interrupt enabled
Receive Align Frame
0 = interrupt masked
1 = interrupt enabled
Transmit Multiframe
0 = interrupt masked
1 = interrupt enabled
One-Second Timer
0 = interrupt masked
1 = interrupt enabled
Transmit Align Frame
0 = interrupt masked
1 = interrupt enabled
Loss-of-Transmit Clock
0 = interrupt masked
1 = interrupt enabled
Receive CRC4 Multiframe
0 = interrupt masked
1 = interrupt enabled
Pseudorandom Bit-Sequence Detect
0 = interrupt masked
1 = interrupt enabled
33 of 76
2
LOTC
1
RCMF
0
PRBSD
DS21Q59 Quad E1 Transceiver
10.
ERROR COUNT REGISTERS
Each DS21Q59 transceiver contains a set of four counters that record bipolar (BPVs) or code violations (CVs),
errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The E-bit
counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four
counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.7 = 1)
as determined by the timer in status register 2 (SR2.4). Hence, these registers contain performance data from
either the previous second or the previous 62.5ms. The user can use the interrupt from the one-second timer to
determine when to read these registers. The user has a full second (or 62.5ms) to read the counters before the
data is lost. The counters saturate at their respective maximum counts and do not roll over.
10.1 BPV or CV Counter
Violation count register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit
counter that records either BPVs or CVs. If CCR2.6 = 0, the VCR counts BPVs. BPVs are defined as consecutive
marks of the same polarity. In this mode, if the HDB3 mode is set for the receiver through CCR1.2, then HDB3
codewords are not counted as BPVs. If CCR2.6 = 1, the VCR counts CVs as defined in ITU O.161. CVs are
defined as consecutive BPVs of the same polarity. In most applications, the framer should be programmed to count
BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times
and is not disabled by loss-of-sync conditions. The counter saturates at 65,535 and does not roll over. The bit-error
-2
rate on an E1 line would have to be greater than 10 before the VCR would saturate.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
V15
V7
NAME
V15
V0
VCR1, VCR2
Bipolar Violation Count Registers
00 Hex, 01 Hex
6
V14
V6
BIT
VCR1.7
VCR2.0
5
V13
V5
4
V12
V4
3
V11
V3
2
V10
V2
1
V9
V1
0
V8
V0
FUNCTION
MSB of the 16-bit code violation count.
LSB of the 16-bit code violation count.
10.2 CRC4 Error Counter
CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit
counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 count in a
one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the
FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. CRCCR1 and
CRCCR2 have an alternate function.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
CRC15
CRC7
NAME
CRC15
CRC0
CRCCR1, CRCCR2
CRC4 Count Registers
02 Hex, 03 Hex
6
CRC14
CRC6
BIT
CRCCR1.7
CRCCR2.0
5
CRC13
CRC5
4
CRC12
CRC4
3
CRC11
CRC/3
2
CRC10
CRC2
FUNCTION
MSB of the 16-bit CRC4 error count.
LSB of the 16-bit CRC4 error count.
34 of 76
1
CRC9
CRC1
0
CRC8
CRC0
DS21Q59 Quad E1 Transceiver
10.3 E-Bit/PRBS Bit-Error Counter
E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit
counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running
with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since
the maximum E-bit count in a one-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the
CAS level.
Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function is enabled.
In this mode, the counter is active when the receive PRBS detector can synchronize to the PRBS pattern. This
pattern can be framed, unframed, or in any time slot. See Section 13 for more details.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
EB15
EB7
NAME
EB15
EB0
EBCR1, EBCR2
E-Bit Count Registers
04 Hex, 05 Hex
6
EB14
EB6
BIT
EBCR1.7
EBCR2.0
5
EB13
EB5
4
EB12
EB4
3
EB11
EB3
2
EB10
EB2
1
EB9
EB1
0
EB8
EB0
FUNCTION
MSB of the 16-bit E-bit error count.
LSB of the 16-bit E-bit error count.
10.4 FAS Error Counter
FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit
counter that records word errors in the FAS in time slot 0. This counter is disabled when RLOS is high. FAS errors
are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4
multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot
saturate.
Register Name:
Register Description:
Register Address:
Bit #
Name
NAME
FAS15
FAS0
7
FAS15
FAS7
FASCR1, FASCR2
FAS Error Count Registers
06 Hex, 07 Hex
6
FAS14
FAS6
BIT
FASCR1.7
FASCR2.0
5
FAS13
FAS5
4
FAS12
FAS4
3
FAS11
FAS3
2
FAS10
FAS2
FUNCTION
MSB of the 16-bit FAS error count.
LSB of the 16-bit FAS error count.
35 of 76
1
FAS9
FAS1
0
FAS8
FAS0
DS21Q59 Quad E1 Transceiver
11.
SIGNALING OPERATION
Registers SA1 and SA16 are used to access the transmit and receive signaling function. Normally, reading these
registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter.
The user can read what was written to the transmit signaling buffer by setting CCR6.5 = 1, then reading
SA1–SA16. In most applications, however, CCR6.5 should be set = 0.
11.1 Receive Signaling
Signaling data is sampled from time slot 16 in the receive data stream and copied into the receive signaling buffers.
The host can access the signaling data by reading SA1 through SA16. The signaling information in these registers
is always updated on multiframe boundaries. The SR2.7 bit in status register 2 can be used to alert the host that
new signaling data is present in the receive signaling buffers. The host has 2ms to read the signaling buffers before
they are updated.
11.2 Transmit Signaling
Insertion of signaling data from the transmit signaling buffers is enabled by setting CCR6.3 = 1. Signaling data is
loaded into the transmit signaling buffers by writing the signaling data to SA1–SA16. On multiframe boundaries, the
contents of the transmit signaling buffer is loaded into a shift register for placement in the appropriate bit position in
the outgoing data stream. The user can use the transmit multiframe interrupt in status register 2 (SR2.5) to know
when to update the signaling bits. The host has 2ms to update the signaling data. The user only needs to update
the signaling data that has changed since the last update.
11.3 CAS Operation
For CAS mode, the user must provide the CAS alignment pattern (four 0s in the upper nibble of TS16). Typically
this is done by setting the upper four bits of SA1 = 0. The lower four bits are alarm bits. The user only needs to
update the appropriate channel associated signaling data in SA2–SA16 on multiframe boundaries.
Register Name:
Register Description:
Register Address:
(MSB)
0
CH1-A
CH2-A
CH3-A
CH4-A
CH5-A
CH6-A
CH7-A
CH8-A
CH9-A
CH10-A
CH11-A
CH12-A
CH13-A
CH14-A
CH15-A
0
CH1-B
CH2-B
CH3-B
CH4-B
CH5-B
CH6-B
CH7-B
CH8-B
CH9-B
CH10-B
CH11-B
CH12-B
CH13-B
CH14-B
CH15-B
SA1 to SA16
Signaling Registers
30h to 3Fh
0
CH1-C
CH2-C
CH3-C
CH4-C
CH5-C
CH6-C
CH7-C
CH8-C
CH9-C
CH10-C
CH11-C
CH12-C
CH13-C
CH14-C
CH15-C
0
CH1-D
CH2-D
CH3-D
CH4-D
CH5-D
CH6-D
CH7-D
CH8-D
CH9-D
CH10-D
CH11-D
CH12-D
CH13-D
CH14-D
CH15-D
X
CH16-A
CH17-A
CH18-A
CH19-A
CH20-A
CH21-A
CH22-A
CH23-A
CH24-A
CH25-A
CH26-A
CH27-A
CH28-A
CH29-A
CH30-A
Y
CH16-B
CH17-B
CH18-B
CH19-B
CH20-B
CH21-B
CH22-B
CH23-B
CH24-B
CH25-B
CH26-B
CH27-B
CH28-B
CH29-B
CH30-B
36 of 76
X
CH16-C
CH17-C
CH18-C
CH19-C
CH20-C
CH21-C
CH22-C
CH23-C
CH24-C
CH25-C
CH26-C
CH27-C
CH28-C
CH29-C
CH30-C
(LSB)
X
CH16-D
CH17-D
CH18-D
CH19-D
CH20-D
CH21-D
CH22-D
CH23-D
CH24-D
CH25-D
CH26-D
CH27-D
CH28-D
CH29-D
CH30-D
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
DS21Q59 Quad E1 Transceiver
12.
DS0 MONITORING FUNCTION
Each DS21Q59 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the
receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored
by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0 to RCM4 bits in
the CCR4 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits appear in the
transmit DS0 monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits appear in the
receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 in the transmit direction and DS0
channel 15 in the receive direction needed to be monitored, then the following values would be programmed into
CCR4 and CCR5:
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
Register Name:
Register Description:
Register Address:
Bit #
Name
7
RLB
BIT
7
6
5
TCM4
4
TCM3
TCM2
TCM1
TCM0
3
2
1
0
Register Name:
Register Description:
Register Address:
Bit #
Name
CCR3 (Repeated here from Section 6 for convenience.)
Common Control Register 3
14 Hex
6
LLB
NAME
RLB
LLB
LIAIS
7
B1
BIT
B1
7
B2
B3
B4
B5
B6
B7
6
5
4
3
2
1
B8
0
5
LIAIS
4
TCM4
3
TCM3
2
TCM2
1
TCM1
0
TCM0
FUNCTION
Remote Loopback
Local Loopback
Line Interface AIS Generation Enable
Transmit Channel Monitor Bit 4. MSB of a channel decode that
determines which transmit channel data appears in the TDS0M register.
See Section 10 or details.
Transmit Channel Monitor Bit 3
Transmit Channel Monitor Bit 2
Transmit Channel Monitor Bit 1
Transmit Channel Monitor Bit 0. LSB of the channel decode.
TDS0M
Transmit DS0 Monitor Register
22 Hex
6
B2
NAME
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
5
B3
4
B4
3
B5
2
B6
1
B7
0
B8
FUNCTION
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be
transmitted).
Transmit DS0 Channel Bit 2
Transmit DS0 Channel Bit 3
Transmit DS0 Channel Bit 4
Transmit DS0 Channel Bit 5
Transmit DS0 Channel Bit 6
Transmit DS0 Channel Bit 7
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be
transmitted).
37 of 76
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
LIRST
NAME
LIRST
RESA
RESR
BIT
7
6
5
RCM4
4
RCM3
RCM2
RCM1
RCM0
3
2
1
0
Register Name:
Register Description:
Register Address:
Bit #
Name
NAME
B1
B2
B3
B4
B5
B6
B7
B8
7
B1
BIT
7
6
5
4
3
2
1
0
CCR4 (Repeated here from Section 6 for convenience.)
Common Control Register 4
15 Hex
6
RESA
5
RESR
4
RCM4
3
RCM3
2
RCM2
1
RCM1
0
RCM0
FUNCTION
Line Interface Reset
Receive Elastic Store Align
Receive Elastic Store Reset
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data appears in the RDS0M register.
See Section 10 for details.
Receive Channel Monitor Bit 3
Receive Channel Monitor Bit 2
Receive Channel Monitor Bit 1
Receive Channel Monitor Bit 0. LSB of the channel decode.
RDS0M
Receive DS0 Monitor Register
2A Hex
6
B2
5
B3
4
B4
3
B5
2
B6
1
B7
0
B8
FUNCTION
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received).
Receive DS0 Channel Bit 2
Receive DS0 Channel Bit 3
Receive DS0 Channel Bit 4
Receive DS0 Channel Bit 5
Receive DS0 Channel Bit 6
Receive DS0 Channel Bit 7
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit received).
38 of 76
DS21Q59 Quad E1 Transceiver
13.
PRBS GENERATION AND DETECTION
15
The DS21Q59 can transmit and receive the 2 - 1 PRBS pattern. This PRBS pattern complies with ITU-T O.151
specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except
TS0), or in any single time slot. Register CCR5 contains the control bits for configuring the transmit and receives
PRBS functions. See Table 13-A and Table 13-B for selecting the transmit and receive modes of operation. In
transmit and receive mode 1 operation, the transmit- and receive-channel monitor-select bits of registers CCR3
and CCR4 have an alternate use. When this mode is selected, these bits determine which time slot transmits
and/or receives the PRBS pattern.
SR2.0 indicates when the receiver has synchronized to the PRBS pattern. The PRBS synchronizer remains in sync
until it experiences six or more bit errors within a 64-bit span. Choosing any receive mode other than NORMAL
causes the 16-bit E-bit error counter—EBCR1 and EBCR2—to be reconfigured for counting PRBS errors.
User-definable outputs OUTA or OUTB can be configured to output a pulse for every bit error received. See
Section 20 and Table 20-A for details. This signal can be used with external circuitry to keep track of bit-error rates
during PRBS testing. Once synchronized, any bit errors received cause a positive-going pulse, synchronous with
RCLK.
Table 13-A. Transmit PRBS Mode Select
TPRBS1
(CCR5.3)
TPBRS0
(CCR5.2)
0
0
Mode 0: Normal (PRBS disabled)
0
1
Mode 1: PRBS in TSx. PRBS pattern is transmitted in a single time slot (TS). In this mode, the
transmit-channel monitor-select bits in register CCR3 are used to select a time slot in which to
transmit the PRBS pattern.
1
0
Mode 2: PRBS in all but TS0. PRBS pattern is transmitted in time slots 1 through 31.
1
1
Mode 3: PRBS unframed. PRBS pattern is transmitted in all time slots.
MODE
Table 13-B. Receive PRBS Mode Select
RPRBS1
(CCR5.1)
RPBRS0
(CCR5.0)
0
0
Mode 0: Normal (PRBS disabled)
0
1
Mode 1: PRBS in TSx. PRBS pattern is received in a single time slot (TS). In this mode, the
receive-channel monitor-select bits in register CCR4 are used to select a time slot in which to
receive the PRBS pattern.
1
0
Mode 2: PRBS in all but TS0. PRBS pattern is received in time slots 1 through 31.
1
1
Mode 3: PRBS unframed. PRBS pattern is received in all time slots.
MODE
39 of 76
DS21Q59 Quad E1 Transceiver
14.
SYSTEM CLOCK INTERFACE
A single system clock interface (SCI) is common to all four DS21Q59 transceivers. The SCI is designed to allow
any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q59s are
used to build an N port system, the SCI allows any one of the N ports to be the master. The selected reference is
then distributed to the other DS21Q59s through the REFCLK pin. The REFCLK pin acts as an output on the
DS21Q59, which has been selected to provide the reference clock from one of its four receivers. On DS21Q59s not
selected to source the reference clock, this pin becomes an input by writing 0s to the SCSx bits. The reference
clock is also passed to the clock synthesizer PLL to generate a 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
clock. This clock can then be used with the IBO function to merge up to eight E1 lines onto a single high-speed
PCM bus. In the event that the master E1 port fails (enters a receive carrier loss condition), that port automatically
switches to the clock present on the MCLK pin. Therefore, MCLK acts as the backup source of master clock. The
host can then find and select a functioning E1 port as the master. Because the selected port’s clock is passed to
the other DS21Q59s in a multiple device configuration, one DS21Q59’s synthesizer can always be the source of
the high-speed clock. This allows smooth transitions when clock-source switching occurs. The SCI control register
exists in Transceiver 1 only (TS0, TS1 = 0).
Register Name:
Register Description:
Register Address:
Bit #
Name
7
AJACKE
NAME
AJACKE
BIT
7
6
BUCS
SOE
5
CSS1
CSS0
SCS2
SCS1
SCS0
4
3
2
1
0
SCICR
System Clock Interface Control Register
(Note: This register is valid only for Transceiver 1 (TS0 = 0, TS1 = 0).)
1D Hex
6
BUCS
5
SOE
4
CSS1
3
CSS0
2
SCS2
1
SCS1
0
SCS0
FUNCTION
AJACK Enable. This bit enables the alternate jitter attenuator.
Backup Clock Select. Selects which clock source to switch to
automatically during a loss-of-transmit clock event.
0 = during an LOTC event switch to MCLK
1 = during an LOTC event switch to system reference clock
Synthesizer Output Enable
0 = 2/4/8/16MCK pin in high-Z mode
1 = 2/4/8/16MCK pin active
Clock Synthesizer Select Bit 1 (Table 14-A)
Clock Synthesizer Select Bit 0 (Table 14-A)
System Clock Select Bit 2 (Table 14-B)
System Clock Select Bit 1 (Table 14-B)
System Clock Select Bit 0 (Table 14-B)
Table 14-A. Synthesizer Output Select
CSS1
CSS0
0
0
1
1
0
1
0
1
SYNTHESIZER OUTPUT
FREQUENCY (MHz)
2.048
4.096
8.192
16.384
Table 14-B. System Clock Selection
SCS2
0
0
0
0
1
1
1
1
SCS1
0
0
1
1
0
0
1
1
SCS0
0
1
0
1
0
1
0
1
PORT SELECTED AS MASTER
None (Master Port can be derived from another DS21Q59 in the system.)
Transceiver 1
Transceiver 2
Transceiver 3
Transceiver 4
Reserved for future use.
Reserved for future use.
Reserved for future use.
40 of 76
DS21Q59 Quad E1 Transceiver
15.
TRANSMIT CLOCK SOURCE
Depending on the DS21Q59’s operating mode, the transmit clock can be derived from different sources. In a basic
configuration, where the IBO function is disabled, the transmit clock is normally sourced from the TCLK pin. In this
mode, a 2.048MHz clock with ±50ppm accuracy is applied to the TCLK pin. If the signal at TCLK is lost, the
DS21Q59 automatically switches to either the system reference clock present on the REFCLK pin or to the
recovered clock off the same port, depending on which source the host assigned as the backup clock. At the same
time the host can be notified of the loss-of-transmit clock through an interrupt. The host can at any time force a
switchover to one of the two backup clock sources regardless of the state of the TCLK pin.
When the IBO function is enabled, the transmit clock must be synchronous to the system clock since slips are not
allowed in the transmit direction. In this mode, the TCLK pin is ignored, and a transmit clock is automatically
provided by the IBO circuit by dividing the clock present on the SYSCLK pin by 2, 4, or 8. In this configuration, if the
signal present on the SYSCLK pin is lost, the DS21Q59 automatically switches to either the system reference clock
or to the recovered clock off the same port, depending on which source the host assigned as the backup clock. The
host can at any time force a switchover to one of the two backup clock sources regardless of the state of the
SYSCLK pin.
16.
IDLE CODE INSERTION
The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code
placed in the transmit idle definition register (TIDR). This allows the same 8-bit code to be placed into any of the 32
E1 channels. Each of the bit positions in the transmit idle registers represents a DS0 channel in the outgoing frame.
When these bits are set to 1, the corresponding channel transmits the idle code contained in the TIDR.
TIR1, TIR2, TIR3, TIR4
Transmit Idle Registers
24 Hex, 25 Hex, 26 Hex, 27 Hex
Register Name:
Register Description:
Register Address:
Bit #
Name
7
CH8
CH16
CH24
CH32
6
CH7
CH15
CH23
CH31
5
CH6
CH14
CH22
CH30
NAME
BIT
CH1 to CH32
TIR1.0 to 4.7
NAME
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
7
TIDR7
3
CH4
CH12
CH20
CH28
2
CH3
CH11
CH19
CH27
1
CH2
CH10
CH18
CH26
0
CH1
CH9
CH17
CH25
FUNCTION
Transmit Idle Code-Insertion Control Bits
0 = do not insert the idle code in the TIDR into this channel
1 = insert the idle code in the TIDR into this channel
TIDR
Transmit Idle Definition Register
23 Hex
Register Name:
Register Description:
Register Address:
Bit #
Name
4
CH5
CH13
CH21
CH29
6
TIDR6
BIT
7
6
5
4
3
2
1
0
5
TIDR5
4
TIDR4
3
TIDR3
2
TIDR2
1
TIDR1
FUNCTION
MSB of the Idle Code (This bit is transmitted first.)
—
—
—
—
—
—
LSB of the Idle Code (This bit is transmitted last.)
41 of 76
0
TIDR0
DS21Q59 Quad E1 Transceiver
17.
PER-CHANNEL LOOPBACK
The DS21Q59 has per-channel loopback capability that can operate in one of two modes: remote per-channel
loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are
looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which channels (if any) in the transmit
direction should be replaced with the data from the receiver or, in other words, off the E1 line. In local per-channel
loopback mode, PCLB1/2/3/4 determine which channels (if any) in the receive direction should be replaced with the
data from the transmit. If either mode is enabled, transmit and receive clocks and frame syncs must be
synchronized. There are no restrictions on which channels can be looped back or on how many channels can be
looped back.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
CH8
CH16
CH24
CH32
PCLB1, PCLB2, PCLB3, PCLB4
Per-Channel Loopback Registers
2B Hex, 2C Hex, 2D Hex, 2E Hex
6
CH7
CH15
CH23
CH31
5
CH6
CH14
CH22
CH30
NAME
BIT
CH1 to CH32
PCLB1.0 to 4.7
18.
4
CH5
CH13
CH21
CH29
3
CH4
CH12
CH20
CH28
2
CH3
CH11
CH19
CH27
1
CH2
CH10
CH18
CH26
0
CH1
CH9
CH17
CH25
FUNCTION
Per-Channel Loopback Control Bits
0 = do not loopback this channel
1 = loopback this channel
ELASTIC STORE OPERATION
The DS21Q59 contains a two-frame (512 bits) elastic store for the receive direction. The elastic store is used to
absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not
frequency locked) backplane clock that can be 2.048MHz for normal operation or 4.096MHz, 8.192MHz, or
16.384MHz when using the IBO function. The elastic store contains full controlled slip capability.
If the receive elastic store is enabled (RCR.4 = 1), the user must provide a 2.048MHz clock to the SYSCLK pin. If
the IBO function is enabled, a 4.096MHz, 8.192MHz, or 16.384MHz clock must be provided at the SYSCLK pin.
The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR.5 = 1) or having the
RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5 = 0). If the user wishes to obtain pulses at the
frame boundary, RCR1.6 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary,
RCR1.6 must be set to 1. If the elastic store is enabled, either CAS (RCR.7 = 0) or CRC4 (RCR.7 = 1) multiframe
boundaries are indicated through the RSYNC output. See Section 24 for timing details. If the 512-bit elastic buffer
either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of data (256 bits) is repeated at
RSER, and the SR1.4 and RIR.3 bits are set to 1. If the buffer fills, a full frame of data is deleted, and the SR1.4
and RIR.4 bits are set to 1.
42 of 76
DS21Q59 Quad E1 Transceiver
19.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
On the receiver, the RAF and RNAF registers always report the data as it is received in the additional (Sa) and
international (Si) bit locations. The RAF and RNAF registers are updated with the setting of the receive align frame
bit in status register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers.
It has 250ms to retrieve the data before it is lost.
On the transmitter, data is sampled from the TAF and TNAF registers with the setting of the transmit align frame bit
in status register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and TNAF registers. It
has 250ms to update the data or else the old data is retransmitted. Data in the Si bit position is overwritten if either
the framer is programmed (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or if the framer (3)
has automatic E-bit insertion enabled. Data in the Sa bit position is overwritten if any of the TCR.3–TCR.7 bits are
set to 1. Please see the TCR register descriptions for more details.
RAF
Receive Align Frame Register
28 Hex
Register Name:
Register Description:
Register Address:
Bit #
Name
NAME
Si
0
0
1
1
0
1
1
7
Si
BIT
7
6
5
4
3
2
1
0
6
0
NAME
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
7
Si
BIT
7
6
5
4
3
2
1
0
4
1
3
1
2
0
1
1
0
1
1
Sa7
0
Sa8
FUNCTION
International Bit
Frame Alignment Signal Bit
Frame Alignment Signal Bit
Frame Alignment Signal Bit
Frame Alignment Signal Bit
Frame Alignment Signal Bit
Frame Alignment Signal Bit
Frame Alignment Signal Bit
RNAF
Receive Nonalign Frame Register
29 Hex
Register Name:
Register Description:
Register Address:
Bit #
Name
5
0
6
1
5
A
4
Sa4
3
Sa5
FUNCTION
International Bit
Frame Nonalignment Signal Bit
Remote Alarm
Additional Bit 4
Additional Bit 5
Additional Bit 6
Additional Bit 7
Additional Bit 8
43 of 76
2
Sa6
DS21Q59 Quad E1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
7
Si
TAF
Transmit Align Frame Register
20 Hex
6
0
5
0
4
1
3
1
2
0
1
1
0
1
Note: This register must be programmed with the 7-bit FAS word. The DS21Q59 does not automatically set these bits.
NAME
Si
0
0
1
1
0
1
1
BIT
7
6
5
4
3
2
1
0
Register Name:
Register Description:
Register Address:
Bit #
Name
7
Si
FUNCTION
International Bit
Frame Alignment Signal Bit. Set this bit = 0.
Frame Alignment Signal Bit. Set this bit = 0.
Frame Alignment Signal Bit. Set this bit = 1.
Frame Alignment Signal Bit. Set this bit = 1.
Frame Alignment Signal Bit. Set this bit = 0.
Frame Alignment Signal Bit. Set this bit = 1.
Frame Alignment Signal Bit. Set this bit = 1.
TNAF
Transmit Nonalign Frame Register
21 Hex
6
1
5
A
4
Sa4
3
Sa5
2
Sa6
Note: Bit 6 must be programmed to 1. The DS21Q59 does not automatically set this bit.
NAME
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
BIT
7
6
5
4
3
2
1
0
FUNCTION
International Bit
Frame Nonalignment Signal Bit. Set this bit = 1.
Remote Alarm (Used to transmit the alarm.)
Additional Bit 4
Additional Bit 5
Additional Bit 6
Additional Bit 7
Additional Bit 8
44 of 76
1
Sa7
0
Sa8
DS21Q59 Quad E1 Transceiver
20.
USER-CONFIGURABLE OUTPUTS
There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be
programmed to output various clocks, alarms for line monitoring, or logic 0 and 1 levels to control external circuitry.
They can also be used to access transmit data between the framer and transmit LIU. OUTA and OUTB can be
active low or active high when operating as clock and alarm outputs. OUTA is active high if OUTAC.4 = 1 and
active low if OUTAC.3 = 0. OUTB is active high if OUTBC.4 = 1 and active low if OUTBC.4 = 0 (Table 20-A). Select
mode 0000 to control external circuitry. In this configuration, the OUTA pin follows OUTAC.4 and the OUTB pin
follows OUTBC.4. The OUTAC register also contains a control bit for CMI operation. See Section 22 for details
about CMI operation.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
TTLIE
NAME
BIT
TTLIE
7
CMII
6
CMIE
5
OA4
OA3
OA2
OA1
OA0
4
3
2
1
0
Register Name:
Register Description:
Register Address:
Bit #
Name
7
NRZE
NAME
BIT
NRZE
7
—
—
OB4
OB3
OB2
OB1
OB0
6
5
4
3
2
1
0
OUTAC
OUTA Control Register
1A Hex
6
CMII
5
CMIE
4
OA4
3
OA3
2
OA2
1
OA1
0
OA0
FUNCTION
TTL Input Enable. When this bit is set, the receiver can accept TTL
positive and negative data at the RTIP and RRING inputs. The data is
clocked in on the falling edge of MCLK.
CMI Invert. See Section 22 for details.
0 = CMI input data not inverted
1 = CMI input data inverted
CMI Enable. See Section 22 for details.
0 = CMI disabled
1 = CMI enabled
OUTA Control Bit 4. Inverts OUTA output.
OUTA Control Bit 3. See Table 20-A for details.
OUTA Control Bit 2. See Table 20-A for details.
OUTA Control Bit 1. See Table 20-A for details.
OUTA Control Bit 0. See Table 20-A for details.
OUTBC
OUTB Control Register
1B Hex
6
—
5
—
4
OB4
3
OB3
2
OB2
1
OB1
0
OB0
FUNCTION
NRZ Enable. When this bit is set, the receiver can accept TTL-type NRZ
data at the RTIP input. RRING becomes a clock input.
0 = RTIP and RRING are in normal mode.
1 = RTIP becomes an NRZ TTL-type input and RRING is its associated
clock input. Data at RTIP is clocked in on the falling edge of the clock
present on RRING.
Unused. Should be set = 0 for proper operation.
Unused. Should be set = 0 for proper operation.
OUTB Control Bit 4. Inverts OUTB output.
OUTB Control Bit 3
OUTB Control Bit 2
OUTB Control Bit 1
OUTB Control Bit 0
45 of 76
DS21Q59 Quad E1 Transceiver
Table 20-A. OUTA and OUTB Function Select
OA3
OB3
OA2
OB2
OA1
OB1
OA0
OB0
0
0
0
0
External Hardware Control Bit. In this mode, OUTA and OUTB can be used as simple
control pins for external circuitry. Use OA4 and OB4 to toggle OUTA and OUTB.
0
0
0
1
RCLK. Receive recovered clock.
0
0
1
0
Receive Loss-of-Sync Indicator. Real-time hardware version of SR1.0 (Table 9-A).
0
0
1
1
Receive Loss-of-Carrier Indicator. Real-time hardware version of SR1.1 (Table 9-A).
0
1
0
0
Receive Remote Alarm Indicator. Real-time hardware version of SR1.2 (Table 9-A).
0
1
0
1
Receive Unframed All-Ones Indicator. Real-time hardware version of SR1.3 (Table 9-A).
0
1
1
0
0
1
1
1
1
0
0
0
Receive Slip-Occurrence Indicator. One-clock-wide pulse for every slip of the receive
elastic store. Hardware version of SR1.4.
Receive CRC Error Indicator. One-clock-wide pulse for every multiframe that contains a
CRC error. Output forced to 0 during loss of sync.
Loss-of-Transmit Clock Indicator. Real-time hardware version SR2.2 (Table 9-A).
1
0
0
1
RFSYNC. Recovered frame-sync pulse.
1
0
1
0
PRBS Bit Error. A half-clock-wide pulse for every bit error in the received PRBS pattern.
1
0
1
1
TDATA/RDATA. OUTB outputs an NRZ version of the transmit data stream (TDATA) prior
to the transmit line interface. OUTA outputs the received serial data stream (RDATA) prior
to the elastic store.
1
1
0
0
Receive CRC4 Multiframe Sync. Recovered CRC4 MF sync pulse.
1
1
0
1
Receive CAS Multiframe Sync. Recovered CAS MF sync pulse.
1
1
1
0
1
1
1
1
FUNCTION
Transmit Current Limit. Real-time indicator that the TTIP and TRING outputs have
reached their 50mA current limit.
TPOS/TNEG Output. This mode outputs the AMI/HDB3 encoded transmit data. OUTA
outputs TNEG data. OUTB outputs TPOS data.
46 of 76
DS21Q59 Quad E1 Transceiver
21.
LINE INTERFACE UNIT
The line interface unit contains three sections: the receiver, which handles clock and data recovery; the transmitter,
which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR),
described below, controls each of these three sections.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
L2
LICR
Line Interface Control Register
17 Hex
6
L1
NAME
L2
L1
L0
BIT
7
6
5
EGL
4
JAS
3
JABDS
2
DJA
1
TPD
0
5
L0
4
EGL
3
JAS
2
JABDS
1
DJA
0
TPD
FUNCTION
Line Build-Out Select Bit 2. Sets the transmitter build-out.
Line Build-Out Select Bit 1. Sets the transmitter build-out.
Line Build-Out Select Bit 0. Sets the transmitter build-out.
Receive Equalizer Gain Limit
0 = -12dB
1 = -43dB
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
Disable Jitter Attenuator
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down
0 = powers down the transmitter and tri-states the TTIP and TRING pins
1 = normal transmitter operation
21.1 Receive Clock and Data Recovery
The DS21Q59 contains a digital clock recovery system. (See Figure 3-1 and Figure 21-1 for more details.) The
device couples to the receive E1 shielded twisted pair or coax through a 1:1 transformer (Table 21-B). The
2.048MHz clock attached at the MCLK pin is internally multiplied by 16 through an internal PLL and fed to the clock
recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times oversampler,
which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance
(Figure 21-4).
Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs.
When no AMI signal is present at RTIP and RRING, an RCL condition occurs and the RCLK is sourced from the
clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, RCLK can
exhibit slightly shorter high cycles of the clock. This is because of the highly oversampled digital clock recovery
circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator
restores the RCLK to being close to 50% duty cycle. See Receive AC Characteristics in Section 26.4 for more
details.
21.1.1 Termination
The DS21Q59 is designed to be fully software-selectable for 75W and 120W termination without the need to change
any external resistors. The user can configure the DS21Q59 for 75W or 120W receive termination by setting the
IRTSEL (CCR5.4) bit. When using the internal termination feature, the external termination resistance should be
120W (typically two 60W resistors). Setting IRTSEL = 1 causes the DS21Q59 to internally apply parallel resistance
to the external resistors to adjust the termination to 75W (Figure 21-2).
47 of 76
DS21Q59 Quad E1 Transceiver
21.2
Transmit Waveshaping and Line Driving
The DS21Q59 uses a set of laser-trimmed delay lines and a precision digital-to-analog converter (DAC) to create
the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications
(Figure 21-3). The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in
the line interface control register (LICR). The DS21Q59 can be set up in a number of various configurations
depending on the application (Table 21-A).
Table 21-A. Line Build-Out Select in LICR
L2
L1
L0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
APPLICATION
*
TRANSFORMER
RETURN LOSS
Rt (W)
1:2 step-up
1:2 step-up
1:2 step-up
1:2 step-up
1:2 step-up
1:2 step-up
N.M.
N.M.
N.M.
N.M.
21dB
21dB
0
0
2.5
2.5
6.2
11.6
75W normal
120W normal
75W with protection resistors
120W with protection resistors
75W with high return loss
120W with high return loss
**
*N.M. = Not meaningful (return loss value too low for significance)
**See Application Note 336: Transparent Operation on T1, E1 Framers and Transceivers for details on E1 line interface design.
Because of the nature of the transmitter’s design, very little jitter (less than 0.005UIP-P broadband from 10Hz to
100kHz) is added to the jitter present on TCLK (or source used for transmit clock). Also, the waveform created is
independent of the duty cycle of TCLK. The transmitter in the device couples to the E1 transmit-shielded twisted
pair or coax through a 1:2 step-up transformer, as shown in Figure 21-1. For the devices to create the proper
waveforms, the transformer used must meet the specifications listed in Table 21-B. The line driver in the device
contains a current limiter that prevents more than 50mA (RMS) from being sourced in a 1W load.
Table 21-B. Transformer Specifications
SPECIFICATION
Turns Ratio
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
RECOMMENDED VALUE
1:1 (receive) and 1:2 (transmit) ±3%
600mH minimum
1.0mH maximum
40pF maximum
1.2W maximum
Figure 21-1. External Analog Connections (Basic Configuration)
0.47mF
(NONPOLARIZED)
1/4 DS21Q59
TTIP
TRING
E1 TRANSMIT
LINE
2:1
1:1
RTIP
E1 RECEIVE
LINE
RRING
Rr
Rr
0.1mF
48 of 76
DVDD
DVSS
+3.3V
0.1mF
0.01mF
RVDD
RVSS
0.1mF
TVDD
TVSS
0.1mF
MCLK
2.048MHz
DS21Q59 Quad E1 Transceiver
Figure 21-2. External Analog Connections (Protected Interface)
+VDD
FUSE
D2
D1
2:1
+VDD
TTIP1
TRANSMIT
LINE
0.47mF
S
(NONPOLARIZED)
FUSE
C1
TRING1
+VDD
FUSE
RECEIVE
LINE
TVDD
TVSS
0.1mF
0.01mF
0.1mF
0.1mF
1/4 DS21Q59
D6
D5
1:1
RVDD
RVSS
D4
D3
DVDD
DVSS
RTIP1
S
C2
RRING1
FUSE
60
60 D7
MCLK
D8
0.1mF
Note 1: All resistor values are ±1%.
Note 2: C1 = C2 = 0.1mF.
Note 3: S is a 6V transient suppressor.
Note 4: D1 to D8 are Schottky diodes.
Note 5: The fuses are optional to prevent AC power line crosses from compromising the transformers.
Note 6: The 68mF is used to keep the local power plane potential within tolerance during a surge.
49 of 76
2.048MHz
68mF
DS21Q59 Quad E1 Transceiver
Figure 21-3. Transmit Waveform Template
1.2
1.1
269ns
(in 75W systems, 1.0 on the scale = 2.37Vpeak
in 120W systems, 1.0 on the scale = 3.00Vpeak)
SCALED AMPLITUDE
1.0
0.9
0.8
0.7
G.703
TEMPLATE
194ns
0.6
0.5
219ns
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-250
-200
-150
-100
-50
0
50
100
150
200
250
TIME (ns)
21.3 Jitter Attenuators
The DS21Q59 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated
“clock only” jitter attenuator. This undedicated jitter attenuator is shown in the block diagram (Figure 3-1) as the
alternate jitter attenuator.
21.3.1 Clock and Data Jitter Attenuators
The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer
depths of either 32 or 128 bits through the LICR. The 128-bit mode is used in applications where large excursions
of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the
attenuators are shown in Figure 21-5. The jitter attenuators can be placed in either the receive path or the transmit
path by appropriately setting or clearing the JAS bit in the LICR. Also, setting the DJA bit in the LICR can disable
the jitter attenuator (in effect, remove it). For the jitter attenuator to operate properly, a 2.048MHz clock (±50ppm)
must be applied at the MCLK pin. On-board circuitry adjusts either the recovered clock from the clock/data
recovery block or the clock applied at the TCLKI pin to create a smooth jitter-free clock that is used to clock data
out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter
attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or
28UIP-P (buffer depth is 32 bits), the DS21Q59 divides the internal nominal 32.768MHz clock by either 15 or 17
instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also
sets the jitter attenuator limit trip (JALT) bit in the receive information register (RIR.5).
50 of 76
DS21Q59 Quad E1 Transceiver
21.3.2 Undedicated Clock Jitter Attenuator
The undedicated jitter attenuator is useful for preparing a user-supplied clock for use as a transmission clock
(TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL or other
synthesizers can contain too much jitter to be appropriate for transmission. Network requirements limit the amount
of jitter that can be transmitted onto the network. This feature is enabled by setting SC1CR.7 = 1 in Transceiver 1.
Figure 21-4. Jitter Tolerance
UNIT INTERVALS (UIP-P)
1k
DS21Q59
TOLERANCE
100
40
10
1.5
1
0.1
MINIMUM TOLERANCE
LEVEL AS PER
ITU G.823
1
10
20
0.2
100
1k
FREQUENCY (Hz)
2.4k
10k
18k
100k
Figure 21-5. Jitter Attenuation
JITTER ATTENUATION (dB)
0
ITU G.7XX
PROHIBITED AREA
-20
ETS 300 011 AND TBR12
PROHIBITED AREA
-40
JITTER ATTENUATION CURVE
-60
1
10
40
100
1k
FREQUENCY (Hz)
51 of 76
10k
100k
DS21Q59 Quad E1 Transceiver
22.
CODE MARK INVERSION (CMI)
The DS21Q59 provides a CMI interface for connecting to optical transports. This interface is a unipolar 1T2Bcoded signal. Ones are alternately encoded as a logical 1 or 0 level for the full duration of the clock period. Zeros
are encoded as a 0-to-1 transition at the middle of the clock period. Figure 22-1 shows an example data pattern
and its CMI result. The control bit for enabling CMI is in the OUTAC register, as shown below.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
TTLIE
NAME
BIT
TTLIE
7
CMII
6
CMIE
5
OA4
OA3
OA2
OA1
OA0
4
3
2
1
0
OUTAC
OUTA Control Register
1A Hex
6
CMII
5
CMIE
4
OA4
3
OA3
CLOCK
1
1
OA1
0
OA0
FUNCTION
TTL Input Enable. When this bit is set, the receiver can accept TTL
positive and negative data at the RTIP and RRING inputs. The data is
clocked in on the falling edge of MCLK.
CMI Invert
0 = CMI input data not inverted
1 = CMI input data inverted
Transmit and Receive CMI Enable
0 = Transmit and receive line interface operates in normal AMI/HDB3 mode
1 = Transmit and receive line interface operate in CMI mode. TTIP is CMI
output and RTIP is CMI input. In this mode of operation TRING and RRING
are no connects.
OUTA Control Bit 4. Inverts OUTA output.
OUTA Control Bit 3. See Table 20-A for details.
OUTA Control Bit 2. See Table 20-A for details.
OUTA Control Bit 1. See Table 20-A for details.
OUTA Control Bit 0. See Table 20-A for details.
Figure 22-1. CMI Coding
DATA
2
OA2
1
0
1
0
0
1
CMI
52 of 76
DS21Q59 Quad E1 Transceiver
Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMIcoded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is
enabled, the user can also use HDB3 coding.
When this register bit is set, the RTIP pin becomes a unipolar CMI input. The CMI signal is processed to extract
and align the clock with data. The bipolar code-violation counter counts CVs in the CMI signal. CVs are defined as
consecutive 1s of the same polarity, as shown in Figure 22-2. If HDB3 precoding is enabled, the CVs generated by
HDB3 are not counted as errors.
Figure 22-2. Example of CMI Code Violation
CLOCK
DATA
1
1
0
1
0
0
1
CMI
CODE VIOLATION
53 of 76
DS21Q59 Quad E1 Transceiver
23.
INTERLEAVED PCM BUS OPERATION
In many architectures, the PCM outputs of individual framers are combined into higher-speed PCM buses to
simplify transport across the system backplane. The DS21Q59 can be configured to allow PCM data buses to be
multiplexed into higher-speed data buses, eliminating external hardware and saving board space and cost. The
DS21Q59 uses a channel interleave method. See Figure 24-4 and Figure 24-7 for details of the channel interleave.
The interleaved PCM bus option supports three bus speeds. The 4.096MHz bus speed allows two PCM data
streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to share a common bus.
The 16.384MHz bus speed allows eight PCM data streams to share a common bus. See Figure 23-1 for an
example of four transceivers sharing a common 8.192MHz PCM bus. The receive elastic stores of each transceiver
must be enabled. Through the IBO register the user can configure each transceiver for a specific bus speed and
position. For all IBO bus configurations each transceiver is assigned an exclusive position in the high-speed PCM
bus. When the device is configured for IBO operation, the TSYNCx pin should be configured as an output or as an
input connected to ground. The user cannot supply a TSYNCx signal in this mode. When IBO operation is enabled,
TSYNCx will be internally tied to RSYNCx. If TSYNCx is configured as an input, the physical pin will be
disconnected from the internal TSYNCx signal and should therefore be connected to ground to keep it from
floating.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
—
IBO
Interleave Bus Operation Register
1C Hex
6
IBOTCS
NAME
—
BIT
7
IBOTCS
6
SCS1
SCS0
5
4
IBOEN
3
DA2
DA1
DA0
2
1
0
5
SCS1
SCS0
0
0
3
IBOEN
2
DA2
1
DA1
0
DA0
FUNCTION
Not Assigned. Should be set to 0.
IBO Transmit Clock Source
0 = TCLK pin is the source of transmit clock
1 = Transmit clock is internally derived from the clock at the SYSCLK pin
System Clock Select Bit 1 (Table 23-A)
System Clock Select Bit 0 (Table 23-A)
Interleave Bus Operation Enable
0 = IBO disabled
1 = IBO enabled
Device Assignment Bit 3 (Table 23-B)
Device Assignment Bit 2 (Table 23-B)
Device Assignment Bit 1(Table 23-B)
Table 23-A. IBO System Clock Select
SCS1
4
SCS0
Table 23-B. IBO Device Assignment
DA2
0
0
0
0
1
1
1
1
FUNCTION
2.048MHz, single device on bus
0
1
4.096MHz, two devices on bus
1
0
8.192MHz, four devices on bus
1
1
16.384MHz, eight devices on bus
54 of 76
DA1
0
0
1
1
0
0
1
1
DA0
0
1
0
1
0
1
0
1
FUNCTION
1st device on bus
2nd device on bus
3rd device on bus
4th device on bus
5th device on bus
6th device on bus
7th device on bus
8th device on bus
DS21Q59 Quad E1 Transceiver
Figure 23-1. IBO Configuration Using Two DS21Q59 Transceivers (Eight E1 Lines)
E1 #1
E1 #2
E1 #3
E1 #4
XFMR
TTIP1/TRING1
XFMR
RTIP1/RRING1
XFMR
TTIP2/TRING2
XFMR
RTIP2/RRING2
DS21Q59
XFMR
TTIP3/TRING3
XFMR
RTIP3/RRING3
XFMR
TTIP4/TRING4
XFMR
RTIP4/RRING4
E1 #5
E1 #6
E1 #7
E1 #8
TTIP1/TRING1
XFMR
RTIP1/RRING1
XFMR
TTIP2/TRING2
XFMR
RTIP2/RRING2
REFCLK
4/8/16MCK
4/8/16MCK
DS21Q59
XFMR
TTIP3/TRING3
XFMR
RTIP3/RRING3
XFMR
TTIP4/TRING4
XFMR
RTIP4/RRING4
PCM IN
16.384MHz INTERLEAVED
PCM OUT PCM BUS
TSER3
RSER3
SYSCLK3
RSYNC3
REFCLK
XFMR
TSER1
RSER1
SYSCLK1
TSYNC1
RSYNC1
TSER2
RSER2
SYSCLK2
RSYNC2
TSER4
RSER4
SYSCLK4
RSYNC4
TSER1
RSER1
SYSCLK1
RSYNC1
TSER2
RSER2
SYSCLK2
RSYNC2
TSER3
RSER3
SYSCLK3
RSYNC3
TSER4
RSER4
SYSCLK4
RSYNC4
NOTE: SEE SECTION 21 FOR DETAILS ON LINE INTERFACE CIRCUIT.
55 of 76
16.384MHz CLOCK DERIVED FROM
ONE OF THE EIGHT E1 LINES
DS21Q59 Quad E1 Transceiver
24.
FUNCTIONAL TIMING DIAGRAMS
24.1
Receive
Figure 24-1. Receive Frame and Multiframe Timing
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
RSYNC 1
RSYNC
2
NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0).
NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
Figure 24-2. Receive Boundary Timing (With Elastic Store Disabled)
RCLK
CHANNEL 32
RSER
LSB
Si
1
A
CHANNEL 1
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 2
RSYNC
Figure 24-3. Receive Boundary Timing (With Elastic Store Enabled)
SYSCLK
CHANNEL 31
RSER
CHANNEL 32
LSB MSB
CHANNEL 1
LSB MSB
RSYNC1
RSYNC 2
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR.5 = 1). RSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG
AS IT TRANSITIONS LOW ONE CLOCK CYCLE BEFORE TRANSITIONING HIGH AGAIN FOR THE NEXT SYNC PULSE.
56 of 76
DS21Q59 Quad E1 Transceiver
Figure 24-4. Receive Interleave Bus Operation
RSYNC
RSER
1
RSER2
FR1 CH32
FR2 CH32 FR3 CH32
FR0 CH1
FR0 CH1
FR1 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR0 CH2
FR1 CH2
FR1 CH2
FR2 CH2
FR3 CH2
RSER3
FR4 CH32
FR6 CH32 FR0 CH1 FR2 CH1 FR4 CH1 FR6 CH1
FR0 CH2 FR2 CH2 FR4 CH2 FR6 CH2
FR1 CH2 FR3 CH2 FR5 CH2 FR7 CH2
FR5 CH32 FR7 CH32 FR1 CH1 FR3 CH1 FR5 CH1 FR7 CH1
BIT DETAIL
SYSCLK
RSYNC
4
FRAMER 3, CHANNEL 32
RSER
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
LSB MSB
LSB MSB
LSB
NOTE 1: 4.096MHZ BUS CONFIGURATION.
NOTE 2: 8.192MHZ BUS CONFIGURATION.
NOTE 3: 16.384MHZ BUS CONFIGURATION.
NOTE 4: RSYNC IS IN THE INPUT MODE (RCR.5 = 1). RSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG AS IT
TRANSITIONS LOW ONE CLOCK CYCLE BEFORE TRANSITIONING HIGH AGAIN FOR THE NEXT SYNC PULSE.
57 of 76
DS21Q59 Quad E1 Transceiver
24.2
Transmit
Figure 24-5. Transmit Frame and Multiframe Timing
FRAME#
14 15 16 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
9 10
1
TSYNC
TSYNC
2
NOTE 1: TSYNC IN FRAME MODE (TCR.1 = 0).
NOTE 2: TSYNC IN MULTIFRAME MODE (TCR.1 = 1).
Figure 24-6. Transmit Boundary Timing
TCLK
CHANNEL 1
TSER
LSB
Si
1
A
CHANNEL 2
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
LSB MSB
TSYNC1
TSYNC2
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). TSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG
AS IT TRANSITIONS LOW ONE CLOCK CYCLE BEFORE TRANSITIONING HIGH AGAIN FOR THE NEXT SYNC PULSE.
58 of 76
DS21Q59 Quad E1 Transceiver
Figure 24-7. Transmit Interleave Bus Operation
TSYNC
1
TSER
TSER2
FR1 CH32
FR0 CH1
FR2 CH32 FR3 CH32 FR0 CH1
FR1 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR0 CH2
FR1 CH2
FR1 CH2
FR2 CH2
FR3 CH2
TSER 3
FR4 CH32
FR6 CH32 FR0 CH1
FR2 CH1
FR5 CH32 FR7 CH32 FR1 CH1
FR4 CH1
FR3 CH1
FR6 CH1
FR5 CH1
FR0 CH2 FR2 CH2
FR7 CH1
FR1 CH2 FR3 CH2
FR6 CH2
FR5 CH2
BIT DETAIL
SYSCLK
4
TSYNC
FRAMER 3, CHANNEL 32
TSER
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
LSB MSB
LSB MSB
LSB
NOTE 1: 4.096MHZ BUS CONFIGURATION.
NOTE 2: 8.192MHZ BUS CONFIGURATION.
NOTE 3: 16.384MHZ BUS CONFIGURATION.
NOTE 4: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). TSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG AS IT
TRANSITIONS LOW ONE CLOCK CYCLE BEFORE TRANSITIONING HIGH AGAIN FOR THE NEXT SYNC PULSE.
59 of 76
DS21Q59 Quad E1 Transceiver
Figure 24-8. Framer Synchronization Flowchart
Power Up
RLOS = 1
FAS Search
FASSA = 1
RLOS = 1
FAS Sync
Criteria Met
FASSA = 0
Resync if
RCR1.0 = 0
Increment CRC4
Sync Counter;
CRC4SA = 0
8ms
Time
Out
CRC4 Multiframe Search
(if enabled via CCR1.0)
CRC4SA = 1
CRC4 Sync Criteria
Met; CRC4SA = 0;
Reset CRC4
Sync Counter
Set FASRC
(RIR.1)
CRC4 Resync
Criteria Met
(RIR.2)
CAS Resync
Criteria Met;
Set CASRC
(RIR.0)
Check for FAS
Framing Error
(depends on RCR1.2)
FAS Resync
Criteria Met
Check for >=915
Out of 1000
CRC4 Word Errors
If CRC4 is on
(CCR1.0 = 1)
Check for CAS
MF Word Error
If CAS is on
(CCR1.3 = 0)
60 of 76
CAS Multiframe Search
(if enabled via CCR1.3)
CASSA = 1
Sync Declared
RLOS = 0
CAS Sync
Criteria Met
CASSA = 0
DS21Q59 Quad E1 Transceiver
Figure 24-9. Transmit Data Flow
TSER
TAF
TNAF.5-7
0
1
Timeslot 0
Pass-Through
(TCR.6)
1
0
Si Bit Insertion
Control
(TCR.3)
CRC4 Multiframe
Alignment Word
Generation (CCR.4)
Receive Side
CRC4 Error
Detector
0
1
1
E-Bit Generation
(TCR.5)
Auto Remote Alarm
Generation (CCR.4)
TIDR
0
1
Idle Code / Channel
Insertion Control via
TIR1/2/3/4
SA1 - SA16
0
1
Signaling Insertion
CCR6.3
Code Word
Generation
0
1
CRC4 Enable
(CCR.4)
Transmit Unframed All
Ones (TCR.4) or
Auto AIS (CCR2.5)
AMI or HDB3
Converter
CCR.6
KEY:
= Register
To Waveshaping
and Line Drivers
= Device Pin
= Selector
NOTES:
1. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the
Not Align Frames if the alarm needs to be sent.
61 of 76
DS21Q59 Quad E1 Transceiver
25.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range for DS21Q59L
Operating Temperature Range for DS21Q59LN
Storage Temperature Range
Soldering Temperature Range
-1.0V to +6.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to +70°C for DS21Q59L; TA = -40°C to +85°C for DS21Q59LN.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 1
VIH
2.0
5.5
V
Logic 0
VIL
-0.3
+0.8
V
Supply
VDD
(Note 1)
3.135
3.3
3.465
V
MIN
TYP
MAX
UNITS
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
Input Capacitance
Output Capacitance
CONDITIONS
CIN
5
pF
COUT
7
pF
DC CHARACTERISTICS
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
230
UNITS
Supply Current at 3.3V
IDD
(Note 2)
Input Leakage
IIL
(Note 3)
Output Leakage
ILO
(Note 4)
Output Current (2.4V)
IOH
-1.0
mA
Output Current (0.4V)
IOL
+4.0
mA
-1.0
mA
+1.0
mA
+1.0
mA
Note 1: Applies to RVDD, TVDD, and DVDD.
Note 2: TCLKs = SYSCLKs = MCLK = 2.048MHz; outputs open circuited; TTIPs and TRINGs driving 30W; QRSS data pattern.
0.0V < VIN < VDD.
Note 3: Applied to INT when tri-stated.
Note 4: Applies to output pins in a tri-state condition.
62 of 76
DS21Q59 Quad E1 Transceiver
26.
AC TIMING PARAMETERS AND DIAGRAMS
26.1
Multiplexed Bus AC Characteristics
Table 26-A. AC Characteristics—Multiplexed Parallel Port
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-1, Figure 26-2, and Figure 26-3)
PARAMETER
Cycle Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tCYC
200
ns
Pulse Width, DS Low or RD High
PW EL
100
ns
Pulse Width, DS High or RD Low
PW EH
100
ns
Input Rise/Fall times
tR, tF
R/W Hold Time
tRWH
10
ns
R/W Setup Time Before DS High
tRWS
50
ns
CS Setup Time Before DS, WR, or
RD Active
tCS
20
ns
CS Hold Time
tCH
0
ns
Read Data Hold Time
tDHR
10
Write Data Hold Time
tDHW
0
ns
Muxed Address Valid to AS or ALE
Fall
tASL
15
ns
Muxed Address Hold Time
tAHL
10
ns
Delay Time DS, WR, or RD to AS or
ALE Rise
tASD
20
ns
PW ASH
30
ns
tASED
10
ns
tDDR
20
tDSW
50
Pulse Width AS or ALE High
Delay Time, AS or ALE to DS, WR,
or RD
Output Data-Delay Time from DS or
RD
Data Setup Time
20
63 of 76
50
140
ns
ns
ns
ns
DS21Q59 Quad E1 Transceiver
Figure 26-1. Intel Bus Read AC Timing (PBTS = 0)
t CYC
ALE
PWASH
t ASD
WR
t ASED
t ASD
RD
PWEL
PWEH
t CH
t CS
CS
t ASL
t DHR
t DDR
AD0–AD7
t AHL
Figure 26-2. Intel Bus Write Timing (PBTS = 0)
t CYC
ALE
PWASH
t ASD
RD
WR
t ASD
PWEL
t ASED
PWEH
t CH
t CS
CS
t ASL
t DHW
AD0–AD7
t AHL
64 of 76
t DSW
DS21Q59 Quad E1 Transceiver
Figure 26-3. Motorola Bus AC Timing (PBTS = 1)
PWASH
AS
DS
PWEH
t ASED
t ASD
PWEL
t CYC
t RWS
t RWH
R/W
AD0–AD7
t DDR
t ASL
t DHR
(READ)
t AHL
t CH
t CS
CS
AD0–AD7
t DSW
t ASL
(WRITE)
t DHW
t AHL
65 of 76
DS21Q59 Quad E1 Transceiver
26.2
Nonmultiplexed Bus AC Characteristics
Table 26-B. AC Characteristics—Nonmultiplexed Parallel Port
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-4 through Figure 26-7)
PARAMETER
SYMBOL
Setup Time for A0 to A7, Valid to CS Active
t1
0
ns
t2
0
ns
Setup Time for CS Active to Either RD, WR,
or DS Active
Delay Time from Either RD or DS Active to
Data Valid
Hold Time from Either RD, WR, or DS
Inactive to CS Inactive
Hold Time from CS Inactive to Data Bus
Tri-State
Wait Time from Either WR or DS Active to
Latch Data
Data Setup Time to Either WR or DS
Inactive
Data Hold Time from Either WR or DS
Inactive
Address Hold from Either WR or DS
Inactive
CONDITIONS
MIN
TYP
t3
140
t5
5.0
t6
75
ns
t7
10
ns
t8
10
ns
t9
10
ns
D0–D7
ns
20
DATA VALID
5ns MIN/20ns MAX
t5
WR
0ns MIN
CS
0ns MIN
RD
t2
ns
0
ADDRESS VALID
t1
UNITS
t4
Figure 26-4. Intel Bus Read Timing (PBTS = 0)
A0–A7
MAX
t3
75ns MAX
66 of 76
t4
0ns MIN
ns
DS21Q59 Quad E1 Transceiver
Figure 26-5. Intel Bus Write Timing (PBTS = 0)
A0–A7
ADDRESS VALID
D0–D7
t7
10ns
MIN
RD
t1
CS
0ns MIN
t8
10ns
MIN
0ns MIN
t2
t6
75ns MIN
WR
t4
0ns MIN
Figure 26-6. Motorola Bus Read Timing (PBTS = 1)
ADDRESS VALID
A0–A7
DATA VALID
D0–D7
5ns MIN/20ns MAX
t5
R/W
t1
0ns MIN
CS
0ns MIN
t2
t3
t4
0ns MIN
75ns MAX
DS
Figure 26-7. Motorola Bus Write Timing (PBTS = 1)
ADDRESS VALID
A0–A7
D0–D7
10ns
MIN
R/W
t1
t7 t8
10ns
MIN
0ns MIN
CS
0ns MIN
DS
t2
t6
75ns MIN
67 of 76
t4
0ns MIN
DS21Q59 Quad E1 Transceiver
26.3
Serial Port
Table 26-C. AC Characteristics—Serial Port (BTS1 = 1, BTS0 = 0)
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-8)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
50
ns
tCSS
Setup Time CS to SCLK
Setup Time SDI to SCLK
tSSS
50
ns
Hold Time SCLK to SDI
tSSH
50
ns
SCLK High/Low Time
tSLH
200
ns
SCLK Rise/Fall Time
tSRF
50
ns
50
ns
tLSC
SCLK to CS Inactive
250
ns
tCM
CS Inactive Time
SCLK to SDO Valid
tSSV
50
ns
SCLK to SDO Tri-State
tSSH
100
ns
100
ns
tCSH
CS Inactive to SDO Tri-State
Figure 26-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0)
tCM
CS
1
tSRF
tCSS
tLSC
tSLH
SCLK
2
SCLK
tSSS
SDI
tSSH
LSB
tCSH
MSB
LSB
MSB
tSSV
SDO
HIGH-Z
LSB
NOTE 1: OCES = 1 AND ICES = 0.
NOTE 2: OCES = 0 AND ICES = 1.
68 of 76
tSSH
MSB
HIGH-Z
DS21Q59 Quad E1 Transceiver
26.4
Receive AC Characteristics
Table 26-D. AC Characteristics—Receiver
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-9 and Figure 26-10)
PARAMETER
SYMBOL
CONDITIONS
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
MIN
TYP
648
488
244
122
61
0.5 tSP
0.5 tSP
MAX
UNITS
SYSCLK Period
tSP
SYSCLK Pulse Width
tSH
tSL
20
20
RSYNC Setup to SYSCLK Falling
tSU
20
ns
RSYNC Hold from SYSCLK Falling
tHD
20
ns
RSYNC Pulse Width
tPW
50
ns
Delay RCLK to RSER Valid
tD1
50
ns
Delay RCLK to RSYNC, OUTA, OUTB
tD2
50
ns
Delay SYSCLK to RSER Valid
tD3
22
ns
Delay SYSCLK to RSYNC, OUTA,
OUTB
tD4
22
ns
Note 1: SYSCLK = 1.544MHz.
Note 2: SYSCLK = 2.048MHz.
Note 3: SYSCLK = 4.096MHz.
Note 4: SYSCLK = 8.192MHz.
Note 5: SYSCLK = 16.384MHz.
69 of 76
ns
ns
DS21Q59 Quad E1 Transceiver
Figure 26-9. Receive AC Timing (Receive Elastic Store Disabled)
1
OUTA/OUTB (RCLK)
2
OUTA/OUTB (RCLK)
t D1
MSB OF
CHANNEL 1
RSER
tD2
3
RSYNC
4
OUTA/OUTB
5
OUTA/OUTB
NOTE 1: OUTA OR OUTB CONFIGURED TO OUTPUT RCLK (NONINVERTED).
NOTE 2: OUTA OR OUTB CONFIGURED TO OUTPUT RCLK (INVERTED).
NOTE 3: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 4: OUTA OR OUTB CONFIGURED TO OUTPUT RFSYNC, CRC4 MF SYNC, OR CAS MF SYNC (NONINVERTED).
NOTE 5: OUTA OR OUTB CONFIGURED TO OUTPUT RFSYNC, CRC4 MF SYNC, OR CAS MF SYNC (INVERTED).
70 of 76
DS21Q59 Quad E1 Transceiver
Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled)
tR
t SL
tF
t SH
SYSCLK
t SP
t D3
RSER
MSB OF
CHANNEL 1
t D4
1
RSYNC
2
OUTA/OUTB
t HD
t SU
3
RSYNC
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0).
NOTE 2: OUTA OR OUTB CONFIGURED AS CRCR MF SYNC OR CAS MF SYNC.
NOTE 3: RSYNC IS IN THE INPUT MODE (RCR.5 = 1).
71 of 76
DS21Q59 Quad E1 Transceiver
26.5
Transmit AC Characteristics
Table 26-E. AC Characteristics—Transmit
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-11 and Figure 26-12)
PARAMETER
TCLK Period
TCLK Pulse Width
SYSCLK Period
SYMBOL
tCP
CONDITIONS
(Note 1)
MIN
(Note 2)
TYP
648
20
0.5 tCP
tCL
20
0.5 tCP
(Note 1)
648
(Note 2)
488
(Note 3)
244
(Note 4)
122
(Note 5)
61
UNITS
ns
488
tCH
tSP
MAX
ns
ns
tSH
20
0.5 tSP
tSL
20
0.5 tSP
TSYNC Setup to TCLK
tSU
20
ns
TSYNC Pulse Width
tPW
50
ns
tSU
20
ns
tHD
20
ns
SYSCLK Pulse Width
TSER Setup to TCLK or SYSCLK
Falling
TSER Hold from TCLK or
SYSCLK Falling
TCLK Rise and Fall Times
tR, tF
ns
25
Note 1: SYSCLK = 1.544MHz.
Note 2: SYSCLK = 2.048MHz.
Note 3: SYSCLK = 4.096MHz.
Note 4: SYSCLK = 8.192MHz.
Note 5: SYSCLK = 16.384MHz.
72 of 76
ns
DS21Q59 Quad E1 Transceiver
Figure 26-11. Transmit AC Timing (IBO Disabled)
t CP
tR
t CL
tF
t CH
TCLK
SU
TSER
t D2
1
TSYNC
t HD
t SU
2
TSYNC
t D2
3
OUTA/OUTB
NOTE 1: TSYNC IS IN OUTPUT MODE (TCR.0 = 1).
NOTE 2: TSYNC IS IN INPUT MODE (TCR.0 = 0). TSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG AS IT
TRANSITIONS LOW AT LEAST TWO CLOCK CYCLES BEFORE TRANSITIONING HIGH AGAIN.
NOTE 3: APPLIES TO OUTA AND OUTB WHEN CONFIGURED FOR TPOS AND TNEG OUTPUTS.
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DS21Q59 Quad E1 Transceiver
Figure 26-12. Transmit AC Timing (IBO Enabled)
t SP
t SH
t SL
tF
tR
SYSCLK
tSU
TSER
t HD
NOTE: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF SYSCLK WHEN THE IBO MODE IS ENABLED.
26.6
Special Modes AC Characteristics
Table 26-F. AC Characteristics—Special Modes
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-13)
PARAMETER
SYMBOL
RTIP Period
CONDITIONS
MIN
tCP
TYP
MAX
488
UNITS
ns
tCH
75
tCL
75
RTIP Setup to RRING Falling
tSU
20
ns
TSER Hold from TCLK Falling
tHD
20
ns
RTIP Pulse Width
RTIP, RRING Rise and Fall Times
tR, tF
25
Special Mode: OUTBC.7 = 1.
Note: RTIP and RRING become NRZ data and clock inputs.
Figure 26-13. NRZ Input AC Timing
tR
tF
RTIP
SU
ns
t CL
t CH
t CP
t HD
RRING
74 of 76
ns
DS21Q59 Quad E1 Transceiver
27.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
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DS21Q59 Quad E1 Transceiver
28.
REVISION HISTORY
DATE
DESCRIPTION
042403
New product release.
1) Add 16MHz IBO timing diagram and AC characteristics
2) Correct typos in Figure 26-10. Reference to RSYNC as an input, not an output as
shown in Note 3.
3) Added clarification to Section 23 regarding the TSYNCx pin when the part is configured
for IBO mode.
4) Modified Table 26-D for clarification and corrected values.
5) Modified Table 26-E for clarification and corrected values.
6) Added tHD parameter to Figure 26-12.
7) Added Notes to Figures 24-3, 24-4, 24-6, 24-7, 26-11 regarding the duration of the Sync
pin when configured as an input.
8) Corrected typo on Figure 24-4 Note 3, incorrect bit value for RSYNC configured as an
input. (should be RCR.5 = 1).
090104
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products · Printed USA
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