DS2417P+T&R;

DS2417 1-Wire Time Chip with Interrupt FEATURES            Real-time clock (RTC) with fully compatible 1-Wire® MicroLAN interface Uses the same binary time/date representation as the DS2404 but with 1 second resolution Clock accuracy ±2 minutes per month at 25°C Programmable interrupt output for system wakeup Communicates at 16.3kbits per second Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike 8-bit family code specifies device communication requirements to bus master Built-in multidrop controller ensures compatibility with other MicroLAN products Operates over a wide VDD voltage range of 2.5V to 5.5V from -40°C to +85°C Low power, 200nA typically with oscillator running Compact, low cost 6-pin TSOC and Flip-Chip surface mount package PIN ASSIGNMENT 1 6 2 5 3 4 6 5 4 Flip Chip, Top View with Laser Mark, Contacts Not Visible. “rrd” = Revision/Date #xx = Lot Number DS2417 rrd#xx 1 2 TSOC 150 mil Top view 3 PIN DESCRIPTION Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 GND 1-Wire INT VDD X1 X2 ORDERING INFORMATION DS2417P DS2417P/T&R DS2417P+ DS2417P+T&R DS2417X 6-pin TSOC package TSOC Package, Tape & Reel 6-pin TSOC Package TSOC Package, Tape & Reel Flip-Chip, 10k Tape & Reel + Denotes a lead(Pb)-free/RoHS-compliant package. DESCRIPTION The DS2417 1-Wire Time Chip with Interrupt offers a simple solution for storing and retrieving vital time information with minimal hardware. The DS2417 contains a unique lasered ROM and a real-time clock/calendar implemented as a binary counter. Only one pin is required for communication with the device. Utilizing a backup energy source, the data is nonvolatile and allows for stand-alone operation. The DS2417 features can be used to add functions such as calendar, time and date stamp, and logbook to any type of electronic device or embedded application that uses a microcontroller. 1 of 15 19-8222; Rev 2; 3/16 DS2417 OVERVIEW The DS2417 has two main data components: 1) 64-bit lasered ROM, and 2) real-time clock counter (Figure 1). The real-time clock utilizes an on-chip oscillator that is connected to an external 32.768kHz crystal. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. The protocol for these ROM functions is described in Figure 7. After a ROM function command is successfully executed, the real-time clock functions become accessible and the master may then provide one of the real-time clock function commands. The protocol for these commands is described in Figure 5. All data is read and written least significant bit first. DETAILED PIN DESCRIPTION PIN 1 2 3 4 5, 6 SYMBOL GND 1-Wire INT VDD X1, X2 DESCRIPTION Ground Pin Data input/output Open drain. Interrupt pin Open drain. Power input pin. 2.5V to 5.5V. Crystal pins. Connections for a standard 32.768kHz quartz crystal, EPSON part number C-002RX or C-004R (be sure to request 6pF load capacitance). NOTE: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. See Figure 10 and Application Note 58 for details. BLOCK DIAGRAM Figure 1 1-WIRE INT ROM FUNCTION CONTROL 64-BIT LASERED ROM CLOCK FUNCTION CONTROL INT\ READ/WRITE BUFFER INT. GENERATOR RTC COUNTER (32-BIT) VDD OSCILLATOR CONTROL 32.768 kHz OSC./DIVIDER X1 Page 2 of 15 X2 1 Hz DS2417 64-BIT LASERED ROM Each DS2417 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros. The 64-bit ROM and ROM Function Control section allow the DS2417 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section "1Wire Bus System". HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 1-Wire Bus Bus Master Other Devices DS2417 Command Level 1-Wire ROM Function Commands (see Figure 7) DS2417 specific Function Commands (see Figure 5) Available Commands Data Fields Affected Read ROM Match ROM Search ROM Skip ROM 64-bit ROM 64-bit ROM 64-bit ROM N/A Write Clock Read Clock RTC Counter, Device Control RTC Counter, Device Control 64-BIT LASERED ROM Figure 3 MSB LSB 8-Bit CRC Code MSB 48-Bit Serial Number LSB MSB 8-Bit Family Code (27h) LSB Page 3 of 15 MSB LSB DS2417 1-WIRE CRC GENERATOR Figure 4 Polynomial = X8 + X5 + X4 + 1 R 1ST STAGE X0 2ND STAGE X2 X1 5TH STAGE 4TH STAGE 3RD STAGE 6TH STAGE X5 X4 X3 S X6 7TH STAGE 8TH STAGE X7 X8 INPUT DATA TIMEKEEPING A 32.768kHz crystal oscillator is used as the time base for the real-time clock counter. The oscillator can be turned on or off under software control. The oscillator must be on for the real-time clock to function. The real-time clock counter is double buffered. This allows the master to read time without the data changing while it is being read. To accomplish this, a snapshot of the counter data is transferred to a read/write buffer, which the user accesses. DEVICE CONTROL BYTE The DS2417 can generate interrupt pulses to trigger activities that have to occur at regular intervals. The selection of this interval and the on/off control of the 32.768kHz crystal oscillator are done through the device control byte. This byte can be read and written through the Clock Function commands. Device Control Byte 7 6 5 IE IS2 IS1 Bit 0 - 1 0 4 IS0 3 OSC 2 OSC 1 0 0 0 No function Bits 0 and 1 are hard-wired to read all 0’s. Bit 2 - 3 OSC Oscillator Enable/Disable These bits control/report whether the 32.768kHz crystal oscillator is running. If the oscillator is running, both OSC bits will read 1. If the oscillator is turned off these bits will all read 0. When writing the device control byte both occurrences of the OSC bit should have identical data. Otherwise, the value in bit address 3 (bold) takes precedence. Page 4 of 15 DS2417 Bit 4 - 6 IS Interval Select These bits determine the time between interrupt pulses. The values available are shown below. IS2 IS1 IS0 Interrupt Interval 0 0 0 1s 0 0 1 4s 0 1 0 32s = 0.53 min. 0 1 1 64s = 1.07 min. 1 0 0 2048s = 34.13 min. 1 0 1 4096s = 68.27 min. 1 1 0 65536s = 18.20 hours 1 1 1 131072s = 36.41 hours Bit 7 IE Interrupt Enable This bit controls whether the interrupt pulse will be generated at the selected interval. To enable interrupts this bit needs to be 1. REAL-TIME CLOCK The real-time clock is a 32-bit binary counter. It is incremented once per second. The real-time clock can accumulate 136 years of seconds before rolling over. Time/date is represented by the number of seconds since a reference point, which is determined by the user. For example, 12:00 a.m., January 1, 1970 could be a reference point. CLOCK FUNCTION COMMANDS The “Clock Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the real-time clock. With only four bytes of real-time clock and one control byte the DS2417 does not provide random access. Reading and writing always starts with the device control byte followed by the least significant byte of the time data. READ CLOCK [66h] The read clock command is used to read the device control byte and the contents of the real-time clock counter. After having received the most significant bit of the command code the device copies the actual contents of the real-time clock counter to the read/write buffer. Now, the bus master reads data beginning with the device control byte followed by the least significant byte through the most significant byte of the real-time clock. After this the bus master may continue reading from the DS2417. The data received will be the same as in the first pass through the command flow. The read clock command can be ended at any point by issuing a Reset Pulse. WRITE CLOCK [99h] The write clock command is used to set the real-time clock counter and to write the device control byte. After issuing the command, the bus master writes first the device control byte, which becomes immediately effective. After this the bus master sends the least significant byte through the most significant byte to be written to the real-time clock counter. The new time data is copied from the read/write buffer to the real-time clock counter and becomes effective as the bus master generates a reset pulse. If enabled, an interrupt pulse will be generated either immediately or delayed, depending on the actual time and the selected interval duration (see Figure 11). If the oscillator is intentionally stopped the real-time clock counter behaves as a four-byte nonvolatile memory. Page 5 of 15 DS2417 CLOCK FUNCTION COMMAND FLOW CHART Figure 5 Master TX Control Function Command 66H Read Clock ? Y 99H Write Clock ? Y N DS2417 copies RTC Counter to R/W Buffer N Bus Master TX Device Control Byte Bus Master RX Device Control Byte Bus Master TX LS Byte (7:0) Bus Master RX LS Byte (7:0) Bus Master TX next Byte (15:8) Bus Master RX next Byte (15:8) Bus Master TX next Byte (23:16) Bus Master RX next Byte (23:16) Bus Master TX MS Byte (31:24) Bus Master RX MS Byte (31:24) N N Bus Master TX Reset ? Y Bus Master TX Reset ? Y DS2417 copies R/W Buffer to RTC Counter DS2417 TX Presence Pulse Page 6 of 15 N Bus Master TX Reset ? Y DS2417 HARDWARE CONFIGURATION Figure 6 BUS MASTER Open Drain Port Pin DS2417 1-WIRE PORT VPUP 5 kΩ Typ. DATA RX TX TX RX = RECEIVE TX = TRANSMIT RX 5 µA Typ. 100 Ω MOSFET 1-WIRE BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS2417 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire input of the DS2417 is open drain with an internal circuit equivalent to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3kbits per second and requires a pullup resistor of approximately 5kΩ. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120µs, one or more of the devices on the bus may be reset. Since the DS2417 gets all its energy for operation through its VDD pin it will NOT perform a power-on reset if the 1-Wire bus is low for an extended time period. TRANSACTION SEQUENCE The protocol for accessing the DS2417 via the 1-Wire port is as follows:  Initialization  ROM Function Command  Clock Function Command Page 7 of 15 DS2417 INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2417 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four ROM function commands that the DS2417 supports. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 7): Read ROM [33h] This command allows the bus master to read the DS2417’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number read by the master will be invalid. Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2417 on a multidrop bus. Only the DS2417 that exactly matches the 64-bit ROM sequence will respond to the following clock function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this three-step routine on each bit of the ROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify the ROM codes of the remaining devices. See Application Note 187 for a comprehensive discussion of a search ROM, including an actual example. Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the clock functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result). Page 8 of 15 DS2417 ROM FUNCTIONS FLOW CHART Figure 7 Master TX Reset Pulse DS2417 TX Presence Pulse Master TX ROM Function Command 33H Read ROM Command ? Y DS2417 TX Family Code 1 Byte N 55H Match ROM Command ? F0H Search ROM Command ? Y N Y DS2417 TX Bit 0 Master TX Bit 0 DS2417 TX Bit 0 Master TX Bit 0 Bit 0 Match ? N N Bit 0 Match ? Y Y DS2417 TX Serial Number 6 Bytes DS2417 TX Bit 1 Master TX Bit 1 Bit 1 Match ? N DS2417 TX Bit 1 Master TX Bit 1 N Bit 1 Match ? Y Y DS2417 TX Bit 63 DS2417 TX CRC Byte Master TX Bit 63 DS2417 TX Bit 63 Master TX Bit 63 Bit 63 Match ? N N Bit 63 Match ? Y Y Master TX Control Function Command (SEE FIGURE 5) Page 9 of 15 N CCH Skip ROM Command ? Y N DS2417 1–WIRE SIGNALING The DS2417 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read Data. Except for the presence pulse the bus master initiates all these signals. The initialization sequence required to begin any communication with the DS2417 is shown in Figure 8. A reset pulse followed by a presence pulse indicates the DS2417 is ready to send or receive data. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480µs). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After detecting the rising edge on the data line, the DS2417 waits (tPDH, 15μs to 60μs) and then transmits the presence pulse (tPDL, 60μs to 240μs). INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 8 MASTER TX "RESET PULSE" MASTER RX "PRESENCE PULSE" tRSTH VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V tRSTL RESISTOR MASTER DS2417 * ** tR tPDH tPDL 480 µs ≤ tRSTL < ∞* 480 µs ≤ tRSTH < ∞** 15 µs ≤ tPDH < 60 µs 60 ≤ tPDL < 240 µs In order not to mask interrupt signaling by other devices on the 1-Wire bus tRSTL + tR should always be less than 960µs. Includes recovery time READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 9. The master initiates all time slots by driving the data line low. The falling edge of the data line synchronizes the DS2417 to the master by triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS2417 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit determines how long the DS2417 will hold the data line low. If the data bit is a “1”, the DS2417 will not hold the data line low at all. Page 10 of 15 DS2417 READ/WRITE TIMING DIAGRAM Figure 9 Write-one Time Slot tSLOT VPULLUP tREC VPULLUP MIN VIH MIN DS2417 Sampling Window VIL MAX 0V tLOW1 15µs (OD: 2µs) 60µs RESISTOR MASTER (OD: 6µs) 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOW1 < 15 µs 1 µs ≤ tREC < ∞ Write-zero Time Slot tSLOT VPULLUP VPULLUP MIN VIH MIN DS2417 Sampling Window VIL MAX 0V 15µs (OD: 2µs) RESISTOR MASTER (OD: 6µs) 60µs t LOW0 60 µs ≤ tLOW0 < tSLOT < 120 µs 1 µs ≤ tREC < ∞ Page 11 of 15 tREC DS2417 READ/WRITE TIMING DIAGRAM (continued) Figure 9 Read-data Time Slot tREC tSLOT VPULLUP VPULLUP MIN VIH MIN Master Sampling Window VIL MAX 0V tSU tRELEASE tLOWR tRDV 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOWR < 15 µs 0 ≤ tRELEASE < 45 µs RESISTOR 1 µs ≤ tREC < ∞ tRDV = 15 µs tSU < 1 µs MASTER DS2417 CRYSTAL PLACEMENT ON PCB Figure 10 LOCAL GROUND PLANE BENEATH SIGNAL PLANE OR ON OTHER SIDE OF PCB GND X1 CRYSTAL PADS 1-Wire INT\ X2 VDD GUARD RING ON SIGNAL PLANE Page 12 of 15 DS2417 INTERRUPT TIMING Figure 11 VINT Case A: Latency < 0.5 t INTERVAL t LATENCY VINT t INTERVAL t PULSE = 122 µs Time Case B: 0 < Latency < t INTERVAL t LATENCY t INTERVAL t PULSE = 122 µs Time The latency depends on the selected interrupt interval (IS0 to IS2 settings) and the contents of the RTC counter at the time of writing the device control byte. In Case A, the flip-flop that determines the interval duration is reset and toggles before half of the interval time is over. In Case B, this flip-flop is set that generates an immediate interrupt pulse; the latency, therefore, can be up to one full interval duration. If enabled, the interrupt pulse may also be triggered while reading from or writing to the control byte. Page 13 of 15 DS2417 ABSOLUTE MAXIMUM RATINGS* Voltage on 1-Wire to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.5V to +7.0V -40°C to +85°C -55°C to +125°C See J-STD-020A Specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (VPUP = 2.5V to 6.0V; VDD = 2.5V to 5.5V, -40°C to +85°C) PARAMETER Logic 1 Logic 0 Output Logic Low @ 4mA Output Logic High Input Load Current Interrupt Sink Current @ 0.4V Operating Current (Osc. On) Quiescent Current (Osc. Off) Interrupt Sink Current @ 0.4V Operating Current (Osc. On) Quiescent Current (Osc. Off) SYMBOL VIH1 VIL1 VOL1 VOH1 IL1 IINT3 IDD3 IDDQ3 IINT5 MIN 2.2 -0.3 TYP MAX 6.0 UNITS V V V V µA mA NOTES 1, 11 1, 6 1 1, 3 4 9 250 50 nA nA mA 2, 9 2, 8, 9 10 450 100 nA nA 2, 10 2, 8, 10 0.8 0.4 VPUP 5 5 10 IDD5 IDDQ5 CAPACITANCE PARAMETER Capacitance 1-Wire (TA = 25°C) SYMBOL CIN MIN TYP MAX 50 UNITS pF NOTES AC ELECTRICAL CHARACTERISTICS (VPUP = 2.5V to 6.0V; VDD = 2.5V to 5.5V, -40°C to +85°C) PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset High Time Reset Low Time Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 60 1 60 1 0 1 480 480 15 60 Page 14 of 15 TYP 15 15 MAX 120 15 120 15 45 1 960 60 240 UNITS µs µs µs µs µs µs µs µs µs µs µs µs NOTES 13 13 12 5 7 DS2417 NOTES: 1. 2. 3. 4. 5. All voltages are referenced to ground. Measured with outputs open. VPUP = external pullup voltage. Input load is to ground. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 µs of this falling edge. 6. Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse. 7. The reset low time (tRSTL) should be restricted to a maximum of 960µs, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 8. When VDD ramps up, the oscillator is always off. 9. At VDD = 3V ± 10% 10. At VDD = 5V ± 10% 11. VIH1 has to be VDD – 0.3V or higher. 12. The optimal sampling point for the master is as close as possible to the end time of the 15μs tRDV period without exceeding tRDV. For the case of a Read-One Time Slot, this maximizes the amount of time for the pull-up resistor to recover to a high level. For a Read-Zero Time Slot, it ensures that a read will occur before the fastest 1-Wire device(s) release the line. 13. The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value as short as possible to allow time for the pull-up resistor to recover the line to a high level before the 1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a Read-One Time. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 6 TSOC D6+1 21-0382 6 Flip Chip BF611-2 21-0289 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2016 Maxim Integrated 15 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. Page 15 of 15