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DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
General Description
Benefits and Features
The DS2477 secure I2C coprocessor with built-in 1-Wire®
master combines FIPS202-compliant secure hash algorithm (SHA-3) challenge and response authentication with
Maxim’s patented ChipDNA™ feature, a physically unclonable technology (PUF) to provide a cost-effective solution
with the ultimate protection against security attacks. The
ChipDNA implementation utilizes the random variation of
semiconductor device characteristics that naturally occur
during wafer fabrication. The ChipDNA circuit generates a
unique output value that is repeatable over time, temperature, and operating voltage. Attempts to probe or observe
ChipDNA operation modifies the underlying circuit characteristics thus preventing discovery of the unique value
used by the chip cryptographic functions. The DS2477 utilizes the ChipDNA output as key content to cryptographically secure all device-stored data. With ChipDNA capability, the device provides a core set of cryptographic
tools derived from integrated blocks including a SHA-3 engine, a FIPS/NIST compliant true random number generator (TRNG), 2Kb of secured EEPROM, and a unique
64-bit ROM identification number (ROM ID). The unique
ROM ID is used as a fundamental input parameter for
cryptographic operations and serves as an electronic serial number within the application. The DS2477 provides
the SHA-3 and memory functionality required by a host
system to communicate with and operate a 1-Wire SHA-3
slave. In addition, it performs protocol conversion between
the I2C master and any attached 1-Wire SHA-3 slaves.
For 1-Wire line driving, internal user-adjustable timers relieve the system host processor from generating time-critical 1-Wire waveforms, supporting both standard and overdrive 1-Wire communication speeds. The 1-Wire line can
be powered down under software control. Strong pullup
features support 1-Wire power delivery for commands that
require higher current consumption.
● Robust Countermeasures Protect Against Security
Attacks
• Patented Physically Unclonable Function Secures
Device Data
• Actively Monitored Die Shield Detects and Reacts
to Intrusion Attempts
• All Stored Data Cryptographically Protected from
Discovery
Applications
●
●
●
●
●
●
Authentication of Medical Sensors and Tools
Secure Management of Limited Use Consumables
IoT Node Authentication
Peripheral Authentication
Reference Design License Management
Printer Cartridge Identification and Authentication
● Efficient Secure Hash Algorithm Authenticates and
Manages Peripherals
• FIPS 202-Compliant SHA-3 Algorithm for
Bidirectional Authentication
• FIPS 198-Compliant Keyed-Hash Message
Authentication Code (HMAC)
• TRNG with NIST SP 800-90B Compliant Entropy
Source
● Supplemental Features Enable Easy Integration into
End Applications
• 2Kb of EEPROM for User Data, Key, and Control
Registers
• One Open-Drain GPIO Pin
• Unique and Unalterable Factory-Programmed
64-Bit Identification Number (ROM ID)
• Large 1-Wire Block Buffer (126 Bytes) for Efficient
Data Transfer
• 1-Wire Standard and Overdrive Timing
Communication Speeds
• I2C Communication, up to 1MHz
• Operating Range: 3.3V ±10%, -40°C to +85°C
• 6-Pin TDFN-EP Package (3mm x 3mm)
Request DS2477
Security User Guide
Ordering Information appears at end of data sheet.
1-Wire is a registered trademark and ChipDNA is a trademark of Maxim Integrated Products, Inc.
19-100402; Rev 2; 11/20
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Typical Application Circuit
VCC
RP3
RP1
RP2
GPIO
VCC
I2 C
µC
VCC
PORT
DS2477
SDA
SCL
GND
GND
IO
IO
IO
IO
GPIO
IO
DS28E50
CEXT
GND
www.maximintegrated.com
IO
GPIO
IO
DS28E50
CX
CEXT
GND
GPIO
IO
DS28E50
CX
CEXT
GND
CX
Maxim Integrated | 2
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 TDFN-EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Design Resource Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Open-Drain GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1-Wire Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transaction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1-Wire Signaling and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read/Write Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Master-to-Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Slave-to-Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Strong Pullup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Active Pullup (APU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Active Pullup for 1-Wire Reset Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Active Pullup for Read/Write Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bus Idle or Not Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STOP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Repeated START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
www.maximintegrated.com
Maxim Integrated | 3
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
LIST OF FIGURES
Figure 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. 1-Wire Reset/Presence-Detect Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Read/Write Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Strong Pullup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Active Pullup for a 1-Wire Reset Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Active Pullup for 1-Wire Write Time Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Active Pullup for 1-Wire Read Time Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. I2C Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. DS2477 I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
www.maximintegrated.com
Maxim Integrated | 4
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND ........... -0.5V to 4.0V
Maximum Current into Any Pin............................ -20mA to 20mA
Operating Temperature Range ............................ -40°C to +85°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ..............................-40°C to +125°C
Lead Temperature (soldering, 10s)................................... +300°C
Soldering Temperature (reflow) ........................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
6 TDFN-EP
Package Code
T633+2
Outline Number
21-0137
Land Pattern Number
90-0058
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
55°C/W
Junction to Case (θJC)
9°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
42°C/W
Junction to Case (θJC)
9°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
PARAMETER
Supply Voltage
Supply Current
1-Wire Input High
Low-to-High Switching
Threshold
www.maximintegrated.com
SYMBOL
VCC
ICC
VIH1
VTH
CONDITIONS
(Note 1)
MIN
TYP
MAX
2.97
3.3
3.63
V
400
μA
10
mA
Standby
Communicating/active (Note 2)
Low configuration
0.6 x
VCC
Medium configuration
0.6 x
VCC
High configuration
0.85 x
VCC
UNITS
V
Low configuration (Note 3, Note 4)
0.25 x
VCC
Medium configuration (Note 3, Note 4)
0.4V x
VCC
High configuration (Note 3, Note 4)
0.75 x
VCC
V
Maxim Integrated | 5
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
PARAMETER
1-Wire Input Low
SYMBOL
VIL1
CONDITIONS
Medium configuration
0.3 x
VCC
High configuration
0.3 x
VCC
(Note 3, Note 5)
Switching Hysteresis
VHY
(Note 3, Note 6)
1-Wire Output Low
VOL1
0.65 x
VCC
0.3
VIAPO
Active Pullup on Time
(Note 3, Note 8)
tAPU
Active Pullup
Impedance
RAPU
Operation Time
tOP
333
UNITS
V
V
V
Ultra-low range
250
Low range
375
500
750
High range
750
1000
1400
External high impedance
Active Pullup on
Threshold
MAX
Low configuration
VTL
RWPU
TYP
0.15 x
VCC
High-to-Low Switching
Threshold
1-Wire Weak Pullup
Resistor (Note 3, Note
7)
MIN
675
Ω
10M
VCC = 2.97V, 4mA sink current
0.28
Low configuration (Note 3)
0.25 x
VCC
Medium configuration (Note 3)
0.4 x
VCC
High configuration (Note 3)
0.75 x
VCC
1-Wire standard speed (default value)
2.5
1-Wire overdrive speed (default value)
0.5
V
V
μs
VCC = 2.97V, 10mA load (Note 3)
50
Ω
(Note 3)
5
ms
IO PIN: 1-Wire TIMING (Note 9)
1-Wire Output Fall Time
(Note 3)
tF
Standard and overdrive
Reset Low Time
tRSTL
Standard and overdrive
-5%
Settable
+5%
μs
Reset High Time
tRSTH
Standard and overdrive (Note 10)
-5%
Settable
+5%
μs
Presence-Detect
Sample Time
tMSP
Standard and overdrive
-5%
Settable
+5%
μs
Sampling for Short and
Interrupt
tMSI
Standard and overdrive
-5%
Settable
+5%
μs
Write-One/Read Low
Time
tW1L
Standard and overdrive
-5%
Settable
+5%
μs
Read Sample Time
tMSR
Standard and overdrive
-5%
Settable
+5%
μs
Write-Zero Low Time
tW0L
Standard and overdrive
-5%
Settable
+5%
μs
Recovery Time
tREC
Standard and overdrive (Note 10)
-5%
Settable
+5%
μs
www.maximintegrated.com
Settable
μs
Maxim Integrated | 6
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
PARAMETER
1-Wire Time Slot
SYMBOL
CONDITIONS
MIN
TYP
MAX
Equal to
tW0L +
tREC
UNITS
tSLOT
Standard and overdrive
μs
Computation Current
ICMP
(Note 3, Note 11)
Computation Time
tCMP
(Note 3)
TRNG Generation
tRNG
TRNG On-Demand
Check
tODC
50
ms
CRYPTO FUNCTIONS
10
mA
5
ms
25
ms
EEPROM
Read Memory
tRM
50
ms
Write Memory
tWM
100
ms
Write State
tWS
15
ms
Write/Erase Cycles
(Endurance)
NCY
TA = +85°C (Note 12)
Data Retention
tDR
TA = +85°C (Note 13, Note 14)
100k
10
years
GPIO PIN
Output Low
GPIO VOL
Input Low
GPIO VIL
Input High
Leakage Current
GPIOIOL = 4mA (Note 15)
0.4
V
-0.3
0.2 x
VCC
V
GPIO VIH
0.7 x
VCC
VCC +
0.3
V
GPIO IL
-1
+1
μA
I2C SCL AND SDA PINS (Note 16)
Low-Level Input Voltage
VIL
-0.3
0.2 ×
VCC
V
High-Level Input Voltage
VIH
0.7 ×
VCC
VCC +
0.3V
V
Hysteresis of Schmitt
Trigger Inputs
VHYS
(Note 3)
Low-Level Output
Voltage at 4mA Sink
Current
VOL
(Note 15)
Output Fall Time from
VIH(MIN) to VIL(MAX)
with a Bus Capacitance
from 10pF to 400pF
tOF
(Note 3)
Pulse Width of Spikes
that are Suppressed by
the Input Filter
tSP
(Note 3)
www.maximintegrated.com
0.05 ×
VCC
V
0.4
30
V
ns
50
ns
Maxim Integrated | 7
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.)
PARAMETER
SYMBOL
CONDITIONS
Input Current with an
Input Voltage Between
0.1VCC(MAX) and
0.9VCC(MAX)
II
(Note 3, Note 17)
Input Capacitance
CI
(Note 3)
SCL Clock Frequency
fSCL
(Note 1)
Hold Time (Repeated)
START Condition
tHD:STA
Low Period of the SCL
Clock
tLOW
High Period of the SCL
Clock
MIN
TYP
-1
MAX
UNITS
+1
µA
10
0
pF
1
MHz
0.45
µs
(Note 18)
0.65
µs
tHIGH
(Note 3)
0.35
µs
Setup Time for a
Repeated START
Condition
tSU:STA
(Note 3)
0.35
µs
Data Hold Time
tHD:DAT
(Note 3, Note 18, Note 19)
Data Setup Time
tSU:DAT
(Note 3, Note 18, Note 20)
100
ns
Setup Time for STOP
Condition
tSU:STO
(Note 3)
0.35
µs
tBUF
(Note 3)
0.6
µs
Bus Free Time Between
a STOP and START
Condition
Capacitive Load for
Each Bus Line
Warm-Up Time
0.35
µs
CB
(Note 1, Note 21)
400
pF
tOSCWUP
(Note 1, Note 22)
1
ms
Note 1: System requirement.
Note 2: Operating current with 1-Wire write byte sequence followed by continuous write/read of 1-Wire Block command at 1MHz in
overdrive.
Note 3: Guaranteed by design and/or characterization only. Not production tested.
Note 4: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 5: Voltage below which, during a tF on IO, a logic-zero is detected.
Note 6: After VTH is crossed during a rising edge on IO for high configuration only, the voltage on IO must drop by at least VHY to be
detected as logic-zero.
Note 7: Active pullup or resistive pullup and range are configurable.
Note 8: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire reset cycle or during the recovery
after a short on the 1-Wire line.
Note 9: All 1-Wire timing specifications are derived from the same timing circuit.
Note 10: Up to an additional 10μs of idle high time may occur between a 1-Wire Reset Cycle and the first time slot or between each
1-Wire byte during a command sequence.
Note 11: Current drawn from VCC during the EEPROM programming interval or SHA-3 computation.
Note 12: Write-cycle endurance is tested in compliance with JESD47G.
Note 13: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 14: Data retention is tested in compliance with JESD47G.
Note 15: The I-V characteristic is linear for voltages less than 1V.
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Maxim Integrated | 8
DS2477
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
All I2C timing values are referred to VIH(MIN) and VIL(MAX) levels.
I/O pins of the DS2477 do not obstruct the SDA and SCL lines if VCC is switched off.
tLOW min = tHD:DAT max + 200ns for rise or fall time + tSU:DAT min. Values greater than these can be accommodated by
extending tLOW accordingly.
The DS2477 provides a hold time of at least 100ns for the SDA signal (referenced to the VIH(MIN) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
The DS2477 can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. Also,
the acknowledge timing must meet this setup time (I2C bus specification Rev. 03, 19 June 2007).
CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending
on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007).
I2C communication should not take place for the max tOSCWUP time following a power-on reset.
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Maxim Integrated | 9
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Pin Configuration
Top view
GPIO 1
IO 2
GND 3
+
EP
6 VCC
5 SDA
4 SCL
TDFN-EP
(3mm x 3mm)
Pin Description
PIN
NAME
1
GPIO
Open-Drain, General-Purpose Input/Output. Requires external pullup resistor to VCC when used
as an output.
2
IO
1-Wire Input/Output Driver. The 1-Wire line can be pulled up by an internal weak pullup (RWPU),
an external pullup, or have both an external pullup and internal weak pullup.
3
GND
Ground
4
SCL
I2C Serial Clock Input. Must be connected to VCC through a pullup resistor.
5
SDA
Open-Drain, I2C Serial Data Input/Output. Must be connected to VCC through a pullup resistor.
6
VCC
Power Supply Input
—
EP
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FUNCTION
Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer
to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
Maxim Integrated | 10
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Detailed Description
The DS2477 integrates the Maxim ChipDNA capability to protect all device stored data from invasive discovery. In
addition to the PUF, the device integrates a FIPS/NIST compliant TRNG, 2Kb EEPROM for user memory, secret storage,
and control registers. The self-timed 1-Wire master function supports advanced 1-Wire waveform features including
standard and overdrive speeds, active pullup, and strong pullup for power delivery. The active pullup affects rising edges
on the 1-Wire side. The strong pullup function uses the same pullup transistor as the active pullup, but with a different
control algorithm. Once supplied with command and data, the input/output controller of the DS2477 performs timecritical 1-Wire communication functions such as reset/presence-detect cycle, read-byte, write-byte, read-block, writeblock, single-bit R/W, triplets for ROM Search, and full command sequences for 1-Wire authenticators, without requiring
interaction with the host processor. The GPIO pin can be independently operated under command control. All secrets,
GPIO control, ROM memory, and user memory are located in a linear address space. The DS2477 communicates with
a host processor through its I2C bus interface in standard mode or in fast mode.
VCC
64-BIT ROM ID
SDA
SCL
I2 C
INFC
AND
CMD
BUFFER
SHA3-256
TRNG
2Kb E2 ARRAY
USER MEMORY
SHA3 SECRETS
REGISTERS
IO
1-WIRE
MASTER
XCVR
GPIO
ChipDNA
GPIO
DS2477
Figure 1. Block Diagram
Design Resource Overview
Operation of the DS2477 involves use of device EEPROM and execution of specified device commands. Refer to the
DS2477 Security User Guide for details.
Memory
A 2Kb secured EEPROM array provides SHA-3 secret storage and/or general-purpose, user-programmable memory.
Depending on the memory area, there are either default or user-programmable options to set protection modes.
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Maxim Integrated | 11
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Open-Drain GPIO
A dedicated volatile memory region is used to control and/or read the open-drain GPIO pin. Upon power-up, the GPIO
pin is high impedance. Refer to the DS2477 Security User Guide for details.
1-Wire Master
The 1-Wire master reports data and status from the 1-Wire side to the host processor. Refer to the DS2477 Security User
Guide for details.
Transaction Sequence
The protocol for accessing a connected slave device through the 1-Wire master is as follows:
●
●
●
●
Initialization
ROM Function command
Device Function command
Transaction/data
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset
pulse transmitted by the 1-Wire master followed by presence pulse(s) transmitted by the slave(s). The presence pulse
lets the bus master know that the slave is on the bus and is ready to operate. For more details, see the 1-Wire Signaling
and Timing section.
1-Wire Signaling and Timing
The 1-Wire protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse,
write-zero, write-one, and read-data. Except for the presence pulse, the 1-Wire master initiates all falling edges. The
1-Wire master can communicate at two speeds: standard and overdrive. While in overdrive mode, the fast timing applies
to all waveforms.
Figure 2 shows the initialization sequence required to begin any communication. A reset pulse followed by a presence
pulse indicates that a slave is ready to receive data, given the correct ROM and device function command.
MASTER TX “RESET PULSE”
MASTER RX “PRESENCE PULSE”
tMSP
tMSI
VCC
VIH1
VTH
APU SETTABLE
CONTROLLED EDGE
VTL
VIL1
0V
tF
tRSTL
RESISTOR (RWPU)
tRSTH
DS2477 PULLDOWN
1-WIRE SLAVE PULLDOWN
Figure 2. 1-Wire Reset/Presence-Detect Cycle
Read/Write Time Slots
Data communication on the 1-Wire bus takes place in time slots that carry a single bit each. Write time slots transport
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Maxim Integrated | 12
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
data from 1-Wire master to a connected slave. Read time slots transfer data from slave to the 1-Wire master. Figure 3
illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the
threshold VTL, the slave starts its internal timing generator that determines when the data line is sampled during a write
time slot and how long data is valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the write-one low
time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until
the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not
exceed VILMAX during the entire tW0L or tW1L window required by the slave. After the VTH threshold has been crossed,
the DS2477 needs a recovery time tREC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read
low time tRL(read low time) is expired. During the tRL window, when responding with a 0, the slave starts pulling the
data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When
responding with a 1, the slave does not hold the data line low at all, and the voltage starts rising as soon as tRL is over.
Note that the slave tRL during a logic 1 is adequately an approximation of the 1-Wire master tW1L setting.
The slave tRL plus the bus rise time on the near end and the internal timing generator of the slave on the far end define
the 1-Wire master sampling window, in which the 1-Wire master performs a read from the data line. After reading from
the data line, the 1-Wire master waits until tSLOT is expired. This guarantees sufficient recovery time tREC for the slave
to get ready for the next time slot. Note that tREC specified herein applies only to a single slave attached to a 1-Wire line.
For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device input capacitance.
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Maxim Integrated | 13
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
WRITE-ZERO TIME SLOT
tW0L
tMSR
VCC
VIH1
VTH
VTL
VIL1
0V
tF
tREC
tSLOT
RESISTOR (RWPU)
DS2477 PULLDOWN
WRITE-ONE/READ-DATA TIME SLOT
tMSR
tW1L
VCC
VIH1
VTH
VTL
VIL1
0V
tF
RECOVERY TIME WILL BE tREC OR LONGER DEPENDANT ON TIME SLOT TYPE
tSLOT
RESISTOR (RWPU)
DS2477 PULLDOWN
1-WIRE SLAVE PULLDOWN
Figure 3. Read/Write Timing Diagrams
Strong Pullup
The strong pullup function can be activated prior to a 1-Wire Write Byte, 1-Wire Read Byte, 1-Wire Single Bit, 1-Wire
Block or 1-Wire Write Block command. Strong pullup is commonly used with 1-Wire EEPROM devices when copying
buffer data to the main memory or when performing a SHA computation. The respective device data sheets specify
the location in the communications protocol after which the strong pullup should be applied. The strong pullup can be
enabled immediately prior to issuing the command that puts the 1-Wire device into the state where it needs the extra
power for primitive 1-Wire commands or as an integral part of advanced commands. The strong pullup uses the same
internal pullup transistor as the active pullup feature. See the RAPU parameter in the Electrical Characteristics table to
determine whether the voltage drop is low enough to maintain the required 1-Wire voltage at a given load current and
supply voltage. If the strong pullup is enabled, the DS2477 treats the rising edge of the time slot in which the strong pullup
starts as if the active pullup was activated. However, in contrast to the active pullup, the strong pullup (i.e., the internal
pullup transistor) remains conducting, as shown in Figure 4, until the DS2477 receives a command that generates 1-Wire
communication (the typical case), or until the strong pullup is disabled or the 1-Wire master is reset. When the strong
pullup ends, it is automatically disabled. Using the strong pullup feature does not change the active pullup settings.
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Maxim Integrated | 14
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
LAST BIT OF 1-WIRE WRITE BYTE, 1-WIRE READ BYTE, OR 1-WIRE SINGLE BIT
VCC
WRITE-ONE CASE
VIAPO
WRITE-ZERO CASE
0V
tSLOT
DS2477 RESISTOR (RWPU)
NEXT
TIME SLOT
DS2477 PULLDOWN
DS2477 STRONG PULLUP
Figure 4. Strong Pullup Timing
Active Pullup (APU)
The APU is a function that accelerates the rise-time during a 1-Wire reset cycle, write time slot, or read time slot.
The 1-Wire master triggering mechanism is always ready after the initial low time of a 1-Wire reset cycle or time slot
completes. This rise-time acceleration is accomplished by an active pullup impedance (RAPU) that begins driving once
the active pullup on threshold (VIAPO) is crossed from low to high. APU does not apply to the rising edge of a recovery
from a short on the line, a power-up presence pulse of a slave, or any other event outside of a 1-Wire reset cycle or a
time slot. Enabling APU is generally recommended for best 1-Wire performance.
Active Pullup for 1-Wire Reset Cycle
Figure 5 illustrates an active pullup for a 1-Wire reset cycle. A 1-Wire reset cycle begins by driving the line low for a
tRSTL period. When the tRSTL expires, the APU triggering mechanism is on and triggers when the VIAPO level is crossed
from low to high. APU then remains on for the remaining duration of tAPU. After the completion of tAPU, the APU trigger
mechanism is reset to be on again and triggers when the VIAPO level is crossed from low to high upon a presence pulse
completing. APU then remains on until the duration of tRSTH expires.
ACTIVE PULLUP FOR 1-WIRE RESET CYCLE
VCC
VIAPO
0V
tAPU
tRSTL
DS2477 RESISTOR (RWPU)
tRSTH
DS2477 PULLDOWN
DS2477 ACTIVE PULLUP
1-WIRE SLAVE PULLDOWN
Figure 5. Active Pullup for a 1-Wire Reset Cycle
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Maxim Integrated | 15
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Active Pullup for Read/Write Time Slots
Figure 6 illustrates an active pullup for a 1-Wire write-zero or write-one time slot. A write-zero time slot begins by the
1-Wire master driving the line low for a tW0L period. When the tW0L expires, the APU triggering mechanism is on and
triggers when the VIAPO level is crossed from low to high. APU then remains on until tREC expires. A write-one time slot
begins by the 1-Wire master driving the line low for a tW1L period. When the tW1L expires, the APU triggering mechanism
is on and triggers when the VIAPO level is crossed from low to high. Unlike the write-zero time slot, the write-one time
slot has APU for a much longer recovery duration defined by (tW0L - tW1L) + tREC.
ACTIVE PULLUP FOR WRITE
WRITE-ZERO
WRITE-ONE
VCC
VIAPO
0V
tW0L
tREC
tSLOT
DS2477 RESISTOR (RWPU)
DS2477 PULLDOWN
tW1L
(tW0L – tW1L) + tREC
tSLOT
DS2477 ACTIVE PULLUP
1-WIRE SLAVE PULLDOWN
Figure 6. Active Pullup for 1-Wire Write Time Slot
Figure 7 illustrates an active pullup for 1-Wire read time slots. On a 1-Wire read-zero time slot, the master pulls the line
low. The slave detects the low, and takes over driving the line. At that point, both the master and slave are driving the
line low until tW1L expires. After tW1L, the master turns on the normal pullup (RWPU), and enables the APU triggering
mechanism. The master samples the read data at tMSR. After the slave response time (tSPD) expires, the slave releases
the line. The APU triggers when the VIAPO level is crossed from low to high. The APU remains on until the end of the
slot as defined in Figure 7. On a 1-Wire read-one time slot, the master pulls the line low for tW1L. The slave detects the
low, but does not drive the line. When the tW1L expires, the master turns on the normal pullup, and enables the APU
triggering mechanism. The APU triggers when the VIAPO level is crossed from low to high. The APU remains on until the
end of the slot as defined by (tW0L - tW1L) + tREC. The read-one recovery time is longer than the read-zero case.
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Maxim Integrated | 16
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
ACTIVE PULLUP FOR READ
READ-ZERO
tMSR
VCC
tMSR
READ-ONE
tSPD
VIAPO
VTL(SLAVE)
0V
tW0L + tREC – (tF + tSPD)
tW1L
tW1L
tSLOT
DS2477 RESISTOR (RWPU)
DS2477 PULLDOWN
DS2477 ACTIVE PULLUP
tW0L + tREC – tW1L
tSLOT
1-WIRE SLAVE PULLDOWN
Figure 7. Active Pullup for 1-Wire Read Time Slot
I 2C
General Characteristics
The I2C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional
lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are
high. The output stages of devices connected to the bus must have an open drain or open collector to perform the wiredAND function. Data on the I2C bus can be transferred at rates of up to 100kbps in standard mode and up to 400kbps
in fast mode. The DS2477 works in both modes or up to a clock rate of 1MHz. A device that sends data on the bus is
defined as a transmitter, and a device receiving data is defined as a receiver. The device that controls the communication
is called a master. The devices that are controlled by the master are slaves. To be individually accessed, each device
must have a slave address that does not conflict with other devices on the bus. Data transfers can be initiated only when
the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and
STOP conditions, and determines the number of data bytes transferred between START and STOP Figure 8. Data is
transferred in bytes with the most significant bit being transmitted first. After each byte follows an acknowledge bit to
allow synchronization between master and slave.
Slave Address
The slave address to which the DS2477 responds is shown in Figure 9. The slave address is part of the slave address/
control byte. The last bit of the slave address/control byte (R/W) defines the data direction. When set to 0, subsequent
data flows from master to slave (write access); when set to 1, data flows from slave to master (read access).
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Maxim Integrated | 17
DS2477
IDLE
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
S
MSB FIRST
LSB
MSB
P
LSB
MSB
SDA
SLAVE
ADDRESS
SCL
R/W
ACK
8
9
1-7
DATA
1-7
8
ACK/
NACK
DATA
ACK
9
1-7
8
9
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 8. I2C Protocol Overview
7-BIT SLAVE ADDRESS
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
0
1
1
MSB
R/W
DETERMINES READ OR
WRITE
Figure 9. DS2477 I2C Slave Address
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. The timing references are defined in Figure
10.
Bus Idle or Not Busy
Both SDA and SCL are inactive and in their logic-high states.
START Condition
To initiate communication with a slave, the master must generate a START condition. A START condition is defined as a
change in state of SDA from high to low while SCL remains high.
STOP Condition
To end communication with a slave, the master must generate a STOP condition. A STOP condition is defined as a
change in state of SDA from low to high while SCL remains high.
Repeated START Condition
Repeated STARTs are commonly used for read accesses after having specified a memory address to read from in a
preceding write access. The master can use a repeated START condition at the end of a data transfer to immediately
initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal
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Maxim Integrated | 18
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
START condition, but without leaving the bus idle after a STOP condition.
Data Valid
With the exception of the START and STOP condition, transitions of SDA can occur only during the low state of SCL.
The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold
time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL; see Figure 10). There is one clock
pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT,
+ tR in Figure 10) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the
falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master
generates all SCL clock pulses, including those needed to read from a slave.
tF IF MASTER DRIVEN OR tOF IF SLAVE DRIVEN
tF/tOF
Sr
S
P
S
SDA
tF
tR
tSU:DAT
tSU:STA
tLOW
tBUF
tSP
SCL
tHD:STA
tHD:DAT
tHIGH
tSU:STO
NOTE: TIMING REFERENCED TO VIH(MIN) AND VIL(MAX).
Figure 10. I2C Timing Diagram
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Maxim Integrated | 19
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Ordering Information
PART
DS2477Q+T
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
6 TDFN (2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Maxim Integrated | 20
DS2477
DeepCover Secure SHA-3 Coprocessor with
ChipDNA PUF Protection
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/18
0.1
DESCRIPTION
PAGES
CHANGED
Initial release
—
Added Security User Guide and Developer Software hyperlink
1
1
3/19
Updated Benefits and Features section
1
2
11/20
Updated tAPU time description
12
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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