DS26503DK

DS26503DK T1/E1/J1 BITS Element Design Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26503DK is an easy-to-use evaluation board for the DS26503 T1/E1/J1 BITS element. The DS26503DK is intended to be used as a stand-alone design kit. The board is complete with a DS26503 BITS element, transformers, termination resistors, FPGA-based configuration switches, and network connectors. Dallas’ ChipView software gives pointand-click access to configuration and status registers from a Windows®-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status as well as multiple clock and signal routing configurations. Expedites New Designs by Eliminating FirstPass Prototyping Demonstrates Key Functions of DS26503 BITS Element Includes DS26503 BITS Element, Transformers, BNC, and RJ48 Network Connectors and Termination Passives BNC Connections for 75Ω E1 Bantam and RJ48 Connectors for 120Ω E1 and 100Ω T1 Interface Directly to Windows-Based Computers ChipView Software Provides Point-and-Click Access to the DS26503 Register Set Software-Controlled (Register Mapped) Configuration Switches to Facilitate Clock and Signal Routing All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-of-Signal and Interrupt Status as well as Indications for Multiple Clock and Signal Routing Configurations Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs Windows is a registered trademark of Microsoft Corp. DESIGN KIT CONTENTS DS26503DK Design Kit CD_ROM Including: • • • • ChipView Software DS26503DK Data Sheet DS26503 Data Sheet DS26503 Errata Sheet (if applicable) ORDERING INFORMATION PART DESCRIPTION DS26503DK Stand-Alone Design Kit for DS26503 1 of 30 REV: 031507 DS26503DK COMPONENT LIST DESIGNATION QTY DESCRIPTION C1, C4, C23, C51, C53 5 10μF 20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M C2–C3, C6–C9, C11, C12, C14, C15, C17, C18, C20, C21, C25–C30, C32, C33, C35, C36, C38, C45–C50, C52, C54, C55, C57–C60, C62, C63, C68 41 1μF 10%, 16V ceramic capacitors (1206) Panasonic ECJ-3YB1C105K C5, C10, C22, C24, C31, C34, C37, C39–C41, C43, C65–C67, C69, C70 16 0.1μF 20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT C13, C19, C42, C44, C64 5 10μF 20%, 16V tantalum capacitors (B case) Panasonic ECS-T1CX106R C16, C56, C61 3 68μF 20%, 16V tantalum capacitors (D case) Panasonic ECS-T1CD686R D1 1 1A 50V general-purpose silicon diode General Semiconductor 1N4001 DS1, DS2, DS6–DS9 6 Red LEDs, SMD Panasonic LN1251C DS3 1 Green LED, SMD Panasonic LN1351C DS4 1 Amber LED, SMD Panasonic LN1451C DS5 1 Green LED, SMD (Not populated) Panasonic LN1351C DS10 1 Red/green LED, 5mm right-angle PCMT Digi-Key 350-1055-ND J1 1 Socket, banana plug, horizontal, black J2 1 Socket, banana plug, horizontal, red J3, J6–J8 4 Terminal strip, 16-pin, dual row, vertical Samtec TSW-108-07-T-D J4 1 DB9 right-angle, long case connector AMP 747459-1 J5 1 75Ω vertical 5-pin BNC connector Cambridge CP-BNCPC-004 J9 1 RJ48 8-pin, single-port connector MOLEX 15-43-8588 J10, J11 2 BNC connectors, 75Ω right-angle 5-pin Kruvand UCBJR220 J12, J13 2 Bantam jack, right-angle connectors Switchcraft RTT34B02 JP1, JP3–JP8 7 100-mil, 2-position jumper labstock JP2 1 14-pin header, remove 'missing pin' labstock L1 1 Inductor, 22.0μH 2-pin SMT 20% Coiltronics NP1, NP2 2 R1, R8–R11 5 10pF 5%, 50V tall case ceramic capacitors (1206) Phycomp Do not populate Panasonic 0Ω 5%, 1/8W resistors (1206) R2, R13, R23, R27, R43, R47, R67–R70 10 330Ω 5%, 1/16W resistors (0603) 2 of 30 SUPPLIER Mouser Electronics Mouser Electronics Panasonic PART 164-6218 164-6219 UP1B-220 1206CG100J9B200 ERJ-8GEYJ0R00V ERJ-3GEYJ331V DS26503DK DESIGNATION QTY DESCRIPTION R3, R18–R20, R22, R25, R26, R28–R31, R33–R42, R44–R46, R49, R50, R53, R56, R59, R61, R62, R65, R72 33 10kΩ 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V R4, R5, R48, R51, R54, R55, R57, R58 8 30Ω 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ300V R6, R7 2 61.9Ω 1%, 1/8W resistors (1206) Panasonic ERJ-8ENF61R9V R12 1 51Ω 5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ510V R14–R17, R21, R24, R63, R64, R66, R71 10 1.0kΩ 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ102V R32 1 1.0kΩ 5%, 1/10W resistor (0805) Panasonic ERJ-6GEYJ102V R52 1 51.1Ω 1%, 1/10W resistor (0805) Panasonic ERJ-6ENF51R1V R60 1 1.0MΩ 5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ105V SW1, SW3 2 Switch MOM 4-pin single pole Panasonic EVQPAE04M SW2 1 Switch 8-position, 16-pin DIP, low profile AMP 435668-7 T1 1 XFMR 16P SMT Pulse TX1099 TP1, TP2 2 Test point, 1 plate thru-hole NA NA TP3–TP10 8 Test point, 1 plated hole DO NOT STUFF NA NA U1 1 32-bit microcontroller (lab stock) Avnet MMC2107CFCV33 U3, U6 2 SRAM 5V, 1Mb SO (in lab stock) Cypress CY62128V U4 1 Xilinx Spartan 2.5V FPGA, 20mm x 20mm 144-pin TQFP Xilinx XC2S50-5TQ144C U5 1 8-Pin μMAX/SO 2.5V or Adj Maxim MAX1792EUA25 U7 1 64-pin LQFP T1/E1/J1 BITS element (0°C to +70°C) Dallas Semiconductor DS26503L U8, U9, U13 3 High-speed inverter Fairchild NC7SZ86 U10 1 High-speed buffer Fairchild NC7SZ86 U11 1 Dual RS-232 transceivers with 3.3V/5V internal capacitors Maxim MAX3233E U12 1 1Mb flash-based config mem Xilinx XCF01SV020C U14 1 8-pin SO step-up DC-DC converter 0.5A limit Maxim MAX1675EUA X1 1 Low-profile 8.0MHz crystal PEI EC1-8.000M Y1 1 Oscillator, crystal clock, 3.3V, 6.312MHz SaRonix NTH069A3-6.312 Y2 1 Oscillator, crystal clock, 3.3V, 2.048MHz SaRonix NTH039A3-2.0480 Y3 1 Oscillator, crystal clock, 3.3V, 1.544MHz SaRonix NTH039A3-1.5440 3 of 30 SUPPLIER PART DS26503DK USER SWITCHES BOARD FLOORPLAN GND SYSTEM LEDs DS26503 RESET SRAM (264KB) VCC PROTOTYPE AREA NETWORK CONNECTION FPGA FPGA STATUS & CONFIG DS26503 TEST POINTS USER LEDs MICROCONTROLLER DS26503 BITS ELEMENT DS26503 TEST POINTS JTAG CONFIG RS232 OnCe JTAG SYSTEM RESET OSCILLATORS T1, E1, 6312MHZ + BNC Tx Rx NETWORK CONNECTION DS26503 LEDs ERRATA The design kit errata refer to two different PC board revisions: the DS26502DK01A0 and DS26502DK01B0. The PC board revision code is found on the bottom of the board in the lower right corner. DS26502DK01A0 Circuit Boards • RCLK did not get connected to FPGA. A jumper wire was run from RCLK to TP10 to provide the connection. • Silkscreen for J3.4 is incorrect. Silkscreen reads “JTDIMMC2107” and should read “JTDOMMC2107.” • RJ45 connector J4 does not use the standard pin numbers for connection to the transformer (and subsequently to TTIP/TRING and RTIP/RRING). This connector has been left unpopulated to avoid confusion. The schematic has been updated and is correct. • DC blocking capacitor C4 on TTIP too small. A 10μF capacitor is recommended; a 1μF capacitor was populated. DS26502DK01B0 Circuit Boards • RJ45 connector J4 does not use the standard pin numbers for connection to the transformer (and subsequently to TTIP/TRING and RTIP/RRING). This connector has been left unpopulated to avoid confusion. The schematic has been updated and is correct. ADDITIONS The following signals have been connected to test points via the FPGA: • TP6 is driven with data present at the TS_8K_4 pin of the DS26503. • TP7 is driven with the 400Hz signal mentioned in the TS_8Ksrc register (page 15). • TP8 is driven with the 8KHz signal mentioned in the TS_8Ksrc register (page 15). 4 of 30 DS26503DK BASIC OPERATION This design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/telecom. See the DS26503DK QuickView data sheet for these files. Hardware Configuration • • • Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. DIP switches are unused and can be in either the ON or OFF position with exception for the Flash programming switch, which should be OFF. From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs → ChipView → ChipView. General • Upon power-up the RLOS and RLOF LEDs (red) will be lit, the INT LED (red) will not be lit, and Status LED (DS10 red/green bicolor) will be green. Quick Setup (Register View) • • • • The PC will load ChipView offering a choice among DEMO MODE, REGISTER VIEW, and TERMINAL MODE. Select Register View. The program will then request a definition file. Select DS26503DC_FPGA.def. Through the ‘links’ section, this will also load DS26503.def. The Register View Screen will appear, showing the register names, acronyms, and values for the DS26503. Predefined Register settings for several functions are available as initialization files. • ini files are loaded by selecting the menu File→Reg ini File→Load ini File. • Load the ini file “CompositeClock.ini.” • Load the ini file “DS26502FPGA_2048Clks.ini,” which sets the DS26503 in Intel nonmultiplexed mode with MCLK driven at 2.048MHz. • After loading the ini files the following may be observed: • The RLOS and RLOF LEDs extinguishes upon external loopback. • The part begins operating in composite clock mode. Miscellaneous • • • Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA. The definition file for this FPGA is named DS26503DC_FPGA.def. Table 2 shows the FPGA register definitions. A drop-down menu on the top of the screen allows for switching between definition files. All files referenced above are available for download as described in the section marked “BASIC OPERATION.” 5 of 30 DS26503DK ADDRESS MAP Device address space (DS26503 and FPGA) begins at 0x81000000. All offsets given below are relative to the beginning of the device address space (shown above). Table 1. Device Address Map OFFSET 0x0000 to 0x0030 0x8000 to 0x80ff DEVICE FPGA DESCRIPTION Board identification and clock/signal routing DS26503 T1/E1/J1 DS26503 T1/E1/J1 BITS element BITS element Registers in the FPGA can be easily modified using the ChipView host-based user interface software along with the definition file named “DS26503DC_FPGA.def”. FPGA Register Map Table 2. FPGA Register Map OFFSET 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0007 0x09-0x10 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 REGISTER NAME BID Unused XBIDH XBIDM XBIDL BREV AREV PREV BUSMO Unused LEVEL1 LEVEL2 LEVEL3 LEVEL4 LEVEL5 LEVEL6 LEVEL7 LEVEL8 LEVEL9 LEVEL10 Unused TSERsrc MCLKsrc TCLK TS_8K Unused Unused TYPE Read only — Read only Read only Read only Read only Read only Read only Read only — Control Control Control Control Control Control Control Control Control Control — Control Control Control Control — — DESCRIPTION BOARD ID — HIGH NIBBLE EXTENDED BOARD ID MIDDLE NIBBLE EXTENDED BOARD ID LOW NIBBLE EXTENDED BOARD ID BOARD FAB REVISION BOARD ASSEMBLY REVISION PLD REVISION BUS MODE INFORMATION — DS26503 pin settings (THZE, BTS–HBE, BIS1, BIS0) DS26503 pin settings (RMODE3, RMODE2, RMODE1, RMODE0) DS26503 pin settings (RSM, RITD) DS26503 pin settings (TSM, TITD) DS26503 pin settings (TCSS1, TCSS0) DS26503 pin settings (TMODE3, TMODE2, TMODE1, TMODE0) DS26503 pin settings (L2, L1, L0) DS26503 pin settings (TAIS, RLB) DS26503 pin settings (MPS1, MPSO) DS26503 pin settings (JAMUX, E1TS) — DS26503 TSER source selection DS26503 MCLK source selection DS26503 TCLK source selection DS26503 TS_8K source selection — — 6 of 30 DS26503DK FPGA ID Registers BID: BOARD ID (Offset = 0x0000) BID is read only with a value of 0xD. XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset = 0x0002) XBIDH is read only with a value of 0x0. XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset = 0x0003) XBIDM is read only with a value of 0x1. XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset = 0x0004) XBIDL is read only with a value of 0x6. BREV: BOARD FAB REVISION (Offset = 0x0005). BREV is read only and displays the current fab revision. AREV: BOARD ASSEMBLY REVISION (Offset = 0x0006) AREV is read only and displays the current assembly revision. PREV: PLD REVISION (Offset = 0x0007) PREV is read only and displays the current PLD firmware revision. FPGA Status Registers Register Name: BUSMO Register Description: DS26503 Bus Mode Register Offset: 0x0011 Bit # Name Default 7 LevCPOL — 6 LevCPHA — 5 HW — 4 SPI — 3 INMUX — 2 IMUX — 1 MNMUX — The FPGA derives values in the BUSMO register from the levels present at the DS26503 pins. Bit 7: LevCPOL. When set the DS26503 CPOL pin is high. Note: This pin is called A3/CPOL/L1 in parallel/serial/hardware modes. Bit 6: LevCPHA. When set the DS26503 CPHA pin is high. Note: This pin is called A2/CPHA/L0 in parallel/serial/hardware modes. Bit 5: HW. When set the DS26503 is in hardware mode. Bit 4: SPI. When set the DS26503 is in SPI (3-wire) mode. Bit 3: INMUX. When set the DS26503 is in Intel nonmultiplexed mode. Bit 2: IMUX. When set the DS26503 is in Intel multiplexed mode. Bit 1: MNMUX. When set the DS26503 is in Motorola nonmultiplexed mode. Bit 0: MMUX. When set the DS26503 is in Motorola multiplexed mode. 7 of 30 0 MMUX — DS26503DK FPGA Control Registers The FPGA register set consists of two types of registers: level setting and clock multiplexing. There are 10 registers for tri-state and level-control setting when in hardware mode. The level-setting registers are only valid when the DS26503 is in hardware mode (BIS1:0 = 11). When in nonhardware mode, the FPGA pins affected by the level registers are automatically either tri-stated, or assume an alternate function (e.g., they function as address databus pins or SPI pins). Exceptions are given with the register descriptions. Register Name: LEVEL1 Register Description: DS26503 Pin Settings (THZE, BTS, BIS1, BIS0) Register Offset: 0x0011 Bit # Name Default 7 THZEtri 0 6 THZE_Lev 0 5 BTStri 0 4 BTS_Lev 0 3 BIS1tri 0 2 BIS1_Lev 0 1 BIS0tri 0 Note: This register is only valid in ALL modes (many of the level registers are only valid in hardware mode). Bits 7 and 6: DS26503 THZE Tri-State and Level (THZEtri and THZE_Lev) 00 = FPGA drives THZE with 0V 01 = FPGA drives THZE with 3.3V 1x = FPGA tri-states THZE pin Bit 5 and 4: DS26503 BTS Tri-State and Level (BTStri and BTS_Lev) 00 = FPGA drives BTS with 0V 01 = FPGA drives BTS with 3.3V 1x = FPGA tri-states BTS pin Bits 3 and 2: DS26503 BIS1 Tri-State and Level (BIS1tri and BIS1_Lev) 00 = FPGA drives BIS1 with 0V 01 = FPGA drives BIS1 with 3.3V 1x = FPGA tri-states BIS1 pin Bits 1 and 0: DS26503 BIS0 Tri-State and Level (BIS0tri and BIS0_Lev) 00 = FPGA drives BIS0 with 0V 01 = FPGA drives BIS0 with 3.3V 1x = FPGA tri-states BIS0 pin 8 of 30 0 BIS0_Lev 1 DS26503DK Register Name: LEVEL2 Register Description: DS26503 Pin Settings (RMODE3, RMODE2, RMODE1, RMODE0) Register Offset: 0x0012 Bit # Name Default 7 6 5 4 3 2 1 0 RMODE3 tri RMODE3 _Lev RMODE2 tri RMODE2 _Lev RMODE1 tri RMODE1 _Lev RMODE0 tri RMODE0 _Lev 0 0 0 0 0 0 0 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 7 and 6: DS26503 RMODE3 Tri-State and Level (RMODE3tri and RMODE3_Lev) 00 = FPGA drives RMODE3 with 0V 01 = FPGA drives RMODE3 with 3.3V 1x = FPGA tri-states RMODE3 pin Bits 5 and 4: DS26503 RMODE2 Tri-State and Level (RMODE2tri and RMODE2_Lev) 00 = FPGA drives RMODE2 with 0V 01 = FPGA drives RMODE2 with 3.3V 1x = FPGA tri-states RMODE2 pin Bits 3 and 2: DS26503 RMODE1 Tri-State and Level (RMODE1tri and RMODE1_Lev) 00 = FPGA drives RMODE1 with 0V 01 = FPGA drives RMODE1 with 3.3V 1x = FPGA tri-states RMODE1 pin Bits 1 and 0: DS26503 RMODE0 Tri-State and Level (RMODE0tri and RMODE0_Lev) 00 = FPGA drives RMODE0 with 0V 01 = FPGA drives RMODE0 with 3.3V 1x = FPGA tri-states RMODE0 pin Register Name: LEVEL3 Register Description: DS26503 Pin Settings (RSM, RITD) Register Offset: 0x0013 Bit # Name Default 7 — 0 6 — 0 5 RSMtri 0 4 RSM _Lev 0 3 — 0 2 — 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 5 and 4: DS26503 RSM Tri-State and Level (RSMtri and RSM _Lev) 00 = FPGA drives RSM with 0V 01 = FPGA drives RSM with 3.3V 1x = FPGA tri-states RSM pin Bits 1 and 0: DS26503 RITD Tri-State and Level (RITDtri and RITD_Lev) 00 = FPGA drives RITD with 0V 01 = FPGA drives RITD with 3.3V 1x = FPGA Tristates RITD pin 9 of 30 1 RITDtri 0 0 RITD_Lev 0 DS26503DK Register Name: LEVEL4 Register Description: DS26503 Pin Settings (TSM, TITD) Register Offset: 0x0014 Bit # Name Default 7 — 0 6 — 0 5 TSMtri 0 4 TSM_Lev 0 3 — 0 2 — 0 1 TITDtri 0 0 TITD_Lev 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 5 and 4: DS26503 TSM Tri-State and Level (TSMtri and TSM_Lev) 00 = FPGA drives TSM with 0V 01 = FPGA drives TSM with 3.3V 1x = FPGA tri-states TSM pin Bits 1 and 0: DS26503 TITD Tri-State and Level (TITDtri and TITD_Lev) 00 = FPGA drives TITD with 0V 01 = FPGA drives TITD with 3.3V 1x = FPGA tri-states TITD pin Register Name: LEVEL5 Register Description: DS26503 Pin Settings (TCSS1, TCSS0) Register Offset: 0x0015 Bit # Name 7 6 5 4 3 2 1 0 — — TCSS1tri TCSS1_Lev — — TCSS0tri TCSS0_Lev Default 0 0 0 0 0 0 0 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 5 and 4: DS26503 TCSS1 Tri-State and Level (TCSS1tri and TCSS1_Lev) 00 = FPGA drives with TCSS1 0V 01 = FPGA drives with TCSS1 3.3V 1x = FPGA tri-states TCSS1 pin Bits 1 and 0: DS26503 TCSS0 Tri-State and Level (TCSS0tri and TCSS0_Lev) 00 = FPGA drives TCSS0 with 0V 01 = FPGA drives TCSS0 with 3.3V 1x = FPGA tri-states TCSS0 pin 10 of 30 DS26503DK Register Name: LEVEL6 Register Description: DS26503 Pin Settings (TMODE3, TMODE2, TMODE1, TMODE0) Register Offset: 0x0016 Bit # Name Default 7 6 5 4 3 2 1 0 TMODE3 tri TMODE3 _Lev TMODE2 tri TMODE2 _Lev TMODE1 tri TMODE1 _Lev TMODE0 tri TMODE0 _Lev 0 0 0 0 0 0 0 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 7 and 6: DS26503 TMODE3 Tri-State and Level (TMODE3tri and TMODE3_Lev) 00 = FPGA drives TMODE3 with 0V 01 = FPGA drives TMODE3 with 3.3V 1x = FPGA tri-states TMODE3 pin Bits 5 and 4: DS26503 TMODE2 Tri-State and Level (TMODE2tri and TMODE2_Lev) 00 = FPGA drives TMODE2 with 0V 01 = FPGA drives TMODE2 with 3.3V 1x = FPGA tri-states TMODE2 pin Bits 3 and 2: DS26503 TMODE1 Tri-State and Level (TMODE1tri and TMODE1_Lev) 00 = FPGA drives TMODE1 with 0V 01 = FPGA drives TMODE1 with 3.3V 1x = FPGA tri-states TMODE1 pin Bits 1 and 0: DS26503 TMODE0 Tri-State and Level (TMODE0tri and TMODE0_Lev) 00 = FPGA drives TMODE0 with 0V 01 = FPGA drives TMODE0 with 3.3V 1x = FPGA tri-states TMODE0 pin 11 of 30 DS26503DK Register Name: LEVEL7 Register Description: DS26503 Pin Settings (L2, L1, L0) Register Offset: 0x0017 Bit # Name Default 7 — 0 6 — 0 5 L2tri 0 4 L2_Lev 0 3 L1tri 0 2 L1_Lev 0 1 L0tri 0 0 L0_Lev 0 Note: Settings for L2 are only valid in hardware mode (BIS[1:0] = 11), and ignored for other modes. In serial mode (BIS[1:0] = 10), L0 and L1 are used to set levels for CPHA and CPOL, respectively. Bits 5 and 4: DS26503 L2 Tri-State and Level (L2tri and L2_Lev) 00 = FPGA drives L2 with 0V 01 = FPGA drives L2 with 3.3V 1x = FPGA tri-states L2 pin Bits 3 and 2: DS26503 L1 Tri-State and Level (L1tri and L1_Lev) 00 = FPGA drives L1 with 0V 01 = FPGA drives L1 with 3.3V 1x = FPGA tri-states L1 pin Bits 1 and 0: DS26503 L0 Tri-State and Level (L0tri and L0_Lev) 00 = FPGA drives L0 with 0V 01 = FPGA drives L0 with 3.3V 1x = FPGA tri-states L0 pin Register Name: LEVEL8 Register Description: DS26503 Pin Settings (TAIS, RLB) Register Offset: 0x0018 Bit # Name Default 7 — 0 6 — 0 5 TAIS tri 0 4 TAIS_Lev 0 3 — 0 2 — 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 5 and 4: DS26503 TAIS Tri-State and Level (TAIS tri and TAIS_Lev) 00 = FPGA drives TAIS with 0V 01 = FPGA drives TAIS with 3.3V 1x = FPGA tri-states TAIS pin Bits 1 and 0: DS26503 RLB Tri-State and Level (RLBtri and RLB_Lev) 00 = FPGA drives RLB with 0V 01 = FPGA drives RLB with 3.3V 1x = FPGA tri-states RLB pin 12 of 30 1 RLBtri 0 0 RLB_Lev 0 DS26503DK Register Name: LEVEL9 Register Description: DS26503 Pin Settings (MPS1, MPSO) Register Offset: 0x0019 Bit # Name Default 7 — 0 6 — 0 5 MPS1tri 0 4 MPS1_Lev 0 3 — 0 2 — 0 1 MPSOtri 0 0 MPSO_Lev 0 Bits 5 and 4: DS26503 MPS1 Tri-State and Level (MPS1tri and MPS1_Lev) 00 = FPGA drives MPS1 with 0V 01 = FPGA drives MPS1 with 3.3V 1x = FPGA tri-states MPS1 pin Bits 1 and 0: DS26503 MPS0 Tri-State and Level (MPSOtri and MPSO_Lev) 00 = FPGA drives MPS0 with 0V 01 = FPGA drives MPS0 with 3.3V 1x = FPGA tri-states MPS0 pin Register Name: LEVEL10 Register Description: DS26503 Pin Settings (JAMUX, E1TS) Register Offset: 0x000A Bit # Name 7 6 5 4 3 2 1 0 — — JAMUXtri JAMUX_Lev — — E1TStri E1TS_Lev Default 0 0 0 0 0 0 0 0 Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes. Bits 5 and 4: DS26503 JAMUX Tri-State and Level (JAMUXtri and JAMUX_Lev) 00 = FPGA drives JAMUX with 0V 01 = FPGA drives JAMUX with 3.3V 1x = FPGA tri-states JAMUX pin Bits 1 and 0: DS26503 E1TS Tri-State and Level (E1Tstri and E1TS_Lev) 00 = FPGA drives E1TS with 0V 01 = FPGA drives E1TS with 3.3V 1x = FPGA tri-states E1TS pin 13 of 30 DS26503DK Register Name: TSERsrc Register Description: DS26503 TSER Pin Source Register Offset: 0x001C Bit # Name Default 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 2 ZEROS 0 1 ONES 1 0 RSER 0 Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to TSER. Setting to 0 also tri-states this pin. Bit 2: ZEROS. When set DS26503_TSER ← 0.0V. Bit 1: ONES. When set DS26503_TSER ← 3.3V. Bit 0: RSER. When set DS26503_TSER ← DS26503_RSER. Register Name: MCLKsrc Register Description: DS26503 MCLK Pin Source Register Offset: 0x001D Bit # Name Default 7 — 0 6 — 0 5 — 0 4 — 0 3 ZERO 0 2 EXT 0 1 T1 1 0 E1 0 Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to MCLK. Setting to 0 also tri-states this pin. Bit 3: ZERO. When set DS26503_ MCLK ← 0.0V. Bit 2: EXT. When set DS26503_ MCLK ← External_Osc (BNC connector). Bit 1: T1. When set DS26503_ MCLK ← T1_OSC (1.544MHz). Bit 0: E1. When set DS26503_ MCLK ← E1_OSC (2.048MHz). 14 of 30 DS26503DK Register Name: TCLKsrc Register Description: DS26503 TCLK Pin Source Register Offset: 0x001E Bit # Name Default 7 — 0 6 EXT 0 5 T1 1 4 E1 0 3 64KHZ 0 2 6312 0 1 PLL 0 0 RCLK 0 Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to TCLK. Setting to 0 also tri-states this pin. Bit 6: EXT. When set DS26503_ TCLK ← External_Osc (BNC connector). Bit 5: T1. When set DS26503_ TCLK ← T1_OSC (1.544MHz). Bit 4: E1. When set DS26503_ TCLK ← E1_OSC (2.048MHz). Bit 3: 64KHZ. When set DS26503_ TCLK ← 64kHz clock. Bit 2: 6312. When set DS26503_ TCLK ← 6312kHz clock. Bit 1: PLL. When set DS26503_ TCLK ← DS26503_PLL. Bit 0: RCLK. When set DS26503_ TCLK ← DS26503_RCLK. Register Name: TS_8Ksrc Register Description: DS26503 TS_8K Pin Source Register Offset: 0x001F Bit # Name Default 7 — 0 6 — 0 5 — 0 4 EXT 0 3 _8KHz 0 2 400HZ 0 1 400HZ_502 1 0 RS_8K 0 Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to TS_8K. Setting to 0 also tri-states this pin. Bit 4: EXT. When set DS26503_TS_8K ← External_Osc (BNC connector). Bit 3: _8KHz. When set DS26503_TS_8K ← 8kHz (derived by FPGA). Bit 2: 400HZ. When set DS26503_TS_8K ← 400Hz clock (derived by FPGA). Bit 1: 4KHZ_502. When set DS26503_TS_8K ← DS26503_400hz. Bit 0: RS_8K. When set DS26503_TS_8K ← DS26503_RS_8K. 15 of 30 DS26503DK DS26503 INFORMATION For more information about the DS26503, consult the DS26503 data sheet available on our website at www.maxim-ic.com/DS26503. Software downloads are also available for this design kit. DS26503DK INFORMATION For more information about the DS26503DK, including software downloads, consult the DS26503DK data sheet available on our website at www.maxim-ic.com/DS26503DK. TECHNICAL SUPPORT For additional technical support, go to www.maxim-ic.com/support. SCHEMATICS The DS26503DK schematics are featured in the following pages. DOCUMENT REVISION HISTORY REVISION DATE DESCRIPTION 110205 Initial DS26503DK data sheet release. 071006 Updated descriptions for FPGA Control Registers LEVEL1 to LEVEL10. 110106 Updated schematics. 031507 Corrected typo on Bit 0 of TSERsrc register Corrected typo on Bit 0 of TS_8Ksrc register 16 of 30 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. D 8 7 6 5 4 DS26502 3 DESIGN KIT 4 2 1 CONVERTED TO PDF: Fri Oct 20 10:08:32 2006 ENGINEER: TITLE: 3 STEVE SCULLY 2 DS26502DK01B0 DATE: PAGE: 1 1 / 14 041205 D A C 5 C 6 B 1. CONTENTS 2. DS26502 AND OSCILLATORS 3. DS26502 LINE BUILD OUT 4. XILINX CLOCK MUX AND BUS CONVERSION 5. TEST POINTS FOR DS26502 6. MMC2107 PROCESSOR 7. PROCESSOR CONFIGURATION 8. XILINX CONFIGURATION AND CORE VOLTAGE 9. SERIAL PORTS AND JTAG CONFIGURATION 10. MEMORY 11. PROCESSOR TEST POINTS 12. FLASH VOLTAGE AND DECOUPLING 13. SIGNAL CROSS REFERENCE 14. PART CROSS REFERENCE AND REVISION HISTORY 7 B A 8 8 2 THZE502 BIS0502 BIS1502 RD#502 CS#502 WR#502 BTS502 INT#502 RTIP502 RRING502 49 48 31 23 26 27 44 17 50 57 59 61 60 62 55 46 41 42 TSTRST TSER -/-/TMODE1 -/-/TMODE2 -/-/TCSSI TS_8K_4 RS_8K 400HZ MCLK TCLK THZE BIS0 BIS1 RD*(DS*)/-/RMODE2 CS*/CS*/RLB WR*(R/W*)/-/TMODE3 BTS/-/HBE INT*/INT*/JACKS RTIP RRING R48 6 DVDD2 DVSS1 6 DVSS2 DVSS3 5 1 R57 2 1 30 1 R51 2 30 R54 1 R58 4 4 RSER502 PLL_CLK502 TCLKO502 RCLK502 DAT502 ADDR502 TTIP502 TRING502 0 1 2 3 4 5 6 7 51 54 9 10 11 12 13 14 15 16 TTIP TRING A/-/EITS A/-/TAIS A/-/L0 A/-/L1 A/CPHA/L2 A/CPOL/TMODE0 A/-/MPS0 ALE(AS)/A/-/MPS1 0 1 2 3 4 5 6 7 28 19 20 32 29 30 47 18 25 63 64 1 2 3 4 5 6 PLL_OUT TCLKO RCLK RSER TNEGO TPOSO RLOS RAIS RLOF_CCE 5 TNEGO502 TPOSO502 RLOS502 RAIS502 RLOF502 AD/MISO/TCSS0 AD/MOSI/RMODE3 AD/SCLK/RSM AD/-/TSM AD/-/RMODE0 AD/-/RMODE1 AD/-/TITD AD/-/RITD V3_3 DVDD3 U7 DS26502 DVDD1 TVSS 7 MCLK502 TCLK502 39 21 JTMS JTCLK JTRST JTDI JTDO TMODE1502 TMODE2502 TCSSI502 TS_8K_4502 1 TSTRST502 TSER502 33 34 35 36 37 TVDD RVSS3 D RS_8K502 400HZ502 R55 JTAGTMS JTAGTCK JTRST502 JTDI502 JTDO502 7 3 1 1 OUT VCC 1 OUT VCC OSC GND 8 5 5 8 5 2 V3_3 T1_OSC V3_3 E1_OSC C62 V3_3 2 1UF 1 Y1 6312 KHZ__3.3V OSC VCC OUT 2 STEVE SCULLY DS26502DK01B0 GND 1 8 Y2 2.048MHZ_3.3V GND OSC 1.544MHZ_3.3V Y3 V3_3 1 4 V3_3 1 4 1 4 ENGINEER: TITLE: 3 TP5 TP4 V3_3 6312_OSC DATE: PAGE: 1 TP3 1 2 / 14 041205 1 C B A 8 1.0K 1.0K 1 .1UF .1UF 38 53 58 7 24 RVDD RVSS2 C65 2 1 C66 2 1 R71 R66 2 11 2 RVSS1 40 43 45 52 56 8 22 D C B A R9 0.0 R8 7 2 2 6 C4 10UF R11 2 2 9 11 16 15 14 T1 1:0.8 1:1 1:1 1:0.8 T1 8 1 1 10 5 NOTE: THE DS26502DK01A0 CIRCUIT BOARDS USED A 1UF CAPACITOR (REFERENCE DESIGNATOR C4)FOR DC BLOCKING ON THE TTIP PIN. THIS HAS BEEN INCREASED TO 10UF ON THE DS26502DK01B0 CIRCUIT BOARDS TTIP502 TRING502 0.0 1 0.0 R10 7 8 5 6 2 1 4 3 51.1 D C 1 0.0 R7 R6 61.9 5 4 4 7 6 3 1 H F D B 3 3 5 R 2 2 J12 T CONN_BANTAM_IPC R CONN_BANTAM 5 T J13 2 STEVE SCULLY DS26502DK01B0 2 ENGINEER: TITLE: 75 OHM RA 8 4 2 5 CONN_BNC_5P J10 J9 G E C A 75 OHM RA CONN_RJ48 1 2 3 4 5 CONN_BNC_5P J11 1 2 3 4 5 NOTE: BOARD REVISIONS DS26502DK01A0 AND DS26502DK01B0 DO NOT USE THE CORRECT PIN NUMBERS ON THE RJ48 CONNECTOR (REFERENCE DESIGNATOR J9). THE RJ48 CONNECTOR SHOULD BE REMOVED SINCE IT HAS NON-STANDARD CONNECTION. THE SCHEMATIC HAS BEEN UPDATED AND IS CORRECT. 6 R52 RTIP502 RRING502 7 2 1 B A 8 C34 2 1 .1UF 2 1 1 2 DATE: PAGE: 1 3 / 14 041205 1 D C B A 61.9 D 8 29 30 31 77 100 99 101 7 GCK0 IO12_4 IO11_4 IO10_4 IO9_4/VREF1_4 IO8_4 5 123 79 126 7 14 15 4 6 116 3 122 113 2 5 117 1 114 83 0 EB0 115 80 78 EB1 4 15 4 3 2 1 0 42 22 23 5 20 19 DAT502 5 40 12 6 7 GCK3 IO9_0 IO8_0 IO7_0/VREF2_0 IO6_0 IO5_0 IO4_0 IO3_0 IO2_0/VREF1_0 IO1_0 OUTPUT CLOCKS 7 3 RCLK502 2 EXT_OSC IO1_2/IRDY_2 IO2_2 IO3_2/D3 IO13_2/DOUT/BUSY IO12_2/DIN/D0 IO11_2 IO10_2/VREF2_2 IO9_2 IO8_2 IO7_2/D1 IO6_2/D2 IO5_2 IO4_2/VREF1_2 SPARE FPGA IO U4 BANK 1 PORT XC2S50_QFP I/O BANK 3 2 STEVE SCULLY DS26502DK01B0 502 BUS MODE DETECTION ENGINEER: TITLE: 3 1 51 11 49 13 48 46 44 0 1 2 3 4 5 6 7 V3_3 1 C58 1UF CFG_DINXI PAGE: 1 R2 CONN_BNC_5P J5 1 1 DS5 GREEN 21 4 / 14 A B C 75 OHM VERT D 2 2 330 1 041205 DATE: TIM_INTERUPT ADDR502 41 TSER502 47 INT#502 43 1.0K 1.0K 29 RSER502 39 38 2 3 4 5 R63 R64 1 1 2 2 6 IO1_6/TRDY_6 IO2_6 IO3_6/D3 IO4_6/VREF1_6 IO5_6 IO6_6 IO7_6 IO8_6 IO9_6 IO10_6/VREF2_6 IO11_6 IO12_6 112 IO11_1 INPUT CLOCKS BANK 5 PORT U4 XC2S50_QFP I/O BANK 7 IO13_6 4 IO1_1/CS* TP9 28 103 IO7_4 IO6_4 IO5_4 IO4_4 IO3_4/VREF2_4 IO2_4 IO1_4 5 TP7 TP6 TP8 TP10 27 140 CPUCLK_OUT 88 26 96 136 25 23 85 137 22 130 24 21 131 6 IO10_1 IO3_3 GCK2 BANK 2 IO1_3/INIT* IO9_1/VREF2_1 IO4_3/VREF1_3 IO5_5 1 1 1 1 IO8_1 IO5_3 IO2_1/WRITE* IO11_3/D4 IO7_1 IO6_3 GCK1 IO2_7 IO6_1 IO7_3/D6 IO9_5 IO3_7/VREF1_7 IO4_1/VREF1_1 IO9_3 IO8_5/VREF2_5 IO4_7 IO5_1 IO8_3/D5 20 7 IO2_5/VREF1_5 TMODE1502 TMODE2502 TCSSI502 IO3_1 IO10_3/VREF2_3 IO7_5 IO5_7 MOSI MISO SCK SS IO12_3 IO6_5 IO6_7 BANK 0 IO4_5 OE RW CS2 TA IO13_3/TRDY_3 IO3_5 IO9_7/VREF2_7 16 IO2_3/D7 X_INITXI IO10_7 17 31 30 10 28 6 4 3 63 21 66 64 18 BIS0502 BIS1502 BTS502 IO1_5 18 54 26 57 58 27 60 62 59 50 65 56 67 68 MCLK502 1 R4 2 TCLK502 1 30 30 2 TS_8K_4502 R5 THZE502 RD#502 CS#502 WR#502 400HZ502 PLL_CLK502 RS_8K502 6312_OSC T1_OSC E1_OSC IO7_7 BANK 6 IO1_7 PROC_RESET_OUT IO11_7 134 102 84 75 74 76 138 94 141 91 IO8_7 BANK 4 IO12_7/IRDY_7 129 124 121 132 87 118 120 133 95 139 93 86 19 C B A 8 PD PA D C B A 8 V3_3 SW3 TPOSO502 3 1 TSTRST502 TNEGO502 5 3 TCLKO502 11 7 RCLK502 13 9 RSER502 RLOF502 RAIS502 RLOS502 15 8 RS_8K502 PLL_CLK502 4 1 2 400HZ502 1 1.0K 2 .1UF C10 2 1 R17 1 1 1 J8 2 6 1 5 8 4 7 10 3 9 11 12 13 14 15 16 2 1 4 2 RAIS502 RLOS502 MCLK502 7 6 10 DS8 DS7 DS6 RLOF502 2 2 2 8 12 14 16 RED 2 1 RED 2 1 RED CONN_16P R70 330 R69 330 R68 330 7 6 6 5 5 4 0 1 2 2 4 6 12 10 8 4 14 3 5 16 6 7 8 6 4 2 9 7 5 3 1 J7 10 12 11 14 13 16 15 8 6 4 2 9 7 5 3 1 12 11 10 J6 CONN_16P 2 ADDR502 RD#502 4 6 CS#502 WR#502 10 8 BIS1502 12 BTS502 BIS0502 14 14 13 16 15 9 7 5 3 1 6 5 4 3 2 1 0 3 13 11 7 1 3 5 7 9 11 13 15 3 2 MCLK502 THZE502 JTDI502 1 2 1 2 R65 10K R56 10K R59 10K R31 1 2 1 2 10K 2 R33 RD#502 CS#502 10K 1 2 10K R39 10K 10K R46 R42 10K R49 10K R34 2 2 WR#502 TCLK502 1 1 TS_8K_4502 1 TSTRST502 INT#502 1 10K 10K BIS1502 2 R37 R35 BIS0502 1 1 2 1 2 2 DATE: PAGE: 1 1 V3_3 5 / 14 041205 BIS[1:0] : 01 = PARALLEL PORT MODE DEFAULT MODE (NON-MULTIPLEXED) STEVE SCULLY 2 DS26502DK01B0 DAT502 ENGINEER: TITLE: 15 CONN_16P 16 INT#502 4 D C B A ICOC20 ICOC21 ICOC22 ICOC23 56 55 54 53 52 EXTAL TRST* 60 4 30 31 2 1 144 4 5 29 5 3 27 28 26 CSE1 CSE0 TC1 TC2 62 78 7 10 15 12 16 24 22 17 23 25 67 CS3 CS1 CS2 21 3 VDDSYN 2 FLASH_SW 0.0 MMC2107 PORT VSS6 VSS5 VSS4 VSS3 VSS2 U1 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 2 1 VSS7 6 TCLK R1 VSS8 7 CSE1 CSE0 TC2 81 83 85 86 20 20 21 19 18 22 D17 VSSSYN TC1 CS3* CS2* CS1* CS0* CS0 RESET_B 128 CPUCLK_OUT 118 PROC_RESET_OUT SCK 17 25 VSSF ICOC23 XTAL ICOC22 MOSI ICOC21 MMC2107 CONTROL YC0 ICOC20 ICOC13 ICOC12 ICOC11 INT0* 8 ICOC13 57 U1 ICOC12 58 ICOC10 INT1* D C ICOC11 61 RESET* 120 93 ONCE_DE_B 16 PD DS26502DK01B0 STEVE SCULLY 2 V3_3 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATE: PAGE: 1 1 116 21 22 18 117 17 19 122 16 20 131 119 132 15 121 134 14 9 13 8 136 13 7 137 14 6 12 23 5 139 24 4 10 26 11 28 3 11 29 1 2 6 47 0 49 50 041205 6 / 14 PA ENGINEER: TITLE: 3 A10 VSS1 CLKOUT RSTOUT* SCK 143 SS D16 D15 D14 D13 D12 VSSA JTDI2107 JTDO2107 TMS TEST TXD2 RXD2 TXD1 94 30 31 27 34 15 13 35 14 12 D0 0 11 D11 D1 1 DE* 4 D2 2 RXD1 SS* 5 D3 3 INT3* VRH D4 4 MISO XTAL OSC_MCU JTAGTCK ONCE_TRST_B JTAGTMS 6 D5 5 PQB3 PQB2 PQB1 PQB0 PQA4 PQA3 PQA1 PQA0 YCO MOSI MISO ICOC10 TEST 63 GND SCI2_OUT 66 68 SCI2_IN SCI1_OUT 69 70 SCI1_IN 7 D6 6 INT4 TA TEA D7 7 B A 8 D8 8 EB3 EB2 INT5* RW OE RCON RW D10 EB1 EB0 INT2* 59 OE* 95 SHS* 97 TA* 99 TEA* 102 VSTBY 92 VRH 113 VRL 112 VPP 87 VDDA 115 VDDF 74 VDDH 103 VDDSYN 123 VDD8 141 VDD7 129 VDD6 77 VDD5 65 VDD4 45 VDD3 33 VDD2 19 VDD1 9 D9 9 36 37 38 39 40 41 42 43 46 48 51 114 73 126 140 127 76 64 44 32 18 8 10 TIM_16H_8L 88 EB3* 96 EB2* 98 EB1* 100 EB0* 101 PQB3 104 PQB2 105 PQB1 106 PQB0 107 PQA4 108 PQA3 109 PQA1 110 PQA0 111 TDI 133 TDO 135 INT6* INT7* 89 84 82 79 75 72 71 80 90 91 124 125 130 142 138 USER_LED1 USER_LED2 USER_IN1 USER_IN2 RUN_KIT_USR TIM_STATUS TIM_INTERUPT D C B A 7 PD PD PD 1 R53 2 2 1 2 1 2 2 BOOT_SEL 5 4 1 2 R16 4 TP1 1 USER_LED2 USER_LED1 TP2 TIM_INTERUPT TIM_STATUS V3_3 2 1.0K 1 U8 NC7SZ86_U U13 4 4 1 1 3 V5_0 R27 2 1 1 2 1 4 2 1 1 SW2 3 12 13 14 2 16 4 11 15 5 SWITCH 8 POS 6 10 2 7 9 2 GREEN DS26502DK01B0 STEVE SCULLY 2 V3_3 FLASH_SW 1 GREEN RED RED RED R12 51 PAGE: DATE: RED_GREEN BICOLOR 8 1 GREEN DS3 1 2 R24 RESET AND CHIP CONFIGURATION 2 DS1 DS9 RED DS10 RED DS2 1 RED RED USER_IN1 USER_IN2 USER_IN3 USER_IN4 2 330 U9 R47 330 R67 330 R13 NC7SZ86_U 2 1 330 R43 330 1.0K V3_3 1.0K NC7SZ86_U 1 2 ENGINEER: TITLE: 3 1 2 1 R15 2 1 R14 6 V3_3 RESET CONFIGURATION 10K 1 R20 10K 2 R19 1 R25 10K PD 2 1 R29 2 1 10K 10K PD 2 10K R22 R26 1 R18 10K 10K R30 PD 1 PD PD PD 10K RESET_B 5 1 2 2 RESET_XI R32 6 2 R50 10K U10 4 1 NC7SZ86_U V3_3 1 1.0K 7 2 1.0K 1 1.0K R21 1 8 R72 D MASTER MODE FULL DRIVE XTAL W/ PLL INTERNAL FLASH ENABLE 4 1 BOOT INTERN/EXTERN RCON 1 3 SW1 2 10K C B A 8 2 1 2 1 1 2 DS4 AMBER V3_3 7 / 14 041205 1 D C B A 1UF 8 V2_5XI 7 8 7 6 V2_5XI 2 C39 V3_3 1 U5 MAX1792 OUT 6 .1UF JTDO_XI 1 2 IN OUT 1 2 1 2 IN 5 20 19 18 17 16 15 14 13 5 4 144 V3_3 127 108 107 71 90 70 36 53 35 16 1 VCCO12 VCCO11 VCCO10 VCCO9 VCCO8 VCCO7 VCCO6 VCCO5 VCCO4 VCCO3 VCCO2 VCCO1 3 U4 XC2S50_QFP CONTROL ENGINEER: TITLE: 3 GND13 GND14 GND15 2 TMS TDI TCK TDO CCLK PROGRAM* DONE M2 M1 M0 NC2 NC1 DS26502DK01B0 STEVE SCULLY 2 142 32 34 2 37 69 72 106 111 109 105 104 JTAGTMS JTDI_XI JTAGTCK JTD_S2F CCLKXI RESET_XI DONEXI CLOCKS DATE: PAGE: 1 8 / 14 041205 1 VCC 10K 1 R28 2 SET VCCJ VCCO VCCINT TDO DNC3 DNC5 DNC4 CF* 12 11 VCCINT8 GND12 2 1 DNC6 VCCINT7 GND11 3 GND U12 D0 DNC1 CLK TDI TMS 10UF CEO* C51 OE/RST* TCK C23 GND VCCINT6 GND10 RST SHDN 1 3 2 4 5 6 7 8 9 DNC2 CE* 4 VCCINT5 GND9 4 CFG_DINXI 2 CCLKXI JTD_S2F JTAGTMS JTAGTCK RESET_XI R3 X_INITXI 10K 10 5 VCCINT4 GND8 1 2 1 2 XILINX_XCF01S 10UF C40 6 VCCINT3 GND7 V3_3 .1UF C31 1 .1UF DONEXI 7 GND16 VCCINT2 GND6 2 1 9 14 24 55 82 92 97 125 VCCINT1 GND5 D C B A 8 GND1 GND2 GND3 GND4 8 17 25 33 45 52 61 73 81 89 98 110 119 128 135 143 2 1 C2 C41 .1UF C37 .1UF D C B A D 8 V3_3 1 2 7 19 20 18 17 16 15 14 13 12 11 5 4 V3_3 FPGA JTAG / ONCE DEBUG SELECTION TDO TDI CONFIG FLASH TDO 3 JUMPER JUMPER TITLE: JTDI2107 JTDO2107 JTAGTCK GND RESET_B DS26502 3 1 6 4 2 1 10K R40 10K 1 9 / 14 041205 R41 2 V3_3 JP2 5 CON14P 7 9 12 14 DATE: PAGE: 2 1 10K R38 8 ALIGN KEY JTAGTMS 10 ONCE_DE_B ONCE_TRST_B 11 13 TDO TESTP0INT 2 STEVE SCULLY DS26502DK01B0 V3_3 TDI ENGINEER: 2 1 6 TDI JTAG CONFIGURATION (BOUNDARY SCAN) ONCETDO PIN 3 1 2 2 1 OSC_MCU XTAL MMC2107 TDI 4 ...OTHER DEVICES... PROCESSOR DEBUG CONFIGURATION (ONCE) MMC2107 TDO J3 2 1 X1 8.0MHZ T2OUT R2IN U11 MAX3233E R2OUT INVALID* C2- GND FORCEON C2+ T2IN R1OUT C1- V- T1OUT C1+ T1IN R1IN V+2 ONCETDI PIN ONCETDI PIN 5 10K 10K 3 4 5 6 7 8 VCC 9 8 7 6 V+1 F G H J 6 CONN_16P R62 R61 JTRST502 5 7 9 11 13 15 JTAGTCK JTAGTMS JTDO502 JTDI502 2 1 JTDO2107 JTDO_XI 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 JTDI2107 1 JTDI_XI 3 NP2 R36 FORCEOFF* V3_3 J4 A B C D E 7 10PF 10K 1 2 1 2 1 2 10K 9 10 1 2 3 4 R45 CONN_DB9P 5 1 2 SCI1_OUT PRT1_IN 10K NP1 PRT1_OUT SCI1_IN PRT1_OUT PRT1_IN 2 1 C B A 8 10PF R44 1 2 R60 1.0M D C B A D 8 13 14 15 16 4 28 3 31 2 5 12 25 17 11 6 21 17 19 14 18 15 20 24 25 26 27 28 29 30 31 5 4 11 12 13 14 15 16 23 25 10 28 11 31 12 9 10 26 17 9 V3_3 3 CY62128V CE2 U3 A16 A15 A14 A13 A12 A11 A10 A9 A8 OE* 7 IO7 IO6 13 PA WE* V3_3 CY62128V IO5 IO4 IO3 IO2 IO1 IO0 4 EB1 OE N_C U6 A16 A15 A14 A13 A12 A11 A10 A9 A8 PD 5 IO7 IO6 IO5 IO4 IO3 IO2 IO1 13 14 20 19 21 15 17 18 16 17 18 19 20 21 22 23 2 PD 2 STEVE SCULLY DS26502DK01B0 IO0 ENGINEER: TITLE: 3 1 23 26 6 A1 2 10 9 PA 7 GND A0 CS0 CE1* A2 3 C B A 8 1 A3 4 A1 2 A4 5 CE1* A2 3 VCC CS0 CE2 A3 4 A5 OE* A4 5 32 1 29 24 30 22 16 6 WE* A5 6 A6 7 A6 7 A7 8 7 6 5 4 3 2 27 8 GND A0 EB0 OE N_C 32 1 29 24 30 22 16 VCC A7 6 7 8 9 10 11 12 27 8 DATE: 1 10 / 14 041205 PAGE: 1 D C B A D C ICOC22 ICOC23 55 54 53 52 8 ICOC21 EXTAL TCLK TRST* 5 4 31 2 1 144 3 2 VSS2 U2 D31 D30 MMC2107 PORT VSS3 6 30 D29 D28 D27 D26 D25 D24 VSS4 7 TC2 29 4 10 D23 D22 D21 VSS5 CSE1 CSE0 67 TC1 5 3 27 28 26 12 7 24 25 23 15 16 22 21 D20 VSS6 60 78 CS3 62 81 CS2 CS1 83 85 CS0 RESET_B CPUCLK_OUT PROC_RESET_OUT SCK ONCE_DE_B 17 VSS7 CSE1 CSE0 TC2 TC1 CS3* CS2* CS1* 86 118 128 120 93 143 20 VSS8 U2 ICOC23 ICOC22 ICOC21 XTAL ICOC20 MMC2107 CONTROL MISO ICOC20 ICOC13 ICOC12 MOSI 56 57 YC0 ICOC13 58 CS0* RESET* CLKOUT RSTOUT* SCK DE* 19 20 VSSSYN ICOC12 ICOC11 ICOC10 TEST TXD2 INT0* VDDSYN VSSF ICOC11 63 61 66 ICOC10 SCI2_OUT 68 RXD2 TXD1 SS D19 VSSA JTDI2107 JTDO2107 TMS TEST SCI2_IN 69 94 21 D18 D17 D16 D15 D14 D13 D12 V3_3 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATE: PAGE: 1 18 22 17 116 122 16 21 131 15 117 132 14 19 134 13 20 136 119 137 12 121 139 11 8 6 7 9 14 6 10 23 11 24 5 13 26 2 3 1 4 47 0 28 49 29 50 1 11 / 14 041205 PA PD 2 STEVE SCULLY DS26502DK01B0 TEST-POINTS FOR PROCESSOR ENGINEER: TITLE: 3 A10 VSS1 SCI1_OUT SS* 18 27 22 30 25 15 31 17 14 16 13 34 35 D0 0 12 11 D11 D1 1 INT3* FLASH_SW D2 2 RXD1 4 D3 3 INT4 VRH D4 4 70 5 D5 5 SCI1_IN 6 D6 6 PQB3 PQB2 PQB1 PQB0 PQA4 PQA3 PQA1 PQA0 INT1* 7 D7 7 B A 8 D8 8 EB1 EB0 INT2* 59 OE* 95 SHS* 97 TA* 99 TEA* 102 VSTBY 92 VRH 113 VRL 112 VPP 87 VDDA 115 VDDF 74 VDDH 103 VDDSYN 123 VDD8 141 VDD7 129 VDD6 77 VDD5 65 VDD4 45 VDD3 33 VDD2 19 VDD1 9 D9 EB3 EB2 INT5* RW OE RCON TA TEA RW D10 10 36 37 38 39 40 41 42 43 46 48 51 114 73 126 140 127 76 64 44 32 18 8 9 TIM_16H_8L 88 EB3* 96 EB2* 98 EB1* 100 EB0* 101 PQB3 104 PQB2 105 PQB1 106 PQB0 107 PQA4 108 PQA3 109 PQA1 110 PQA0 111 TDI 133 TDO 135 INT6* INT7* 89 84 82 79 75 72 71 80 90 91 124 125 130 142 138 USER_LED1 USER_LED2 USER_IN1 USER_IN2 RUN_KIT_USR TIM_STATUS TIM_INTERUPT YCO MOSI MISO XTAL OSC_MCU JTAGTCK ONCE_TRST_B JTAGTMS D C B A D C B A 8 8 7 7 1 1 1 2 C19 2 2 C35 2 2 V3_3 1UF 1 1 10UF C48 1 1UF 1 1UF 1 1 R23 C59 2 D1 1 2 C63 1 1UF C61 2 C25 1 2 1 1UF 8 3 FB 1 2 U14 MAX1675 OUT LBI 1 1UF LX 1UF C52 1 7 2 1 LBO* 2 C26 GND ENGINEER: TITLE: 3 1UF C20 1UF REF 2 2 SHDN V3_3 1 6 C11 .1UF C15 1 2 22.0UH 1 C56 C5 1 68UF 5 2 2 L1 2 .1UF 2 C53 1 10UF V5V 1 1UF 2 1 10UF C8 2 .1UF C22 68UF 4 2 1UF 2 330 C64 4 1 V5_0 1 1 1 2 1UF 1UF 68UF C67 2 1 VCC 1UF V3_3 .1UF C16 C47 1 C21 1 2 2 1 10UF 1UF 2 JP3 2 C24 2 5 2 1UF 1UF C42 1 2 2 1UF C45 1 C6 2 1 1UF 2 6 1UF 2 JP4 1 C49 2 2 1 10UF C29 2 BLACK 1 1 1 2 2 JP6 5 1 C70 2 .1UF C60 2 1UF C9 A 1 JP5 1 C3 .1UF C13 2 C27 2 1 1UF 1UF 1 J1 2 1 C17 1 2 C30 2 B 1 JP1 6 1 C38 2 C43 C28 2 1UF C14 CONN_BANANA_2P 1 1UF 10UF 10UF C46 2 1 V3_3 2 JP8 1 C44 RED 1 MNT_HOLE C50 1UF 1 2 1UF 1UF 2 C1 2 1 2 1 A 2 C36 1 1UF 1 MNT_HOLE 1 C32 2 J2 1 JP7 1 MNT_HOLE MNT_HOLE 1 MNT_HOLE 1 B CONN_BANANA_2P 1 MNT_HOLE 1 MNT_HOLE MNT_HOLE 1 1 3 4 C12 2 2 DS26502DK01B0 C69 1 2 1UF 1 .1UF C33 2 1 1UF 2 2 STEVE SCULLY 1UF V3_3 C54 1 2 1UF C68 2 1 C55 1UF C7 1 1 DATE: PAGE: 1UF C57 1 2 1UF 2 VDDSYN 2 1 2 1 V3_3 12 / 14 041205 1 1UF C18 1UF D C B A D C B A 8 7 7 4D6 5C8 2C8< 2A1 4D6 2C4> 4C1 5D4< 4A3 5B4 2C8< 5A2< 4A2 5B4 2C8< 5A2< 7B6< 4A2 5B4 2C8< 8B7 8C1< 4B2 8B7 6B5 11B5 4C8< 4A3 5B4 2C8< 5C2< 6B5 10D3 10D6 11C5 6C5 11C5 4A6 6C5 11C5 6C5 11C5 6C5 11C5 6C5 11C5 2C4> 5C2> 4C4 8A7 8B1< 2B2 4D6 4B5 6D7 10D7 11D7 4B5 6D7 10D3 11D7 6D7 11D7 6D7 11D7 4D2 7D2 6D2< 11D3< 6B8 11B8 6B8 11C8 6C8 11C8 6C8 11C8 6C8 11C8 6C8 11C8 6C8 11C8 6C8 11C8 2C8> 4B2 5B4 5B2< 6A6 8A7 9B4 9C3 11A6 2B8< 8C1< 6A6 8B7 9B4 9C2 11A6 2C8< 8C1< 9B4 2B8< 5C2< 6D6 9B5 9C3 11D6 9B5 8C2< 2B8> 9B4 6D6 9C3 9C5 11D6 8B5 9C5 8B7 8C1> 9C4 2B8< 5C7 2C8< 4A3< 5C2< 4A3 4A6 6A6 11A7 4A6 6A6 11A7 4A6 6D3 10D3 10D7 11D3 6B5 9B2 11B5 6A6 9B2 11A6 6A6 9D5 11A6 4C4 6B1> 11A1> 10B4 10B7 6A2> 11A2> 10B2> 4B8 4B8 10B5> 4D6 5C8 2C4< 6D6 11D6 6D6 11D6 6D6 11D7 6D6 11D7 6D6 11D7 6D7 11D7 6D7 11D7 6D7 11D7 4D6 6B5 11B5 9A8 9B8< 9A8 9B8> 2B4> 5C7 5B8< *** Signal Cross-Reference for the entire design *** 400HZ502 6312_OSC ADDR502 BIS0502 BIS1502 BOOT_SEL BTS502 CCLKXI CFG_DINXI CPUCLK_OUT CS#502 CS0 CS1 CS2 CS3 CSE0 CSE1 DAT502 DONEXI E1_OSC EB0 EB1 EB2 EB3 EXT_OSC FLASH_SW ICOC10 ICOC11 ICOC12 ICOC13 ICOC20 ICOC21 ICOC22 ICOC23 INT#502 JTAGTCK JTAGTMS JTDI502 JTDI2107 JTDI_XI JTDO502 JTDO2107 JTDO_XI JTD_S2F JTRST502 MCLK502 MCLK502XI MISO MOSI OE ONCE_DE_B ONCE_TRST_B OSC_MCU PA PA PA PD PD PD PD PLL_CLK502 PQA0 PQA1 PQA3 PQA4 PQB0 PQB1 PQB2 PQB3 PROC_RESET_OUT PRT1_IN PRT1_OUT RAIS502 8 RCLK502 RCON RD#502 RESET_B RESET_XI RLOF502 RLOS502 RRING502 RSER502 RS_8K502 RTIP502 RUN_KIT_USR RW SCI1_IN SCI1_OUT SCI2_IN SCI2_OUT SCK SS T1_OSC TA TC1 TC2 TCLK502 TCLK502XI TCLKO502 TCSSI502 TEA TEST THZE502 TIM_16H_8L TIM_INTERUPT TIM_STATUS TMODE1502 TMODE2502 TNEGO502 TPOSO502 TRING502 TSER502 TSTRST502 TS_8K_4502 TTIP502 USER_IN1 USER_IN2 USER_IN3 USER_IN4 USER_LED1 USER_LED2 V2_5XI V5V VDDSYN VRH WR#502 XTAL X_INITXI YCO 6 5B8 2C4< 6D3 11D3 7B8< 4A3 5B4 2D8< 5C2< 6B5 9C3 11B5 7A6< 7A7 8A7 8C1< 2B4> 5C7 5B8< 2B4> 5C7 5B8< 2D8< 3B7< 4B1 5B8 2C4< 4D6 5B8 2C8< 2D8< 3B7< 6A7 11A7 4A6 6D3 11D3 6B8 9B8> 11B8 6B8 11B8 9B8< 6B8 11B8 6B8 11B8 4A6 6B5 11B5 4A5 6B5 11B5 2D2 4D6 4A6 6D3 11D3 6C5 11C5 6C5 11C5 2C8< 4A3< 5B2< 4A3 5C8 2C4< 2C8 4D3 6D3 11D3 6B8 11B8 4A3 2C8< 5C2< 6D7 11D8 4B1> 6A7 7A4 11A7 6A7 7B4 11A7 4D3 2C8< 4D3 2C8< 2C4> 5C8 2B4> 5C8 2D4> 3C8< 4B1 2C8< 5D8 2C8< 5B2< 4A3 2C8< 5B2< 2D4> 3C8< 6A7 7C3 11A7 6A7 7C3 11A7 7C3 7C3 6A7 11A8 7A4< 6A7 11A7 7A4< 8D6 8A8< 12D4 6D2< 11D2< 12C1< 6D3< 11D3< 4A3 5B4 2C8< 5B2< 6A6 9C5 11A7 4A2 8A7 6A7 11A7 6 5 5 4 4 3 ENGINEER: TITLE: 3 2 DS26502DK01B0 STEVE SCULLY 2 DATE: PAGE: 1 13 / 14 041205 1 D C B A D C B A 8 CAP1 CAP1 CAP CAP CAP1 CAP CAP CAP CAP CAP1 CAP CAP CAP CAP CAP CAP1 CAP CAP CAP CAP CAP CAP1 CAP1 CAP1 CAP CAP CAP CAP CAP CAP CAP1 CAP CAP CAP1 CAP CAP CAP1 CAP CAP1 CAP1 CAP1 CAP CAP1 CAP CAP CAP CAP CAP CAP CAP CAP1 CAP CAP1 CAP CAP CAP CAP CAP1 CAP CAP1 CAP CAP1 CAP CAP CAP1 CAP1 CAP1 CAP CAP1 CAP1 DIODE LED LED LED LED 12A5 8C8 12B5 3D6 12B3 12B5 12B1 12B4 12B5 5D8 12B3 12B2 12C6 12B6 12B3 12A4 12B6 12B1 12C5 12B3 12B5 12A4 8C6 12A4 12B3 12B3 12B6 12C6 12B5 12B6 8C8 12B7 12B2 3A6 12C4 12B7 8C5 12B5 8C6 8C6 8C8 12C5 12A5 12C7 12B5 12B6 12C5 12B4 12C6 12B6 8C7 12B3 12A3 12B2 12B1 12C3 12B1 4D1 12B4 12A4 12D3 2A2 12D4 12D4 2D3 2B3 12A4 12B2 12C2 12A5 12C4 7A3 7A3 7B3 7D1 7 7 *** Part Cross-Reference for the entire design *** C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 D1 DS1 DS2 DS3 DS4 8 6 DS5 LED 4B1 DS6 LED 5B7 DS7 LED 5B7 DS8 LED 5B7 DS9 LED 7B3 DS10 LED2 7B3 J1 CONN_BANANA_2P 12D7 J2 CONN_BANANA_2P 12C7 J3 CONN_16P 9B5 J4 CONN_DB9P 9A7 J5 CONN_BNC_5P 4D1 J6 CONN_16P 5B3 J7 CONN_16P 5D3 J8 CONN_16P 5C7 J9 CONN_RJ48 3B4 J10 CONN_BNC_5P 3D3 J11 CONN_BNC_5P 3A4 J12 CONN_BANTAM_IPC 3C2 J13 CONN_BANTAM 3B2 JP1 JMP 12B6 JP2 CON14P 9C2 JP3 JMP 12B5 JP4 JMP 12B5 JP5 JMP 12B6 JP6 JMP 12B5 JP7 JMP 12A7 JP8 JMP 12A6 L1 COIL_2P 12C3 MNT_HOLE1 MNT_HOLE 12A6 MNT_HOLE2 MNT_HOLE 12A6 MNT_HOLE3 MNT_HOLE 12A7 MNT_HOLE4 MNT_HOLE 12A6 MNT_HOLE5 MNT_HOLE 12A7 MNT_HOLE6 MNT_HOLE 12A7 MNT_HOLE7 MNT_HOLE 12A7 MNT_HOLE8 MNT_HOLE 12A7 NP1 CAP 9C8 NP2 CAP 9C7 R1 RES1 6D2 R2 RES1 4B1 R3 RES1 8A7 R4 RES1 4A3 R5 RES1 4A3 R6 RES1 3B6 R7 RES1 3B6 R8 RES1 3C7 R9 RES1 3D7 R10 RES1 3B6 R11 RES1 3B6 R12 RES1 7D1 R13 RES1 7B3 R14 RES1 7D4 R15 RES1 7D4 R16 RES1 7D4 R17 RES1 5D8 R18 RES1 7C7 R19 RES1 7D7 R20 RES1 7D7 R21 RES1 7D4 R22 RES1 7C7 R23 RES1 12D4 R24 RES1 7D2 R25 RES1 7D7 R26 RES1 7C7 R27 RES1 7C3 R28 RES1 8C1 R29 RES1 7C7 R30 RES1 7C7 R31 RES1 5C1 R32 RES1 7A7 R33 RES1 5C1 R34 RES1 5C1 R35 RES1 5A1 R36 RES1 9A7 R37 RES1 5A1 R38 RES1 9C1 R39 RES1 5B1 6 5 5 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 SW1 SW2 SW3 T1 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 X1 Y1 Y2 Y3 4 RES1 9C1 RES1 9C1 RES1 5B1 RES1 7A3 RES1 9A7 RES1 9A7 RES1 5B1 RES1 7A3 RES1 2C7 RES1 5B1 RES1 7B8 RES1 2C4 RES 3A5 RES1 7D7 RES1 2C4 RES1 2C8 RES1 5C1 RES1 2C5 RES1 2C4 RES1 5C1 RES1 9D6 RES1 9B2 RES1 9C2 RES1 4D2 RES1 4D2 RES1 5C1 RES1 2A2 RES1 7A3 RES1 5B7 RES1 5B7 RES1 5B7 RES1 2A2 RES1 7A8 PUSHBUTTON 7A8 SWITCH_8POS 7D2 PUSHBUTTON 5D8 XFMR_2IN_4OUT_U 3B5 3D5 TESTPOINT_1P 7C4 TESTPOINT_1P 7C4 TESTPOINT 2A1 TESTPOINT 2C2 TESTPOINT 2D2 TESTPOINT 4D2 TESTPOINT 4D2 TESTPOINT 4D3 TESTPOINT 4D2 TESTPOINT 4D3 MMC2107 6D3 6D8 MMC2107 11C4 11D8 CY62128V 10C4 XC2S50_QFP 4C3 4C6 8C3 MAX1792 8D7 CY62128V 10C7 DS26502_U1 2C6 NC7SZ86_U 7B4 NC7SZ86_U 7B3 NC7SZ86_U 7A7 MAX3233E 9B7 XILINX_XCF01S 8B7 NC7SZ86_U 7A4 MAX1675 12D3 XTAL 9D7 OSC1 2A3 OSC1 2C3 OSC1 2D3 4 3 REVISION HISTORY: 2 2 STEVE SCULLY DS26502DK01B0 DATE: PAGE: 1 1 14 / 14 041205 041205 - INITIAL RELEASE OF 01BO VERSION. THIS VERSION IS EXACTLY LIKE THE 01A0 VERSION EXCEPT FOR THE FOLLOWING: - SIGNAL RCLK502 WAS CONNECTED TO THE FPGA, U4, AT PIN 63. - THE PINS WERE SWAPPED ON C13, C42 & C61 ENGINEER: TITLE: 3 D C B A