DS26522DK

DS26522DK Dual T1/E1/J1 Transceiver Demo Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26522DK is an easy-to-use demo kit for the DS26522 T1/E1/J1 dual transceiver. The DS26522DK is a stand-alone system. The board comes complete with a transceiver, transformer, termination resistors, configuration switches, network connectors, microprocessor, and RS-232 connector. The on-board processor and Dallas’ ChipView software give point-and-click access to configuration and status registers from a Windows®-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status, as well as multiple clock and signal routing configurations. Demonstrates Key Functions of DS26522 T1/E1/J1 Dual Transceiver Includes Transceiver, Transformers, and Termination Passives BNC Connections for 75Ω E1 RJ48 Connector for 120Ω E1 and 100Ω T1 On-Board Processor and ChipView Software Provide Point-and-Click Access to the DS26522 Register Set Accessible Address/Data Bus with Tri-State Control to Allow Interface for External Processor All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-of-Signal and Interrupt Status Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs Windows is a registered trademark of Microsoft Corp. DEMO KIT CONTENTS DS26522DK PCB CD_ROM Including: ChipView Software DS26522 Definition files DS26522 Initialization files DS26522DK Data Sheet DS26522 Data Sheet DS26522 Errata Sheet (if applicable) ORDERING INFORMATION PART DS26522DK 1 of 9 DESCRIPTION Demo kit for DS26522 REV: 091806 DS26522DK TABLE OF CONTENTS 1. BOARD FLOORPLAN........................................................................................................3 2. PCB ERRATA.....................................................................................................................3 3. BASIC OPERATION...........................................................................................................4 3.1 HARDWARE CONFIGURATION ........................................................................................................... 4 3.1.1 3.2 General .................................................................................................................................................. 4 QUICK SETUP (REGISTER VIEW) ...................................................................................................... 4 3.2.1 Miscellaneous ........................................................................................................................................ 4 4. ADDRESS MAP..................................................................................................................5 5. TEST POINTS AND CONNECTORS .................................................................................5 6. ADDITIONAL INFORMATION/RESOURCES ....................................................................6 6.1 6.2 6.3 DS26522 INFORMATION .................................................................................................................. 6 DS26522DK INFORMATION ............................................................................................................. 6 TECHNICAL SUPPORT ...................................................................................................................... 6 7. COMPONENT LIST ............................................................................................................7 8. SCHEMATICS ....................................................................................................................9 LIST OF TABLES Table 4-1. Address Map .............................................................................................................................................. 5 Table 5-1. Main Board PCB Configuration .................................................................................................................. 5 2 of 23 DS26522DK 1. BOARD FLOORPLAN BOARD POWER 5.0V DC JACK 5V PROCESSOR FLASH SUPPLY RS-232 DB9 CONNECTOR 1.2V FPGA SUPPLY FPGA CONFIG PROM 2. TEST POINTS: SPI_CPOL, SPI_CPHA, SPI_SWAP, SPI_SEL, BTS, TXENABLE PORT 1 TRANSFORMER BNCs, RJ45 INT LED LATTICE EC3 FPGA MMC2107 PROCESSOR PROCESSOR SRAM TEST POINTS: DS26522 ADDRESS[12:0] DATA[7:0] INT, CS, RW, RD FPGA JTAG RLOS LED RLF LED DS26522 JTAG TEST POINTS: RCHBLK_CLK, RLF_LTC, AL_RSIGF, RM_RFSYNC, TCHBLK CLK TEST POINTS: BPCLK, MCLK, RSYSCLK, TSYSCLK, TCLK, RCLK DS26522 PORT 2 TRANSFORMER BNCs, RJ45 TEST POINTS: TSER, RSER, TSSYNCIO, TSYNC, RSYNC, REFCLKIO, MCLK, RSIG, TSIG OSCILLATOR SELECTION 1.544MHz, 2.048MHz PCB ERRATA DS26522DK01A0 4/17/2006: A 100pF capacitor has been added between processor reset and VCC. This was added to eliminate crosstalk issues present in the OnCE programming pod. 3 of 23 DS26522DK 3. BASIC OPERATION This design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/DS26522DK QuickView page. 3.1 Hardware Configuration • Supply 5.0V to the wall jack receptacle on the bottom of the PCB. • Install the following jumpers (see Table 5-1): • 3.1.1 o JP06: MCLK driven by 1.544MHz for T1. (Set E1 for 2.048MHz.) o JP01, JP03: RSYSCLK driven by MCLK. o JP02, JP04: TSYSCLK driven by MCLK. o JP09, JP12: TCLK driven by MCLK. o JP16 SPI_SEL to GND. JP17 BTS to VCC. JP18, JP19 TXENABLE to VCC. From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs → ChipView → ChipView. General Upon power-up, the RLF and AL_LOS LEDs (red) will be lit, but the INT LED (red) will not be lit. The board draws approximately 200mA at power-up. 3.2 Quick Setup (Register View) 1) The PC loads ChipView, offering a choice among DEMO MODE, REGISTER VIEW, and TERMINAL MODE. Select REGISTER VIEW. 2) The program will request a definition file. Navigate to the .def files in the T1 or E1 folder, then select the file named DS26522_GLB_T1_DEV1.def (T1 mode) or DS26522_GLB_E1_DEV1.def (E1 mode). Note: Through the Links section, this will also load the LIU def file and framer def file. 3) Repeat Step 2 for DS26522_GLB_T1_DEV2.def (or DS26522_GLB_E1_DEV2.def). 4) The Register View Screen will appear, showing the register names, acronyms, and values for the DS26522. 5) Predefined register settings for several functions are available as initialization files. o .ini files are loaded by selecting the menu File→Reg Ini File→Load Ini File. o Load the .ini file Load_T1_LBO0_0_133_impMatchOn_DEV1.ini (T1 mode) or Load_E1_75_impMatchOn_DEV1.ini (E1 mode). o Load the .ini file Load_T1_LBO0_0_133_impMatchOn_DEV2.ini (T1 mode) or Load_E1_75_impMatchOn_DEV2.ini (E1 mode). 6) After loading the .ini file, the following may be observed: 3.2.1 o The DS26522 begins transmitting AIS with impedance match. o The AL_LOS LEDs extinguishes upon external loopback. Miscellaneous The DS26522 uses three register definition files. All three files are loaded when the DS26522_GLOBAL*.def file is loaded. Individual files are selected from the Def File Selection menu in ChipView. 4 of 23 DS26522DK 4. ADDRESS MAP The on-board microcontroller is configured to start the user address space at 0x81000000. All offsets given in Table 4-1 are relative to the beginning of the user address space. Table 4-1. Address Map OFFSET 0X0000 to 0X0087 0X2000 to 0X3FFF 0X4000 to 0X5FFF 5. DEVICE FPGA DESCRIPTION Board identification and FPGA test registers DS26522 DS26522 framer, LIU, and BERT registers on CS1 DS26522 DS26522 framer, LIU and BERT registers on CS2 TEST POINTS AND CONNECTORS The DS26522DK has several connectors, test points, oscillators, and jumpers. Table 5-1 provides a description of these signals, given in order of appearance on the PCB from left to right, then top to bottom (with the board held so that the RS-232 connector is on the top edge). Table 5-1. Main Board PCB Configuration SILKSCREEN REFERENCE JB01 (PCB bottom side) DS01 J02 FUNCTION DEFAULT SETTING SCHEMATIC PAGE DESCRIPTION Power supply 5.0V 3 System VDD. Always connected to power supply. LED On (green) 3 RS-232 Connector Connected to host PC 6 — 6 — 4 Not Installed 6 — 9 Power OK LED. Used for communication with host PC. Basic setting is 57.6K baud, 8 bits, no stop bit, 1 parity bit (57.6, 8, N, 1). OnCE debug connector for MMC2107 processor. System reset. Connects to all device reset pins. Provides flash programming voltage (5V) to processor. JTAG connector for Lattice EC3 FPGA. DS26522 LEDs. Analog loss or receive signaling freeze or framer LOS. DS26522 LEDs. Receive loss of frame or loss of transmit clock. J04 OnCE BDM Connector System Reset Flash VPP Jumper Lattice FPGA DS04, DS06 LED — 11 DS05, DS07 LED — 11 — 10 DS26522 JTAG chains. — 14 DS26522 test points for RCHBLK, TCHBLK, RMSYNC, REFCLKIO. 14 RSYSCLK selection: MCLK (default), BPCLK. 14 TSYSCLK selection: MCLK (default), BPCLK. 14 BPCLK mux, driven to pin 3 of JP01, JP02, JP03, JP04. J01 SW01 J03 J05 J06 DS26522 Test points DS26522 Test points Jumpered Pins 1+2 Jumpered Pins 1+2 Jumpered Pins 1 + 2 JP01, JP03 RSYSCLK Selection JP02, JP04 TSYSCLK Selection JP05 BPCLK MUX J07 DS26522 Test points — 14 DS26522 test points for RSYNC, TSYNC, and TSSYNCIO. YB01, YB02 (PCB bottom side) Oscillators — 14 Oscillators for 2.048MHz and 1.544MHz. J08, J09 Test points — 8 Test points for DS26522 address/data bus and control lines. 5 of 23 DS26522DK SILKSCREEN REFERENCE FUNCTION DEFAULT SETTING SCHEMATIC PAGE J09.12 + J09.14 Bus Tri-state Not Jumpered 8 Install jumper to tri-state the FPGA pins that connect to the DS26522. JP06 MCLK Selection 14 MCLK Selection: 1.544MHz, 2.048MHz (default). JP09, JP12 TCLK Selection 14 TCLK Selection: MCLK (default), RCLK. JP07, JP08 JP14, JP11 JP10 JP13 JP15 TSER Selection TSIG Selection SPI_CPOL Bias SPI_CPHA Bias SPI_SWAP Bias 14 14 10 10 10 TSERx Selection: RSER2, RSER1. TSIGx Selection: RSIG2, RSIG1. SPI_CPOL Selection: pulldown, pullup. SPI_CPHA Selection: pulldown, pullup SPI_SWAP Selection: pulldown, pullup JP16 SPI_SEL Bias 10 SPI_SEL Selection: pulldown (default), pullup. JP17 BTS Bias 10 BTS Selection: pulldown, pullup (default). JP18, JP19 TXENABLE Bias 10 TXENABLE Selection: pulldown, pullup (default). J15 + J14 Network BNC J11 Network RJ48 — 12 Port 2 BNC for 75Ω network connection and RJ48 network connection. J12 + J13 J10 Network BNC Network RJ48 — 13 Port 1 BNC for 75Ω network connection and RJ48 network connection. Jumpered Pins 2+3 Jumpered Pins 1+2 Not Jumpered Not Jumpered Not Jumpered Not Jumpered Not Jumpered Jumpered Pins 1+2 Jumpered Pins 2+3 Jumpered Pins 2+3 6. ADDITIONAL INFORMATION/RESOURCES 6.1 DS26522 Information DESCRIPTION For more information about the DS26522, refer to the DS26522 data sheet at www.maxim-ic.com/DS26522. 6.2 DS26522DK Information For more information about the DS26522DK including software downloads, refer to the DS26522DK Quick View page at www.maxim-ic.com/DS26522DK. 6.3 Technical Support For additional technical support, e-mail your questions to telecom.support@dalsemi.com. 6 of 23 DS26522DK 7. COMPONENT LIST DESIGNATION C01, CB08, CB11-CB13, CB16, CB18, CB21, CB31, CB34-CB36, CB38-CB40 QTY 15 0.1µF ±10%, 16V ceramic capacitors (0603) Phycomp 06032R104K7B20D C02 1 1µF ±10%, 16V ceramic capacitor (1206) Panasonic ECJ-3YB1C105K C03, C04, CB01, CB02 4 10F ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M CB03, CB05 2 68µF ±20%, 16V tantalum capacitors (D case) Panasonic ECS-T1CD686R CB04 1 470µF ±20%, 6.3V tantalum capacitor (D case) Digi-Key 399-3002-1-ND 11 10µF ±20% 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M 6 0.1µF ±20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT 8 4.7µF, 6.3V multilayer ceramic capacitors (0603) Digi-Key ECJ-1VB0J475M CB45, CB46 2 560pF ±5%, 50V ceramic capacitors (1206) Digi-Key 478-1489-2-ND DB01 1 1A, 40V Schottky diode Internatioanl Rectifier 10BQ040 DS01 1 Green LED (SMD) Panasonic LN1351C DS02 1 Green LED (SMD) Panasonic LN1351C DS03–DS07 5 Red LEDs (SMD) Panasonic LN1251C 6 Standard ground clip Keystone Electronics 4954 6 Kit, 4-40 hardware, 0.50 nylon standoff and nylon hex-nut — 4-40KIT4 J01 1 100-mil 2-7 position jumper Lab Stock — J02 1 DB9 right-angle connector (long case) AMP 747459-1 J03 1 100-mil 2-position jumper Lab Stock — J04, J05, J06 3 10-pin terminal strip headers (dual row, vertical) Samtec TSW-105-07-T-D J07 1 14-pin header (dual row, vertical) Samtec HDR-TSW-107-14-T-D J08, J09 2 14-pin headers (dual row, vertical) NON POPULATED Samtec NOPOP-HDR-TSW107-14-T-D CB06, CB09, CB15, CB17, CB19, CB25, CB27, CB29, CB32, CB41, CB42 CB07, CB24, CB26, CB28, CB43, CB44 CB10, CB14, CB20, CB22, CB23, CB30, CB33, CB37 GND_TP02, GND_TP19– GND_TP22, GND_TP24 H01, H02, H04, H07, h08, H09 DESCRIPTION 7 of 23 SUPPLIER PART DS26522DK DESIGNATION QTY J10, J11 2 8-pin single-port connectors (RJ48) Molex 15-43-8588 J12–J15 4 5-pin right-angle BNC connectors Trompetor UCBJR220 1 2.1mm/5.5mm closed frame power jack, high current (right angle PCB, 24VDC at 5A) Also requires 5V AC-DC adapter. Input: 100–240VAC, 50–60Hz, 0.6A. Output: DC 5V, 2.6A. PN DMS050260-P5P-SZ. Model 3Z-161WP05 CUI Inc. PJ-002AH 19 3 position jumpers (100 mils) Lab Stock — 11 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ102V 9 0Ω ±5%,1/8W resistors (1206) Panasonic ERJ-8GEYJ0R00V 17 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V RB07 1 1.0MΩ ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ105V RB08, RB24, RB32–RB35 6 330Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V RB10, RB19, RB25, RB26, RB31, RB38, RB39, RB40 8 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V RB18 1 1.0kΩ ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ102V RB22 1 330Ω ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ331V RB27 1 0.0Ω ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEY0R00V RB29 1 10kΩ ±1%, 1/10W resistor (0805) Panasonic ERJ-6ENF1002V RB36, RB37 2 30Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ300V RB44–RB47 4 61.9Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF61R9V RB53, RB54 2 51.1Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF51R1V RPB01–RPB07 7 30Ω ±5% 4-pack resistors (0402) Panasonic EXB-N8V300JX SW01 1 4-pin single-pole switch Panasonic EVQPAE04M TB01, TB02 2 16-pin SMT transformers Pulse Engineering TX1099 TP01, TP02 2 1 plated hole test points DO NOT STUFF Lab Stock — U01, U04 2 Cypress SRAM Lab Stock — U02 1 3V to 5V Regulating charge pump Maxim MAX1686HEUA U03 1 Processor Freescale Semiconductor MMC2107 JB01 JP01–JP09, JP10–JP19 R01, R02, RB28, RB41, RB42, RB43, RB48–RB52 R03–R09, R10, RB09 RB01–RB06, RB11–RB17, RB20, RB21, RB23, RB30 DESCRIPTION 8 of 23 SUPPLIER PART DS26522DK DESIGNATION QTY U05 1 1.2V FPGA (144-pin, 20mm x 20mm TQFP) Lattice LFEC3E-3T144C U06 1 Dual T1/E1/J1 transceiver (144-pin, 12mm x 12mm CSBGA) Dallas Semiconductor DS26522 UB01 1 Dual RS-232 transceivers with 3.3V/5V internal capacitors Maxim MAX3233E UB02 1 Linear regulator (1.5W, 3.3V or adjustable, 1A, 16-pin TSSOP-EP) Maxim MAX1793EUE-33 UB03 1 Microprocessor voltage monitor (2.93V reset, 4-pin SOT143) Maxim MAX811SEUS-T UB04 1 2Mb High-speed serial flash memory (2.7V to 3.6V, 8-pin SO) Atmel AT25F2048N10SU-2.7 UB05 1 300mA LDO regulator with RESET (1.20V output, 6-pin thin SOT23-6) Maxim MAX1963EZT120-T UB06, UB07 2 High-speed buffers Fairchild NC7SZ86 XB01 1 8.0MHz low-profile crystal ECL EC1-8.000M YB01 1 3.3V 1.544MHz crystal clock oscillator SaRonix NTH 039A3-1.5440 YB02 1 3.3V 2.048MHz crystal clock oscillator SaRonix NTH 039A3-2.0480 8. DESCRIPTION SUPPLIER PART SCHEMATICS The DS26522DK schematics are featured in the following 14 pages. 9 of 23 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. A B C D CR-1 : D_DUT A_DUT RESET_DUT D_DUT A_DUT RESET_DUT CONTENTS BLOCKS: POWER SUPPLY MICROPROCESSOR AND INTERFACE DS26522 DEVICE, LINE BUILDOUT BLOCKS AND TESTPOINTS HIERARCHY 5 7 6 5 NOTES: EACH HIERARCHY BLOCK IS INDEPENDENT OF THE NEXT. ONLY SIGNALS WITH IMPORT/OUTPORT CONNECTORS HAVE CONNECTION OUTSIDE THE HIERARCHY BLOCK. THESE SIGNALS APPEAR AS PINS ON THE HIERARCHY BLOCK CONNECTOR PAGES 03-03: PAGES 04-09: PAGES 10-14: HIERARCHY DS26522 DESIGN KIT TOP LEVEL DECOUPLING / MOUNTING HOLES _motprocrescard_dn RESET BLOCK I9 _DS26522DK01A0DUTDN_ WR_DUT WR_DUT WR_DUT D_DUT RD_DUT RD_DUT RD_DUT CS_X5 CS_X4 A_DUT_ PAGE 01: PAGE 02: 8 CS_X2 CS_X2 CS_X3 CS_X1 INT5 SPI_MISO CS_X1 INT4 SPI_SCK INT_DUT CS_X2 INT3 SPI_CS HIERARCHY 6 PAGES 10-14 DS26522 CS_X1 INT2 SPI_MOSI INT_2 BLOCK MICROPROCESSOR HIERARCHY PAGES 04-09 7 8 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1 4 4 3 3 2 _ds26522topdn_. STEVE SCULLY BLOCK NAME: ENGINEER: TOP LEVEL DS26522DK01A0 DS26522DK TITLE: 2 04/17/2006 PARENT BLOCK: 1 PAGE: 1/2(BLOCK) 1/14(TOTAL) DATE: 1 A B C D A 8 REGULATOR_INPUT 7 V3_3 RESET_OUT REGULATOR_OUTPUT POWER_SUPPLY BLOCK 0.1UF PAGES 03-03 POWER SUPPLY HIERARCHY 0.1UF 7 0.1UF B 8 6 6 V3_3 V3_3 5 5 4 4 470UF 10UF 0.1UF @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE2 0.1UF C : 2 CB36 1 2 CB39 1 2 CB40 1 2 CB35 1 2 CB31 1 D CR-2 2 1 CB12 10UF 4.7UF 0.1UF CB17 CB20 0.1UF CB08 2 1 10UF 4.7UF 0.1UF CB15 CB37 CB16 2 1 10UF 4.7UF 0.1UF CB29 CB33 2 CB38 1 CB32 CB14 2 CB34 1 4.7UF 0.1UF 10UF 4.7UF 0.1UF CB41 CB23 2 CB21 1 CB42 CB10 2 10UF 4.7UF 0.1UF 10UF 4.7UF 0.1UF CB18 1 4.7UF 0.1UF CB06 CB22 2 C01 1 CB30 CB11 2 1 1 2 CB04 GND_TP22 GND_TP24 3 BLOCK NAME: 4 2 _ds26522topdn_. 1 H07 STEVE SCULLY DS26522DK01A0 ENGINEER: TITLE: 3 GND_TP19 GND_TP20 GND_TP02 GND_TP21 1 1 4 H04 4 H09 2 4 1 4 1 H02 1 04/17/2006 1 PAGE: 2/2(BLOCK) 2/14(TOTAL) DATE: 4 H08 PARENT BLOCK: H01 1 A B C D 8 OUT 7 REGULATOR_INPUT SHDN IN4 5 7 IN3 4 RST IN2 3 6 IN1 2 3C8> 17 GND C04 68UF REGULATOR_OUTPUT REGULATOR_OUTPUT 5 330 DS01 2 1 6 RESET_OUT 3D4> 10 11 15 14 13 12 GND SET OUT4 OUT3 OUT2 OUT1 10UF 1 A 3A6< IN RESET_OUT 3A4 MAX1793_U 10K UB02 1 CB03 2 RB10 3.3V 1% REGULATOR OUT 3A6 4 1 2 CB05 3.3V 4 3D7< 3 REGULATOR_INPUT 10UF 5 CB02 6 10UF 7 CB01 B 8 DB01 1 AMP 1 2 JB01 2 REVERSE BIAS PROTECTION 5V DC POWER SUPPLY 1 3 BLOCK NAME: RB08 2 2 power_supply_1amp_dn. STEVE SCULLY DS26522DK01A0 ENGINEER: TITLE: 04/17/2006 PARENT BLOCK: 1 A B C D \_ds26522topdn_\ PAGE: 1/1(BLOCK) 3/14(TOTAL) DATE: BEGINNING OF POWER SUPPLY HIERARCHY BLOCK END OF POWER SUPPLY HIERARCHY BLOCK 10UF @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE2_I230@MODULES.POWER_SUPPLY_1AMP_DN(SCH_1):PAGE1 C03 C : 1 2 D CR-3 GREEN 68UF A B C 54 55 56 57 58 61 ICOC21 ICOC20 ICOC13 ICOC12 ICOC11 ICOC10 70 SCI1_IN 6B8> 8 69 SCI1_OUT 68 SCI2_IN 6B8< 66 SCI2_OUT TEST 63 53 ICOC22 GND 52 ICOC23 RXD1 TXD1 RXD2 TXD2 TEST ICOC10 ICOC11 ICOC12 ICOC13 ICOC20 ICOC21 ICOC22 ICOC23 U03 INT6* D 8 TIM_16H_8L INT7* 89 88 EB3 EB2 84 96 EB3* INT5* 98 EB2* INT4 7 MMC2107 CONTROL 7 6D3 3 2 120 94 143 93 1 3 OUT GND MR* VCC 5 4 V3_3 2 R01 1.0K RESET PARENT BLOCK: RESET* MAX811_U UB03 2.93V SPI_CS ONCE_DE_B 6C2 OUT PROC_RESET_OUT SPI_SCK 7C8 CPUCLK_OUT 128 5B3 PROC_RESET 6C3 118 85 4A4< CS0 86 7D5 24 CS2 CS1 83 5B7 25 CS3 81 7D5 26 TC1 78 7D5 27 TC2 8C2> 30 31 34 35 14 13 12 11 1C7^ D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 U03 \_ds26522topdn_\ 4 PROC_RESET 4B5 9B4< 27 7C8 25 16 22 21 20 17 16 15 12 10 7 5 4 3 15 17 18 19 20 21 22 23 28 2 1 30 29 144 67 62 4 31 CSE1 CSE0 5 60 BLOCK NAME: _motprocrescard_dn. 4 1 6 SW01 SS* DE* SCK RSTOUT* CLKOUT RESET* CS0* CS1* CS2* CS3* TC1 TC2 CSE0 CSE1 6 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE1 75 : INT2* CR-4 71 INT0* 7D4 82 8B6 YC0 80 5B4 7D5 5B7 INT1* 72 6A3< MOSI 90 100 8C3< 108 91 YCO SPI_MOSI SPI_MISO OUT 79 104 PQB3 101 EB0* PQB3 PQB2 PQB1 105 PQB2 106 PQB1 PQB0 PQA4 107 PQB0 109 124 6C5 MISO IN 110 PQA3 XTAL 125 6D5 PQA4 PQA3 PQA1 PQA0 PQA1 111 6D3 EXTAL 130 6C3 EB1* 8C3< 3 MMC2107 PORT 6C3 3 2 VDDSYN 5A2> 5A6> 5C7< 5D7< 7D6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 V3_3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 116 117 119 121 122 131 132 134 136 137 139 6 11 13 14 23 24 26 28 29 47 49 50 1 2 PRINTED STEVE SCULLY Fri Aug 04 04/17/2006 13:58:16 1 2006 4/14(TOTAL) PAGE: 1/6(BLOCK) DATE: OF PROCESSOR HIERARCHY BLOCK PD DS26522DK01A0 ENGINEER: TITLE: BEGINNING 36 10 INT3* 8C5< 37 9 EB1 EB0 8C5< 38 8 135 RW 59 39 7 D10 7D5 5B7 95 40 6 D9 7D5 RW OE 5B4 RCON 5D6< 97 OE* 41 5 D8 99 SHS* 42 4 D7 TA* 43 D6 113 VRH 112 VRL 46 D5 6B1 VRH TA TEA 102 TEA* 92 VSTBY FLASH_VPP 3 VSS4 87 2 VSS3 VPP D1 48 1 TDI 115 VDDA D0 51 0 PQA0 74 VDDF VSSA 114 TCLK 103 VDDH VSSF 73 142 123 VDDSYN 126 VSSSYN 133 ONCE_TDI 2107_TDO 6C2 141 VDD8 VSS8 140 TDO 129 VDD7 VSS7 127 TRST* 77 VDD6 VSS6 76 TMS 65 VDD5 RB09 45 VDD4 VSS5 64 D4 0.0 CB07 .1UF 33 VDD3 44 D3 1UF 19 VDD2 32 D2 C02 9 VDD1 VSS2 18 VSS1 8 138 XTAL OSC_MCU ONCE_TCLK ONCE_TRST_B ONCE_TMS 6C1 USER_LED1 USER_LED2 INT3 INT4 RUN_KIT_USR KIT_STATUS INT2 7C4 8B6 8C3< 8C5< 1D7^ PA A B C D A B C D 4A1> 7B8 5A5 7D6 DRIVE 7D6 5A2> 31 3 28 4 25 23 26 27 2 3 4 5 6 7 8 9 PA 2 A8 A9 A10 A11 A12 A13 A14 A15 A16 U01 CY62128V V3_3 INTERN/EXTERN BOOT 7D6 PD PD PD PD PD PD PD PD PD 7D6 4A2> 5A6> 4A2> 4A2> 7D6 4A2> 4A2> 4A2> 4A2> 4A2> 5A2> 5A2> 5A2> 5A2> FLASH ENABLE INTERNAL 7D6 XTAL W/ PLL FULL 1 8 5A2> 5A6> MASTER MODE 7D6 7D6 7 CY62128V 7 5 10 8 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 1 10K 1 1 28 27 26 25 24 18 17 15 14 13 2 2 2 2 2 1 2 6 PD 4A2> 4D3 V3_3 2 1 10K RB11 1 5C7< 5D7< 7D6 7B8 5 5A8 27 26 23 25 4 28 3 31 2 V3_3 A8 A9 A10 A11 A12 A13 A14 A15 A16 U04 CY62128V 4 4 CY62128V \_ds26522topdn_\ PA PARENT BLOCK: 4A1> 9 10 11 12 13 14 15 16 17 WHEN SET FOR BOOT INTERNAL D18 HAS A 10K LOAD TO GND BOOT EXT D18 HAS A 10.5K LOAD TO V3V RCON BLOCK NAME: _motprocrescard_dn. 30 29 19 2 20 31 21 10K RB15 10K 2 RB16 1 10K RB23 10K 1 10K RB13 RB14 1 10K RB21 10K RB17 10K 1 RB20 1 1 1 1 1 2 1 RB12 1 5 RESET CONFIGURATION 6 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE2 32 VCC A6 6 11 : 1 N_C A5 7 12 CR-5 29 WE* 8 13 A4 9 A7 24 OE* CS0 22 EB0 OE 30 CE2 A3 16 14 A7 5 8 A2 32 VCC A6 6 7 GND 10 1 N_C A5 7 6 CE1* 15 29 WE* A4 8 5 A1 11 16 7D5 24 OE* 9 4 A3 10 3 A0 12 17 7D4 4D7 5B7 4D3 30 CE2 EB1 OE 7D5 5B7 4B5 CS0 22 CE1* A2 16 GND A1 11 2 A0 12 1 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 20 19 18 17 16 19 18 17 15 14 13 3 4A2> 5C7< STEVE SCULLY DS26522DK01A0 PD ENGINEER: TITLE: 22 21 20 23 21 3 2 2 5D7< 7D6 04/17/2006 1 PAGE: 2/6(BLOCK) 5/14(TOTAL) DATE: 1 A B C D A B PRT1_OUT PRT1_IN 6A8 6A8 8 6B8< RB02 PRT1_IN PRT1_OUT 6B8> SCI1_IN 4B8 4B8 SCI1_OUT 1 10 9 8 7 6 5 4 3 2 1 V3_3 E D C B A J H G F 9 8 7 6 7 CONN_DB9P 5 4 3 2 1 J02 V3_3 FORCEOFF* VCC R1IN T1OUT R1OUT FORCEON T1IN T2IN INVALID* R2OUT 1 V+1 V+2 C1+ C1- C2+ C2- V- GND T2OUT R2IN UB01 MAX3233E 2 1 8.0MHZ XB01 RB03 11 12 13 14 15 16 17 18 19 20 1 1 1.0M 6 PLACE PADS FOR CAP BUT DO NOT POPULATE 5 XTAL 5 4A7 OSC_MCU 4A6 BLOCK NAME: _motprocrescard_dn. 2 RB07 10K 6 4A4< 4B5 3 V3_3 4A6 4D6 4D6 PARENT BLOCK: 4 \_ds26522topdn_\ V3_3 1 2 3 V3/5* SHDN IN 2 0.1UF CB13 U02 3 2 2 1 330 RB22 1 J03 4A6 13 1 4B5 2 GREEN 1 1 STEVE SCULLY ONCE_TRST_B 14 2 DS02 FLASH_VPP RB01 10K 4A6 1 1 04/17/2006 RB05 10K 1 PAGE: 3/6(BLOCK) 6/14(TOTAL) DATE: ONCE_DE_B 12 V3_3 ALIGN KEY ONCE_TMS 10 8 6 4 2 CON14P J01 CON14P 2 11 9 7 5 3 1 V3_3 DS26522DK01A0 ENGINEER: TITLE: 4A7 8 KIT_STATUS OUT 1 PROC_RESET ONCE_TCLK 2107_TDO ONCE_TDI MAX1686_U 1 NOTE: A 100PF CAPACITOR HAS BEEN ADDED BETWEEN PROC_RESET AND VCC THIS ADDITION IS NOT SHOWN IN THE SCHEMATIC (SEE ERRATA SECTION OF DESIGN KIT USER MANUAL) 4 6 CXN 2 7 CXP C 1 2 RB06 D 10K RB18 2 1 7 1 2 1 CB09 8 4D3< 1 2 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE3 10K GND 4 2 1 : RB04 5 10K 10UF 1.0K CR-6 2 1 PGND A B C D A 8 PL14B PL15A/LDQS15 PL15B PL16A PL16B PL18A/VREF1_6 PL18B/VREF2_6 30 31 32 33 34 35 11 12 13 14 15 16 PL14A 27 9 29 PL13B 26 10 PL13A 25 PL12B/LLM0_PLLC_FB_A 23 6 7 BANK 5 1C7^ 8A6 I/O PORT 5 PLL INPUT BANK 1 BANK 4 6 8B2> 1C7^ 8B7 A_DUT_ BLOCK NAME: _motprocrescard_dn. 8B2 D_DUT U05 97_IO LFEC_T144_U 42 7 7 PL12A/LLM0_PLLT_FB_A 22 5 PLL INPUT 43 6 8 PL11B/LLM0_PLLC_IN_A 21 4 BANK 0 45 5 B PA PL11A/LLM0_PLLT_IN_A PL9B/PCLKC7_0 9 PLL INPUT 20 PL9A/PCLKT7_0 8 3 PL8B PL8A 6 1 7 PL7B 5 0 2 PL7A 46 C 4B5 PL2B/VREF1_7 PB10A 39 PD 47 3 4 4A4 1C7^ 40 27 48 8C2> 30 PL2A/VREF2_7 29 140 31 142 PT10A 141 PT10B PB10B 22 49 1 2 9B4< 2 PB11B 26 137 28 139 PT12B 138 PT13A PB13B RESET 3 CPUCLK_OUT 4 PB14B 4A2> PB15A PT13B PB14A/BDQS14 24 134 PT14B 135 PT14A/TDQS14 23 133 5A2> 82 81 79 PR13B/RLM0_PLLC_IN_A PR14A/RLM0_PLLT_FB_A PR14B/RLM0_PLLC_FB_A 4 \_ds26522topdn_\ 8B2> 8B2> 8B6 1C7^ 1C7^ 330 1D7^ V3_3 8C5< RB24 8C3< 3 MEM_SCK 8B6 3 2 STEVE SCULLY 2 FOR TQFP144 DS26522DK01A0 ENGINEER: TITLE: MEM_SCK MUST BE AT PIN77 TRISTATE_AD_BUS 8C5< INT5 74 8C3< USERFPGA2 75 PR16B 9B8< 9C8< 76 RB27 8A6 8A6 PR16A 0.0 MEM_CS MEM_SI MEM_SO RD_DUT WR_DUT ALE_DUT 4A7 77 PR18A/VREF1_3 PARENT BLOCK: DS03 INT_LED INT2 PR15B 78 83 PR13A/RLM0_PLLT_IN_A PR15A/RDQS15 85 PR12B/DI/CSSPI* 88 86 87 PR11A/D7/SPID0 9C8> PR12A/DOUT/CSO* 100 102 PR8B PR9B/PCLKC2_0 103 PR8A 101 104 PR7B PR9A/PCLKT2_0 105 106 PR2B/VREF1_2 PR7A 107 4 PR2A/VREF2_2 PR11B/BUSY/SISPI PLL INPUT PB17A/PCLKT5_0 51 5A6> 53 5C7< PB17B/PCLKC5_0 5D7< PB18A/WRITE* 56 D 57 1 0 132 21 PB16A/VREF2_5 5 PB18B/CS1* PT15A PB15B 6 PB19A/VREF1_4 58 2 7 59 3 8 60 4 25 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE4 61 5 : 62 CR-7 64 7 6 PT12A PB11A 41 CS_X1 CS_X2 8A6 8B2> 1C7^ 8A6 8B2> PB21B/D1/SPID6 BANK 7 BANK 6 1C7^ PB22A/BDQS22 65 8 PT15B 19 124 18 123 PT18B PT18A 20 130 PT16B/VREF1_0 127 PT17B/PCLKC0_0 129 PT17A/PCLKT0_0 131 PT16A/VREF2_0 PB16B/VREF1_5 50 0 120 PT20A PB20B/D0/SPID7 66 9 PLL INPUT 119 PT20B 17 122 PT19A/VREF1_1 PB19B/CS* 118 PT21A 16 121 PT19B/VREF2_1 PB20A/VREF2_4 4D4 116 OE RW CS0 PB22B/D3/SPID4 PT21B 4B5 114 PT22B 8B2> PB23A 67 12 BANK 3 PB23B/D4/SPID3 68 PB24B/D5/SPID2 69 8A6 8B2> PB21A/D2/SPID5 112 PT25A CS1 4C5 113 PT23A BANK 2 115 PT22A/TDQS22 5B7 4D7 5B4 4D7 CS2 EB0 EB1 111 PT25B PB25B/D6/SPID1 70 8A6 8B2> PLL INPUT CS_X3 CS_X4 CS_X5 04/17/2006 1 PAGE: 4/6(BLOCK) 7/14(TOTAL) DATE: 1 A B C D A B C : 8 8 7 9 11 13 6 5 4 3 7 13 7 13 11 9 7 5 3 14 12 10 8 6 4 2 14 12 10 8 6 4 2 13 11 9 7 5 3 1 14 12 10 8 6 4 2 4A7 INT2 7C4 8C3< 1 2 7A4 7A7 7A7 7C4 7C4 CS_X2 CS_X1 RD_DUT WR_DUT 8 14 12 10 7C3> 8B2> 8B2> 8B2> 8B2> 8B2> 8B2> 1C7^ 1C7^ 1C7^ 1C7^ BLOCK NAME: _motprocrescard_dn. 6 7A5 4 8B6 1D7^ 8C3< 8C5< V3_3 8C3< 8C5< 1D7^ 8C3< 7C4 8B6 8C3< 8C3< 4A7 4A7 4A7 7B4 5 INT2 INT3 INT4 INT5 2 1 2 1 10K RB38 V3_3 4 2 1 RB19 10K RB31 5 PARENT BLOCK: \_ds26522topdn_\ 4 JUMPER PINS 12+14 TO TRISTATE THE ADDRESS DATABUSS OF THE FPGA. THIS ALLOWS THE USER TO CONNECT A DIFFERENT PROCESSOR CS_X3 RB39 CS_X4 0 10K 6 2 4A7 INT3 0 1 2 A_DUT_ 6 TRISTATE_AD_BUS J08D_DUT NOPOP CONN_14P 9 11 6 7 3 4 5 3 5 2 1 5 7 1 3 8 1 J09 NOPOP CONN_14P 1 12 7 10K RB40 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE5 2 1 D CR-8 10K 1D7^ 8C5< 3 3 7B4 4A7 4A7 4A7 IN IN IN IN WR_DUT RD_DUT CS_X1 CS_X2 CS_X3 CS_X4 CS_X5 RESET STEVE SCULLY DS26522DK01A0 D_DUT A_DUT_ ENGINEER: TITLE: 8C5< 8B6 8C5< 8C5< 8B6 7C4 2 2 INT5 INT4 INT3 INT2 IO OUT OUT OUT OUT OUT OUT OUT OUT OUT 8A6 8A6 8A6 8A6 7C8 1C7^ 1C7^ 9B4< 7A6 8A6 1C7^ 7C4 8A6 1C7^ 7C4 8A6 1C7^ 7A6 8B7 1C7^ 7A5 7A5 7A7 7A7 7A4 4A4 04/17/2006 1 PAGE: 5/6(BLOCK) 8/14(TOTAL) DATE: 1C7^ 1 A B C D A 8 7B3< 7B4 9B1 7C4 7C4 2 3 1 1 UB04 I26 2.7V 10 8 6 4 10K RB26 7 GND SHDN* IN I28 RST* IC 4 5 L_TCK 9C1< 4 7 3 8 9C4> 9C4< 9C4< V3_3 V3_3 V1_2 L_TDO L_TDI 6 CB27 10UF CB25 CB19 10UF CB28 .1UF BLOCK NAME: _motprocrescard_dn. OUT UB05 MAX1963 6 GND HOLD* WP* VCC 10K AT25160A_U CS* SO SI MEM_CS 2 5 SCK V3_3 VCC TDO TDI TCK CONN_10P GND 7 5 3 MEM_SCK 6 MEM_SO MEM_SI 9 7 5 3 9C4< 5 8C2> 7C8 PARENT BLOCK: 1C7^ 4 \_ds26522topdn_\ 4A4 L_TMS L_TDO L_TDI RESET 9D6 9D6 9D6 9D6 L_TCK CFG1 CFG0 90 91 19 54 126 VCCJ VCCAUX1 VCCAUX2 9B8< DONE INIT* 7B3< CCLK 97 95 94 10 99 VCC3 XRES 92 VCC2 NEEDS 10K,1% RESISTOR PLACE CLOSE TO PIN STEVE SCULLY DS26522DK01A0 ENGINEER: TITLE: 3 CONTROL U05 LFEC_T144_U I10 97_IO 13 VCC1 V3_3 2 END OF PROCESSOR HIERARCHY ALL LOW FOR SPI3 MODE PROGRAM* CFG2 89 93 TMS TDO TDI TCK 17 18 16 14 GND3A/GND4 72 L_TMS GND3B 80 2 GND4 63 TMS GND5 52 1 GND6A 28 RB25 2 73 VCCIO3A 3 84 VCCIO3B GND6B/GND5 37 4 55 VCCIO4A GND7/GND0 1 5 136 VCCIO0A GND0 128 71 VCCIO4B GND8 15 I24 6 143 VCCIO0B GND1 38 VCCIO5A GND9 96 J04 .1UF 110 VCCIO1A 117 44 VCCIO5B GND10 98 7 CB26 B 8 10K 04/17/2006 1 PAGE: 6/6(BLOCK) 9/14(TOTAL) DATE: BLOCK I5 TP02 I6 TP01 MEM_SCK RB29 9A6< V3_3 V1_2 1 RB30 10UF @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE6 CB24 125 VCCIO1B GND2/GND1 24 VCCIO6A NC1 11 C : .1UF 108 VCCIO2 109 36 VCCIO6B 144 1 VCCIO7 NC2 12 1 1 D CR-9 10K A B C D A B C J3 M4 L4 WR_DUT CS_X2 CS_X1 VCC TDO CONN_10P GND 7 TDI TCK 1.0K RB28 10 8 6 4 2 7 10C8> JTCLK_DUT JTDO_1_DUT V3_3 10C8< 10A7< 10C8< JTDI_1_DUT JTCLK_DUT JTMS_DUT 10C8< BLOCK NAME: 10A7 10C8< U06 I219 BGA DS26522 NA DS26522 A0 A1 A2 A3 A4 A5 A6 A7 A8 A12 10B2< D7 D6 D5 10C2< D4 D3 D2 _ds26522dk01a0dutdn_. 6 6 5 4 3 2 1 0 F2 G1 G2 H1 H2 J1 J2 I235 I234 \_ds26522topdn_\ 4 INT_LED AND TESTPOINTS FOR ADDR/DATA/CTRL TESTPOINTS FOR ADDR/DATA/CTRL ARE IN THE MICRO PROCESSOR BLOCK PARENT BLOCK: 5 7 F1 10D7< 8 E2 1C6^ 12 E1 D6_SPI_CPHA D7_SPI_CPOL 10C2< I236 K1 K2 D5_SPI_SWAP L1 I237 D4 L2 I238 D3 M1 M2 A_DUT 8 7 JTDI_2_DUT 10C8< 5 3 TMS RESETB BTS SPI_SEL SCAN_EN SCAN_MODE CSB1 CSB2 WRB_RWB RDB_DBS JTCLK JTDI1 JTDI2 JTDO1 JTDO2 JTMS L3 M3 4 7 6 5 4 3 2 1 0 3 3 D7_SPI_CPOL PORT) V3_3 2 RB50 1.0K 1.0K (HIGH STEVE SCULLY 2 OF DS26522DK TXENABLE_2 1.0K 2 I538 04/17/2006 BLOCK 1.0K RB52 2 I535 1 PAGE: 1/5(BLOCK) 10/14(TOTAL) DATE: 1 RB51 RB42 1.0K HIERARCHY FOR NORMAL OPERATION) TXENABLE_1 SCANEN_DUT (LOW FOR NORMAL OPERATION) 1.0K 2 I527 R02 2 I525 I515 RB49 2 I521 RB41 1.0K 1.0K 3 SCANMO_DUT (LOW FOR NORMAL OPERATION) 11A7< 11C7< 10B8< 10B8< 10B8< 2 RB43 RB48 1.0K I520 BTS_DUT (HIGH FOR MOTO MODE) DS26522DK01A0 ENGINEER: TITLE: 1C6^ D6_SPI_CPHA 10D7 D5_SPI_SWAP 2 SPISEL_DUT (LOW FOR PARALLEL 10B8< 10C4 10C4 10C4 BEGINNING D_DUT 9 5 JTDO_2_DUT 3 1 J05 I231 RESET_DUT K3 E5 BTS_DUT JTRST_DUT 1 10D7< D7 10C8> 10C8< 1C6^ 10B2< 10B2< SCANEN_DUT D6 10A2< SPISEL_DUT SCANMO_DUT C6 10D7< 1C6^ 10B2< 10D7< 10D7< 1C6^ H3 RD_DUT 10D7< 1C6^ 10A7 1C6^ 10A7< L5 10A7 M6 L7 JTDI_2_DUT 10A8 JTCLK_DUT M7 JTDO_1_DUT 10A7 JTDI_1_DUT M8 JTDO_2_DUT 10A8 M5 JTMS_DUT 10A7 D1 D0 ATVSS2_2 A10 JTRST ATVSS2_1 B10 L6 ATVSS1_2 A3 JTRST_DUT B3 10A8 ATVSS1_1 INT ARVSS2_5 D9 10D7< ARVSS2_4 D10 1D6^ A7 MCLK ARVSS2_3 K4 ARVSS2_2 C7 M9 ARVSS2_1 B7 INT_DUT ARVSS1_5 C1 MCLK_TAP7 V3_3 ARVSS1_4 C4 14D5> DVSS2_8 E9 1C6^ DVSS2_7 H9 10C3 DVSS2_6 G9 C3 IO 1C6^ H5 DVSS2_5 E8 1C6^ D8 10B4 K9 DVSS2_4 ARVSS1_3 A_DUT D_DUT 1D6^ 10B8< D5 DVSS2_3 E10 ARVSS1_2 IN D4 DVSS2_2 F9 ACVDD1_1 C2 RESET_DUT F10 ACVDD2_2 ARVSS1_1 D C10 1C6^ A6 10C8> D3 DVSS2_1 ARVDD1_1 C5 IN B6 1C6^ C11 10B8< C12 1C6^ G4 10B8< D2 DVSS1_4 E3 ARVDD1_2 ACVSS2_2 IN D1 DVSS1_3 F4 ARVDD1_3 K10 RD_DUT WR_DUT INT_DUT H4 1C6^ J4 10B8< G3 10B8< C9 DVSS1_2 E4 ARVDD1_4 ACVSS2_1 IN F3 ARVDD1_5 K11 IN DVSS1_1 ARVDD2_1 ACVSS1_2 CS_X2 CS_X1 G10 5 J9 6 J10 7 C8 ARVDD2_2 F5 8 3 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE1 D11 ARVDD2_3 ACVSS1_1 IN : D12 ARVDD2_4 G5 IN CR-10 H10 ARVDD2_5 1 ATVDD1_1 3 ATVDD1_2 1 ATVDD2_1 3 ATVDD2_2 1 DVDD1_1 3 DVDD1_2 1 DVDD1_3 3 DVDD1_4 1 DVDD2_1 1 DVDD2_2 3 DVDD2_3 JP10 JP17 1 DVDD2_4 JP15 JP13 JP16 JP18 JP19 A B C D A B C D CR-11 : 8 8 14C6< F11 F12 G11 G12 E7 M10 H12 L11 J11 K12 L12 TSYNC_2 TSSYNCIO_2 TCLK_2 TCHBLK_CLK_2 TXENABLE_2 BPCLK_2 RSER_2 RSIG_2 RSYSCLK_2 RSYNC_2 RM_RFSYNC_2 14B5 14A8 14A8 14A6 14C3< 10A2< 14A2 14D3< 14B6< 14A5 14A6 RCHBLK_CLK_2 14A8< 14C3< 7 RCLK_2 14B2 M11 L9 L10 H11 TSYSCLK_2 14B4 REFCLKIO_2 E11 TSIG_2 14D1 14C3< E12 14B3< TSER_2 J6 RCHBLK_CLK_1 14B8< K8 L8 REFCLKIO_1 RCLK_1 14B2 14B3< G6 H6 RSIG_1 14D3< RM_RFSYNC_1 K5 RSER_1 14A2 K7 K6 BPCLK_1 10A2< RSYNC_1 E6 TXENABLE_1 14B3< 14A6 F7 TCHBLK_CLK_1 14B6 J8 G8 TCLK_1 14A8 RSYSCLK_1 G7 TSSYNCIO_1 14A8 14A5 H8 J7 TSYSCLK_1 TSYNC_1 14A5 H7 F8 TSIG_1 TSER_1 14C4 14D1 7 U06 TTIP2A TTIP2B TRING2A TRING2B RRING2A RRING2B RTIP2A RTIP2B _ds26522dk01a0dutdn_. 6 DS26522 RLF_LTC2 TTIP1B TTIP1A TRING1A TRING1B RRING1A RRING1B RTIP1A RTIP1B AL_RSIGF_FLOS2 I2 BGA DS26522 NA U06 RLF_LTC1 AL_RSIG_FLOS1 I1 BGA DS26522 NA DS26522 BLOCK NAME: RCHBLK_CLK2 RCLK2 REFCLKIO2 RM_RFSYNC2 RSYNC2 RSYSCLK2 RSIG2 RSER2 BPCLK2 TXENABLE2 TCHBLK_CLK2 TCLK2 TSSYNCIO2 TSYNC2 TSYSCLK2 TSIG2 TSER2 RCHBLK_CLK1 RCLK1 REFCLKIO1 RM_RFSYNC1 RSYNC1 RSYSCLK1 RSIG1 RSER1 BPCLK1 TXENABLE1 TCHBLK_CLK1 TCLK1 TSSYNCIO1 TSYNC1 TSYSCLK1 TSIG1 TSER1 6 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE2 RLF_LTC_1 A12 B12 B11 A11 B8 A8 A9 B9 J12 M12 A5 B5 A4 B4 A1 B1 A2 B2 12C7< 12B7< 12B7< 12B7< 11B3 11C3 11B3 5 13C7< 13B7< 13B7< 13B7< PARENT BLOCK: TTIP_2 TRING_2 RRING_2 RTIP_2 11B3 \_ds26522topdn_\ AL_RSIGF_FLOS_2 RLF_LTC_2 TTIP_1 TRING_1 RRING_1 RTIP_1 F6AL_RSIGF_FLOS_1 J5 5 4 4 3 3 STEVE SCULLY DS26522DK01A0 RLF_LTC_2 AL_RSIGF_FLOS_2 RLF_LTC_1 AL_RSIGF_FLOS_1 ENGINEER: TITLE: 11B5> 11B5> 11D5> 11D5> 1 2 1 2 1 I13 DS06 1 2 I7 DS04 2 2 2 330 I14 DS07 330 330 RB33 RB32 RB35 RB34 I8 DS05 330 04/17/2006 1 PAGE: 2/5(BLOCK) 11/14(TOTAL) DATE: 1 A B C D A 8 11C5< RRING_1 RTIP_1 TRING_1 11C5> 11D5< TTIP_1 11C5> 7 _1 7 1 2 B 8 BLOCK NAME: 0.0 R09 0.0 R10 0.0 R08 0.0 R07 _ds26522dk01a0dutdn_. 6 6 1:0.8 1:1 1:1 1:0.8 TB01 14 15 16 11 10 9 TB01 5 6 7 8 4 3 2 1 5 5 PARENT BLOCK: 51.1 560PF CB46 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE3 RB54 C : 2 \_ds26522topdn_\ 4 4 B D F H A C E G J10 J12 1 J13 CONN_BNC_5PIN CONN_RJ48 2 4 6 8 1 1 3 5 7 CONN_BNC_5PIN 2 D CR-12 1 CB44 2 1 2 .1UF 61.9 2 61.9 RB44 1 RB45 3 3 STEVE SCULLY DS26522DK01A0 ENGINEER: TITLE: 2 2 04/17/2006 1 PAGE: 3/5(BLOCK) 12/14(TOTAL) DATE: 1 A B C D A 8 11A5< RRING_2 RTIP_2 TRING_2 11A5> 11B5< TTIP_2 11A5> 7 _1 7 1 2 B 8 BLOCK NAME: 0.0 R05 0.0 R06 0.0 R04 0.0 R03 _ds26522dk01a0dutdn_. 6 6 14 15 16 11 10 9 I5 TB02 1:0.8 1:1 1:1 1:0.8 I4 TB02 1 \_ds26522topdn_\ 4 8 H 5 4 3 2 5 PARENT BLOCK: B D F A C E J15 1 J14 CONN_BNC_5PIN I6 CONN_RJ48 2 4 6 G J11 6 7 1 1 3 5 7 CONN_BNC_5PIN I2 I3 4 8 5 51.1 560PF CB45 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE4 2 C : RB53 2 D CR-13 1 CB43 2 1 2 .1UF 61.9 2 61.9 RB46 1 RB47 3 3 STEVE SCULLY DS26522DK01A0 ENGINEER: TITLE: 2 2 04/17/2006 1 PAGE: 2/4(BLOCK) 11/34(TOTAL) DATE: 1 A B C D A B C D 4 1 CR-14 4 1 : 8 14A8 14A8 14A8 14A8 5 11D7 11B7> 11D7 11D7 11B7 JP09 5 TSYNC_1 13 TSYNC_1 13 11 9 7 5 3 1 14 12 10 8 6 4 2 J07 30 RB36 14 12 10 8 6 4 2 7 CONN_14P 11 9 TSYNC_2 TSSYNCIO_1 3 7 1 TSYNC_2 RCLK_2 JP12 MCLK_TAP2 30 RB37 TSSYNCIO_2 11A7> 14C5> JP06 7 MCLK_TAP1 T1_OSC E1_OSC 14C5> RCLK_1 5 8 V3_3 11C7> OUT VCC 11B7> OSC YB01 GND 1 OUT VCC 8 V3_3 1.544MHZ_3.3V GND 1 OSC YB02 2.048MHZ_3.3V 8 1 11A7< 4 3 BLOCK NAME: _ds26522dk01a0dutdn_. 6 PINS CLOSE RESISTORS) RSIG_2 11A7> 4 3 5 11C7< RSYSCLK_1 TSYSCLK_1 RSYSCLK_2 TSYSCLK_2 2 2 2 2 2 2 11B7< TSIG_2 4 MCLK_TAP4 JP01 MCLK_TAP3 JP02 MCLK_TAP5 JP03 MCLK_TAP6 JP04 11D7< 4 TSIG_1 \_ds26522topdn_\ JP11 JP14 PARENT BLOCK: 5 11D7< 11A7> 11B7< 5 6 7 2 30 RPB07 8 14B7 14A7 14A4 1 MCLK_TAP1 MCLK_TAP2 RSIG_1 5 6 MCLK_TAP3 14A4 14A4 MCLK_TAP4 14A4 MCLK_TAP5 10C8< MCLK_TAP7 MCLK_TAP6 14B1 MCLK_TAP8 11C7> 30 7 2 5 6 7 RPB05 8 30 RPB04 8 1 4 3 2 1 PLACE SYNC AND SYNCIO TO DUT (NO TERMINATION 11C7 11D7< UB074 11A7 TCLK_2 RSYNC_1 UB064 NC7SZ86_U BUFFER TCLK_1 RSYNC_2 2 2 2 1 NC7SZ86_U BUFFER 6 @\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE5 3 31 1 3 1 3 1 3 1 3 1 3 3 1 3 1 1 14D5> 14D5> 14D5> 14D5> 11A7> 11C7> 3 5 6 2 BPCLK_1 JP05 BPCLK_2 ENGINEER: STEVE SCULLY DS26522DK01A0 2 5 10 9 7 5 3 1 9 7 5 3 1 14B1 14D5> 14B1 14D5> 04/17/2006 1 PAGE: 5/5(BLOCK) 14/14(TOTAL) DATE: BLOCK MCLK_TAP8 MCLK_TAP8 11B7< TSER_2 2 HIERARCHY 11C7> 10 8 6 4 2 J06 11D7< TSER_1 1 2 CONN_10P 8 6 4 2 JP08 JP07 11A7> REFCLKIO_2 REFCLKIO_1 4 6 7 2 3 RPB02 8 1 30 5 6 4 30 7 2 3 RPB01 8 1 2 END OF DS26522DK TITLE: 4 30 7 2 11A7 11C7 RM_RFSYNC_1 TCHBLK_CLK_1 RCHBLK_CLK_1 RM_RFSYNC_2 TCHBLK_CLK_2 RPB03 8 3 5 6 RCHBLK_CLK_2 4 3 7 2 30 RPB06 8 1 1 11C7> 11D7> 11B7> 11A7> 11A7> 11A7> RSER_2 RSER_1 3 3 1 3 31 1 A B C D