DS26524
Quad T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS26524 is a single-chip 4-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
Four Complete T1, E1, or J1 Long-Haul/ShortHaul Transceivers (LIU plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
TYPICAL OPERATING CIRCUIT
DS26524
Transmit Open- and Short-Circuit Detection
T1/E1/J1
NETWORK
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
T1/J1/E1
Transceiver
x4
Transmit Synchronizer
BACKPLANE
TDM
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
ORDERING INFORMATION
J1 Support
PART
TEMP RANGE
PIN-PACKAGE
E1 G.704 and CRC-4 Multiframe
DS26524G
DS26524G+
DS26524GN
DS26524GN+
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
T1-to-E1 Conversion
Features Continued in Section 2.
+ Denotes lead-free/RoHS compliant device.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS26524 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
DETAILED DESCRIPTION.................................................................................................9
1.1
2.
MAJOR OPERATING MODES .............................................................................................................9
FEATURE HIGHLIGHTS ..................................................................................................10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
GENERAL ......................................................................................................................................10
LINE INTERFACE ............................................................................................................................10
CLOCK SYNTHESIZER ....................................................................................................................10
JITTER ATTENUATOR .....................................................................................................................10
FRAMER/FORMATTER ....................................................................................................................10
SYSTEM INTERFACE ......................................................................................................................11
HDLC CONTROLLERS ...................................................................................................................12
TEST AND DIAGNOSTICS ................................................................................................................12
CONTROL PORT ............................................................................................................................12
3.
APPLICATIONS ...............................................................................................................13
4.
SPECIFICATIONS COMPLIANCE ...................................................................................14
5.
ACRONYMS AND GLOSSARY .......................................................................................16
6.
BLOCK DIAGRAMS.........................................................................................................17
7.
PIN DESCRIPTIONS ........................................................................................................19
7.1
8.
PIN FUNCTIONAL DESCRIPTION ......................................................................................................19
FUNCTIONAL DESCRIPTION .........................................................................................26
8.1
8.2
PROCESSOR INTERFACE ................................................................................................................26
CLOCK STRUCTURE.......................................................................................................................26
8.2.1
8.3
8.4
8.4.1
8.5
8.6
8.7
8.8
Example Device Initialization Sequence .............................................................................................. 29
GLOBAL RESOURCES ....................................................................................................................29
PER-PORT RESOURCES ................................................................................................................29
DEVICE INTERRUPTS .....................................................................................................................29
SYSTEM BACKPLANE INTERFACE ...................................................................................................31
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
Backplane Clock Generation ............................................................................................................... 26
RESETS AND POWER-DOWN MODES ..............................................................................................28
INITIALIZATION AND CONFIGURATION ..............................................................................................29
Elastic Stores ....................................................................................................................................... 31
IBO Multiplexer..................................................................................................................................... 34
H.100 (CT Bus) Compatibility .............................................................................................................. 40
Receive and Transmit Channel Blocking Registers............................................................................. 41
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41
FRAMERS ......................................................................................................................................42
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
T1 Framing........................................................................................................................................... 42
E1 Framing........................................................................................................................................... 45
T1 Transmit Synchronizer .................................................................................................................... 47
Signaling .............................................................................................................................................. 48
T1 Data Link......................................................................................................................................... 52
E1 Data Link......................................................................................................................................... 54
Maintenance and Alarms ..................................................................................................................... 55
E1 Automatic Alarm Generation .......................................................................................................... 58
Error-Count Registers .......................................................................................................................... 59
DS0 Monitoring Function...................................................................................................................... 61
Transmit Per-Channel Idle Code Insertion........................................................................................... 62
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DS26524 Quad T1/E1/J1 Transceiver
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
8.10
HDLC CONTROLLERS ................................................................................................................66
8.10.1
8.10.2
8.11
Receive HDLC Controller..................................................................................................................... 66
Transmit HDLC Controller.................................................................................................................... 69
LINE INTERFACE UNITS (LIUS)....................................................................................................71
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.12
LIU Operation....................................................................................................................................... 74
Transmitter ........................................................................................................................................... 75
Receiver ............................................................................................................................................... 78
Jitter Attenuator.................................................................................................................................... 81
LIU Loopbacks ..................................................................................................................................... 82
BIT-ERROR-RATE TEST (BERT) FUNCTION ................................................................................84
8.12.1
8.12.2
9.
Receive Per-Channel Idle Code Insertion............................................................................................ 62
Per-Channel Loopback ........................................................................................................................ 62
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 62
T1 Programmable In-Band Loop Code Generator............................................................................... 63
T1 Programmable In-Band Loop Code Detection................................................................................ 64
Framer Payload Loopbacks ................................................................................................................. 65
BERT Repetitive Pattern Set ............................................................................................................... 85
BERT Error Counter............................................................................................................................. 85
DEVICE REGISTERS .......................................................................................................86
9.1
REGISTER LISTINGS ......................................................................................................................86
9.1.1
9.1.2
9.1.3
9.2
REGISTER BIT MAPS......................................................................................................................97
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4
9.5
9.6
FUNCTIONAL TIMING ...................................................................................................233
THERMAL CHARACTERISTICS ....................................................................................................249
LINE INTERFACE CHARACTERISTICS ..........................................................................................249
AC TIMING CHARACTERISTICS ..................................................................................250
12.1
12.2
12.3
13.
T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................233
T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................238
E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................243
E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................245
OPERATING PARAMETERS.........................................................................................248
11.1
11.2
12.
Receive Register Definitions.............................................................................................................. 122
Transmit Register Definitions............................................................................................................. 181
LIU REGISTER DEFINITIONS.........................................................................................................216
BERT REGISTER DEFINITIONS.....................................................................................................225
10.1
10.2
10.3
10.4
11.
Global Register Bit Map ....................................................................................................................... 97
Framer Register Bit Map ...................................................................................................................... 98
LIU Register Bit Map .......................................................................................................................... 106
BERT Register Bit Map ...................................................................................................................... 106
GLOBAL REGISTER DEFINITIONS ..................................................................................................107
FRAMER REGISTER DEFINITIONS .................................................................................................122
9.4.1
9.4.2
10.
Global Register List.............................................................................................................................. 88
Framer Register List............................................................................................................................. 89
LIU and BERT Register List................................................................................................................. 96
MICROPROCESSOR BUS AC CHARACTERISTICS ........................................................................250
JTAG INTERFACE TIMING .........................................................................................................259
SYSTEM CLOCK AC CHARACTERISTICS ....................................................................................260
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................261
13.1
13.1.1
13.1.2
13.1.3
13.1.4
TAP CONTROLLER STATE MACHINE .........................................................................................262
Test-Logic-Reset................................................................................................................................ 262
Run-Test-Idle ..................................................................................................................................... 262
Select-DR-Scan ................................................................................................................................. 262
Capture-DR ........................................................................................................................................ 262
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DS26524 Quad T1/E1/J1 Transceiver
13.1.5
13.1.6
13.1.7
13.1.8
13.1.9
13.1.10
13.1.11
13.1.12
13.1.13
13.1.14
13.1.15
13.1.16
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.3
13.4
13.4.1
13.4.2
13.4.3
Shift-DR.............................................................................................................................................. 262
Exit1-DR............................................................................................................................................. 262
Pause-DR........................................................................................................................................... 262
Exit2-DR............................................................................................................................................. 262
Update-DR ......................................................................................................................................... 262
Select-IR-Scan ............................................................................................................................... 262
Capture-IR ...................................................................................................................................... 263
Shift-IR............................................................................................................................................ 263
Exit1-IR........................................................................................................................................... 263
Pause-IR......................................................................................................................................... 263
Exit2-IR........................................................................................................................................... 263
Update-IR ....................................................................................................................................... 263
INSTRUCTION REGISTER ...........................................................................................................265
SAMPLE:PRELOAD .......................................................................................................................... 265
BYPASS ............................................................................................................................................. 265
EXTEST ............................................................................................................................................. 265
CLAMP............................................................................................................................................... 265
HIGHZ ................................................................................................................................................ 265
IDCODE ............................................................................................................................................. 265
JTAG ID CODES......................................................................................................................266
TEST REGISTERS .....................................................................................................................266
Boundary Scan Register .................................................................................................................... 266
Bypass Register ................................................................................................................................. 266
Identification Register......................................................................................................................... 266
14.
PIN CONFIGURATION...................................................................................................271
15.
PACKAGE INFORMATION ............................................................................................272
15.1
16.
256-BALL TE-CSBGA (56-G6028-001) ...................................................................................272
DOCUMENT REVISION HISTORY ................................................................................273
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DS26524 Quad T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. Backplane Clock Generation................................................................................................................... 27
Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 30
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 35
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 36
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 37
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode................................................................................................... 40
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ....................................................................... 41
Figure 8-8. CRC-4 Recalculate Method .................................................................................................................... 62
Figure 8-9. Receive HDLC Example.......................................................................................................................... 68
Figure 8-10. HDLC Message Transmit Example....................................................................................................... 70
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal Protection ............................. 72
Figure 8-12. T1/J1 Transmit Pulse Templates .......................................................................................................... 76
Figure 8-13. E1 Transmit Pulse Templates ............................................................................................................... 77
Figure 8-14. Typical Monitor Application ................................................................................................................... 79
Figure 8-15. Jitter Attenuation ................................................................................................................................... 81
Figure 8-16. Analog Loopback................................................................................................................................... 82
Figure 8-17. Local Loopback ..................................................................................................................................... 82
Figure 8-18. Remote Loopback ................................................................................................................................. 83
Figure 8-19. Dual Loopback ...................................................................................................................................... 83
Figure 9-1. Register Memory Map for the DS26524.................................................................................................. 87
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 233
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 233
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 234
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 234
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 235
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 236
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 237
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 238
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 238
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 239
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 239
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 240
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 241
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 242
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 243
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 243
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 245
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 245
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 247
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 251
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 251
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 252
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DS26524 Quad T1/E1/J1 Transceiver
Figure 12-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 252
Figure 12-5. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 254
Figure 12-6. Receive-Side Timing, Elastic Store Enabled (T1 Mode)..................................................................... 255
Figure 12-7. Receive Framer Timing—Line Side .................................................................................................... 255
Figure 12-8. Transmit Formatter Timing—Backplane ............................................................................................. 257
Figure 12-9. Transmit Formatter Timing, Elastic Store Enabled ............................................................................. 258
Figure 12-10. BPCLK Timing................................................................................................................................... 258
Figure 12-11. Transmit Formatter Timing—Line Side ............................................................................................. 258
Figure 12-12. JTAG Interface Timing Diagram........................................................................................................ 259
Figure 13-1. JTAG Functional Block Diagram ......................................................................................................... 261
Figure 13-2. TAP Controller State Diagram............................................................................................................. 264
Figure 14-1. Pin Configuration—256-Ball TE-CSBGA ............................................................................................ 271
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LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14
Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15
Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 19
Table 8-1. Reset Functions........................................................................................................................................ 28
Table 8-2. Registers Related to the Elastic Store...................................................................................................... 31
Table 8-3. Elastic Store Delay After Initialization....................................................................................................... 32
Table 8-4. Registers Related to the IBO Multiplexer ................................................................................................. 34
Table 8-5. RSER Output Pin Definitions.................................................................................................................... 38
Table 8-6. RSIG Output Pin Definitions ..................................................................................................................... 38
Table 8-7. TSER Input Pin Definitions ....................................................................................................................... 39
Table 8-8. TSIG Input Pin Definitions ........................................................................................................................ 39
Table 8-9. RSYNC Input Pin Definitions .................................................................................................................... 39
Table 8-10. D4 Framing Mode................................................................................................................................... 42
Table 8-11. ESF Framing Mode ................................................................................................................................ 43
Table 8-12. SLC-96 Framing ..................................................................................................................................... 43
Table 8-13. E1 FAS/NFAS Framing .......................................................................................................................... 45
Table 8-14. Registers Related to Setting Up the Framer .......................................................................................... 46
Table 8-15. Registers Related to the Transmit Synchronizer.................................................................................... 47
Table 8-16. Registers Related to Signaling ............................................................................................................... 48
Table 8-17. Registers Related to SLC-96.................................................................................................................. 51
Table 8-18. Registers Related to T1 Transmit BOC.................................................................................................. 52
Table 8-19. Registers Related to T1 Receive BOC................................................................................................... 53
Table 8-20. Registers Related to T1 Transmit FDL................................................................................................... 53
Table 8-21. Registers Related to T1 Receive FDL.................................................................................................... 54
Table 8-22. Registers Related to E1 Data Link ......................................................................................................... 54
Table 8-23. Registers Related to Maintenance and Alarms...................................................................................... 56
Table 8-24. T1 Alarm Criteria .................................................................................................................................... 58
Table 8-25. T1 Line Code Violation Counting Options .............................................................................................. 59
Table 8-26. E1 Line Code Violation Counting Options .............................................................................................. 60
Table 8-27. T1 Path Code Violation Counting Arrangements ................................................................................... 60
Table 8-28. T1 Frames Out of Sync Counting Arrangements ................................................................................... 60
Table 8-29. Registers Related to DS0 Monitoring ..................................................................................................... 61
Table 8-30. Registers Related to T1 In-Band Loop Code Generator ........................................................................ 63
Table 8-31. Registers Related to T1 In-Band Loop Code Detection ......................................................................... 64
Table 8-32. Registers Related to Framer Payload Loopbacks.................................................................................. 65
Table 8-33. Registers Related to the HDLC .............................................................................................................. 66
Table 8-34. Recommended Supply Decoupling ........................................................................................................ 73
Table 8-35. Registers Related to Control of DS26524 LIU ....................................................................................... 74
Table 8-36. Telecommunications Specification Compliance for DS26524 Transmitters .......................................... 75
Table 8-37. Transformer Specifications..................................................................................................................... 75
Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications .......................................... 79
Table 8-39. Jitter Attenuator Standards Compliance................................................................................................. 81
Table 8-40. Registers Related to BERT Configure, Control, and Status................................................................... 84
Table 9-1. Register Address Ranges (in Hex)........................................................................................................... 86
Table 9-2. Global Register List .................................................................................................................................. 88
Table 9-3. Framer Register List ................................................................................................................................. 89
Table 9-4. LIU Register List ....................................................................................................................................... 96
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DS26524 Quad T1/E1/J1 Transceiver
Table 9-5. BERT Register List ................................................................................................................................... 96
Table 9-6. Global Register Bit Map............................................................................................................................ 97
Table 9-7. Framer Register Bit Map .......................................................................................................................... 98
Table 9-8. LIU Register Bit Map .............................................................................................................................. 106
Table 9-9. BERT Register Bit Map .......................................................................................................................... 106
Table 9-10. Global Register Set .............................................................................................................................. 107
Table 9-11. Backplane Reference Clock Select ...................................................................................................... 111
Table 9-12. Master Clock Input Selection................................................................................................................ 112
Table 9-13. Device ID Codes in this Product Family ............................................................................................... 115
Table 9-14. LIU Register Set ................................................................................................................................... 216
Table 9-15. Transmit Load Impedance Selection.................................................................................................... 217
Table 9-16. Transmit Pulse Shape Selection .......................................................................................................... 217
Table 9-17. Receive Level Indication....................................................................................................................... 222
Table 9-18. Receive Impedance Selection.............................................................................................................. 223
Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 224
Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 224
Table 9-21. BERT Register Set ............................................................................................................................... 225
Table 9-22. BERT Pattern Select ............................................................................................................................ 227
Table 9-23. BERT Error Insertion Rate ................................................................................................................... 228
Table 9-24. BERT Repetitive Pattern Length Select ............................................................................................... 228
Table 11-1. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-2. Capacitance.......................................................................................................................................... 248
Table 11-3. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-4. Thermal Characteristics........................................................................................................................ 249
Table 11-5. Transmitter Characteristics................................................................................................................... 249
Table 11-6. Receiver Characteristics....................................................................................................................... 249
Table 12-1. AC Characteristics—Microprocessor Bus Timing ................................................................................ 250
Table 12-2. Receiver AC Characteristics ................................................................................................................ 253
Table 12-3. Transmit AC Characteristics................................................................................................................. 256
Table 12-4. JTAG Interface Timing.......................................................................................................................... 259
Table 12-5. System Clock AC Charateristics .......................................................................................................... 260
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 265
Table 13-2. ID Code Structure................................................................................................................................. 266
Table 13-3. Boundary Scan Control Bits ................................................................................................................. 266
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DS26524 Quad T1/E1/J1 Transceiver
1.
DETAILED DESCRIPTION
The DS26524 is a 4-port monolithic device featuring independent transceivers that can be software configured for
T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic
store, and a TDM backplane interface. The DS26524 is controlled via an 8-bit parallel port. Internal impedance
matching is provided for both transmit and receive paths, reducing external component count.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes
for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be
programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be
placed in either transmit or receive data paths.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane
interface section.
Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives
data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot, or to FDL
(T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to
manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). The interleave bus option (IBO) is provided to allow up to eight transceivers to share a
high-speed backplane. The DS26524 also contains an internal clock adapter useful for the creation of a
synchronous, high-frequency backplane timing source.
The parallel port provides access for configuration and status of all the DS26524’s features. Diagnostic capabilities
include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and
detection.
1.1
Major Operating Modes
The DS26524 has two major modes of operation: T1 mode and E1 mode. The mode of operation for the LIU is
configured in the LIU Transmit Receive Control register (LTRCR). The mode of operation for the framer is
configured in the Transmit Master Mode register (TMMR). J1 operation is a special case of T1 operating mode.
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DS26524 Quad T1/E1/J1 Transceiver
2.
FEATURE HIGHLIGHTS
2.1
General
Member of the TEX-series transceiver family of devices. Software compatible with the DS26521 single,
DS26522 dual, and DS26528 octal transceivers
256-pin TE-CSBGA package (17mm x 17mm, 1.00mm pitch)
3.3V supply with 5V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Development support includes evaluation kit, driver source code, and reference designs
2.2
Line Interface
Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,
2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz
Fully software configurable
Short- and long-haul applications
Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to
30dB, 0dB to 20dB, and 0dB to -15dB for T1
Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB
increments
Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines
Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB
G.703 receive synchronization signal mode
Flexible transmit waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
Analog loss-of-signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmitter short-circuit limiter with current-limit-exceeded indication
Transmit open-circuit-detected indication
2.3
Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from user-selected recovered receive clock
2.4
Jitter Attenuator
32-bit or 128-bit crystal-less jitter attenuator
Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication
2.5
Framer/Formatter
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704, G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
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DS26524 Quad T1/E1/J1 Transceiver
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
− T1: BPV, CV, CRC-6, and framing bit errors
− E1: BPV, CV, CRC-4, E-bit, and frame alignment errors
− Timed or manual update modes
DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths
− User defined
− Digital Milliwatt
ANSI T1.403-1999 support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
− Three independent generators and detectors
− Patterns from 1 to 8 bits or 16 bits in length
Bit-oriented code (BOC) support
Flexible signaling support
− Software or hardware based
− Interrupt generated on change of signaling data
− Optional receive-signaling freeze on loss of frame, loss of signal, or frame slip
− Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock
(LOTC), or signaling freeze condition
Automatic RAI generation to ETS 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Ability to calculate and check CRC-6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
T1-to-E1 conversion
2.6
System Interface
Independent two-frame receive and transmit elastic stores
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz
Supports T1 to CEPT (E1) conversion
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation
Hardware signaling capability
Receive-signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
User-selectable synthesized clock output
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DS26524 Quad T1/E1/J1 Transceiver
2.7
HDLC Controllers
One HDLC controller engine for each T1/E1 port
Independent 64-byte Rx and Tx buffers with interrupt support
Access FDL, Sa, or single DS0 channel
Compatible with polled or interrupt driven environments
2.8
Test and Diagnostics
IEEE 1149.1 support
Per-channel programmable on-chip bit error-rate testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion single and continuous
Total-bit and errored-bit counts
Payload error insertion
Error insertion in the payload portion of the T1 frame in the transmit path
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel loopback)
2.9
Control Port
8-bit parallel control port
Intel or Motorola nonmultiplexed support
Flexible status registers support polled, interrupt, or hybrid program environments
Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
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DS26524 Quad T1/E1/J1 Transceiver
3.
APPLICATIONS
The DS26524 is useful in applications such as:
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
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DS26524 Quad T1/E1/J1 Transceiver
4.
SPECIFICATIONS COMPLIANCE
The DS26524 LIU meets all the latest relevant telecommunications specifications. Table 4-1 and Table 4-2 provide
the T1 and E1 specifications and relevant sections that are applicable to the DS26524.
Table 4-1. T1-Related Telecommunications Specifications
ANSI T1.102: Digital Hierarchy Electrical Interface
AMI Coding
B8ZS Substitution Definition
DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.6V peak; power level between
12.6dBm to 17.9dBm. The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is
greater than -26dB. The DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cables of 1000 feet.
ANSI T1.231: Digital Hierarchy—Layer 1 in Service Performance Monitoring
BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition.
ANSI T1.403: Network and Customer Installation Interface—DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100Ω. Pulse shape and template compliance
according to T1.102; power level 12.4dBm to 19.7dBm when all ones are transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB, and -15dB. Line rate is ±32ppm. Pulse Amplitude
is 2.4V to 3.6V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS26524 functions with up to -36dB cable loss.
Note that the pulse template defined by T1.403 and T1.102 are different, specifically at Times 0.61, -0.27, -34, and
0.77. The DS26524 is compliant to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter the G.823.
(ANSI) “Digital Hierarchy—Electrical Interfaces”
(ANSI) “Digital Hierarchy—Formats Specification”
(ANSI) “Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring”
(ANSI) “Network and Customer Installation Interfaces—DS1 Electrical Interface”
(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super
Frame Format”
(AT&T) “High Capacity Digital Service Channel Interface Specification”
(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”
(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”
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DS26524 Quad T1/E1/J1 Transceiver
Table 4-2. E1-Related Telecommunications Specifications
ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces
Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-topeak space voltage is ±0.237V; nominal pulse width is 244ns.
Return loss 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB.
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse template for E1 is defined in G.703.
ITU-T G.736 Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048kbps
The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.
Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.
ITU-T G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps
The DS26524 jitter attenuator is complaint with jitter transfer curve for sinusoidal jitter input.
ITU-T G.772
This specification provides the method for using receiver for transceiver 0 as a monitor for the remaining seven
transmitter/receiver combinations.
ITU-T G.775
An LOS detection criterion is defined.
ITU-T G.823 The control of jitter and wander within digital networks that are based on 2.048kbps hierarchy.
G.823 Provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and
100kHz.
ETS 300 233
This specification provides LOS and AIS signal criteria for E1 mode.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter than G.823.
(ITU-T) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels”
(ITU-T) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures
Defined in Recommendation G.704”
(ITU-T) “Characteristics of Primary PCM Multiplex Equipment Operating at 2048kbps”
(ITU-T) Characteristics of a Synchronous Digital Multiplex Equipment Operating at 2048kbps”
(ITU-T) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
(ITU-T) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy”
(ITU-T) “Primary Rate User-Network Interface—Layer 1 Specification”
(ITU-T) “Error Performance Measuring Equipment Operating at the Primary Rate and Above”
(ITU-T) “In-Service Code Violation Monitors for Digital Systems”
(ETS) “Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface (UNI); Part 1/Layer 1
Specification”
(ETS) “Transmission and Multiplexing; Physical/Electrical Characteristics of Hierarchical Digital Interfaces for
Equipment Using the 2048kbps-Based Plesiochronous or Synchronous Digital Hierarchies”
(ETS) “Integrated Services Digital Network (ISDN); Access Digital Section for ISDN Primary Rate”
(ETS) “Integrated Services Digital Network (ISDN); Attachment Requirements for Terminal Equipment to Connect
to an ISDN Using ISDN Primary Rate Access”
(ETS) “Business Telecommunications (BT); Open Network Provision (ONP) Technical Requirements; 2048kbps
Digital Unstructured Leased Lines (D2048U) Attachment Requirements for Terminal Equipment Interface”
(ETS) “Business Telecommunications (BTC); 2048kbps Digital Structured Leased Lines (D2048S); Attachment
Requirements for Terminal Equipment Interface”
(ITU-T) “Synchronous Frame Structures Used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels”
(ITU-T) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures
Defined in Recommendation G.704”
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DS26524 Quad T1/E1/J1 Transceiver
5.
ACRONYMS AND GLOSSARY
This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125µs T1
frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. For T1 and E1, each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is
transmitted first. Bit 8, the LSB, is transmitted last.
Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
Table 5-1. Time Slot Numbering Schemes
TS
Channel
Phone
Channel
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
16 of 273
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DS26524 Quad T1/E1/J1 Transceiver
6.
BLOCK DIAGRAMS
Figure 6-1. Block Diagram
DS26524
LIU #4
LIU #3
LIU #2
RTIP
RRING
TTIP
FRAMER #4
FRAMER #3
FRAMER #2
T1/E1 FRAMER
LINE
INTERFACE
UNIT
INTERFACE #2
BACKPLANE
INTERFACE
HDLC
BERT
TRING
INTERFACE #4
INTERFACE #3
ELASTIC
STORES
X4
RECEIVE
BACKPLANE
SIGNALS
TRANSMIT
BACKPLANE
SIGNALS
HARDWARE
ALARM
INDICATORS
X4
MICRO PROCESSOR
INTERFACE
JTAG PORT
CLOCK
GENERATION
CONTROLLER
PORT
TEST
PORT
CLOCK
ADAPTER
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DS26524 Quad T1/E1/J1 Transceiver
Figure 6-2. Detailed Block Diagram
Tx
BERT
TRANSCEIVER #1 of 4:
Tx
HDLC
Tx Signaling/
Channel Blocking
Rx
BERT
DS26524
JTAG
PORT
RESET
BLOCK
RESETB
JTDO
JTDI
JTMS
JTCLK
JTRST
A[12:0]
D[7:0]
CSB
RDB/DSB
WRB/RWB
BTS
INTB
18 of 273
Elastic
Store
System IF
B8ZS/
HDB3
Decode
BACKPLANE INTERFACE
PLB
Rx FRAMER:
Clock/Data
Recovery
MICROPROCESSOR
INTERFACE
System IF
RRINGn
RECEIVE
LIU
Elastic
Store
RLB
ALB
RTIPn
B8ZS/
HDB3
Encode
TCLKn
TSERn
FLB
LLB
Waveform
Shaper/Line
Driver
JITTER ATTENUATOR
TRINGn
Tx FRAMER:
TRANSMIT
LIU
TRANSMIT
ENABLE
TTIPn
TSYNCn
TSSYNCIO
(Input Mode)
TSYSCLK
RSYSCLK
RSYNCn
RSERn
RCLKn
Rx Signaling/
Channel Blocking
Rx
HDLC
PRESCALER
PLL
BACKPLANE
CLOCK
GENERATOR
MCLK
TSSYNCIO
(Output Mode)
BPCLK
REFCLK
DS26524 Quad T1/E1/J1 Transceiver
7.
PIN DESCRIPTIONS
7.1
Pin Functional Description
Table 7-1. Detailed Pin Descriptions
NAME
PIN
TTIP1
A1, A2
TTIP2
H1, H2
TTIP3
J1 J2
TTIP4
T1, T2
TRING1
A3, B3
TRING2
G3, H3
TRING3
J3, K3
TRING4
R3, T3
TXENABLE
L13
RTIP1
RTIP2
RTIP3
RTIP4
RRING1
RRING2
RRING3
RRING4
C1
F1
L1
P1
C2
F2
L2
P2
TYPE
Analog
Output,
High
Impedance
FUNCTION
ANALOG TRANSMIT
Transmit Bipolar Tip for Transceiver 1 to 4. These pins are differential line
driver tip outputs. These pins can be high impedance if:
If TXENABLE is low, the TTIP/TRING will be high impedance. Note that if
TXENABLE is low, the register settings for control of the TTIP/TRING are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 75Ω , E1 120Ω, T1 100Ω, or J1 110Ω. The user has the option
of turning off internal termination.
Note: The two pins shown for each transmit bipolar tip (e.g., pins A1 and A2 for
TTIP1) should be tied together.
Analog
Output,
High
Impedance
Transmit Bipolar Ring for Transceiver 1 to 4. These pins are differential line
driver ring outputs. These pins can be high impedance if:
If TXENABLE is low, the TTIP/TRING will be high impedance. Note that if
TXENABLE is low, the register settings for control of the TTIP/TRING are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω. The user has the option
of turning off internal termination.
Note: The two pins shown for each transmit bipolar ring (e.g., pins A3 and B3 for
TRING1) should be tied together.
I
Transmit Enable. If this pin is pulled low, all transmitter outputs (TTIP and
TRING) are high impedance. The register settings for tri-state control of
TTIP/TRING are ignored if TXENABLE is low. If TXENABLE is high, the particular
driver can be tri-stated by the register settings.
ANALOG RECEIVE
Analog
Input
Receive Bipolar Tip for Transceiver 1 to 4. The differential inputs of RTIPn and
RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω,
or J1 110Ω. The user has the option of turning off internal termination via the LIU
Receive Impedance and Sensitivity Monitor register (LRISMR).
Analog
Input
Receive Bipolar Ring for Transceiver 1 to 4. The differential inputs of RTIPn and
RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω,
or J1 110Ω. The user has the option of turning off internal termination via the LIU
Receive Impedance and Sensitivity Monitor register (LRISMR).
TRANSMIT FRAMER
TSER1
F6
TSER2
E7
TSER3
R4
TSER4
N7
I
Transmit NRZ Serial Data. These pins are sampled on the falling edge of TCLK
when the transmit-side elastic store is disabled. These pins are sampled on the
falling edge of TSYSCLK when the transmit-side elastic store is enabled.
In IBO mode, data for multiple framers can be used in high-speed multiplexed
scheme. This is described in Section 8.8.2. The table there presents the
combination of framer data for each of the streams.
TSYSCLK is used as a reference when IBO is invoked.
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DS26524 Quad T1/E1/J1 Transceiver
NAME
PIN
TCLK1
TCLK2
TCLK3
C5
D7
P5
TYPE
Transmit Clock. A 1.544MHz or a 2.048MHz primary clock. Used to clock data
through the transmit side of the transceiver. TSER data is sampled on the falling
edge of TCLK. TCLK is used to sample TSER when the elastic store is not enabled
or IBO is not used.
I
TCLK4
L8
TSYSCLK
P13
TSYNC1
B4
TSYNC2
F7
TSYNC3
M6
TSYNC4
M7
TSSYNCIO
N13
FUNCTION
I
I/O
I/O
When the elastic store is enabled, TCLKn is used as the internal transmit clock for
the framer side or the elastic store, including the transmit framer and LIU. With the
elastic store enabled, TCLKn can be either synchronous or asynchronous to
TSYSCLKn, which either prevents or allows for slips. In addition, when IBO mode
is enabled, TCLKn must be synchronous to TSYSCLKn, which prevents slips in the
elastic store.
Note: This clock must be provided for proper device operation. The only exception
is when the TCR3 register is configured to source TCLK internally from RCLK.
Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz clock. Only used when the transmit-side elastic store function is
enabled. Should be tied low in applications that do not use the transmit-side elastic
store. This is a common clock that is used for the transmitters. The clock can be
4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.
Transmit Synchronization. A pulse at these pins establishes either frame or
multiframe boundaries for the transmit side. These signals can also be
programmed to output either a frame or multiframe pulse. If these pins are set to
output pulses at frame boundaries, they can also be set to output double-wide
pulses at signaling frames in T1 mode. The operation of these signals is
synchronous with TCLK.
Transmit System Synchronization In. Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for all four transmitters. Should be tied low
in applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out. If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26524
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
TSIG1
D5
TSIG2
A6
TSIG3
T4
TSIG4
R6
TCHBLK/
CLK1
A5
TCHBLK/
CLK2
C7
TCHBLK/
CLK3
L7
TCHBLK/
CLK4
P7
I
Transmit Signaling. When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams
can run up to 16.384MHz.
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low during any
of the channels. It is synchronous with TCLK when the transmit-side elastic store is
disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is
enabled. It is useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1,
384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels
in drop-and-insert applications, for external per-channel loopback, and for perchannel conditioning.
O
TCHCLK. TCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, TCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, TCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-toserial conversion of channel data. In either mode, TCHCLKn is synchronous with
TCLKn when the receive-side elastic store is disabled or it is synchronous with
TSYSCLKn when the receive-side elastic store is enabled. The mode of TCHCLKn
is determined by the TGCLKEN bit in the TESCR register.
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DS26524 Quad T1/E1/J1 Transceiver
NAME
PIN
TYPE
FUNCTION
RECEIVE FRAMER
RSER1
E5
RSER2
D6
RSER3
N4
RSER4
N6
RCLK1
F4
RCLK2
G4
RCLK3
L4
RCLK4
M4
RSYSCLK
L12
RSYNC1
A4
RSYNC2
B6
RSYNC3
N5
RSYNC4
T6
RMSYNC1/
RFSYNC1
RMSYNC2/
RFSYNC2
RMSYNC3/
RFSYNC3
RMSYNC4/
RFSYNC4
RSIG1
RSIG2
RSIG3
RSIG4
AL/
RSIGF/
FLOS1
When IBO mode is used, the RSER pins can output data for multiple framers. The
RSER data is synchronous to RSYSCLK. This is described in Section 8.8.2.
O
I
I/O
C4
C6
O
P4
P6
D4
E6
M5
R5
O
C3
AL/
RSIGF/
FLOS2
F3
AL/
RSIGF/
FLOS3
L3
AL/
RSIGF/
FLOS4
P3
RLF/
LTC1
RLF/
LTC2
RLF/
LTC3
RLF/
LTC4
O
Received Serial Data. Received NRZ serial data. Updated on rising edges of
RCLK when the receive-side elastic store is disabled. Updated on the rising edges
of RSYSCLK when the receive-side elastic store is enabled.
O
Receive Clock. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock
data through the receive-side framer. This clock is recovered from the signal at
RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used
to output RSER when the elastic store is not enabled or IBO is not used. When the
elastic store is enabled or IBO is used, the RSER is clocked by RSYSCLK.
Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic store
function is enabled. Should be tied low in applications that do not use the receiveside elastic store. Multiple of 2.048MHz is expected when the IBO mode is used.
Note that RSYSCLK is used for all four transceivers.
Receive Synchronization. If the receive-side elastic store is enabled, then this
signal is used to input a frame or multiframe boundary pulse. If set to output frame
boundaries, then RSYNC can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNC out can be used to indicate
CAS and CRC-4 multiframe. The DS26524 can accept H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the RIOCR.2 register.
Receive Multiframe/Frame Synchronization. A dual function pin to indicate
frame or multiframe synchronization. RFSYNC is an extracted 8kHz pulse, one
RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one
RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled),
that identifies multiframe boundaries. When the receive elastic store is enabled,
the RMSYNC signal indicates the multiframe sync on the system (backplane) side
of the elastic store. In E1 mode, this pin can indicate either the CRC-4 or CAS
multiframe as determined by the RSMS2 control bit in the Receive I/O
Configuration register (RIOCR.1).
Receive Signaling. Outputs signaling bits in a PCM format. Updated on rising
edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.
Analog Loss/Receive-Signaling Freeze/Framer LOS. Analog LOS reflects the
LOS (loss of signal) detected by the LIU front-end and framer LOS is LOS
detection by the corresponding framer; the same pins can reflect receive-signaling
freeze indications. This selection can be made by settings in the Global
Transceiver Clock Control register (GTCCR ).
If framer LOS is selected, this pin can be programmed to toggle high when the
framer detects an LOS condition, or when the signaling data is frozen via either
automatic or manual intervention. The indication is used to alert downstream
equipment of the condition.
D3
E3
O
M3
Receive Loss of Frame/Loss of Transmit Clock. This pin can be programmed to
either toggle high when the synchronizer is searching for the frame and multiframe,
or to toggle high if the TCLK pin has not been toggled for approximately three clock
periods.
N3
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DS26524 Quad T1/E1/J1 Transceiver
NAME
PIN
RCHBLK/
CLK1
E4
RCHBLK/
CLK2
B5
RCHBLK/
CLK3
L6
TYPE
FUNCTION
O
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a userprogrammable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in dropand-insert applications, for external per-channel loopback, and for per-channel
conditioning.
T5
RCHCLK. RCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, RCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-toserial conversion of channel data. In either mode, RCHCLK is synchronous with
RCLKn when the receive-side elastic store is disabled or it is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. The mode of
RCHCLKn is determined by the RGCLKEN bit in the RESCR register.
BPCLK
E8
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
C8
A8
B8
F8
B9
A9
C9
D9
E9
F9
B10
A10
C10
T9
N9
M9
R8
T8
P8
L9
N8
CSB
RCHBLK/
CLK4
O
MICROPROCESSOR INTERFACE
I
Address [12:0]. This bus selects a specific register in the DS26524 during
read/write access. A12 is the MSB and A0 is the LSB.
I
Data [7:0]. This 8-bit, bidirectional data bus is used for read/write access of the
DS26524 information and control registers. D7 is the MSB and D0 is the LSB.
T7
I
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
RDB/
DSB
M8
I
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26524 registers. The DS26524 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
WRB/
RWB
R7
I
Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies
write access to one of the DS26524 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
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DS26524 Quad T1/E1/J1 Transceiver
NAME
PIN
TYPE
INTB
R9
U
BTS
M13
I
FUNCTION
Interrupt Bar. This active-low, open-drain output is asserted when an unmasked
interrupt event is detected. INTB will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global level,
framer, LIU, and BERT level.
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins.
SYSTEM INTERFACE
MCLK
B7
I
RESETB
J12
I
REFCLKIO
A7
I/O
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLK must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See Table 9-12.
Reset Bar. Active-low reset. This input forces the complete DS26524 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference
clock. This allows for multiple DS26524s to share the same reference for
generation of the backplane clock. Hence, in a system consisting of multiple
DS26524s, one can be a master and others a slave using the same reference
clock.
TEST
DIGIOEN
D8
I, Pullup
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to VDD for normal operation.
JTRST
L5
I, Pullup
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTMS
K4
I, Pullup
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTCLK
F5
I
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTDI
H4
I, Pullup
JTDO
J4
O, High
impedance
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
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DS26524 Quad T1/E1/J1 Transceiver
NAME
PIN
TYPE
FUNCTION
POWER SUPPLIES
ATVDD1
B1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
ATVDD7
ATVDD8
ATVSS1
ATVSS2
ATVSS3
ATVSS4
ATVSS5
ATVSS6
ATVSS7
ATVSS8
G1
K1
R1
R16
K16
G16
B16
B2
G2
K2
R2
R15
K15
G15
B15
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
D1
E1
M1
N1
N16
M16
E16
D16
D2
E2
M2
N2
N15
M15
E15
D15
ACVDD
—
3.3V Analog Transmit Power Supply. These VDD inputs are used for the transmit
LIU sections of the DS26524.
—
Analog Transmit VSS. These pins are used for transmit analog VSS.
—
3.3V Analog Receive Power Supply. These VDD inputs are used for the receive
LIU sections of the DS26524.
—
Analog Receive VSS. These pins are used for analog VSS for the receivers.
H7
—
Analog Clock Conversion VDD. This VDD input is used for the clock conversion
unit of the DS26524.
ACVSS
J7
—
Analog Clock VSS. This pin is used for clock converter analog VSS.
DVDD
G5–G12,
H8, H9
—
3.3V Power Supply for Digital Framers
DVDDIO
H5, H6,
H10, H11
—
3.3V Power Supply for I/Os
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DS26524 Quad T1/E1/J1 Transceiver
NAME
PIN
TYPE
FUNCTION
DVSS
A11, A13,
B11, B13,
C11, C13,
D12, D13,
E10, F10,
H12, H13,
J8, J9,
K5–K12,
L10, L11,
M10, N10,
N11, P12,
R10, R12,
T10, T12
-—
Digital Ground for the Framers
DVSSIO
J5, J6,
J10, J11
—
Digital Ground for the I/Os
N.C.
A12, A14,
A15, A16,
B12, B14,
C12, C14,
C15, C16,
D10, D11,
D14,
E11–E14,
F11–F16,
G13, G14,
H14, H15,
H16,
J13–J16,
K13, K14,
L14, L15,
L16, M11,
M12, M14
N12, N14,
P9, P10,
P11, P14,
P15, P16,
R11, R13,
R14, T11,
T13–T16
—
No Connection. These pins must not be connected to VDD or VSS.
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DS26524 Quad T1/E1/J1 Transceiver
8.
8.1
FUNCTIONAL DESCRIPTION
Processor Interface
Microprocessor control of the DS26524 is accomplished through the 28 hardware pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select
(BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 12-1 and Figure 12-2.
When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 12-3 and Figure 12-4. The
address space is mapped through the use of 13 address lines, A[12:0]. Multiplexed mode is not supported on the
processor interface.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the readwrite bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the interface.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The device has
a bulk write mode that allows a microprocessor to write all four internal transceivers with each bus write cycle. By
setting the BWE bit (GTCR1.2), each port write cycle will write to all four framers, LIUs, or BERTs at the same time.
The BWE bit must be cleared before normal write operation is resumed. This function is useful for device
initialization. The register map is shown in Figure 9-1.
8.2
Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
8.2.1
Backplane Clock Generation
The DS26524 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure 8-1). The Global Transceiver Clock Control register (GTCCR) is used to control the backplane clock
generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can output MCLKT1
or MCLKE1 as shown in Figure 8-1.
This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26524 and other IBO-equipped devices
as an IBO bus master. Hence, the DS26524 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock.
This can be used by the link layer devices and frames connected to the IBO bus.
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-1. Backplane Clock Generation
BPREFSEL3:0
BPCLK1:0
RCLK1
RCLK2
BFREQSEL
RCLK3
RCLK4
Clock
Multiplexor
MCLK
Pre
Scaler
PLL
BPCLK
CLK
GEN
MCLKT1
MCLKE1
REFCLKIO
TSSYNCIO
REFCLKIO
The reference clock for the backplane clock generator can be as follows:
• External Master Clock. A prescaler can be used to generate T1 or E1 frequency.
• External Reference Clock REFCLKIO. This allows for multiple DS26524s to use the backplane clock from
a common reference.
• Internal LIU recovered RCLKs 1 to 4.
• The clock generator can be used to generate BPCLK of 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
for the IBO.
• If MCLK or RCLK are used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz
clock for external use.
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DS26524 Quad T1/E1/J1 Transceiver
8.3
Resets and Power-Down Modes
A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs,
and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be
reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing
reserved locations to 00h.
The DS26524 has several features included to reduce power consumption. The LIU transmitters can be powered
down by setting the TPDE bit in the LIU Maintenance Control register (LMCR). Note that powering down the
transmit LIU results in a high-impedance state for the corresponding TTIP and TRING pins and reduced operating
current. The RPDE bit in the LMCR register can be used to power down the LIU receiver.
The TE (transmit enable) bit in the LMCR register can be used to disable the TTIP and TRING outputs and place
them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for
equipment protection-switching applications.
Table 8-1. Reset Functions
RESET FUNCTION
LOCATION
Hardware Device Reset
RESETB
Hardware JTAG Reset
JTRST
COMMENTS
Transition to a logic 0 level resets the DS26524.
Resets the JTAG test port.
Global Framer and BERT Reset
GFSRR.0:3
Writing to these bits resets the framer and BERT (transmit
and receive).
Global LIU Reset
GLSRR.0:3
Writing to these bits resets the associated LIU.
Framer Receive Reset
RMMR.1
Writing to this bit resets the receive framer.
Framer Transmit Reset
TMMR.1
Writing to this bit resets the transmit framer.
HDLC Receive Reset
RHC.6
Writing to this bit resets the receive HDLC controller.
HDLC Transmit Reset
THC1.5
Writing to this bit resets the transmit HDLC controller.
Elastic Store Receive Reset
RESCR.2
Writing to this bit resets the receive elastic store.
Elastic Store Transmit Reset
TESCR.2
Writing to this bit resets the transmit elastic store.
Bit Oriented Code Receive Reset
T1RBOCC.7
Writing to this bit resets the receive BOC controller.
Loop Code Integration Reset
T1RDNCD1,
T1RUPCD1
Writing to these registers resets the programmable in-band
code integration period.
Spare Code Integration Reset
T1RSCD1
Writing to this register resets the programmable in-band
code integration period.
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DS26524 Quad T1/E1/J1 Transceiver
8.4
Initialization and Configuration
8.4.1
Example Device Initialization Sequence
STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software
reset bits outlined in Section 8.3. Clear all reset bits. Allow time for the reset recovery.
STEP 2: Check the device ID in the Device Identification register (IDR).
STEP 3: Write the GTCCR register to correctly configure the system clocks. If supplying a 1.544MHz MCLK, follow
this write with at least a 300ns delay to allow the clock system to properly adjust.
STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register
locations.
STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR and RMMR
registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using software transmit
signaling in E1 mode, program the E1TAF and E1TNAF registers as required. Configure the framer Transmit
Control registers (TCR1:TCR4). Configure the Framer Receive Control registers (RCR1 (T1)/RCR1 (E1),
T1RCR2/E1RCR2, RCR3). Configure other framer features as appropriate.
STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR register.
Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE bit to turn on the
TTIP and TRING outputs.
STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed.
STEP 8: Set the INIT_DONE bit in the TMMR and RMMR registers for each framer.
8.5
Global Resources
All four framers share a common microprocessor port. All ports share a common MCLK, and there is a common
software-configurable BPCLK output. A set of global registers are located at 0F0h–0FFh and include global resets,
global interrupt status, interrupt masking, clock configuration, and the device ID registers. See the global register
definitions in Table 9-2. A common JTAG controller is used.
8.6
Per-Port Resources
Each port has an associated framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller. Each of the
per-port functions has its own register space.
8.7
Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR, GLISR, and GBISR to identify which of the four transceivers is causing the
interrupt(s). The host can then read the specific transceiver’s interrupt information registers (TIIR, RIIR) and the
latched status registers (LLSR, BLSR) to further identify the source of the interrupt(s). If TIIR or RIIR is the source,
the host will then read the transmit-latched status or the receive-latched status registers for the source of the
interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been
serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status
register. The host must clear all latched status bits by writing a 1 to the bit location of the interrupt condition that
has been serviced. Latched status bits that have been masked by the interrupt mask registers are masked from the
interrupt information registers. The interrupt mask register bits prevent individual latched status conditions from
generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when servicing
interrupts, the user should XOR the latched status with the associated interrupt mask in order to exclude bits for
which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll
the latched status bits for noninterrupt conditions, while using only one set of registers.
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-2. Device Interrupt Information Flow Diagram
0
1
INTERRUPT
STATUS
REGISTERS
REGISTER NAME
INTERRUPT MASK
REGISTERS
REGISTER NAME
2
RLS4
RIIR
RLS3
RLS2
RLS1
DRAWING LEGEND:
RLS5
3
30 of 273
INTERRUPT PIN
GTCR1.0
GFIMR
GLIMR
GFISR1
GBIMR
1
BERTs 2–4
TLS3
TIIR
TLS2
2
GLISR1
LIUs 2–4
TLS1
5
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
GBISR1
RLS7
FRAMERS 2–4
4
LLSR
7
6
5
4
3
2
1
0
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4
3
2
1
0
—
—
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
BLSR
Receive Remote Alarm Indication Clear
Receive Alarm Condition Clear
Receive Loss of Signal Clear
Receive Loss of Frame Clear
Receive Remote Alarm Indication
Receive Alarm Condition
Receive Loss of Signal
Receive Loss of Frame
Receive Signal All Ones
Receive Signal All Zeros
Receive CRC-4 Multiframe
Receive Align Frame
Loss of Receive Clock Clear/Loss of Receive Clock Clear
Spare Code Detected Condition Clear
Loop-Down Code Clear/V52 Link Clear
Loop-Up Code Clear/Receive Distant MF Alarm Clear
Loss of Receive Clock/Loss of Receive Clock
Spare Code Detect
Loop-Down Detect/V52 Link Detect
Loop-Up Detect/Receive Distant MF Alarm Detect
Receive Elastic Store Full
Receive Elastic Store Empty
Receive Elastic Store Slip
Receive Signaling Change of State (Enable in RSCSE1:4)
One-Second Timer
Timer
Receive Multiframe
Receive FIFO Overrun
Receive HDLC Opening Byte
Receive Packet End
Receive Packet Start
Receive Packet High Watermark
Receive FIFO Not Empty
Receive RAI-CI
Receive AIS-CI
Receive SLC-96 Alignment
Receive FDL Register Full
Receive BOC Clear
Receive BOC
Transmit Elastic Store Full
Transmit Elastic Store Empty
Transmit Elastic Store Slip
Transmit SLC-96 Multiframe
Transmit Pulse Density Violation/Transmit Align Frame
Transmit Multiframe
Loss of Transmit Clock Clear
Loss of Transmit Clock
Transmit FDL Register Empty
Transmit FIFO Underrun
Transmit Message End
Transmit FIFO Below Low Watermark
Transmit FIFO Not Full Set
—
—
Loss of Frame
Loss of Frame Synchronization
Jitter Attenuator Limit Trip Clear
Open-Circuit Detect Clear
Short-Circuit Detect Clear
Loss of Signal Detect Clear
Jitter Attenuator Limit Trip
Open-Circuit Detect
Short-Circuit Detect
Loss of Signal Detect
BERT Bit-Error Detected
BERT Bit Counter Overflow
BERT Error Counter Overflow
BERT Receive All Ones
BERT Receive All Zeros
BERT Receive Loss of Synchronization
BERT in Synchronization
DS26524 Quad T1/E1/J1 Transceiver
8.8
System Backplane Interface
The DS26524 provides a versatile backplane interface that can be configured to the following:
• Transmit and receive two-frame elastic stores
• Mapping of T1 channels into a 2.048MHz backplane
• IBO mode for multiple framers to share the backplane signals
• Transmit and receive channel-blocking capability
• Fractional T1/E1/J1 support
• Hardware-based (through the backplane interface) or processor-based signaling
• Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz
• Backplane clock and frame pulse (TSSYNCIOn) generator
8.8.1
Elastic Stores
The DS26524 contains dual two-frame elastic stores for each framer: one for the receive direction and one for the
transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be
enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a
1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic
store. Since the DS26524 has a common TSYSCLK and RSYSCLK for all four ports, the backplane signals in each
direction must be synchronous for all ports on which the elastic stores are enabled. However, the transmit and
receive signals are not required to be synchronous to each other. The TIOCR and RIOCR settings should be
identical for all ports on which the elastic stores are enabled.
The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26524 is in
the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the
elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Second, the elastic stores can be used
to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not
locked) backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate
difference and perform controlled slips, deleting or repeating frames of data to manage the difference between the
network and the backplane.
If the elastic store is enabled while in E1 mode, then either CAS or CRC-4 multiframe boundaries are indicated via
the RMSYNC output as controlled by the RSMS2 control bit (RIOCR.1). If the user selects to apply a 1.544MHz
clock to the RSYSCLK pin, then the Receive Blank Channel Select registers (RBCS1:RBCS4) registers determine
which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the
RSER data and set to 1. Also, in 1.544MHz applications, the RCHBLK output will not be active in Channels 25 to
32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip
occurs. If the buffer empties, a full frame of data is repeated at RSER and the RLS4.5 and RLS4.6 bits are set to 1.
If the buffer fills, a full frame of data is deleted and the RLS4.5 and RLS4.7 bits are set to 1.
The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the
Interleave Bus Option (IBO), which is discussed in Section 8.8.2. Table 8-2 shows the registers related to the
elastic stores.
Table 8-2. Registers Related to the Elastic Store
REGISTER
Receive I/O Configuration Register (RIOCR)
Receive Elastic Store Control Register
(RESCR)
Receive Latched Status Register 4 (RLS4)
Receive Interrupt Mask Register 4 (RIM4)
Transmit Elastic Store Control Register
(TESCR)
Transmit Latched Status Register 1 (TLS1)
Transmit Interrupt Mask Register 1 (TIM1)
FRAMER
ADDRESSES
084h
FUNCTION
Sync and clock selection for the receiver.
085h
Receive elastic store control.
093h
0A3h
Receive elastic store empty full status.
Receive interrupt mask for elastic store.
Transmit elastic control such as minimum
mode.
Transmit elastic store latched status.
Transmit elastic store interrupt mask.
185h
190h
1A0h
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h), where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.8.1.1 Elastic Stores Initialization
There are two elastic store initializations that can be used to improve performance in certain applications: elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK,
respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align
bit is used to “center” the read/write pointers to the extent possible.
Table 8-3. Elastic Store Delay After Initialization
INITIALIZATION
REGISTER BIT
DELAY
Receive Elastic Store Reset
RESCR.2
N bytes < Delay < 1 Frame + N bytes
Transmit Elastic Store Reset
TESCR.2
N bytes < Delay < 1 Frame + N bytes
Receive Elastic Store Align
RESCR.3
1/2 Frame < Delay < 1 1/2 Frames
Transmit Elastic Store Align
TESCR.3
1/2 Frame < Delay < 1 1/2 Frames
N = 9 for RSZS = 0; N = 2 for RSZS = 1.
8.8.1.2 Minimum Delay Mode
Elastic store minimum-delay mode can be used when the elastic store’s system clock is locked to its network clock
(i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side).
RESCR.1 enables the receive elastic store minimum-delay mode. When enabled, the elastic stores are forced to a
maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that
interface to a 2.048MHz bus. Certain restrictions apply when minimum-delay mode is used. In addition to the
restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in
minimum-delay mode and TSYNC must be configured as an output when transmit minimum-delay mode is
enabled. In this mode the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a
typical application, RSYSCLK and TSYSCLK are locked to RCLK and RSYNC (frame-output mode) is connected to
TSSYNCIO (frame-input mode). The slip zone select bit (RSZS at RESCR.4) must be set to 1. All the slip
contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and
TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2)
should be toggled from a 0 to 1 to ensure proper operation
8.8.1.3 Additional Receive Elastic Store Information
If the receive-side elastic store is enabled, the user must provide either a 1.544MHz or 2.048MHz clock at the
RSYSCLK pin. See Section 8.8.2 for higher rate system-clock applications. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe
boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe sync
input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the
elastic store. The framer always indicates frame boundaries on the network side of the elastic store via the
RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries arel always indicated via the
RMSYNC output. If the elastic store is enabled, RMSYNC outputs the multiframe boundary on the backplane side
of the elastic store. When the device is receiving T1 and the backplane is enabled for 2.048MHz operation, the
RMSYNC signal outputs the T1 multiframe boundaries as delayed through the elastic store. When the device is
receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNC signal outputs the E1 multiframe
boundaries as delayed through the elastic store.
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, the user can use the Receive Blank Channel
Select registers (RBCS1:RBCS4) to determine which channels will have the data output at RSER forced to all
ones.
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DS26524 Quad T1/E1/J1 Transceiver
8.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane
Setting the TSCLKM bit (TIOCR.4) enables the transmit elastic store to operate with a 2.048MHz backplane (32
time slots/frame). In this mode the user can choose which of the backplane channels on TSER will be mapped into
the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1:TBCS4). A logic 1 in the
associated bit location forces the transmit elastic store to ignore backplane data for that channel. Typically the user
will want to program eight channels to be ignored. The default (power-up) configuration ignores channels 25 to 32,
so that the first 24 backplane channels are mapped into the T1 transmit data stream.
For example, if the user desired to transmit data from the 2.048MHz backplane channels 2 to 16 and 18 to 26, the
TBCS1:TBCS4 registers should be programmed as follows:
TBCS1 = 01h :: ignore backplane channel 1 ::
TBCS2 = 00h
TBCS3 = 01h :: ignore backplane channel 17 ::
TBCS4 = FCh :: ignore backplane channels 27 to 32 ::
8.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane
Setting the RSCLKM bit (RIOCR.4) enables the receive elastic store to operate with a 2.048MHz backplane (32
time slots/frame). In this mode the user can choose which of the backplane channels on RSER receive the T1 data
by programming the Receive Blank Channel Select registers (RBCS1:RBCS4). A logic 1 in the associated bit
location forces RSER high for that backplane channel. Typically the user will want to program eight channels to be
blanked. The default (power-up) configuration blanks channels 25 to 32, so that the 24 T1 channels are mapped
into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by setting
RBCS1.0 = 1, the F-bit will be passed into the MSB of TS0 on RSER.
For example, if:
RBCS1 = 01h
RBCS2 = 00h
RBCS3 = 01h
RBCS4 = FCh
Then on RSER:
Channel 1 (MSB) = F-bit
Channel 1 (bits 1 to 7) = all ones
Channels 2 to 16 = T1 channels 1 to 15
Channel 17 = all ones
Channels 18 to 26 = T1 channels 16 to 24
Channels 27 to 32 = all ones
Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit should
be set to 0. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to 1,
which can provide a lower occurrence of slips in certain applications.
If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of
data is repeated at RSER and the RLS4.5 and RLS4.6 bits are set to 1. If the buffer fills, a full frame of data is
deleted and the RLS4.5 and RLS4.7 bits are set to 1.
8.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane
The user can use the TSCLKM bit in TIOCR.4 to enable the transmit elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will have allones data inserted by programming the Transmit Blank Channel Select registers (TBCS1:TBCS4). A logic 1 in the
associated bit location causes the elastic store to force all ones at the outgoing E1 data for that channel. Typically
the user will want to program eight channels to be blanked. The default (power-up) configuration blanks channels
25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane.
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DS26524 Quad T1/E1/J1 Transceiver
8.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane
The user can use the RSCLKM bit (RIOCR.4) to enable the receive elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be
ignored (not transmitted onto RSER) by programming the Receive Blank Channel Select registers
(RBCS1:RBCS4). A logic 1 in the associated bit location causes the elastic store to ignore the incoming E1 data for
that channel. Typically the user will want to program eight channels to be ignored. The default (power-up)
configuration will ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the
1.544MHz backplane. In this mode the F-bit location at RSER is always set to 1.
For example, if the user wants to ignore E1 time slots 0 (channel 1) and TS16 (channel 17), the RBCS1:RBCS4
registers would be programmed as follows:
RBCS1 = 01h
RBCS2 = 00h
RBCS3 = 01h
RBCS4 = FCh
8.8.2
IBO Multiplexer
The Interleaved Bus Operation (IBO) multiplexer is used in conjunction with the IBO function located within each
framer/formatter block (controlled by the RIBOC and TIBOC registers). When enabled, the IBO multiplexer
simplifies user interface by connecting bus signals internally. The IBO multiplexer eliminates the need for ganged
external wiring and tri-state output drivers on the RSER and RSIG pins. This option provides a more controlled,
cleaner, and lower power mode of operation.
Note that the channel block signals TCHBLK and RCHBLK are output at the rate of the of IBO selection. Hence, a
4.096MHz IBO would have the channel blocks (if programmed active at the rate of 4.096MHz). The particular
blocking channel would be active for a duration of the channel if programmed.
The DS26524 also supports the traditional mode of IBO operation by allowing complete access to individual
framers, and tri-stating the RSER and RSIG pins at the appropriate times for external bus wiring. This mode of
operation is enabled per framer in the associated RIBOC and TIBOC registers, while leaving the IBO multiplexer is
disabled (IBOMS0 = 0 and IBOMS1 = 0).
Figure 8-3, Figure 8-4, and Figure 8-5 show the equivalent internal circuit for each IBO mode. Table 8-4 describes
the pin function changes for each mode of the IBO multiplexer.
Table 8-4. Registers Related to the IBO Multiplexer
REGISTER
FRAMER
ADDRESSES
Global Transceiver Control Register 1
(GTCR1)
0F0h
Receive Interleave Bus Operation
Control Register (RIBOC)
088h
Transmit Interleave Bus Operation
Control Register (TIBOC)
188h
FUNCTION
This is a global register for all four framers. It can be
used to specify ganged operation for the IBO.
This register can be used for control of how many
framers and the corresponding speed for the IBO
links for the receiver.
This register can be used for control of how many
framers and the corresponding speed for the IBO
links for the transmitter.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated by using the following: Framer n = (Framer 1
address + (n - 1) x 200h), where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz
RSER1
Port # 1
Backplane
Interface
Port # 2
Backplane
Interface
Port # 3
Backplane
Interface
Port # 4
Backplane
Interface
RSIG1
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
RSYNC1
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER3
RSIG3
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
RSYNC3
RSYSCLK
TSER3
TSIG3
TSSYNCIO
TSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz
RSER1
RSIG1
DS26524 #1
Port # 1
Backplane
Interface
DS26524 #1
Port # 2
Backplane
Interface
DS26524 #1
Port # 3
Backplane
Interface
DS26524 #1
Port # 4
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
RSYNC1
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSSYNC
TSYSCLK
TSER
TSIG
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz
RSER1*
RSIG1**
DS26524 #1
Port # 1
Backplane
Interface
DS26524 #1
Port # 2
Backplane
Interface
DS26524 #1
Port # 3
Backplane
Interface
DS26524 #1
Port # 4
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
RSYNC1
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSSYNC
TSYSCLK
RSER1*
TSER
TSIG
RSIG1**
DS26524 #2
Port # 1
Backplane
Interface
DS26524 #2
Port # 2
Backplane
Interface
DS26524 #2
Port # 3
Backplane
Interface
DS26524 #2
Port # 4
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
RSYNC1
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-5. RSER Output Pin Definitions
PIN
NORMAL USE
4.096MHz IBO
8.192MHz IBO
16.384MHz IBO
RSER1
Receive Serial Data
for Port 1
Combined Receive
Serial Data for
Ports 1 and 2
Combined Receive
Serial Data for
Ports 1–4
Receive Serial Data
for Ports 1–4
RSER2
Receive Serial Data
for Port 2
Reserved
Unused
Unused
RSER3
Receive Serial Data
for Port 3
Combined Receive
Serial Data for Ports 3
and 4
Unused
Unused
RSER4
Receive Serial Data
for Port 4
Unused
Unused
Unused
Table 8-6. RSIG Output Pin Definitions
PIN
NORMAL USE
4.096MHz IBO
8.192MHz IBO
16.384MHz IBO
RSIG1
Receive Signaling
Data for Port 1
Combined Receive
Signaling Data for
Ports 1 and 2
Combined Receive
Signaling Data for
Ports 1–4
Receive Signaling
Data for Ports 1–4
RSIG2
Receive Signaling
Data for Port 2
Unused
Unused
Unused
RSIG3
Receive Signaling
Data for Port 3
Combined Receive
Signaling Data for
Ports 3 and 4
Unused
Unused
RSIG4
Receive Signaling
Data for Port 4
Unused
Unused
Unused
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-7. TSER Input Pin Definitions
PIN
NORMAL USE
4.096MHz IBO
8.192MHz IBO
16.384MHz IBO
TSER1
Transmit Serial Data
for Port 1
Combined Transmit
Serial Data for
Ports 1 and 2
Combined Transmit
Serial Data for Ports
1–4
Transmit Serial Data
for Ports 1–4
TSER2
Transmit Serial Data
for Port 2
Unused
Unused
Unused
TSER3
Transmit Serial Data
for Port 3
Combined Transmit
Serial Data for
Ports 3 and 4
Unused
Unused
TSER4
Transmit Serial Data
for Port 4
Unused
Unused
Unused
4.096MHz IBO
Combined Transmit
Signaling Data for
Ports 1 and 2
8.192MHz IBO
Combined Transmit
Signaling Data for
Ports 1–4
16.384MHz IBO
Table 8-8. TSIG Input Pin Definitions
PIN
NORMAL USE
TSIG1
Transmit Signaling
Data for Port 1
TSIG2
Transmit Signaling
Data for Port 2
Unused
Unused
Unused
TSIG3
Transmit Signaling
Data for Port 3
Combined Transmit
Signaling Data for
Ports 3 and 4
Unused
Unused
TSIG4
Transmit Signaling
Data for Port 4
Unused
Unused
Unused
Transmit Signaling
Data for Ports 1–4
Table 8-9. RSYNC Input Pin Definitions
PIN
NORMAL USE
4.096MHz IBO
8.192MHz IBO
16.384MHz IBO
RSYNC1
Receive Frame Pulse
for Port 1
Receive Frame Pulse
for Ports 1 and 2
Receive Frame Pulse
for Ports 1–4
Receive Frame Pulse
for Ports 1–4
RSYNC2
Receive Frame Pulse
for Port 2
Unused
Unused
Unused
RSYNC3
Receive Frame Pulse
for Port 3
Receive Frame Pulse
for Ports 3 and 4
Unused
Unused
RSYNC4
Receive Frame Pulse
for Port 4
Unused
Unused
Unused
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DS26524 Quad T1/E1/J1 Transceiver
8.8.3
H.100 (CT Bus) Compatibility
The registers used for controlling the H.100 backplane are RIOCR and TIOCR.
The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard
also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN
(RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26524 to accept a CT buscompatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs.
The following rules apply to the H100EN control bit.
1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input mode)
only. The RSYNC output and other sync signals are not affected.
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz
IBO mode or 2.048MHz backplane operation.
4) The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for
the TSSYNCIO).
5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must
be set high to invert the inbound sync signals.
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode
RSYNC1
RSYNC2
RSYSCLK
RSER
BIT 8
BIT 1
BIT 2
3
tBC
NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION.
NOTE 2: RSYNC INPUT MODE, H100EN = 1 AND RSYNCINV = 1.
NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns or 488ns ALSO ACCEPTABLE.
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode
TSSYNCIO1
TSSYNCIO2
TSYSCLK
TSER
BIT 8
BIT 1
BIT 2
tBC3
NOTE 1: TSSYNCIO IN NORMAL OPERATION.
NOTE 2: TSSYNCIO WITH H100EN = 1 and TSSYNCINV = 1.
NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns OR 488ns ALSO ACCEPTABLE.
8.8.4
Receive and Transmit Channel Blocking Registers
The Receive Channel Blocking registers (RCBR1:RCBR4) and the Transmit Channel Blocking registers
(TCBR1:TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are userprogrammable outputs that can be forced either high or low during individual channels. These outputs can be used
to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to 1,
the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. When used with a T1
(1.544MHz) backplane, only TCBR1:TCBR2:TCBR3 are used. TCBR4 is included to support an E1 (2.048MHz)
backplane when the elastic store is configured for T1-to-E1 rate conversion. See Section 8.8.1.
8.8.5
Transmit Fractional Support (Gapped Clock Mode)
The DS26524 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled
via the Transmit Gapped-Clock Channel Select registers (TGCCS1:TGCCS4). The transmit path is enabled for
gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
8.8.6
Receive Fractional Support (Gapped Clock Mode)
The DS26524 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled
via the Receive Gapped-Clock Channel Select registers (RGCCS1:RGCCS4). The receive path is enabled for
gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
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DS26524 Quad T1/E1/J1 Transceiver
8.9
Framers
The DS26524 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and
multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding,
synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides
clock/data and frame-sync signals to the backplane interface section. Diagnostic capabilities include loopbacks,
and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access
and control of the device.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS (zero code suppression) and AMI line coding.
Both the transmit and receive path have an HDLC controller. The HDLC controller transmits and receives data via
the framer block. The HDLC controller can be assigned to any time slot, portion of a time slot, or to FDL (T1). The
HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to
manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). An IBO is provided to allow multiple framers in the DS26524 to share a high-speed
backplane.
8.9.1
T1 Framing
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit
contains a fixed pattern for the receiver to delineate the frame boundaries. The F-bit is inserted once per frame at
the beginning of the transmit frame boundary. The frames are further grouped into bundles of frames 12 for D4 and
24 for ESF.
The D4 and ESF framing modes are outlined in Table 8-10 and Table 8-11. In the D4 mode, framing bit for frame
12 is ignored if Japanese Yellow is selected.
Table 8-10. D4 Framing Mode
FRAME
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
Ft
Fs
SIGNALING
1
0
0
0
1
1
A
0
1
1
1
0
0
B
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-11. ESF Framing Mode
FRAME
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FRAMING
FDL
CRC
SIGNALING
√
CRC-1
√
0
√
√
CRC-2
√
0
√
CRC-3
√
√
√
CRC-4
√
0
√
√
CRC-5
√
1
√
CRC-6
√
√
1
Table 8-12. SLC-96 Framing
FRAME NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Ft
1
Fs
SIGNALING
0
0
0
1
1
A
0
1
1
1
0
0
B
1
0
0
0
1
1
0
1
1
1
0
43 of 273
C
DS26524 Quad T1/E1/J1 Transceiver
FRAME NUMBER
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ft
Fs
C1 (Concentrator Bit)
SIGNALING
D
1
C2 (Concentrator Bit)
0
C3 (Concentrator Bit)
1
C4 (Concentrator Bit)
A
0
C5 (Concentrator Bit)
1
C6 (Concentrator Bit)
0
C7 (Concentrator Bit)
B
1
C8 (Concentrator Bit)
0
C9 (Concentrator Bit)
1
C10 (Concentrator Bit)
C
0
C11 (Concentrator Bit)
1
0 (Spoiler Bit)
0
D
1 (Spoiler Bit)
1
0 (Spoiler Bit)
0
M1 (Maintenance Bit)
1
M2 (Maintenance Bit)
A
0
M3 (Maintenance Bit)
1
A1 (Alarm Bit)
0
A2 (Alarm Bit)
B
1
S1 (Switch Bit)
0
S2 (Switch Bit)
1
C
S3 (Switch Bit)
0
S4 (Switch Bit)
1
1 (Spoiler Bit)
0
0
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D
DS26524 Quad T1/E1/J1 Transceiver
8.9.2
E1 Framing
The E1 framing consists of FAS, NFAS detection as shown in Table 8-13.
Table 8-13. E1 FAS/NFAS Framing
CRC-4
FRAME
#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TYPE
1
2
3
4
5
6
7
8
FAS
NFAS
FAS
NFAS
FAS
NFAS
FAS
NFAS
FAS
NFAS
FAS
NFAS
FAS
NFAS
FAS
NFAS
C1
0
C2
0
C3
1
C4
0
C1
1
C2
1
C3
E1
C4
E2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
0
A
0
A
0
A
0
A
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
C = C bits are the CRC-4 remainder, A = alarm bits, Sa = bits for data link.
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-14 shows registers that are related to setting up the framing.
Table 8-14. Registers Related to Setting Up the Framer
REGISTER
FRAMER
ADDRESSES
FUNCTION
Transmit Master Mode Register (TMMR)
180h
T1/E1 mode.
Transmit Control Register 1 (TCR1)
181h
Source of the F-bit.
Transmit Control Register 2 (TCR2)
182h
F-bit corruption, selection of SLC-96.
Transmit Control Register 3 (TCR3)
183h
ESF or D4 mode selection.
Receive Master Mode Register (RMMR)
080h
T1/E1 selection for receiver.
Receive Control Register 1 (RCR1)
081h
Resynchronization criteria for the framer.
Receive Control Register 2 (T1RCR2)
014h
T1 remote alarm and OOF criteria.
Receive Control Register 2 (E1RCR2)
082h
E1 receive loss of signal criteria selection.
Receive Latched Status Register 1 (RLS1)
090h
Receive latched status 1.
Receive Interrupt Mask Register 1 (RIM1)
0A0h
Receive interrupt mask 1.
Receive Latched Status Register 2 (RLS2)
091h
Receive latched status 2.
Receive Interrupt Mask Register 2 (RIM2)
0A1h
Receive interrupt mask 2.
Receive Latched Status Register 4 (RLS4)
093h
Receive latched status 4.
Receive Interrupt Mask Register 4 (RIM4)
0A3h
Receive interrupt mask 4.
054h
Framer out of sync register 1.
055h
Framer out of sync register 2.
064h
RAF byte.
065h
RNAF byte.
164h
Transmit SLC-96 bits.
165h
Transmit SLC-96 bits.
166h
Transmit SLC-96 bits.
064h
Receive SLC-96 bits.
065h
Receive SLC-96 bits.
066h
Receive SLC-96 bits.
Frames Out of Sync Count Register 1
(FOSCR1)
Frames Out of Sync Count Register 2
(FOSCR2)
E1 Receive Align Frame Register (E1RAF)
E1 Receive Non-Align Frame Register
(E1RNAF)
Transmit SLC-96 Data Link Register 1
(T1TSLC1)
Transmit SLC-96 Data Link Register 2
(T1TSLC2)
Transmit SLC-96 Data Link Register 3
(T1TSLC3)
Receive SLC-96 Data Link Register 1
(T1RSLC1)
Receive SLC-96 Data Link Register 2
(T1RSLC2)
Receive SLC-96 Data Link Register 3
(T1RSLC3)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.3
T1 Transmit Synchronizer
The DS26524 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the TSYNCC register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss-of-frame
synchronization has occurred. The real-time bit (LOF) is also provided to indicate when the synchronizer is
searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB.
Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the
recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multiframe sync pulse is output if
enabled with TIOCR.0 (TSM = 1).
Other key points concerning the E1 transmit synchronizer:
1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes.
2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify
CRC-4 codewords.
The Tx synchronizer cannot search for the CAS multiframe. Table 8-15 shows the registers related to the transmit
synchronizer.
Table 8-15. Registers Related to the Transmit Synchronizer
REGISTER
FRAMER
ADDRESSES
Transmit Synchronizer Control Register
(TSYNCC)
18Eh
Resynchronization control for the transmit
synchronizer.
Transmit Control Register 3 (TCR3)
183h
TFM bit selects between D4 and ESF for the
transmit synchronizer.
Transmit Latched Status Register 3
(TLS3)
192h
Provides latched status for the transmit
synchronizer.
Transmit Interrupt Mask Register 3
(TIM3)
1A2h
Provides mask bits for the TLS3 status.
Transmit I/O Configuration Register
(TIOCR)
184h
TSYNC should be set as an output.
FUNCTION
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4
Signaling
The DS26524 supports both software- and hardware-based signaling. Interrupts can be generated on changes of
signaling data. The DS26524 is also equipped with receive-signaling freeze on loss of synchronization (OOF),
carrier loss, or change of frame alignment. The DS26524 also has hardware pins to indicate signaling freeze.
• Flexible signaling support
o Software or hardware based
o Interrupt generated on change of signaling data
o Receive-signaling freeze on loss of frame, loss of signal, or change of frame alignment
• Hardware pins for carrier loss and signaling freeze indication
Table 8-16. Registers Related to Signaling
REGISTER
FRAMER ADDRESSES
FUNCTION
Transmit-Signaling Registers 1 to 16
(TS1 to TS16)
140h to 14Bh (T1/J1)
140h to 14Fh (E1 CAS)
Transmit ABCD signaling.
Software-Signaling Insertion Enable
Registers 1 to 4 (SSIE1 to SSIE4)
118h, 119h, 11Ah, 11Bh
When enabled, signaling is inserted for
the channel.
1C8h, 1C9h, 1CAh, 1CBh
Bits determine which channels will have
signaling inserted in hardware-signaling
mode.
Transmit Hardware-Signaling Channel
Select Registers 1 to 4
(THSCS1 to THSCS4)
Receive-Signaling Control Register
(RSIGC)
013h
Freeze control for receive signaling.
Receive-Signaling All-Ones Insertion
Registers 1 to 3
(T1RSAOI1 to T1RSAOI3)
038h, 039h, 03Ah
Receive-Signaling Registers 1 to 16
(RS1 to RS16)
040h to 04Bh (T1/J1)
040h to 04Fh (E1)
Receive-signaling bytes.
Receive-Signaling Status Registers 1
to 4 (RSS1 to RSS4)
Receive-Signaling Change of State
Enable Registers 1 to 4 (RSCSE1 to
RSCSE4)
Receive Latched Status Register 4
(RLS4)
098h to 09Ah (T1/J1)
98h to 9Fh (E1)
Receive-signaling change of status bits.
Receive Interrupt Mask Register 4
(RIM4)
Receive-Signaling Reinsertion Enable
Registers 1 to 4 (RSI1 to RSI4)
0A8h, 0A9h, 0AAh, 0ABh
Registers for all-ones insertion (T1 mode
only).
Receive-signaling change of state
interrupt enable.
093h
Receive-signaling change of state bit.
0A3h
Receive-signaling change of state
interrupt mask bit.
0C8h, 0C9h, 0CAh, 0CBh
Registers for signaling reinsertion.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.1 Transmit-Signaling Operation
There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or
hardware based. Processor based refers to access through the transmit-signaling registers, TS1:TS16, while
hardware based refers to using the TSIG pins. Both methods can be used simultaneously.
8.9.4.1.1 Processor-Based Signaling
In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1:TS16) via the host
interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in
the appropriate bit position in the outgoing data stream. The user can use the transmit multiframe interrupt in
Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any
transmit-signaling register for which there is no change of state for that register.
Each transmit-signaling register contains the robbed-bit signaling (TCR1.4 in T1 mode) or TS16 CAS signaling
(TCR1.6 in E1 mode) for one time slot that will be inserted into the outgoing stream. Signaling data can be sourced
from the TS registers on a per-channel basis by using the software-signaling insertion enable registers,
SSIE1:SSIE4.
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1:TS12 contain a full
multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1
D4 framing mode, the framer uses A and B bit positions for the next multiframe. The C and D bit positions become
“don’t care” in D4 mode.
In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common-channel
signaling) or CAS (channel-associated signaling) format. The 32 time slots are referenced by two different channel
number schemes in E1. In channel numbering, TS0 to TS31 are labeled channel 1 to channel 32. In phone channel
numbering, TS1 to TS15 are labeled channel 1 to channel 15, and TS17 to TS31 are labeled channel 15 to
channel 30.
8.9.4.2 Time Slot Numbering Schemes
TS
0
1
2
3
4
5
6
7
8
Channel
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
Phone
Channel
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
8.9.4.2.1 Hardware-Based Signaling
In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and
inserted to the data stream being input at the TSER pin.
Signaling data can be input via the transmit hardware-signaling channel select (THSCS1) function. The framer can
be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data
stream that is being input at the TSER pin. The user can control which channels are to have signaling data from the
TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available
whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock
(TSYSCLK) can be either 1.544MHz or 2.048MHz.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.3 Receive-Signaling Operation
There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e.,
software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling
registers, RS1:RS16. Hardware based refers to the RSIG pin. Both methods can be used simultaneously.
8.9.4.3.1 Processor-Based Signaling
Signaling information is sampled from the receive data stream and copied into the receive-signaling registers,
RS1:RS16. The signaling information in these registers is always updated on multiframe boundaries. This function
is always enabled.
8.9.4.3.2 Change of State
To avoid constant monitoring of the receive-signaling registers, the DS26524 can be programmed to alert the host
when any specific channel or channels undergo a change of their signaling state. RSCSE1:RSCSE4 are used to
select which channels can cause a change-of-state indication. The change of state is indicated in Latched Status
Register 4 (RLS4.3). If signaling integration is enabled, the new signaling state must be constant for three
multiframes before a change-of-state indication is indicated. The user can enable the INTB pin to toggle low upon
detection of a change in signaling by setting the interrupt mask bit RIM4.3. The signaling integration mode is global
and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the receive-signaling
status (RSS1:RSS4) registers. The information from these registers tells the user which RSx register to read for the
new signaling data. All changes are indicated in the RSS1:RSS4 registers regardless of the RSCSE1:RSCSE4
registers.
8.9.4.3.3 Hardware-Based Receive Signaling
In hardware-based signaling, the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a
signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The T1 robbed bit or E1
TS16 signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data
to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment
that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can be
enabled or disabled. If the receive elastic store is enabled, the backplane clock (RSYSCLK) can be either
1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble
of each channel. The RSIG data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for E1 CAS)
unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the
lower nibble of each channel. Thus, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each
channel.
8.9.4.3.4 Receive-Signaling Reinsertion at RSER
In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data will be reinserted based
on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original
signaling data is based on the Fs/ESF frame positions, and the realigned data is based on the user-supplied
multiframe sync applied at RSYNC. In voice channels, this extra copy of signaling data is of little consequence.
Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,
the elastic store must be enabled; for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1 signaling
information cannot be reinserted into a 1.544MHz backplane.
Signaling-reinsertion mode is enabled on a per-channel basis by setting the receive-signaling reinsertion channel
select bit high in the Receive-Signaling Reinsertion Enable register (RSI1:RSI4). The channels that are to have
signaling reinserted are selected by writing to the RSI1:RSI4 registers. In E1 mode, the user generally selects all
channels or none for reinsertion.
8.9.4.3.5 Force Receive-Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to 1. This is done by
using the T1-mode Receive-Signaling All-Ones Insertion registers (T1RSAOI1:T1RSAOI3). The user sets the
channel select bit in the T1RSAOI1:T1RSAOI3 registers to select the channels that are to have the signaling forced
to one.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.3.6 Receive-Signaling Freeze
The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the
requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE
control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2)
high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer
provides a three multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receivesignaling reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data is held in the last known
good state until the corrupting error condition subsides. When the error condition subsides, the signaling data is
held in the old state for at least an additional 9ms (4.5ms in D4 framing mode, 6ms for E1 mode) before being
allowed to be updated with new signaling data.
The receive-signaling registers are frozen and not updated during a loss-of-sync condition. They will contain the
most recent signaling information before the LOF occurred.
8.9.4.4 Transmit SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into
alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008. Registers related to the transmit FDL are shown
in Table 8-17.
Table 8-17. Registers Related to SLC-96
REGISTER
Transmit FDL Register (T1TFDL)
Transmit SLC-96 Data Link Registers 1
to 3 (T1TSLC1:T1TSLC3)
FRAMER
ADDRESSES
FUNCTION
162h
For sending messages in transmit SLC-96 Ft/Fs
bits.
164h, 165h, 166h
Registers that control the SLC-96 overhead
values.
Transmit Control Register 2 TCR2)
182h
Transmit control for data selection source for the
Ft/Fs bits.
Transmit Latched Status Register 1
(TLS1)
190h
Status bit for indicating transmission of data link
buffer.
Receive SLC-96 Data Link Registers 1
to 3 (T1RSLC1:T1RSLC3)
Receive Latched Status Register 7
(RLS7)
064h, 065h, 066h
096h
—
Receive SLC-96 alignment event.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
The T1TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the
T1TFDL register, the user should configure the DS26524 as shown:
Enable transmit SLC-96.
• TCR2.6 (TSLC96) = 1
Source FS bits via TFDL or SLC-96 formatter.
• TCR2.7 (TFDLS) = 0
D4 framing mode.
• TCR3.2 (TFM) = 1
Do not “pass through” TSER F-bits.
• TCR1.6 (TFPT) = 0
The DS26524 automatically inserts the 12-bit alignment pattern in the Fs bits for the SLC-96 data link frame. Data
from T1TSLC1:T1TSLC3 is inserted into the remaining Fs-bit locations of the SLC-96 multiframe. The status bit
TSLC96 located at TLS1.4 is set to indicate that the SLC-96 data link buffer has been transmitted and that the user
should write new message data into T1TSLC1:T1TSLC3. The host has 9ms after the assertion of TLS1.4 to write
the registers T1TSLC1:T1TSLC3. If no new data is provided in these registers, the previous values are
retransmitted.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.5 Receive SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into
alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008.
To enable the DS26524 to synchronize onto a SLC-96 pattern, the following configuration should be used:
• RCR1.5 (RFM) = 1
Set to D4 framing mode.
Set to cross-couple Ft and Fs bits.
• RCR1.3 (SYNCC) = 1
• T1RCR2.4 (RSLC96) = 1 Enable SLC-96 synchronizer.
Set to minimum sync time.
• RCR1.7 (SYNCT) = 0
The SLC-96 message bits can be extracted via the T1RSLC1:T1RSLC3 registers. The status bit RSLC96 located
at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit indicates when the framer has updated
the data link registers T1RSLC1:T1RSLC3 with the latest message data from the incoming data stream. Once the
RSLC96 bit is set, the user has 9ms (or until the next RSLC96 interrupt) to retrieve the most recent message data
from the T1RSLC1:T1RSLC3 registers. Note that RSLC96 will not set if the DS26524 is unable to detect the 12-bit
SLC-96 alignment pattern.
8.9.5
T1 Data Link
8.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller
The DS26524 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC
function is available only in T1 mode. Table 8-18 shows the registers related to the transmit bit-oriented code.
Table 8-18. Registers Related to T1 Transmit BOC
REGISTER
FRAMER
ADDRESSES
FUNCTION
Transmit BOC Register (T1TBOC)
163h
Transmit bit-oriented message code register.
Transmit HDLC Control Register 2 (THC2)
113h
Bit to enable sending of transmit BOC.
Transmit Control Register 1(TCR1)
181h
Determines the sourcing of the F-bit.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
Bits 0 to 5 in the T1TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6)
causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The
transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as
SBOC is set. Note that the TFPT (TCR1.6) control bit must be set to 0 for the BOC message to overwrite F-bit
information being sampled on TSER.
8.9.5.1.1 To Transmit a BOC
1) Write 6-bit code into the T1TBOC register.
2) Set SBOC bit in THC2 = 1.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.5.2 Receive Bit-Oriented Code (BOC) Controller
The DS26524 framers contain a BOC generator on the transmit side and a BOC detector on the receive side. The
BOC function is available only in T1, ESF mode in the data link bits. Table 8-19 shows the registers related to the
receive BOC operation.
Table 8-19. Registers Related to T1 Receive BOC
REGISTER
FRAMER
ADDRESSES
FUNCTION
Receive BOC Control Register
(T1RBOCC)
015h
Controls the receive BOC function.
Receive BOC Register (T1RBOC)
063h
Receive bit-oriented message.
Receive Latched Status Register 7(RLS7)
096h
Receive Interrupt Mask Register 7 (RIM7)
0A6h
Indicates changes to the receive bit-oriented
messages.
Mask bits for RBOC for generation of
interrupts.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
In ESF mode, the DS26524 continuously monitors the receive message bits for a valid BOC message. The BOC
detect (BD) status bit at RLS7.0 is set once a valid message has been detected for a time determined by the
receive BOC filter bits RBF0 and RBF1 in the T1RBOCC register. The 6-bit BOC message is available in the
T1RBOC register. Once the user has cleared the BD bit, it remains clear until a new BOC is detected (or the same
BOC is detected following a BOC clear event). The BOC clear (BC) bit at RLS7.1 is set when a valid BOC is no
longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the
T1RBOCC register.
The BD and BC status bits can create a hardware interrupt on the INTB signal as enabled by the associated
interrupt mask bits in the RIM7 register.
8.9.5.3 Legacy T1 Transmit FDL
It is recommended that the DS26524’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL. Table 8-21 shows the registers related to control of the transmit FDL.
Table 8-20. Registers Related to T1 Transmit FDL
REGISTER
Transmit FDL Register (T1TFDL)
FRAMER
ADDRESSES
162h
FUNCTION
FDL code used to insert transmit FDL.
Transmit Control Register 2 (TCR2)
182h
Defines the source of the FDL.
Transmit Latched Status Register 2 (TLS2)
Transmit Interrupt Mask Register 2 (HDLC)
(TIM2)
191h
Transmit FDL empty bit.
1A1h
Mask bit for TFDL empty.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
When enabled with TCR2.7, the transmit section shifts out into the T1 data stream either the FDL (in the ESF
framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (T1TFDL). When a
new value is written to the T1TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1
data stream. After the full eight bits have been shifted out, the framer signals the host controller that the buffer is
empty and that more data is needed by setting the TLS2.4 bit to a 1. The INTB bit also toggles low if enabled via
TIM2.4. The user has 2ms to update the T1TFDL with a new value. If the T1TFDL is not updated, the old value in
the T1TFDL is transmitted once again. Note that in this mode, no zero stuffing is applied to the FDL data. It is
strongly suggested that the HDLC controller be used for FDL messaging applications.
In the D4 framing mode, the framer uses the T1TFDL register to insert the Fs framing pattern. To accomplish this,
the T1TFDL register must be programmed to 1Ch and TCR2.7 should be set to 0 (source Fs data from the T1TFDL
register).
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DS26524 Quad T1/E1/J1 Transceiver
The Transmit FDL register (T1TFDL) contains the facility data link (FDL) information that is to be inserted on a byte
basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
8.9.5.4 Legacy T1 Receive FDL
It is recommended that the DS26524’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL. Table 8-21 shows the registers related to the receive FDL.
Table 8-21. Registers Related to T1 Receive FDL
REGISTER
FRAMER
ADDRESSES
FUNCTION
Receive FDL Register (T1RFDL)
062h
FDL code used to insert transmit FDL.
Receive Latched Status Register 7(RLS7)
096h
Receive FDL full bit is in this register.
Receive Interrupt Mask Register 7(RIM7)
0A6h
Mask bit for RFDL full.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register
(T1RFDL). Since the T1RFDL is 8 bits in length, it fills up every 2ms (8 x 250µs). The framer signals an external
controller that the buffer has filled via the RLS7.2 bit. If enabled via RIM7.2, the INTB pin toggles low, indicating
that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no
zero destuffing is applied for the data provided through the T1RFDL register. The T1RFDL reports the incoming
facility data link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, T1RFDL updates on
multiframe boundaries and reports only the Fs bits.
8.9.6
E1 Data Link
Table 8-22 shows the registers related to E1 data link.
Table 8-22. Registers Related to E1 Data Link
REGISTER
E1 Receive Align Frame Register (E1RAF)
E1 Receive Non-Align Frame Register
Register (E1RNAF)
E1 Received Si Bits of the Align Frame
Register (E1RSiAF)
Received Si Bits of the Non-Align Frame
Register E1RSiNAF)
Received Sa4 to Sa8 Bits Register
(E1RSa4 to E1RSa8)
Transmit Align Frame Register (E1TAF)
Transmit Non-Align Frame Register
(E1TNAF)
Transmit Si Bits of the Align Frame
Register (E1TSiAF)
Transmit Si Bits of the Non-Align Frame
Register (E1TSiNAF)
Transmit Sa4 to Sa8 Bits Register
(E1TSa4 to E1TSa8)
E1 Transmit Sa-Bit Control Register
(E1TSACR)
FRAMER
ADDRESSES
064h
FUNCTION
Receive frame alignment register.
065h
Receive non-frame alignment register.
066h
Receive Si bits of the frame alignment frames.
067h
Receive Si bits of the non-frame alignment
frames.
069h, 06Ah,
06Bh, 06Ch,
06Dh
Receive Sa bits.
164h
Transmit align frame register.
165h
Transmit non-align frame register.
166h
Transmit Si bits of the frame alignment frames.
167h
Transmit Si bits of the non-frame alignment
frames.
169h, 16Ah,
16Bh, 16Ch,
16Dh
114h
Transmit Sa4 to Sa8.
Transmit sources of Sa control.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode)
The DS26524, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods.
The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves
an expanded version of the first method.
8.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1)
On the receive side, the E1RAF and E1RNAF registers will always report the data as it received in the Sa- and Sibit locations. The E1RAFand E1RNAF registers are updated on align frame boundaries. The setting of the receive
align frame bit in Receive Latched Status Register 2 (RLS2.0) indicates that the contents of the RAF and RNAF
have been updated. The host can use the RLS2.0 bit to know when to read the E1RAF and E1RNAF registers. The
host has 250µs to retrieve the data before it is lost.
8.9.6.1.2 Internal Register Scheme Based on CRC-4 Multiframe (Receive Side)
On the receive side there is a set of eight registers (E1RSiAF, E1RSiNAF, E1RRA, E1RSa4:E1RSa8) that report
the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4
multiframe bit in Receive Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to
read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions for
additional information.
8.9.6.1.3 Internal Register Scheme Based on CRC-4 Multiframe (Transmit Side)
On the transmit side there is a set of eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4:E1TSa8) that, via the
Transmit Sa-Bit Control register (E1TSACR), can be programmed to insert both Si and Sa data. Data is sampled
from these registers with the setting of the transmit multiframe bit in Transmit Latched Status Register 1 (TLS1.3).
The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the
old data will be retransmitted. See the register descriptions for additional information.
8.9.6.2 Sa-Bit Monitoring and Reporting
In addition to the registers outlined above, the DS26524 provides status and interrupt capability in order to detect
changes in the state of selected Sa bits. The E1RSAIMR register can be used to select which Sa bits are
monitored for a change of state. When a change of state is detected in one of the enabled Sa-bit positions, a status
bit is set in the RLS7 register via the SaXCD bit (bit 0). This status bit can, in turn, be used to generate an interrupt
by unmasking RIM7.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the SaBITS register at
address 06Eh to determine the current value of each Sa bit.
For the Sa6 bits, additional support is available to detect specific codewords per ETS 300 233. The Sa6CODE
register reports the received Sa6 codeword. The codeword must be stable for a period of three submultiframes and
be different from the previous stored value in order to be updated in this register. See the Sa6CODE register
description for further details on the operation of this register and the values reported in it. An additional status bit is
provided in RLS7 (Sa6CD) to indicate if the received Sa6 codeword has changed. A mask bit is provided for this
status bit in RIM7 to allow for interrupt generation when enabled.
8.9.7
Maintenance and Alarms
The DS26524 provides extensive functions for alarm detection and generation. It also provides diagnostic functions
for monitoring of performance and sending of diagnostic information such as the following:
•
•
•
•
•
•
•
•
Real-time and latched status bits, interrupts, and interrupt mask for transmitter and receiver
LOS detection
RIA detection and generation
PDV violation detection
Error counters
DS0 monitoring
Milliwatt generation and detection
Slip buffer status for transmit and receive
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-23 shows some of the registers related to maintenance and alarms.
Table 8-23. Registers Related to Maintenance and Alarms
REGISTER
FRAMER
ADDRESSES
Receive Real-Time Status Register 1 (RRTS1)
0B0h
Real-time receive status 1.
Receive Interrupt Mask Register 1(RIM1)
0A0h
Real-time interrupt mask 1.
Receive Latched Status Register 2 (RLS2)
091h
Real-time latched status 2.
Receive Real-Time Status Register 3 (RRTS3)
0B2h
Real-time receive status 2.
Receive Latched Status Register 3 (RLS3)
092h
Real-time latched status 3.
Receive Interrupt Mask Register 3 (RIM3)
0A2h
Real-time interrupt mask 3.
Receive Interrupt Mask Register 4 (RIM4)
0A3h
Real-time interrupt mask 3.
Receive Latched Status Register 7 (RLS7)
096h
Real-time latched status 7.
Receive Interrupt Mask Register 7 (RIM7)
0A6h
Real-time interrupt mask 7.
Transmit Latched Status Register 1 (TLS1)
190h
Loss of transmit clock status, TPDV, etc.
Transmit Latched Status Register 3
(Synchronizer) (TLS3)
192h
Loss of frame status.
Receive DS0 Monitor Register (RDS0M)
060h
Receive DS0 monitor.
Error-Counter Configuration Register (ERCNT)
086h
Configuration of the error counters.
Line Code Violation Count Register 1
(LCVCR1)
050h
Line code violation counter 1.
Line Code Violation Count Register 2
(LCVCR2)
051h
Line code violation counter 2.
Path Code Violation Count Register 1
(PCVCR1)
052h
Receive path code violation counter 1.
Path Code Violation Count Register 2
(PCVCR2)
053h
Receive path code violation counter 2.
Frames Out of Sync Count Register 1
(FOSCR1)
054h
Receive frame out of sync counter 1
Frames Out of Sync Count Register 2
(FOSCR2)
055h
Receive frame out of sync counter 2
E-Bit Count Register 1 (E1EBCR1)
056h
E-bit count register 1.
E-Bit Count Register 2 (E1EBCR2)
057h
E-bit count register 2.
FUNCTION
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.7.1 Status and Information Bit Operation
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1.
Status bits can operate in either a latched or real-time fashion. Some latched bits can be enabled to generate a
hardware interrupt via the INTB signal.
8.9.7.1.1 Real-Time Bits
Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm
or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the
internal status signals can be read at any time from the real-time status registers without changing any the latched
status register bits.
8.9.7.1.2 Latched Bits
When an event or an alarm occurs and a latched bit is set to 1, it remains set until cleared by the user. These bits
typically respond on a change-of-state for an alarm, condition, or event, and operate in a read-then-write fashion.
The user should read the value of the desired status bit and then write a 1 to that particular bit location to clear the
latched value (write a 0 to locations not to be cleared). Once the bit is cleared, it is not set again until the event has
occurred again.
8.9.7.1.3 Mask Bits
Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Receive Interrupt
Mask registers (RIM1:RIM7). When unmasked, the INTB signal is forced low when the enabled event or condition
occurs. The INTB pin is allowed to return high (if no other unmasked interrupts are present) when the user reads
and then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and
the INTB pin clear even if the alarm is still present.
Note that some conditions can have multiple status indications. For example, receive loss of frame (RLOF)
provides the following indications:
RRTS1.0
(RLOF)
Real-time indication that the receiver is not synchronized with
incoming data stream. Read-only bit that remains high as long as
the condition is present.
RLS1.0
(RLOFD)
Latched indication that the receiver has lost synchronization since
the bit was last cleared. Bit clears when written by the user, even
if the condition is still present (rising edge detect of RRTS1.0).
RLS1.4
(RLOFC)
Latched indication that the receiver has reacquired
synchronization since the bit was last cleared. Bit clears when
written by the user, even if the condition is still present (falling
edge detect of RRTS1.0).
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-24. T1 Alarm Criteria
ALARM
AIS
(Blue Alarm) (See Note 1)
1) D4 Bit 2 Mode
(T1RCR2.0 = 0)
RAI
(Yellow
Alarm)
2) D4 12th F-Bit Mode
(T1RCR2.0 = 1)
(Note: This mode is
also referred to as the
“Japanese Yellow
Alarm.”)
3) ESF Mode
LOS
(Loss of Signal)
(Note: This alarm is also referred to
as receive carrier loss (RCL).)
SET CRITERIA
CLEAR CRITERIA
When over a 3ms window, 4 or
fewer zeros are received.
When bit 2 of 256 consecutive
channels is set to zero for at least
254 occurrences.
When the 12th framing bit is set to
one for two consecutive
occurrences.
When over a 3ms window, 5 or
more zeros are received.
When bit 2 of 256 consecutive
channels is set to zero for less than
254 occurrences.
When the 12th framing bit is set to
zero for two consecutive
occurrences.
When 16 consecutive patterns of
00FF appear in the FDL.
When 14 or fewer patterns of 00FF
hex out of 16 possible appear in the
FDL.
When 192 consecutive zeros are
received.
When 14 or more ones out of 112
possible bit positions are received
starting with the first one received.
Note 1:
The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate
properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria
in the DS26524 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit.
Note 2:
The following terms are equivalent:
RAIS = Blue Alarm
RLOS = RCL
RLOF = Loss of Frame (conventionally RLOS for Dallas Semiconductor devices)
RRAI = Yellow Alarm
8.9.8
E1 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is
enabled (TCR2.6 = 1), the device monitors the receive-side framer to determine if any of the following conditions
are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or
signal). If any one (or more) of these conditions is present, the framer forces an AIS.
When automatic RAI generation is enabled (TCR2.5 = 1), the framer monitors the receive side to determine if any
of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, loss of
receive carrier (or signal), or if CRC-4 multiframe synchronization cannot be found within 128ms of FAS
synchronization (if CRC-4 is enabled). If any one (or more) of the above conditions is present, the framer transmits
an RAI alarm. RAI generation conforms to ETS 300 011 and ITU-T G.706 specifications.
Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm generation enabled
at the same time.
8.9.8.1 Receive AIS-CI and RAI-CI Detection
AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all-ones pattern and 0.15
seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in
length in which, if the first bit is numbered bit 0, bits 3088, 3474, and 5790 are logical zeros and all other bits in the
pattern are logical ones (T1.403). AIS-CI is an unframed pattern, so it is defined for all T1 framing formats. The
RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1.2) is set. RAIS-CI is a latched bit
that should be cleared by the host when read. RAIS-CI continues to set approximately every 1.2 seconds that the
condition is present. The host needs to poll the bit in conjunction with the normal AIS indicators to determine when
the condition has cleared.
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DS26524 Quad T1/E1/J1 Transceiver
RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially
interleaving 0.99 seconds of “00000000 11111111” (right-to-left ) with 90ms of “00111110 11111111.” The RRAI-CI
bit is set when a bit-oriented code of “00111110 11111111” is detected while RRAI (RRTS1.3) is set. The RRAI-CI
detector uses the receive BOC filter bits (RBF0 and RBF1) located in RBOCC to determine the integration time for
RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read.
RRAI-CI continues to set approximately every 1.1 seconds that the condition is present. The host needs to poll the
bit in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to
enable the 200ms ESF RAI integration time with the RAIIE control bit (T1RCR2.1) in networks that use RAI-CI.
8.9.8.2 T1 Receive-Side Digital Milliwatt Code Generation
Receive-side digital milliwatt code generation involves using the T1 Receive Digital Milliwatt registers
(T1RDMWE1:T1RDMWE3) to determine which of the 24 T1 channels of the T1 line going to the backplane should
be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents
a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMWE1, T1RDMWE2, and T1RDMWE3
registers represents a particular channel. If a bit is set to 1, the receive data in that channel is replaced with the
digital milliwatt code. If a bit is set to 0, no replacement occurs.
8.9.9
Error-Count Registers
The DS26524 contains four counters that are used to accumulate line coding errors, path errors, and
synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1
mode only), or manually. See the Error-Counter Configuration register (ERCNT). When updated automatically, the
user can use the interrupt from the timer to determine when to read these registers. All four counters saturate at
their respective maximum counts and they will not roll over. (Note: Only the Line Code Violation Count register has
the potential to overflow, but the bit error would have to exceed 10E-2 before this would occur.)
The DS26524 can share the one-second timer from Port 1 across all ports. All DS26524 error/performance
counters can be configured to update on the shared one-second source, or a separate manual update signal input.
See the Error-Counter Configuration register ERCNT register for more information. By allowing multiple framer
cores to synchronously latch their counters, the host software can be streamlined to read and process performance
information from multiple spans in a more controlled manner.
8.9.9.1 Line Code Violation Count Register (LCVCR)
Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of
the same polarity. In T1 mode, if the B8ZS mode is set for the receive side, then B8ZS codewords are not counted
as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as
BPVs. If ERCNT.0 is set, then the LCVCR counts code violations as defined in ITU-T O.161. Code violations are
defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be
programmed to count BPVs when receiving AMI code and to count CVs when receiving B8ZS or HDB3 code. This
counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and
will not rollover. The bit-error rate on an E1 line would have to be greater than 10E-2 before the PCVCR would
saturate. See Table 8-25 and Table 8-26 for details of exactly what the LCVCRs count.
Table 8-25. T1 Line Code Violation Counting Options
COUNT EXCESSIVE
ZEROS?
(ERCNT.0)
No
Yes
No
Yes
B8ZS ENABLED?
(RCR1.6)
WHAT IS COUNTED IN
LCVCR1, LCVCR2
No
No
Yes
Yes
BPVs
BPVs + 16 consecutive zeros
BPVs (B8ZS/HDB3 codewords not counted)
BPVs + 8 consecutive zeros
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-26. E1 Line Code Violation Counting Options
E1 CODE VIOLATION SELECT
(ERCNT.0)
WHAT IS COUNTED IN
LCVCR1, LCVCR2
0
1
BPVs
CVs
8.9.9.2 Path Code Violation Count Register (PCVCR)
In T1 operation, the Path Code Violation Count register (PCVCR) records either Ft, Fs, or CRC-6 errors. When the
receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC-6
codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position.
Via the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. PCVCR is
disabled during receive loss of synchronization (RLOF = 1) conditions. See Table 8-27 for a detailed description of
exactly what errors the PCVCR counts in T1 operation.
In E1 operation, PCVCR records CRC-4 errors. Since the maximum CRC-4 count in a one-second period is 1000,
this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4 level; it
continues to count if loss of multiframe sync occurs at the CAS level.
The Path Code Violation Count Register 1 (PCVCR1) is the most significant word and Path Code Violation Count
Register 2 (PCVCR2) is the least significant word of a 16-bit counter that records path violations (PVs).
Table 8-27. T1 Path Code Violation Counting Arrangements
FRAMING MODE
COUNT Fs ERRORS?
WHAT IS COUNTED IN
PCVCR1, PCVCR2
D4
No
Errors in the Ft pattern
D4
Yes
Errors in both the Ft and Fs patterns
ESF
Don’t Care
Errors in the CRC-6 codewords
8.9.9.3 Frames Out of Sync Count Register (FOSCR)
The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is
useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events
as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during
receive loss of synchronization (RLOF = 1) conditions. The FOSCR has an alternate operating mode whereby it will
count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF
mode). When the FOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOF = 1)
conditions. See Table 8-28 for a detailed description of what the FOSCR is capable of counting.
In E1 mode, the FOSCR counts word errors in the frame alignment signal in time slot 0. This counter is disabled
when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or
synchronization at either the CAS or CRC-4 multiframe level. Since the maximum FAS word error count in a onesecond period is 4000, this counter cannot saturate.
The Frames Out of Sync Count Register 1 (FOSCR1) is the most significant word and Frames Out of Sync Count
Register 2 (FOSCR2) is the least significant word of a 16-bit counter that records frames out of sync.
Table 8-28. T1 Frames Out of Sync Counting Arrangements
FRAMING MODE
(RCR1.5)
D4
D4
ESF
ESF
COUNT MOS OR F-BIT ERRORS
(ERCNT.1)
MOS
F-Bit
MOS
F-Bit
60 of 273
WHAT IS COUNTED IN
FOSCR1, FOSCR2
Number of multiframes out of sync
Errors in the Ft pattern
Number of multiframes out of sync
Errors in the FPS pattern
DS26524 Quad T1/E1/J1 Transceiver
8.9.9.4 E-Bit Counter (EBCR)
This counter is only available in E1 mode. E-Bit Count Register 1 (E1EBCR1) is the most significant word and E-Bit
Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end block errors
(FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These count
registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second
period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4
level; it continues to count if loss of multiframe sync occurs at the CAS level.
8.9.10 DS0 Monitoring Function
The DS26524 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive
direction at the same time. Table 8-29 shows the registers related to the control of transmit and receive DS0.
Table 8-29. Registers Related to DS0 Monitoring
REGISTER
Transmit DS0 Channel Monitor Select
(TDS0SEL)
Transmit DS0 Monitor Register
(TDS0M)
Receive Channel Monitor Select Register
(RDS0SEL)
Receive DS0 Monitor Register
(RDS0M)
FRAMER
ADDRESSES
FUNCTION
189h
Transmit channel to be monitored.
1BBh
Monitored data.
012h
Receive channel to be monitored.
060h
Monitored data.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM[4:0] bits
in the TDS0SEL register. In the receive direction, the RCM[4:0] bits in the RDS0SEL register need to be properly
set. The DS0 channel pointed to by the TCM[4:0] bits appear in the Transmit DS0 Monitor register (TDS0M) and
the DS0 channel pointed to by the RCM[4:0] bits appear in the Receive DS0 Monitor register (RDS0M). The
TCM[4:0] and RCM[4:0] bits should be programmed with the decimal decode of the appropriate T1 or E1 channel.
T1 channels 1 to 24 map to register values 0 to 23. E1 channels 1 to 32 map to register values 0 to 31. For
example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be
monitored, then the following values would be programmed into TDS0SEL and RDS0SEL:
TCM4 = 0
RCM4 = 0
TCM3 = 0
RCM3 = 1
TCM2 = 1
RCM2 = 1
TCM1 = 0
RCM1 = 1
TCM0 = 1
RCM0 = 0
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DS26524 Quad T1/E1/J1 Transceiver
8.9.11 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions.
The Transmit Idle Code Definition registers (TIDR1:TIDR32) are provided to set the 8-bit idle code for each
channel. The Transmit Channel Idle Code Enable registers (TCICE1:TCICE4) are used to enable idle code
replacement on a per-channel basis.
8.9.12 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The
Receive Idle Code Definition registers (RIDR1:RIDR32) are provided to set the 8-bit idle code for each channel.
The Receive Channel Idle Code Enable registers (RCICE1:RCICE4) are used to enable idle code replacement on
a per-channel basis.
8.9.13 Per-Channel Loopback
The Per-Channel Loopback Enable registers (PCL1:PCL4) determine which channels (if any) from the backplane
should be replaced with the data from the receive side, i.e., off the T1 or E1 line. If this loopback is enabled, the
transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie
RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on
how many channels can be looped back.
Each of the bit positions in the Per-Channel Loopback Enable registers (PCL1:PCL4) represents a DS0 channel in
the outgoing frame. When these bits are set to 1, data from the corresponding receive channel replaces the data
on TSER for that channel.
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
The DS26524 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is
enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word,
and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will
be used to modify the CRC-4 checksum. This modification, however, does not corrupt any error information the
original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode.
The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input, the user must assert TSYNC
aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe align
the data presented to TSER. This mode is enabled with the TCR3.0 control bit (CRC4R). Note that the E1
transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4).
Figure 8-8. CRC-4 Recalculate Method
TTIP/TRING
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
TSER
+
CRC-4
CALCULATOR
XOR
MODIFY
Sa-BIT
POSITIONS
NEW Sa-BIT
DATA
62 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.9.15 T1 Programmable In-Band Loop Code Generator
The DS26524 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is available only in T1 mode.
Table 8-30. Registers Related to T1 In-Band Loop Code Generator
REGISTER
Transmit Code Definition Register 1
(T1TCD1)
Transmit Code Definition Register 2
(T1TCD2)
FRAMER
ADDRESSES
FUNCTION
1ACh
Pattern to be sent for loop code.
1ADh
Length of the pattern to be sent.
Transmit Control Register 3 (TCR3)
183h
TLOOP bit for control of number of patterns being
sent.
Transmit Control Register 4 (TCR4)
186h
Length of the code being sent.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
To transmit a pattern, the user loads the pattern to be sent into the Transmit Code Definition registers (T1TCD1
and T1TCD2) and selects the proper length of the pattern by setting the TC1 and TC0 bits in Transmit Control
Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both T1TCD1 and T1TCD2 must be filled
with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires T1TCD1 to be filled. Once this is
accomplished, the pattern is transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless
the transmit formatter is programmed to not insert the F-bit position) the framer overwrites the repeating pattern
once every 193 bits to allow the F-bit position to be sent.
As an example, to transmit the standard loop-up code for Channel Service Units (CSUs), which is a repeating
pattern of ...10000100001..., set TCD1 = 80h, TC0 = 0, TC1 = 0, and TCR3.0 = 1.
63 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.9.16 T1 Programmable In-Band Loop Code Detection
The DS26524 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is available only in T1 mode.
Table 8-31. Registers Related to T1 In-Band Loop Code Detection
REGISTER
FRAMER
ADDRESSES
FUNCTION
Receive In-Band Code Control Register
(T1RIBCC)
082h
Used for selecting length of receive inband loop code register.
Receive Up Code Definition Register 1
(T1RUPCD1)
0ACh
Receive up code definition register 1.
Receive Up Code Definition Register 2
(T1RUPCD2)
0ADh
Receive up code definition register 2.
Receive Down Code Definition Register 1
(T1RDNCD1)
0AEh
Receive down code definition register 1.
Receive Down Code Definition Register 2
(T1RDNCD2)
0AFh
Receive up code definition register 2.
Receive Spare Code Register 1 (T1RSCD1)
09Ch
Receive spare code register 1.
Receive Spare Code Register 2 (T1RSCD2)
09Dh
Receive spare code register 2.
Receive Real-Time Status Register 3 (RRTS3)
0B2h
Real-time loop code detect.
Receive Latched Status Register 3 (RLS3)
092h
Latched loop code detect bits.
Receive Interrupt Mask Register 3 (RIM3)
0A2h
Mask for latched loop code detect bits.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and
“loop-down” code detection. The user programs the codes to be detected in the Receive Up Code Definition
registers (T1RUPCD1 and T1RUPCD2) and the Receive Down Code Definition registers (T1RDNCD1 and
T1RDNCD2). The length of each pattern is selected via the Receive In-Band Code Control register (T1RIBCC).
There is a third detector (Spare) and it is defined and controlled via the T1RSCD1/T1RSCD2 and T1RSCC
registers. When detecting a 16-bit pattern, both receive code definition registers are used together to form a 16-bit
register. For 8-bit patterns, both receive code definition registers are filled with the same value. Detection of a 1-,
2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer
detects repeating pattern codes in both framed and unframed circumstances with bit-error rates as high as 10E-2.
The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the
receive code definition register resets the integration period for that detector. The code detector has a nominal
integration period of 48ms. Thus, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and
LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN,
and LSP (RRTS3 and RLS3). Normally codes are sent for a period of 5 seconds. It is recommended that the
software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously
present.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.17 Framer Payload Loopbacks
The framer, payload, and remote loopbacks are controlled by Receive Control Register 3 (RCR3).
Table 8-32. Registers Related to Framer Payload Loopbacks
FRAMER
ADDRESSES
FUNCTION
Framer Loopback
083h
Transmit data output from the framer is looped back to the receiver.
Payload Loopback
083h
The 192-bit payload data is looped back to the transmitter.
Remote Loopback
083h
Data recovered by the receiver is looped back to the transmitter.
RECEIVE CONTROL
REGISTER 3 (RCR3)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.10
HDLC Controllers
8.10.1 Receive HDLC Controller
The DS26524 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as
specific Sa bits (E1 mode).
The HDLC controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 8-33 shows the registers related to the HDLC.
Table 8-33. Registers Related to the HDLC
REGISTER
Receive HDLC Control Register (RHC)
Receive HDLC Bit Suppress Register
(RHBSE)
Receive HDLC FIFO Control Register
(RHFC)
Receive HDLC Packet Bytes Available
Register (RHPBA)
FRAMER
ADDRESSES
010h
011h
087h
0B5h
FUNCTION
Mapping of the HDLC to DS0 or FDL.
Receive HDLC bit suppression register.
Determines the length of the receive HDLC
FIFO.
Tells the user how many bytes are available in
the teceive HDLC FIFO.
Receive HDLC FIFO Register (RHF)
0B6h
The actual FIFDO data.
Receive Real-Time Status Register 5
(RRTS5)
0B4h
Indicates the FIFO status.
Receive Latched Status Register 5 (RLS5)
094h
Latched status.
Receive Interrupt Mask Register 5 (RIM5)
0A4h
Interrupt mask for interrupt generation for the
latched status.
Transmit HDLC Control Register 1(THC1)
110h
Miscellaneous transmit HDLC control.
Transmit HDLC Bit Suppress Register
(THBSE)
111h
Transmit HDLC Control Register 2 (THC2)
113h
Transmit HDLC FIFO Control Register
(THFC)
Transmit Real-Time Status Register 2
(TRTS2)
Transmit HDLC Latched Status Register 2
(TLS2)
Transmit Interrupt Mask Register 2 (HDLC)
Register (TIM2)
Transmit HDLC FIFO Buffer Available
Register (TFBA)
Transmit HDLC FIFO Register (THF)
Transmit HDLC bit suppress for bits not to be
used.
HDLC to DS0 channel selection and other
control.
187h
Used to control the transmit HDLC FIFO.
1B1h
Indicates the real-time status of the transmit
HDLC FIFO.
191h
Indicates the FIFO status.
1A1h
Interrupt mask for the latched status.
1B3h
Indicates the number of bytes that can be
written into the transmit FIFO.
1B4h
Transmit HDLC FIFO.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.10.1.1
HDLC FIFO Control
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and
Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) is set. RHWM and THRM are
real-time bits and remain set as long as the FIFO’s write pointer is above the watermark. When the transmit FIFO
empties below the low watermark, the TLWM bit in the TRTS2 register is set. TLWM is a real-time bit and remains
set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition can also cause an
interrupt via the INTB pin.
If the receive HDLC FIFO does overrun, the current packet being processed is dropped. The receive FIFO is
emptied. The packet status bit in RRTS5 and RLS5.5 (ROVR) indicate an overrun.
8.10.1.2
Receive HDLC Packet Bytes Available
The lower 7 bits of the Receive HDLC Packet Bytes Available register (RHPBA) indicates the number of bytes (0 to
64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many
bytes can be read from the receive FIFO without going past the end of a message. This value refers to one of four
possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet.
After reading the number of bytes indicated by this register, the host then checks the HDLC status registers for
detailed message status.
If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message, then
the MSB of the RHPBA register returns a value of 1. This indicates that the host can safely read the number of
bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register
since the packet has not yet terminated (successfully or otherwise).
8.10.1.3
HDLC Status and Information
RRTS5, RLS5, and TLS2 provide status information for the HDLC controller. When a particular event has occurred
(or is occurring), the appropriate bit in one of these registers is set to 1. Some of the bits in these registers are
latched and some are real-time bits that are not latched. This section contains register descriptions that list which
bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to 1, it remains
set until the user reads and clears that bit. The bit is cleared when a 1 is written to the bit, and it will not be set
again until the event has occurred again. The real-time bits report the current instantaneous conditions that are
occurring and the history of these bits is not latched.
Like the other latched status registers, the user follows a read of the status bit with a write. The byte written to the
register informs the device which of the latched bits the user wishes to clear (the real-time bits are not affected by
writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions he or she
wishes to clear and a 0 in the bit positions he or she does not wish to clear.
The HDLC status registers RLS5 and TLS2 have the ability to initiate a hardware interrupt via the INTB output
signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC
interrupt mask registers RIM5 and TIM2. Interrupts force the INTB signal low when the event occurs. The INTB pin
is allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
8.10.1.4
HDLC Receive Example
The HDLC status registers in the DS26524 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers,
or a combination of polling and interrupt processes can be used. An example routine for using the DS26524 HDLC
receiver is given in Figure 8-9.
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-9. Receive HDLC Example
Configure Receive
HDLC Controller
(RHC, RHBSE, RHFC)
Reset Receive
HDLC Controller
(RHC.6)
Start New
Message Buffer
Enable Interrupts
RPE and RHWM
NO
Interrupt?
No Action Required
Work Another Process.
YES
Read Register
RHPBA
Start New
Message Buffer
NO
MS = 1?
YES
(MS = RHPBA[7])
Read N Bytes From
Rx HDLC FIFO (RHF)
N = RHPBA[5..0]
Read N Bytes From
Rx HDLC FIFO (RHF)
N = RHPBA[5..0]
Read RRTS5 for
Packet Status (PS2..0)
Take appropriate action
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DS26524 Quad T1/E1/J1 Transceiver
8.10.2 Transmit HDLC Controller
8.10.2.1
FIFO Information
The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
8.10.2.2
HDLC Transmit Example
The HDLC status registers in the DS26524 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used. An example routine for using the
DS26524 HDLC receiver is given in Figure 8-10.
69 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 8-10. HDLC Message Transmit Example
Configure Transmit
HDLC Controller
(THC1,THC2,THBSE,THFC)
Reset Transmit
HDLC Controller
(THC.5)
Enable TLWM
Interrupt and
Verify TLWM Clear
Set TEOM
(THC1.2)
Read TFBA
N = TFBA[6..0]
Push Last Byte
into Tx FIFO
Push Message Byte
into Tx HDLC FIFO
(THF)
Enable TMEND
Interrupt
Loop N
Last Byte of
Message?
YES
TMEND
Interrupt?
NO
TLWM
Interrupt?
YES
NO
Read TUDR
Status Bit
A
YES
NO
TUDR = 1
A
YES
No Action Required
Work Another Process
Disable TMEND Interrupt
Prepare New
Message
70 of 273
Disable TMEND Interrupt
Resend Message
NO
A
DS26524 Quad T1/E1/J1 Transceiver
8.11
Line Interface Units (LIUs)
The DS26524 has four identical LIU transmit and receive front-ends for the four framers. Each LIU contains three
sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and
data recovery; and the jitter attenuator. The DS26524 LIUs can switch between T1 or E1 networks without
changing any external components on either the transmit or receive side. Figure 8-11 shows a recommended
circuit for software-selected termination with protection. In this configuration, the device can connect to 100Ω T1
twisted pair, 110Ω J1 twisted pair, 75Ω or 120Ω E1 twisted pair without additional component changes. The signals
between the framer and LIU are not accessible by the user, thus the framer and LIU cannot be separated. The
transmitters have fast high-impedance capability and can be individually powered down.
The DS26524’s transmit waveforms meet the corresponding G.703 and T1.102 specifications. Internal softwareselectable transmit termination is provided for 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1 twisted pair,
and 75Ω E1 coaxial applications. The receiver can connect to 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1
twisted pair, and 75Ω E1 coaxial. The receive LIU can function with a receive signal attenuation of up to 36dB for
T1 mode and 43dB for E1 mode. The receiver sensitivity is programmable from 12dB to 43dB of cable loss. Also, a
monitor gain setting can be enabled to provide 14dB, 20dB, 26dB, and 32dB of resistive gain.
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DS26524 Quad T1/E1/J1 Transceiver
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal
Protection
TX
TIP
F1
3.3 V
T1
T3
DVDD
TTIP
S3
0.01 uF
S1
S7
S4
TX
RING
RX
TIP
560 pF
TRING
2:1
F2
Dallas
Single Chip Transceiver
or
Line Interface Unit
F3
T2
T4
RTIP
S5
68 uF
3.3 V
TVDD
0.1 uF
TVSS
S2
S8
RVDD
S6
RX
RING
0.1 uF
DVSS
RRING
1:1
F4
60
0.1 uF
RVSS
60
0.1 uF
NAME
F1 to F4
S1, S2
S3 to S6
S7, S8
T1 and T2
T3 and T4
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
DESCRIPTION
PART
MANUFACTURER
NOTES
1.25A Slow Blow Fuse
1.25A Slow Blow Fuse
25V (max) Transient Suppressor
180V (max) Transient Suppressor
40V (max) Transient Suppressor
Transformer 1:1CT and 1:2CT (3.3V, SMT)
Dual Common-Mode Choke (SMT)
SMP 1.25
F1250T
P0080SA MC
P1800SC MC
P0300SC MC
PE-68678
PE-65857
Bel Fuse
Teccor Electronics
Teccor Electronics
Teccor Electronics
Teccor Electronics
Pulse Engineering
Pulse Engineering
5
5
1, 5
1, 4, 5
1, 5
2, 3, 5
5
Changing S7 and S8 to P1800SC devices provides symmetrical voltage suppresion between tip, ring, and ground.
The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated
from other circuit lines by at least 150 mils. The area under this portion of the circuit should not contain power planes.
Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers.
The ground trace connected to the S3/S4 pair and the S5/S6 pair should be at least 50 mils wide to conduct the extra current
from a longitudinal power-cross event.
Alternative component recommendations and line interface circuits can be found by contacting
telecom.support@dalsemi.com or in Application Note 324, which is available at www.maxim-ic.com/AN324.
The 560pF on TTIP/TRING must be tuned to your application.
72 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 8-34. Recommended Supply Decoupling
SUPPLY PINS
DECOUPLING CAPACITANCE
DVDD/DVSS
0.01µF + 0.1µF + 1µF + 10µF
DVDDIO/DVSSIO
0.01µF + 0.1µF + 1µF + 10µF
ATVDD/ATVSS
0.1µF (x8) + 1µF (x4) + 10µF (x2)
ARVDD/ARVSS
0.1µF (x8) + 1µF (x4) + 10µF (x2)
ACVDD/ACVSS
0.1µF + 1µF + 10µF
73 of 273
NOTES
—
—
It is recommended to use one 0.1µF capacitor for
each ATVDD/ATVSS pair (8 total), one 1µF for
every two ATVDD/ATVSS pairs (4 total), and two
10µF capacitors for the analog transmit supply
pins. These capacitors should be located as close
to the intended power pins as possible.
It is recommended to use one 0.1µF capacitor for
each ARVDD/ARVSS pair (8 total), one 1µF for
every two ARVDD/ARVSS pairs (4 total), and two
10µF capacitors for the analog receive supply pins.
These capacitors should be located as close to the
intended power pins as possible.
—
DS26524 Quad T1/E1/J1 Transceiver
8.11.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer
coupled into the RTIP and RRING pins of the DS26524. The user has the option to use internal termination,
software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and
data from the analog signal and passes it through the jitter attenuation mux. The DS26524 contains an active filter
that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive
circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to
-43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km
(E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the
waveshaping circuitry and line driver. The DS26524 drives the E1 or T1 line from the TTIP and TRING pins via a
coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in Table 8-35.
Table 8-35. Registers Related to Control of DS26524 LIU
REGISTER
Global Transceiver Control Register 2
(GTCR2)
Global Transceiver Clock Control Register
(GTCCR)
Global LIU Software Reset Register
(GLSRR)
Global LIU Interrupt Status Register
(GLISR)
Global LIU Interrupt Mask Register
(GLIMR)
LIU Transmit Receive Control Register
(LTRCR)
LIU Transmit Impedance and Pulse Shape
Selection Register (LTITSR)
FRAMER
ADDRESSES
FUNCTION
0F2h
Global transceiver control.
0F3h
MPS selections, backplane clock
selections
0F5h
Software reset control for the LIU.
0FBh
Interrupt status bit for each of the 4 LIUs.
0FEh
Interrupt mask register for the LIU.
1000h
1001h
T1/J1/E1 selection, output tri-state, loss
criteria.
Transmit pulse shape and impedance
selection.
Transmit maintenance and jitter
attenuation control register.
LIU Maintenance Control Register (LMCR)
1002h
LIU Real Status Register (LRSR)
1003h
LIU Status Interrupt Mask Register
(LSIMR)
1004h
LIU Latched Status Register (LLSR)
1005h
LIU Receive Signal Level Register (LRSL)
1006h
LIU receive signal level indicator.
LIU Receive Impedance and Sensitivity
Monitor Register (LRISMR)
1007h
LIU impedance match and sensitivity
monitor.
LIU real-time status register.
LIU mask registers based on latched
status bits.
LIU latched status bits related to loss, open
circuit, etc.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following framer: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.11.2 Transmitter
NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data
passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to
generate transmit waveforms complaint with T1.102 and G.703 pulse templates.
A line driver is used to drive an internal matched impedance circuit for provision of 75Ω, 100Ω, 110Ω, and 120Ω
terminations. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1
applications) via a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used
must meet the specifications listed in Table 8-37. The transmitter requires a transmit clock of 2.048MHz for E1 or
1.544MHz for T1/J1 operation.
The DS26524 drivers have a short-circuit and open-circuit detection driver-fail monitor. The TXENABLE pin can
high impedance the transmitter outputs for protection switching. The individual transmitters can also be placed in
high impedance through register settings. The DS26524 also has functionality for powering down the transmitters
individually. The relevant telecommunications specification compliance is shown in Table 8-36.
Table 8-36. Telecommunications Specification Compliance for DS26524 Transmitters
TRANSMITTER FUNCTION
TELECOMMUNICATIONS COMPLIANCE
T1 Telecom Pulse Template Compliance
ANSI T1.403
T1 Telecom Pulse Template Compliance
ANSI T1.102
Transmit Electrical Characteristics for E1 Transmission
and Return Loss Compliance
ITU-T G.703
Table 8-37. Transformer Specifications
SPECIFICATION
Turns Ratio 3.3V Applications
Primary Inductance
Leakage Inductance
Intertwining Capacitance
Primary (Device Side)
Transmit Transformer DC
Resistance
Secondary
Primary
(Device Side)
Receive Transformer DC
Resistance
Secondary
RECOMMENDED VALUE
1:1 (receive) and 1:2 (transmit) ±2%
600µH minimum
1.0µH maximum
40pF maximum
1.0Ω maximum
2.0Ω maximum
1.2Ω maximum
1.2Ω maximum
75 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.2.1
Transmit-Line Pulse Shapes
The DS26524 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The
T1/J1 pulse template is shown in Figure 8-12. The E1 pulse template is shown in Figure 8-13. The transmit pulse
shape can be configured for each LIU on an individual basis. The LIU transmit impedance selection registers can
be used to select an internal transmit terminating impedance of 100Ω for T1, 110Ω for J1 mode, 75Ω or 120Ω for
E1 mode or no internal termination for E1 or T1 mode. The transmit pulse shape and terminating impedance is
selected by LTITSR registers. The pulse shapes will be complaint to T1.102 and G.703. Pulse shapes are
measured for compliance at the appropriate network interface (NI). For T1 long haul and E1, the pulse shape is
measured at the far end. For T1 short haul, the pulse shape is measured at the near end.
Figure 8-12. T1/J1 Transmit Pulse Templates
1.2
1.1
1.0
0.9
0.8
NORMALIZED AMPLITUDE
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
T1.102/87, T1.403,
CB 119 (Oct. 79), &
I.431 Template
-0.2
-0.3
-0.4
-0.5
-500
-400
-300
-200
-100
0
-0.77
-0.39
-0.27
-0.27
-0.12
0.00
0.27
0.35
0.93
1.16
-500
-255
-175
-175
-75
0
175
225
600
750
0.05
0.05
0.80
1.15
1.15
1.05
1.05
-0.07
0.05
0.05
MINIMUM CURVE
UI
Time
Amp.
-0.77
-0.23
-0.23
-0.15
0.00
0.15
0.23
0.23
0.46
0.66
0.93
1.16
-500
-150
-150
-100
0
100
150
150
300
430
600
750
300
400
500
DS1 Template (per ANSI T1.403-1995
DSX-1 Template (per ANSI T1.102-1993
MAXIMUM CURVE
Time
Amp.
UI
100
200
TIME (ns)
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.20
-0.05
-0.05
MAXIMUM CURVE
UI
Time
Amp.
-0.77
-0.39
-0.27
-0.27
-0.12
0.00
0.27
0.34
0.77
1.16
76 of 273
-500
-255
-175
-175
-75
0
175
225
600
750
0.05
0.05
0.80
1.20
1.20
1.05
1.05
-0.05
0.05
0.05
MINIMUM CURVE
UI
Time
Amp.
-0.77
-0.23
-0.23
-0.15
0.00
0.15
0.23
0.23
0.46
0.61
0.93
1.16
-500
-150
-150
-100
0
100
150
150
300
430
600
750
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.26
-0.05
-0.05
600
700
DS26524 Quad T1/E1/J1 Transceiver
Figure 8-13. E1 Transmit Pulse Templates
1.2
1.1
269ns
SCALED AMPLITUDE
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak
in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)
1.0
0.9
0.8
0.7
G.703
Template
194ns
0.6
0.5
219ns
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-250
-200
-150
-100
-50
0
50
100
150
200
250
TIME (ns)
8.11.2.2
Transmit Power-Down
The individual transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control register
(LMCR). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIP
and TRING pins.
When tansmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference. Data
input from the framer is ignored. AIS can be sent by setting a bit in the LMCR. Transmit all ones will also be sent if
the corresponding receiver goes into LOS state and the ATAIS bit is set in the LMCR.
8.11.2.3
Transmit Short-Circuit Detector/Limiter
Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is
approximately 25Ω or less. SCS (LRSR.2) provides a real-time indication of when the current limiter is activated.
The LIU Latched Status register (LLSR) provides latched versions of the information, which can be used to activate
an interrupt when enabled via the LSIMR register.
8.11.2.4
Transmit Open-Circuit Detector
The DS26524 can also detect when the TTIP or TRING outputs are open circuited. OCS (LRSR.1) provides a realtime indication of when an open circuit is detected. Register LLSR provides latched versions of the information,
which can be used to activate an interrupt when enabled via the LSIMR register. The open-circuit detect feature is
not available in T1 CSU operating modes (LBO5, LBO6, and LBO7).
77 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.3 Receiver
The DS26524 contains four identical receivers. The four receivers are designed to be fully software-selectable for
E1, T1, and J1 without the need to change any external resistors. The device couples to the receive E1 or T1
twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1 transformer. See Table 8-37 for transformer
details. Receive termination and sensitivity are user configurable. Receive termination is configurable for 75Ω,
100Ω, 110Ω, or 120Ω termination by setting the appropriate RIMPM[1:0] bits (LRISMR). When using the internal
termination feature, the resistors labeled Rr in Figure 8-11 should be 60Ω each. If external termination is required,
the resistors need to be 37.5Ω, 50Ω, or 60Ω each depending on the line impedance. Receive sensitivity is
configurable by setting the appropriate RSMS[1:0] bits (LRISMR).
The DS26524 uses a digital clock recovery system. The resultant E1, T1, or J1 clock derived from MCLK is
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the
clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This
oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in
Figure 8-15.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. If the jitter attenuator (LTRCR) is placed in the receive path
(as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If
the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See Table 12-2 for
more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs and the
RCLK is derived from the JACLK source.
8.11.3.1
Receive Level Indicator
The DS26524 reports the signal strength at RTIP and RRING in approximately 2.5dB increments via RSL[3:0]
located in the LIU Receive Signal Level register (LRSL). This feature is helpful when trouble shooting line
performance problems.
8.11.3.2
Receive G.703 Section 10 Synchronization Signal
The DS26524 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T
G.703. To use this mode, set the receive G.703 clock-enable bit RG703 (LRISMR.7) found in the LIU Receive
Impedance and Sensitivity Monitor register (LRISMR).
8.11.3.3
Receiver Monitor Mode
The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation
caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to
32dB, along with cable attenuation of 12dB to 30dB as shown in the LIU Receive Impedance and Sensitivity
Monitor register (LRISMR).
78 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 8-14. Typical Monitor Application
PRIMARY
T1/E1 TERMINATING
DEVICE
T1/E1 LINE
Rm
Rm
X
F
M
R
MONITOR
PORT JACK
Rt
DS26524
SECONDARY T1/E1
TERMINATING
DEVICE
8.11.3.4
Loss of Signal (LOS)
The DS26524 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for
T1/J1 and ITU-T G.775, or ETS 300 233 for E1 mode of operation.
Loss of signal (LOS) is detected if the receiver level falls below a threshold analog voltage for certain duration.
Alternatively, this can be termed as having received “0s” for a certain duration. The signal level and timing duration
are defined in accordance with the ANSI T1.231, ITU-T G.775, or ETS 300 233 specifications.
For short-haul mode, the loss-detection thresholds are based on cable loss of 12dB to 18dB for both T1/J1 and E1
modes. The loss thresholds are selectable based on Table 9-19. For long-haul mode, the LOS detection threshold
is based on cable loss of 30dB to 38dB for T1/J1 and 30dB to 45dB for E1 mode. Note there is no explicit bit called
short-haul mode selection. Loss declaration level is set at 3dB lower that the maximum sensitivity setting
programmed in Table 9-19.
The loss state is exited when the receiver detects a certain ones density at the maximum sensitivity level or higher,
which is 3dB higher than the loss-detection level. The loss-detection signal level and loss-reset signal level are
defined with hysteresis to prevent the receiver from bouncing between “LOS” and “no LOS” states. Table 8-38
outlines the specifications governing the loss function.
Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications
CRITERIA
Loss
Detection
Loss Reset
ANSI T1.231
No pulses are detected for 175
±75 bits.
Loss is terminated if a duration
of 12.5% ones are detected
over duration of 175 ±75 bits.
Loss is not terminated if 8
consecutive zeros are found if
B8ZS encoding is used. If
B8ZS is not used, loss is not
terminated if 100 consecutive
pulses are zero.
STANDARD
ITU-T G.775
No pulses are detected for
duration of 10 to 255-bit
periods.
The incoming signal has
transitions for duration of 10 to
255-bit periods.
79 of 273
ETS 300 233
No pulses are detected for a
duration of 2048-bit periods or
1ms.
Loss reset criteria are not
defined.
DS26524 Quad T1/E1/J1 Transceiver
8.11.3.5
ANSI T1.231 for T1 and J1 Modes
For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based
on Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss will be
declared at 15dB. LOS is reset if the following criteria are met:
1) 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and
RRING.
2) During the 192 bits, fewer than 100 consecutive zeros are detected.
For long-haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on
Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity is programmed at 30dB, loss declaration level
will be 33dB. LOS is reset if the following criteria are met:
1) 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and
RRING.
2) During the 192 bits, fewer than 100 consecutive zeros are detected.
8.11.3.6
ITU-T G.775 for E1 Modes
For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based
on Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss will be
declared at 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity
level for a duration of 192-bit periods.
For long-haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on
Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity is programmed at 30dB, loss declaration level
will be 33dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for
a duration of 192-bit periods.
8.11.3.7
ETS 200 233 for E1 Modes
For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based
on Table 9-19) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than
or equal to programmed sensitivity level for a duration of 192-bit periods.
For long-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on
Table 9-19) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than or
equal to the programmed sensitivity level for a duration of 192-bit periods.
80 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.4 Jitter Attenuator
The DS26524 contains a jitter attenuator for each LIU that can be set to a depth of 32 or 128 bits via the JADS
(LTRCR.4) bit in the LIU Transmit Receive Control register (LTRCR).
The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used
in delay-sensitive applications. The characteristics of the attenuation are shown in Figure 8-15. The jitter attenuator
can be placed in either the receive path, the transmit path, or disabled by appropriately setting the JAPS1 and
JAPS0 bits in LTRCR.
For the jitter attenuator to operate properly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x clock must be applied
at MCLK. See the Global Transceiver Clock Control register (GTCCR) for MCLK options. ITU-T specification G.703
requires an accuracy of ±50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an accuracy
of ±32ppm for T1/J1 interfaces. Circuitry adjusts either the recovered clock from the clock/data recovery block or
the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used to clock data out of the jitter
attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed in
the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is
32 bits), the DS26524 sets the jitter attenuator limit trip set (JALTS) bit in the LIU Latched Status register (LLSR.3).
In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz and in E1 mode it is 0.6Hz.
The DS26524 jitter attenuator is complaint with the following specifications shown in Table 8-39.
Table 8-39. Jitter Attenuator Standards Compliance
STANDARD
ITU-T I.431, G.703, G.736, G.823
ETS 300 011, TBR 12/13
AT&T TR62411, TR43802
TR-TSY-009, TR-TSY-253, TR-TSY-499
Figure 8-15. Jitter Attenuation
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
-20dB
C
ur
ve
A
E1
T1
TR 62411 (Dec. 90)
Prohibited Area
-40dB
Cu
B
rve
JITTER ATTENUATION (dB)
0dB
-60dB
1
10
100
1K
FREQUENCY (Hz)
81 of 273
10K
100K
DS26524 Quad T1/E1/J1 Transceiver
8.11.5 LIU Loopbacks
The DS26524 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote
loopback, and dual loopback. In the loopback diagrams that follow, TSER, TCLK, RSER, and RCLK are
inputs/outputs from the framer. Note that the framer input/output can be in IBO mode where a single TSER/RSER
can be shared by up to eight framers.
8.11.5.1
Analog Loopback
The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at
RTIP and RRING is ignored in analog loopback. This is shown in Figure 8-16.
Figure 8-16. Analog Loopback
TCLK
TSER
RCLK
RSER
8.11.5.2
TRANSMIT
FRAMER
OPTIONAL
JITTER
ATTENUATOR
TRANSMIT
DIGITAL
TRANSMIT
ANALOG
RECEIVE
FRAMER
OPTIONAL
JITTER
ATTENUATOR
RECEIVE
DIGITAL
RECEIVE
ANALOG
LINE
DRIVER
RTIP
RRING
Local Loopback
The transmit system data (the internal signals TPOS, TNEG, and TCLK) is looped back to receive-side inputs to
the receive jitter attenuator. The data is also output on TTIP and TRING. Signals at RTIP and RRING are ignored.
This loopback is conceptually shown in Figure 8-17.
Figure 8-17. Local Loopback
TCLK
TSER
TRANSMIT
FRAMER
RCLK
RSER
RECEIVE
FRAMER
OPTIONAL
JITTER
ATTENUATOR
OPTIONAL
JITTER
ATTENUATOR
TRANSMIT
DIGITAL
TRANSMIT
ANALOG
RECEIVE
DIGITAL
82 of 273
RECEIVE
ANALOG
TTIP
LINE
DRIVER
TRING
RTIP
RRING
DS26524 Quad T1/E1/J1 Transceiver
8.11.5.3
Remote Loopback
The outputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer
are ignored during a remote loopback. This loopback is conceptually shown in Figure 8-18.
Figure 8-18. Remote Loopback
TCLK
TSER
TRANSMIT
TRANSMIT
FRAMER
FRAMER
OPTIONAL JITTER
OPTIONAL
ATTENUATOR
JITTER
ATTENUATOR
RCLK
RCLK
RSER
RSER
8.11.5.4
OPTIONAL
RECEIVE
RECEIVE
FRAMER
FRAMER
JITTER
OPTIONAL
JITTER
ATTENUATOR
ATTENUATOR
TRANSMIT
TRANSMIT
DIGITAL
DIGITAL
TRANSMIT
TRANSMIT
ANALOG
ANALOG
TTIP
LINE
DRIVER
DRIVER
TRING
RECEIVE
DIGITAL
RECEIVE
RECEIVE
ANALOG
RECEIVE
RTIP
DIGITAL
ANALOG
RRING
Dual Loopback
The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer
are looped back to the receiver with the optional jitter attenuator. This loopback is invoked if RLB and LLB are both
set in the LIU Maintenance Control register (LMCR). This loopback is conceptually shown in Figure 8-19.
Figure 8-19. Dual Loopback
TTIP
TCLK
TSER
TRANSMIT
FRAMER
RCLK
RSER
RECEIVE
FRAMER
OPTIONAL
JITTER
ATTENUATOR
OPTIONAL
JITTER
ATTENUATOR
TRANSMIT
DIGITAL
TRANSMIT
ANALOG
RECEIVE
DIGITAL
RECEIVE
ANALOG
LINE
DRIVER
TRING
RTIP
RRING
83 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.12
Bit-Error-Rate Test (BERT) Function
The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns. It is
used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.
Table 8-40 shows the registers related to the configure, control, and status of the BERT.
Table 8-40. Registers Related to BERT Configure, Control, and Status
REGISTER
Global BERT Interrupt Status Register
(GBISR)
Global BERT Interrupt Mask Register
(GBIMR)
Receive Expansion Port Control Register
(RXPC)
Receive BERT Port Bit Suppress Register
(RBPBS)
Receive BERT Port Channel Select
Registers 1 to 4 (RBPCS1:RBPCS4)
Transmit Expansion Port Control Register
(TXPC)
Transmit BERT Port Bit Suppress
Register (TBPBS)
Transmit BERT Port Channel Select
Registers 1 to 4 (TBPCS1:TBPCS4)
BERT Alternating Word Count Rate
Register (BAWC)
BERT Repetitive Pattern Set Register 1
(BRP1)
BERT Repetitive Pattern Set Register 2
(BRP2)
BERT Repetitive Pattern Set Register 3
(BRP3)
BERT Repetitive Pattern Set Register 4
(BRP4)
FRAMER
ADDRESSES
FUNCTION
0FAh
When any of the four BERTs issue an
interrupt, a bit is set.
0FDh
When any of the four BERTs issue an
interrupt, a bit is set.
08Ah
Enable for the receiver BERT.
08Bh
Bit suppression for the receive BERT.
0D4h, 0D5h, 0D6h,
0D7h
Channels to be enabled for the framer to
accept data from the BERT pattern generator.
18Ah
Enable for the transmitter BERT
18Bh
Bit suppression for the transmit BERT
1D4h, 1D5h, 1D6h,
1D7h
Channels to be enabled for the framer to
accept data from the transmit BERT pattern
generator.
1100h
BERT alternating pattern count register.
1101h
BERT repetitive pattern set register 1.
1102h
BERT repetitive pattern set register 2.
1103h
BERT repetitive pattern set register 3.
1104h
BERT repetitive pattern set register 4.
BERT Control Register 1 (BC1)
1105h
Pattern selection and miscellaneous control.
BERT Control Register 2 (BC2)
1106h
BERT bit pattern length control.
BERT Bit Count Register 1 (BBC1)
1107h
BERT Bit Count Register 2 (BBC2)
BERT Bit Count Register 3 (BBC3)
BERT Bit Count Register 4 (BBC4)
BERT Error Count Register 1 (BEC1)
BERT Error Count Register 2 (BEC2)
BERT Error Count Register 3 (BEC3)
1108h
1109h
110Ah
110Bh
110Ch
110Dh
BERT Latched Status Register (BLSR)
110Eh
BERT Status Interrupt Mask Register
(BSIM)
110Fh
BERT bit counter—increments for BERT bit
clocks.
BERT bit counter.
BERT bit counter.
BERT bit counter.
BERT error counter.
BERT error counter.
BERT error counter.
BERT status registers—denotes
synchronization loss and other status.
BERT Interrupt mask.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following framer: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
84 of 273
DS26524 Quad T1/E1/J1 Transceiver
The BERT block can generate and detect the following patterns:
• The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS
• A repetitive pattern from 1 to 32 bits in length
• Alternating (16-bit) words that flip every 1 to 256 words
• Daly pattern
The BERT function must be enabled and configured in the TXPC and RXPC registers for each port. The BERT can
then be assigned on a per-channel basis for both the transmitter and receiver, using the special per-channel
function in the TBPCS1:TBPCS4 and RBCS1:RBCS4 registers. Individual bit positions within the channels can be
suppressed with the TBPBS and RBPBS registers. Using combinations of these functions, the BERT pattern can
be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive
bandwidth assignments are independent of each other.
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver can generate interrupts
on: a change in receive-synchronizer status, receive all zeros, receive all ones, error counter overflow, bit counter
overflow, and bit error detection. Interrupts from each of these events can be masked within the BERT function via
the BERT Status Interrupt Mask register (BSIM). If the software detects that the BERT has reported an event, then
the software must read the BERT Latched Status register (BLSR) to determine which event(s) has occurred.
8.12.1 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a
pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32
bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern
was the repeating 5-bit pattern …01101… (where the rightmost bit is the one sent first and received first), then
BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 should be loaded with 5Ah. For a
pseudorandom pattern, all four registers should be loaded with all ones (i.e., FFh). For an alternating word pattern,
one word should be placed into BRP1 and BRP2 and the other word should be placed into BRP3 and BRP4. For
example, if the DDS stress pattern “7E” is to be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in
BRP3, and 7Eh in BRP4, and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h
followed by 100 bytes of 7Eh to be sent and received.
8.12.2 BERT Error Counter
Once the BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error.
Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO
status bit in the BLSR register.
85 of 273
DS26524 Quad T1/E1/J1 Transceiver
9.
DEVICE REGISTERS
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the
Dallas Semiconductor octal framer product, DS26528 and DS26401.
The registers control functions of the framers, LIU, and BERT within the DS26524. The map is divided into four
framers, followed by four LIUs and four BERTs. Global registers (applicable to all four transceivers and BERTs) are
located within the address space of Framer 1.
The bulk write mode is a special mode to write all four transceivers with one write command (see the GTCR1
register). Figure 9-1 shows the register map.
The register details are provided in the following tables. The framer registers bits are provided for Framer 0, and
address bits A[11:8] determine the framer addressed.
9.1
Register Listings
Table 9-1. Register Address Ranges (in Hex)
CHANNEL
GLOBAL
REGISTERS
RECEIVE
FRAMER
TRANSMIT
FRAMER
LIU
BERT
—
00F0–00FF
—
—
—
—
CH1
—
0000–00EF
0100–01EF
1000–101F
1100–110F
CH2
—
0200–02EF
0300–03EF
1020–103F
1110–111F
CH3
—
0400–04EF
0500–05EF
1040–105F
1120–112F
CH4
—
0600–06EF
0700–07EF
1060–107F
1130–113F
86 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 9-1. Register Memory Map for the DS26524
Adrs = 0000 0000 0000
Framer 1 Rx Regs
Adrs = 0000 1111 0000
Global Registers
Adrs = 0001 0000 0000
Framer 1 Tx Regs
Adrs = 0001 1111 0000
Reserved
Adrs = 0010 0000 0000
240 Regs
240 Regs
000
0EF
0F0
0FF
100
1EF
1F0
1FF
200
Framer 2 Regs
3FF
400
Adrs = 0100 0000 0000
Framer 3 Regs
5FF
600
Adrs = 0101 1111 1111
Adrs = 0110 0000 0000
Framer 4 Regs
7FF
800
Adrs = 0111 1111 1111
Adrs = 1000 0000 0000
Reserved
FFF
1000
Adrs = 01111 1111 1111
Adrs = 10000 0000 0000
LIU Regs
Adrs = 10000 1111 1111
Adrs = 10001 0000 0000
10FF
1100
BERT
Adrs = 10001 0111 1111
117F
Reserved
Adrs = 11111 1111 1111
1FFF
87 of 273
DS26524 Quad T1/E1/J1 Transceiver
9.1.1
Global Register List
Table 9-2. Global Register List
GLOBAL REGISTER LIST
ADDRESS
NAME
DESCRIPTION
R/W
0F0h
GTCR1
Global Transceiver Control Register 1
R/W
0F1h
GFCR
Global Framer Control Register
R/W
0F2h
GTCR2
Global Transceiver Control Register 2
R/W
0F3h
GTCCR
Global Transceiver Clock Control Register
R/W
0F4h
—
0F5h
GLSRR
Global LIU Software Reset Register
R/W
0F6h
GFSRR
Global Framer and BERT Software Reset Register
R/W
0F7h
—
0F8h
IDR
0F9h
Reserved
—
Reserved
—
Device Identification Register
R
GFISR
Global Framer Interrupt Status Register
R
0FAh
GBISR
Global BERT Interrupt Status Register
R
0FBh
GLISR
Global LIU Interrupt Status Register
R
0FCh
GFIMR
Global Framer Interrupt Mask Register
R/W
0FDh
GBIMR
Global BERT Interrupt Mask Register
R/W
0FEh
GLIMR
Global LIU Interrupt Mask Register
R/W
01Fh
—
Reserved
—
Note 1:
Reserved registers should only be written with all zeros.
Note 2:
The global registers are located in the framer address space. The corresponding address space for the other framers is
“Reserved,” and should be initialized with all zeros for proper operation.
88 of 273
DS26524 Quad T1/E1/J1 Transceiver
9.1.2
Framer Register List
Table 9-3. Framer Register List
Note: Only the Framer 1 address is presented here.The same set of register definitions applies for transceiver 2 to 4 in accordance with the
DS26524 map offsets. Transceiver offset is (n - 1) x 200 hex, where n designates the transceiver in question.
FRAMER REGISTER LIST
ADDRESS
NAME
000h–00Fh
010h
011h
012h
013h
—
RHC
RHBSE
RDS0SEL
RSIGC
T1RCR2
E1RSAIMR
T1RBOCC
—
RIDR1
RIDR2
RIDR3
RIDR4
RIDR5
RIDR6
RIDR7
RIDR8
RIDR9
RIDR10
RIDR11
RIDR12
RIDR13
RIDR14
RIDR15
RIDR16
RIDR17
RIDR18
RIDR19
RIDR20
RIDR21
RIDR22
RIDR23
RIDR24
T1RSAOI1
RIDR25
T1RSAOI2
RIDR26
T1RSAOI3
RIDR27
RIDR28
T1RDMWE1
RIDR29
T1RDMWE2
RIDR30
T1RDMWE3
RIDR31
014h
015h
016h–01Fh
020h
021h
022h
023h
024h
025h
026h
027h
028h
029h
02Ah
02Bh
02Ch
02Dh
02Eh
02Fh
030h
031h
032h
033h
034h
035h
036h
037h
038h
039h
03Ah
03B
03C
03Dh
03Eh
DESCRIPTION
Reserved
Receive HDLC Control Register
Receive HDLC Bit Suppress Register
Receive Channel Monitor Select Register
Receive-Signaling Control Register
Receive Control Register 2 (T1 Mode)
Receive Sa-Bit Interrupt Mask Register (E1 Mode)
Receive BOC Control Register (T1 Mode Only)
Reserved
Receive Idle Code Definition Register 1
Receive Idle Code Definition Register 2
Receive Idle Code Definition Register 3
Receive Idle Code Definition Register 4
Receive Idle Code Definition Register 5
Receive Idle Code Definition Register 6
Receive Idle Code Definition Register 7
Receive Idle Code Definition Register 8
Receive Idle Code Definition Register 9
Receive Idle Code Definition Register 10
Receive Idle Code Definition Register 11
Receive Idle Code Definition Register 12
Receive Idle Code Definition Register 13
Receive Idle Code Definition Register 14
Receive Idle Code Definition Register 15
Receive Idle Code Definition Register 16
Receive Idle Code Definition Register 17
Receive Idle Code Definition Register 18
Receive Idle Code Definition Register 19
Receive Idle Code Definition Register 20
Receive Idle Code Definition Register 21
Receive Idle Code Definition Register 22
Receive Idle Code Definition Register 23
Receive Idle Code Definition Register 24
Receive-Signaling All-Ones Insertion Register 1 (T1 Mode Only)
Receive Idle Code Definition Register 25 (E1 Mode)
Receive-Signaling All-Ones Insertion Register 2 (T1 Mode Only)
Receive Idle Code Definition Register 26 (E1 Mode)
Receive-Signaling All-Ones Insertion Register 3 (T1 Mode Only)
Receive Idle Code Definition Register 27 (E1 Mode)
Receive Idle Code Definition Register 28 (E1 Mode)
T1 Receive Digital Milliwatt Enable Register 1 (T1 Mode Only)
Receive Idle Code Definition Register 29 (E1 Mode)
T1 Receive Digital Milliwatt Enable Register 2 (T1 Mode Only)
Receive Idle Code Definition Register 30 (E1 Mode)
T1 Receive Digital Milliwatt Enable Register 3 (T1 Mode Only)
Receive Idle Code Definition Register 31 (E1 Mode)
89 of 273
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS
NAME
03Fh
040h
041h
042h
043h
044h
045h
046h
047h
048h
049h
04Ah
04Bh
04Ch
04Dh
04Eh
04Fh
050h
051h
052h
053h
054h
055h
056h
057h
058h–05Fh
060
061
RIDR32
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
LCVCR1
LCVCR2
PCVCR1
PCVCR2
FOSCR1
FOSCR2
E1EBCR1
E1EBCR2
—
RDS0M
—
T1RFDL
E1RRTS7
T1RBOC
T1RSLC1
E1RAF
T1RSLC2
E1RNAF
T1RSLC3
E1RSiAF
E1RSiNAF
E1RRA
E1RSa4
E1RSa5
E1RSa6
E1RSa7
E1RSa8
SaBITS
Sa6CODE
—
RMMR
RCR1
RCR1
T1RIBCC
E1RCR2
062h
063h
064h
065h
066h
067h
068h
069h
06Ah
06Bh
06Ch
06Dh
06Eh
06Fh
070h–07Fh
080h
081h
082h
DESCRIPTION
Receive Idle Code Definition Register 32 (E1 Mode)
Receive-Signaling Register 1
Receive-Signaling Register 2
Receive-Signaling Register 3
Receive-Signaling Register 4
Receive-Signaling Register 5
Receive-Signaling Register 6
Receive-Signaling Register 7
Receive-Signaling Register 8
Receive-Signaling Register 9
Receive-Signaling Register 10
Receive-Signaling Register 11
Receive-Signaling Register 12
Receive-Signaling Register 13 (E1 Mode only)
Receive-Signaling Register 14 (E1 Mode only)
Receive-Signaling Register 15 (E1 Mode only)
Receive-Signaling Register 16 (E1 Mode only)
Line Code Violation Count Register 1
Line Code Violation Count Register 2
Path Code Violation Count Register 1
Path Code Violation Count Register 2
Frames Out of Sync Count Register 1
Frames Out of Sync Count Register 2
E-Bit Counter 1 (E1 Mode Only)
E-Bit Counter 2 (E1 Mode Only)
Reserved
Receive DS0 Monitor Register
Reserved
Receive FDL Register (T1 Mode)
Receive Real-Time Status Register 7 (E1 Mode)
Receive BOC Register (T1 Mode)
Receive SLC-96 Data Link Register 1 (T1 Mode)
E1 Receive Align Frame Register (E1 Mode)
Receive SLC-96 Data Link Register 2 (T1 Mode)
E1 Receive Non-Align Frame Register (E1 Mode)
Receive SLC-96 Data Link Register 3 (T1 Mode)
E1 Received Si Bits of the Align Frame Register (E1 Mode)
Received Si Bits of the Non-Align Frame Register (E1 Mode)
Received Remote Alarm Register (E1 Mode)
E1 Receive Sa4 Bits Register (E1 Mode Only)
E1 Receive Sa5 Bits Register (E1 Mode Only)
E1 Receive Sa6 Bits Register (E1 Mode Only)
E1 Receive Sa7 Bits Register (E1 Mode Only)
Receive Sa8 Bits Register (E1 Mode Only)
E1 Receive SaX Bits Register
Received Sa6 Codeword Register
Reserved
Receive Master Mode Register
Receive Control Register 1 (T1 Mode)
Receive Control Register 1 (E1 Mode)
Receive In-Band Code Control Register (T1 Mode)
Receive Control Register 2 (E1 Mode)
90 of 273
R/W
—
R
R
R
R
R
R
R
R
R
R
R
R
—
—
—
—
R
R
R
R
R
R
R
R
—
R
—
R
R
R
R
R
R
R
R
R
R
R
R
R
R
—
R/W
R/W
R/W
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS
NAME
DESCRIPTION
R/W
083h
084h
085h
086h
087h
088h
089h
08Ah
08B
08Ch–08Fh
090h
091h
092h
093
094h
095h
RCR3
RIOCR
RESCR
ERCNT
RHFC
RIBOC
T1RSCC
RXPC
RBPBS
—
RLS1
RLS2
RLS3
RLS4
RLS5
—
RLS7
RLS7
—
RSS1
RSS2
RSS3
RSS4
T1RSCD1
T1RSCD2
—
RIIR
RIM1
RIM2
RIM3
RIM3
RIM4
RIM5
—
RIM7
—
RSCSE1
RSCSE2
RSCSE3
RSCSE4
T1RUPCD1
T1RUPCD2
T1RDNCD1
T1RDNCD2
RRTS1
—
RRTS3
RRTS3
—
RRTS5
RHPBA
RHF
Receive Control Register 3
Receive I/O Configuration Register
Receive Elastic Store Control Register
Error-Counter Configuration Register
Receive HDLC FIFO Control Register
Receive Interleave Bus Operation Control Register
In-Band Receive Spare Control Register (T1 Mode Only)
Receive Expansion Port Control Register
Receive BERT Port Bit Suppress Register
Reserved
Receive Latched Status Register 1
Receive Latched Status Register 2
Receive Latched Status Register 3
Receive Latched Status Register 4
Receive Latched Status Register 5 (HDLC)
Reserved
Receive Latched Status Register 7 (T1 Mode)
Receive Latched Status Register 7 (E1 Mode)
Reserved
Receive-Signaling Status Register 1
Receive-Signaling Status Register 2
Receive-Signaling Status Register 3
Receive-Signaling Status Register 4 (E1 Mode Only)
Receive Spare Code Definition Register 1 (T1 Mode Only)
Receive Spare Code Definition Register 2 (T1 Mode Only)
Reserved
Receive Interrupt Information Register
Receive Interrupt Mask Register 1
Receive Interrupt Mask Register 2 (E1 Mode Only)
Receive Interrupt Mask Register 3 (T1 Mode)
Receive Interrupt Mask Register 3 (E1 Mode)
Receive Interrupt Mask Register 4
Receive Interrupt Mask Register 5 (HDLC)
Reserved
Receive Interrupt Mask Register 7 (T1 Mode)
Reserved
Receive-Signaling Change of State Enable Register 1
Receive-Signaling Change of State Enable Register 2
Receive-Signaling Change of State Enable Register 3
Receive-Signaling Change of State Enable Register 4 (E1 Mode Only)
Receive Up Code Definition Register 1 (T1 Mode Only)
Receive Up Code Definition Register 2 (T1 Mode Only)
Receive Down Code Definition Register 1 (T1 Mode Only)
Receive Down Code Definition Register 2 (T1 Mode Only)
Receive Real-Time Status Register 1
Reserved
Receive Real-Time Status Register 3 (T1 Mode)
Receive Real-Time Status Register 3 (E1 Mode)
Reserved
Receive Real-Time Status Register 5 (HDLC)
Receive HDLC Packet Bytes Available Register
Receive HDLC FIFO Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
—
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
0A1h
0A2h
0A3h
0A4h
0A5h
0A6h
0A7h
0A8h
0A9h
0AAh
0ABh
0ACh
0ADh
0AEh
0AFh
0B0h
0B1h
0B2h
0B3h
0B4h
0B5h
0B6h
91 of 273
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R
—
R
—
R
R
R
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS
NAME
0B7h–0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h–0EFh
—
RBCS1
RBCS2
RBCS3
RBCS4
RCBR1
RCBR2
RCBR3
RCBR4
RSI1
RSI2
RSI3
RSI4
RGCCS1
RGCCS2
RGCCS3
RGCCS4
RCICE1
RCICE2
RCICE3
RCICE4
RBPCS1
RBPCS2
RBPCS3
RBPCS4
—
Global
Registers
(Section 9.3)
—
THC1
THBSE
—
THC2
E1TSACR
—
SSIE1
SSIE2
SSIE3
SSIE4
—
TIDR1
TIDR2
TIDR3
TIDR4
TIDR5
TIDR6
TIDR7
TIDR8
TIDR9
TIDR10
TIDR11
0F0h–0FFh
100h–10Fh
110h
111h
112h
113h
114h
115h–117h
118h
119h
11Ah
11Bh
11Ch–11Fh
120h
121h
122h
123h
124h
125h
126h
127h
128h
129h
12Ah
DESCRIPTION
R/W
Reserved
Receive Blank Channel Select Register 1
Receive Blank Channel Select Register 2
Receive Blank Channel Select Register 3
Receive Blank Channel Select Register 4 (E1 Mode Only)
Receive Channel Blocking Register 1
Receive Channel Blocking Register 2
Receive Channel Blocking Register 3
Receive Channel Blocking Register 4 (E1 Mode Only)
Receive-Signaling Reinsertion Enable Register 1
Receive-Signaling Reinsertion Enable Register 2
Receive-Signaling Reinsertion Enable Register 3
Receive-Signaling Reinsertion Enable Register 4 (E1 Mode Only)
Receive Gapped Clock Channel Select Register 1
Receive Gapped Clock Channel Select Register 2
Receive Gapped Clock Channel Select Register 3
Receive Gapped Clock Channel Select Register (E1 Mode Only)
Receive Channel Idle Code Enable Register 1
Receive Channel Idle Code Enable Register 2
Receive Channel Idle Code Enable Register 3
Receive Channel Idle Code Enable Register 4 (E1 Mode Only)
Receive BERT Port Channel Select Register 1
Receive BERT Port Channel Select Register 2
Receive BERT Port Channel Select Register 3
Receive BERT Port Channel Select Register (E1 Mode Only)
Reserved
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
See the Global Register list in Table 9-2. Note that this space is
“Reserved” in Framers 2 to 4.
R/W
Reserved
Transmit HDLC Control Register 1
Transmit HDLC Bit Suppress Register
Reserved
Transmit HDLC Control Register 2
E1 Transmit Sa-Bit Control Register (E1 Mode)
Reserved
Software-Signaling Insertion Enable Register 1
Software-Signaling Insertion Enable Register 2
Software-Signaling Insertion Enable Register 3
Software-Signaling Insertion Enable Register 4 (E1 Mode Only)
Reserved
Transmit Idle Code Definition Register 1
Transmit Idle Code Definition Register 2
Transmit Idle Code Definition Register 3
Transmit Idle Code Definition Register 4
Transmit Idle Code Definition Register 5
Transmit Idle Code Definition Register 6
Transmit Idle Code Definition Register 7
Transmit Idle Code Definition Register 8
Transmit Idle Code Definition Register 9
Transmit Idle Code Definition Register 10
Transmit Idle Code Definition Register 11
—
R/W
R/W
—
R/W
R/W
—
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
92 of 273
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS
NAME
12Bh
12Ch
12Dh
12Eh
12Fh
130h
131h
132h
133h
134h
135h
136h
137h
138h
139h
13Ah
13Bh
13Ch
13Dh
13Eh
13Fh
140h
141h
142h
143h
144h
145h
146h
147h
148h
149h
14Ah
14Bh
14Ch
14Dh
14Eh
14Fh
150h
151h
152h
153h
154h–161h
162h
163h
TIDR12
TIDR13
TIDR14
TIDR15
TIDR16
TIDR17
TIDR18
TIDR19
TIDR20
TIDR21
TIDR22
TIDR23
TIDR24
TIDR25
TIDR26
TIDR27
TIDR28
TIDR29
TIDR30
TIDR31
TIDR32
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
TCICE1
TCICE2
TCICE3
TCICE4
—
T1TFDL
T1TBOC
T1TSLC1
E1TAF
T1TSLC2
E1TNAF
T1TSLC3
E1TSiAF
E1TSiNAF
E1TRA
164h
165h
166h
167h
168h
DESCRIPTION
Transmit Idle Code Definition Register 12
Transmit Idle Code Definition Register 13
Transmit Idle Code Definition Register 14
Transmit Idle Code Definition Register 15
Transmit Idle Code Definition Register 16
Transmit Idle Code Definition Register 17
Transmit Idle Code Definition Register 18
Transmit Idle Code Definition Register 19
Transmit Idle Code Definition Register 20
Transmit Idle Code Definition Register 21
Transmit Idle Code Definition Register 22
Transmit Idle Code Definition Register 23
Transmit Idle Code Definition Register 24
Transmit Idle Code Definition Register 25 (E1 Mode Only)
Transmit Idle Code Definition Register 26 (E1 Mode Only)
Transmit Idle Code Definition Register 27 (E1 Mode Only)
Transmit Idle Code Definition Register 28 (E1 Mode Only)
Transmit Idle Code Definition Register 29 (E1 Mode Only)
Transmit Idle Code Definition Register 30 (E1 Mode Only)
Transmit Idle Code Definition Register 31 (E1 Mode Only)
Transmit Idle Code Definition Register 32 (E1 Mode Only)
Transmit-Signaling Register 1
Transmit-Signaling Register 2
Transmit-Signaling Register 3
Transmit-Signaling Register 4
Transmit-Signaling Register 5
Transmit-Signaling Register 6
Transmit-Signaling Register 7
Transmit-Signaling Register 8
Transmit-Signaling Register 9
Transmit-Signaling Register 10
Transmit-Signaling Register 11
Transmit-Signaling Register 12
Transmit-Signaling Register 13
Transmit-Signaling Register 14
Transmit-Signaling Register 15
Transmit-Signaling Register 16
Transmit Channel Idle Code Enable Register 1
Transmit Channel Idle Code Enable Register 2
Transmit Channel Idle Code Enable Register 3
Transmit Channel Idle Code Enable Register 4 (E1 Mode Only)
Reserved
Transmit FDL Register (T1 Mode Only)
Transmit BOC Register (T1 Mode Only)
Transmit SLC-96 Data Link Register 1 (T1 Mode)
Transmit Align Frame Register (E1 Mode)
Transmit SLC-96 Data Link Register 2 (T1 Mode)
Transmit Non-Align Frame Register (E1 Mode)
Transmit SLC-96 Data Link Register 3 (T1 Mode)
Transmit Si Bits of the Align Frame Register (E1 Mode)
Transmit Si Bits of the Non-Align Frame Register (E1 Mode Only)
Transmit Remote Alarm Register (E1 Mode)
93 of 273
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS
NAME
169h
16Ah
16Bh
16Ch
16Dh
16Eh–17Fh
180h
E1TSa4
E1TSa5
E1TSa6
E1TSa7
E1RSa8
—
TMMR
TCR1
TCR1
TCR2
TCR2
TCR3
TIOCR
TESCR
TCR4
THFC
TIBOC
TDS0SEL
TXPC
TBPBS
—
TSYNCC
—
TLS1
TLS2
TLS3
—
TIIR
TIM1
TIM2
TIM3
—
T1TCD1
T1TCD2
—
TRTS2
—
TFBA
THF
—
TDS0M
—
TBCS1
TBCS2
TBCS3
TBCS4
TCBR1
TCBR2
TCBR3
TCBR4
THSCS1
THSCS2
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch–18Dh
18Eh
18F
190h
191h
192h
193h–19Eh
19Fh
1A0h
1A1h
1A2h
1A3h–1ABh
1ACh
1ADh
1AEh–1B0h
1B1h
1B2h
1B3h
1B4h
1B5h–1BhA
1BBh
1BCh–1BFh
1C0h
1C1h
1C2h
1C3h
1C4h
1C5h
1C6h
1C7h
1C8h
1C9h
DESCRIPTION
Transmit Sa4 Bits Register (E1 Mode Only)
Transmit Sa5 Bits Register (E1 Mode Only)
Transmit Sa6 Bits Register (E1 Mode Only)
Transmit Sa7 Bits Register (E1 Mode Only)
Receive Sa8 Bits Register (E1 Mode Only)
Reserved
Transmit Master Mode Register
Transmit Control Register 1 (T1 Mode)
Transmit Control Register 1 (E1 Mode)
Transmit Control Register 2 (T1 Mode)
Transmit Control Register 2 (E1 Mode)
Transmit Control Register 3
Transmit I/O Configuration Register
Transmit Elastic Store Control Register
Transmit Control Register 4 (T1 Mode Only)
Transmit HDLC FIFO Control Register
Transmit Interleave Bus Operation Control Register
Transmit DS0 Channel Monitor Select Register
Transmit Expansion Port Control Register
Transmit BERT Port Bit Suppress Register
Reserved
Transmit Synchronizer Control Register
Reserved
Transmit Latched Status Register 1
Transmit Latched Status Register 2 (HDLC)
Transmit Latched Status Register 3 (Synchronizer)
Reserved
Transmit Interrupt Information Register
Transmit Interrupt Mask Register 1
Transmit Interrupt Mask Register 2 (HDLC)
Transmit Interrupt Mask Register 3 (Synchronizer)
Reserved
Transmit Code Definition Register 1 (T1 Mode Only)
Transmit Code Definition Register 2 (T1 Mode Only)
Reserved
Transmit Real-Time Status Register 2 (HDLC)
Reserved
Transmit HDLC FIFO Buffer Available
Transmit HDLC FIFO Register
Reserved
Transmit DS0 Monitor Register
Reserved
Transmit Blank Channel Select Register 1
Transmit Blank Channel Select Register 2
Transmit Blank Channel Select Register 3
Transmit Blank Channel Select Register 4 (E1 Mode Only)
Transmit Channel Blocking Register 1
Transmit Channel Blocking Register 2
Transmit Channel Blocking Register 3
Transmit Channel Blocking Register 4 (E1 Mode Only)
Transmit Hardware-Signaling Channel Select Register 1
Transmit Hardware-Signaling Channel Select Register 2
94 of 273
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
—
R/W
R/W
—
R
—
R
W
—
R
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS
NAME
1CAh
THSCS3
1CBh
THSCS4
1CCh
1CDh
1CEh
1CFh
1D0h
1D1h
1D2h
1D3h
1D4h
1D5h
1D6h
1D7h
1D8h–1FFh
TGCCS1
TGCCS2
TGCCS3
TGCCS4
PCL1
PCL2
PCL3
PCL4
TBPCS1
TBPCS2
TBPCS3
TBPCS4
—
DESCRIPTION
Transmit Hardware-Signaling Channel Select Register 3
Transmit Hardware-Signaling Channel Select Register 4 (E1 Mode
Only)
Transmit Gapped-Clock Channel Select Register 1
Transmit Gapped-Clock Channel Select Register 2
Transmit Gapped-Clock Channel Select Register 3
Transmit Gapped-Clock Channel Select Register 4 (E1 Mode Only)
Per-Channel Loopback Enable Register 1
Per-Channel Loopback Enable Register 2
Per-Channel Loopback Enable Register 3
Per-Channel Loopback Enable Register 4 (E1 Mode Only)
Transmit BERT Port Channel Select Register 1
Transmit BERT Port Channel Select Register 2
Transmit BERT Port Channel Select Register 3
Transmit BERT Port Channel Select Register 4 (E1 Mode Only)
Reserved
95 of 273
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
DS26524 Quad T1/E1/J1 Transceiver
9.1.3
LIU and BERT Register List
Table 9-4. LIU Register List
LIU REGISTER LIST
ADDRESS
NAME
DESCRIPTION
1000h
LTRCR
LIU Transmit Receive Control Register
1001h
LTITSR
LIU Transmit Impedance and Pulse Shape Selection Register
1002h
LMCR
LIU Maintenance Control Register
1003h
LRSR
LIU Real Status Register
1004h
LSIMR
LIU Status Interrupt Mask Register
1005h
LLSR
LIU Latched Status Register
1006h
LRSL
LIU Receive Signal Level Register
1007
LRISMR
1008h–101Fh
—
LIU Receive Impedance and Sensitivity Monitor Register
Reserved
Table 9-5. BERT Register List
BERT REGISTER LIST
ADDRESS
NAME
DESCRIPTION
1100h
BAWC
BERT Alternating Word Count Rate Register
1101h
BRP1
BERT Repetitive Pattern Set Register 1
1102h
BRP2
BERT Repetitive Pattern Set Register 2
1103h
BRP3
BERT Repetitive Pattern Set Register 3
1104h
BRP4
BERT Repetitive Pattern Set Register 4
1105h
BC1
BERT Control Register 1
1106h
BC2
BERT Control Register 2
1107h
BBC1
BERT Bit Count Register 1
1108h
BBC2
BERT Bit Count Register 2
1109h
BBC3
BERT Bit Count Register 3
110Ah
BBC4
BERT Bit Count Register 4
110Bh
BEC1
BERT Error Count Register 1
110Ch
BEC2
BERT Error Count Register 2
110Dh
BEC3
BERT Error Count Register 3
110Eh
BLSR
BERT Latched Status Register
110Fh
BSIM
BERT Status Interrupt Mask Register
96 of 273
DS26524 Quad T1/E1/J1 Transceiver
9.2
Register Bit Maps
9.2.1
Global Register Bit Map
Table 9-6. Global Register Bit Map
ADDR
0F0h
0F1h
0F2h
0F3h
0F4h
0F5h
0F6h
0F7h
0F8h
0F9h
0Fah
0FBh
0FCh
0FDh
0FEh
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
GTCR1
—
—
RLOFLTS
GIBO
—
GFCR
IBOMS1
IBOMS0
BPCLK1
BPCLK0 RFLOSSFS
GTCR2
—
—
—
—
—
GTCCR BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL
—
—
—
—
—
—
GLSRR
—
—
—
LSRST4
—
GFSRR
—
—
—
FSRST4
—
—
—
—
—
—
—
IDR
ID7
ID6
ID5
ID4
ID3
GFISR
—
—
—
—
FIS4
GBISR
—
—
—
—
BIS4
GLISR
—
—
—
—
LIS4
GFIMR
—
—
—
—
FIM4
GBIMR
—
—
—
—
BIM4
GLIMR
—
—
—
—
LIM4
97 of 273
BIT 2
BWE
RFMSS
LOSS
FREQSEL
—
LSRST3
FSRST3
—
ID2
FIS3
BIS3
LIS3
FIM3
BIM3
LIM3
BIT 1
GCLE
TCBCS
TSSYNCIOSEL
MPS1
—
LSRST2
FSRST2
—
ID1
FIS2
BIS2
LIS2
FIM2
BIM2
LIM2
BIT 0
GIPI
RCBCS
—
MPS0
—
LSRST1
FSRST1
—
ID0
FIS1
BIS1
LIS1
FIM1
BIM1
LIM1
DS26524 Quad T1/E1/J1 Transceiver
9.2.2
Framer Register Bit Map
Table 9-7 contains the framer registers of the DS26524. Some registers have dual functionality based on the
selection of T1/J1 or E1 operating mode in the RMMR and TMMR registers. These dual-function registers are
shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is
the bit functionality in E1 mode, in italics. Bits that are not used for an operating mode are noted with a dash “—“.
When there is only one set of bit definitions listed for a register, the bit functionality does not change with respect to
the selection of T1/J1 or E1 mode. All registers not listed are reserved and should be initialized with a value of 00h
for proper operation. The addresses shown are for Framer 1. Addresses for Framer 2 to 4 can be calculated using
the following formula: Address for Framer N = (Framer 1 address + (N - 1) x 200h).
Table 9-7. Framer Register Bit Map
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
010h
011h
012h
RHC
RHBSE
RDS0SEL
013h
RSIGC
T1RCR2
RCRCD
BSE8
—
—
—
—
RHR
BSE7
—
—
—
—
RHMS
BSE6
—
—
—
—
RHCS4
BSE5
RCM4
RFSA1
CASMS
RSLC96
RHCS3
BSE4
RCM3
—
—
OOF2
RHCS2
BSE3
RCM2
RSFF
RSFF
OOF1
RHCS1
BSE2
RCM1
RSFE
RSFE
RAIIE
RHCS0
BSE1
RCM0
RSIE
RSEI
RD4RM
E1RSAIMR
—
—
—
RSa4IM
RSa5IM
RSa6IM
RSa7IM
RSa8IM
015h
T1RBOCC
RBR
—
RBD1
RBD0
—
RBF1
RBF0
—
020h
RIDR1
C7
C6
C5
C4
C3
C2
C1
C0
021h
022h
023h
024h
025h
026h
027h
028h
029h
02Ah
02Bh
02Ch
02Dh
02Eh
02Fh
030h
031h
032h
033h
034h
035h
036h
037h
RIDR2
RIDR3
RIDR4
RIDR5
RIDR6
RIDR7
RIDR8
RIDR9
RIDR10
RIDR11
RIDR12
RIDR13
RIDR14
RIDR15
RIDR16
RIDR17
RIDR18
RIDR19
RIDR20
RIDR21
RIDR22
RIDR23
RIDR24
T1RSAOI1
RIDR25
T1RSAOI2
RIDR26
T1RSAOI3
RIDR27
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
CH8
C7
CH16
C7
CH24
C7
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
CH7
C6
CH15
C6
CH23
C6
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
CH6
C5
CH14
C5
CH22
C5
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
CH5
C4
CH13
C4
CH21
C4
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
CH4
C3
CH12
C3
CH20
C3
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
CH3
C2
CH11
C2
CH19
C2
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
CH2
C1
CH10
C1
CH18
C1
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
CH1
C0
CH9
C0
CH17
C0
014h
038h
039h
03Ah
98 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
03Bh
RIDR28
03Ch
03Dh
03Eh
T1RDMWE1
RIDR29
T1RDMWE2
RIDR30
T1RDMWE3
RIDR31
03Fh
RIDR32
040h
RS1
041h
RS2
042h
RS3
043h
RS4
044h
RS5
045h
RS6
046h
RS7
047h
RS8
048h
RS9
049h
RS10
04Ah
RS11
04Bh
RS12
04Ch
RS13
04Dh
RS14
04Eh
RS15
04Fh
RS16
050h
051h
052h
053h
054h
055h
LCVCR1
LCVCR2
PCVCR1
PCVCR2
FOSCR1
FOSCR2
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
—
—
—
—
—
—
—
—
C7
C6
C5
C4
C3
C2
C1
C0
CH8
C7
CH16
C7
CH24
C7
—
C7
CH1-A
0
CH2-A
CH7
C6
CH15
C6
CH23
C6
—
C6
CH1-B
0
CH2-B
CH6
C5
CH14
C5
CH22
C5
—
C5
CH1-C
0
CH2-C
CH5
C4
CH13
C4
CH21
C4
—
C4
CH1-D
0
CH2-D
CH4
C3
CH12
C3
CH20
C3
—
C3
CH13-A
X
CH14-A
CH3
C2
CH11
C2
CH19
C2
—
C2
CH13-B
Y
CH14-B
CH2
C1
CH10
C1
CH18
C1
—
C1
CH13-C
X
CH14-C
CH1
C0
CH9
C0
CH17
C0
—
C0
CH13-D
X
CH14-D
CH1-A
CH1-B
CH1-C
CH1-D
CH16-A
CH16-B
CH16-C
CH16-D
CH3-A
CH3-B
CH3-C
CH3-D
CH15-A
CH15-B
CH15-C
CH15-D
CH2-A
CH2-B
CH2-C
CH2-D
CH17-A
CH17-B
CH17-C
CH17-D
CH4-A
CH4-B
CH4-C
CH4-D
CH16-A
CH16-B
CH16-C
CH16-D
CH3-A
CH3-B
CH3-C
CH3-D
CH18-A
CH18-B
CH18-C
CH18-D
CH5-A
CH5-B
CH5-C
CH5-D
CH17-A
CH17-B
CH17-C
CH17-D
CH4-A
CH4-B
CH4-C
CH4-D
CH19-A
CH19-B
CH19-C
CH19-D
CH6-A
CH5-A
CH7-A
CH6-A
CH6-B
CH5-B
CH7-B
CH6-B
CH6-C
CH5-C
CH7-C
CH6-C
CH6-D
CH5-D
CH7-D
CH6-D
CH18-A
CH20-A
CH19-A
CH21-A
CH18-B
CH20-B
CH19-B
CH21-B
CH18-C
CH20-C
CH19-C
CH21-C
CH18-D
CH20-D
CH19-D
CH21-D
CH8-A
CH8-B
CH8-C
CH8-D
CH20-A
CH20-B
CH20-C
CH20-D
CH7-A
CH9-A
CH8-A
CH10-A
CH9-A
CH11-A
CH10-A
CH12-A
CH11-A
CH7-B
CH9-B
CH8-B
CH10-B
CH9-B
CH11-B
CH10-B
CH12-B
CH11-B
CH7-C
CH9-C
CH8-C
CH10-C
CH9-C
CH11-C
CH10-C
CH12-C
CH11-C
CH7-D
CH9-D
CH8-D
CH10-D
CH9-D
CH11-D
CH10-D
CH12-D
CH11-D
CH22-A
CH21-A
CH23-A
CH22-A
CH24-A
CH23-A
CH25-A
CH24-A
CH26-A
CH22-B
CH21-B
CH23-B
CH22-B
CH24-B
CH23-B
CH25-B
CH24-B
CH26-B
CH22-C
CH21-C
CH23-C
CH22-C
CH24-C
CH23-C
CH25-C
CH24-C
CH26-C
CH22-D
CH21-D
CH23-D
CH22-D
CH24-D
CH23-D
CH25-D
CH24-D
CH26-D
—
—
—
—
—
—
—
—
CH12-A
—
CH12-B
—
CH12-C
—
CH12-D
—
CH27-A
—
CH27-B
—
CH27-C
—
CH27-D
—
CH13-A
—
CH13-B
—
CH13-C
—
CH13-D
—
CH28-A
—
CH28-B
—
CH28-C
—
CH28-D
—
CH14-A
—
CH14-B
—
CH14-C
—
CH14-D
—
CH29-A
—
CH29-B
—
CH29-C
—
CH29-D
—
CH15-A
LCVC15
LCVC7
PCVC15
PCVC7
FOS15
FOS7
CH15-B
LCVC14
LCVC6
PCVC14
PCVC6
FOS14
FOS6
CH15-C
LCVC13
LCVC5
PCVC13
PCVC5
FOS13
FOS5
CH15-D
LCVC12
LCVC4
PCVC12
PCVC4
FOS12
FOS4
CH30-A
LCVC11
LCVC3
PCVC11
PCVC3
FOS11
FOS3
CH30-B
LCVC10
LCVC2
PCVC10
PCVC2
FOS10
FOS2
CH30-C
LCVC9
LCVC1
PCVC9
PCVC1
FOS9
FOS1
CH30-D
LCCV8
LCVC0
PCVC8
PCVC0
FOS8
FOS0
99 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
056h
057h
060h
061h
E1EBCR1
E1EBCR2
RDS0M
—
EB15
EB7
B1
—
EB14
EB6
B2
—
EB13
EB5
B3
—
EB12
EB4
B4
—
EB11
EB3
B5
—
EB10
EB2
B6
—
EB9
EB1
B7
—
EB8
EB0
B8
—
T1RFDL
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
E1RRTS7
CSC5
CSC4
CSC3
CSC2
CSC0
CRC4SA
CASSA
FASSA
—
C8
Si
M2
Si
S=1
SiF14
SiF15
RRAF15
RSa4F15
RSa5F15
RSa6F15
RSa7F15
RSa8F15
—
—
FRM_EN
SYNCT
—
—
RSa8S
IDF
—
C7
0
M1
1
S4
SiF12
SiF13
RRAF13
RSa4F13
RSa5F13
RSa6F13
RSa7F13
RSa8F13
—
—
083h
T1RBOC
T1RSLC1
E1RAF
T1RSLC2
E1RNAF
T1RSLC3
E1RSiAF
E1RSiNAF
E1RRA
E1RSa4
E1RSa5
E1RSa6
E1RSa7
E1RSa8
SaBITS
Sa6CODE
RMMR
RCR1 (T1)
RCR1 (E1)
T1RIBCC
E1RCR2
RCR3
RB8ZS
RHDB3
—
RSa7S
—
RBOC5
C6
0
S=0
A
S3
SiF10
SiF11
RRAF11
RSa4F11
RSa5F11
RSa6F11
RSa7F11
RSa8F11
—
—
—
RFM
RSIGM
RUP2
RSa6S
RSERC
RBOC4
C5
1
S=1
Sa4
S2
SiF8
SiF9
RRAF9
RSa4F9
RSa5F9
RSa6F9
RSa7F9
RSa8F9
Sa4
—
—
ARC
RG802
RUP1
RSa5S
—
RBOC3
C4
1
S=0
Sa5
S1
SiF6
SiF7
RRAF7
RSa4F7
RSa5F7
RSa6F7
RSa7F7
RSa8F7
Sa5
Sa6n
—
SYNCC
RCRC4
RUP0
RSa4S
—
RBOC2
C3
0
C11
Sa6
A2
SiF4
SiF5
RRAF5
RSa4F5
RSa5F5
RSa6F5
RSa7F5
RSa8F5
Sa6
Sa6n
—
RJC
FRC
RDN2
—
—
RBOC1
C2
1
C10
Sa7
A1
SiF2
SiF3
RRAF3
RSa4F3
RSa5F3
RSa6F3
RSa7F3
RSa8F3
Sa7
Sa6n
SFTRST
SYNCE
SYNCE
RDN1
—
PLB
RBOC0
C1
1
C9
Sa8
M3
SiF0
SiF1
RRAF1
RSa4F1
RSa5F1
RSa6F1
RSa7F1
RSa8F1
Sa8
Sa6n
T1/E1
RESYNC
RESYNC
RDN0
RLOSA
FLB
084h
RIOCR
RCLKINV
RSYNCINV
H100EN
RSCLKM
RSMS
RSIO
RSMS2
RSMS1
RCLKINV
RSYNCINV
H100EN
RSCLKM
—
RSIO
RSMS2
RSMS1
085h
RESCR
086h
ERCNT
087h
088h
089h
RHFC
RIBOC
T1RSCC
08Ah
RXPC
RDATFMT
1SECS
1SECS
—
—
—
—
RGCLKEN
MCUS
MCUS
—
IBS1
—
—
—
MECU
MECU
—
IBS0
—
—
RSZS
ECUS
ECUS
—
IBOSEL
—
—
RESALGN
EAMS
EAMS
—
IBOEN
—
—
RESR
FSBE
—
—
DA2
RSC2
RBPDIR
RESMDM
MOSCRF
—
RFHWM1
DA1
RSC1
RBPFUS
RESE
LCVCRF
LCVCRF
RFHWM0
DA0
RSC0
RBPEN
—
—
—
—
—
RBPDIR
—
RBPEN
08Bh
RBPBS
BPBSE8
BPBSE7
BPBSE6
BPBSE5
BPBSE4
BPBSE3
BPBSE2
BPBSE1
RLS1
RRAIC
RAISC
RLOSC
RLOFC
RRAID
RAISD
RLOSD
RLOFD
RLS2 (T1)
RPDV
—
COFA
8ZD
16ZD
SEFE
B8ZS
FBE
RLS2 (E1)
—
CRCRC
CASRC
FASRC
RSA1
RSA0
RCMF
RAF
RLS3 (T1)
LORCC
LSPC
LDNC
LUPC
LORCD
LSPD
LDND
LUPD
RLS3 (E1)
LORCC
—
V52LNKC
RDMAC
LORCD
—
V52LNKD
RDMAD
RLS4
RESF
RESEM
RSLIP
—
RSCOS
1SEC
TIMER
RMF
062h
063h
064h
065h
066h
067h
068h
069h
06Ah
06Bh
06Ch
06Dh
06Eh
06Fh
080h
081h
082h
090h
091h
092h
093h
094h
096h
INIT_DONE
RLS5
—
—
ROVR
RHOBT
RPE
RPS
RHWMS
RNES
RLS7 (T1)
—
—
RRAI-CI
RAIS-CI
RSLC96
RFDLF
BC
BD
RLS7 (E1)
—
—
—
—
—
—
Sa6CD
SaXCD
100 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
097h
098h
099h
09Ah
—
RSS1
RSS2
RSS3
09Bh
RSS4
09Ch
T1RSCD1
09Dh
T1RSCD2
—
CH8
CH16
CH24
—
CH32
C7
—
C7
—
CH7
CH15
CH23
—
CH31
C6
—
C6
—
CH6
CH14
CH22
—
CH30
C5
—
C5
—
CH5
CH13
CH21
—
CH29
C4
—
C4
—
CH4
CH12
CH20
—
CH28
C3
—
C3
—
CH3
CH11
CH19
—
CH27
C2
—
C2
—
CH2
CH10
CH18
—
CH26
C1
—
C1
—
CH1
CH9
CH17
—
CH25
C0
—
C0
09Fh
0A0h
RIIR
RIM1
0A1h
RIM2
—
—
RRAIC
—
—
LORCC
LORCC
RESF
—
—
—
RLS7
RAISC
—
—
LSPC
—
RESEM
—
—
CH8
CH16
CH24
CH7
CH15
CH23
—
RLS6*
RLOSC
—
—
LDNC
V52LNKC
RSLIP
ROVR
RRAI-CI
—
CH6
CH14
CH22
—
RLS5
RLOFC
—
—
LUPC
RDMAC
—
RHOBT
RAIS-CI
—
CH5
CH13
CH21
—
RLS4
RRAID
—
RSA1
LORCD
LORCD
RSCOS
RPE
RSLC96
—
CH4
CH12
CH20
—
RLS3
RAISD
—
RSA0
LSPD
—
1SEC
RPS
RFDLF
—
CH3
CH11
CH19
—
RLS2**
RLOSD
—
RCMF
LDND
V52LNKD
TIMER
RHWMS
BC
Sa6CD
CH2
CH10
CH18
—
RLS1
RLOFD
—
RAF
LUPD
RDMAD
RMF
RNES
BD
SaXCD
CH1
CH9
CH17
0A8h
0A9h
0AAh
RIM3 (T1)
RIM3 (E1)
RIM4
RIM5
RIM7 (T1)
RIM7 (E1)
RSCSE1
RSCSE2
RSCSE3
0Abh
RSCSE4
0ACh
T1RUPCD1
0ADh
T1RUPCD2
0AEh
T1RDNCD1
0AFh
T1RDNCD2
0B0h
0B4h
0B5h
0B6h
0C0h
0C1h
0C2h
RRTS1
RRTS3 (T1)
RRTS3 (E1)
RRTS5
RHPBA
RHF
RBCS1
RBCS2
RBCS3
0C3h
RBCS4
0C4h
0C5h
0C6h
RCBR1
RCBR2
RCBR3
0C7h
RCBR4
0C8h
RSI1
0A2h
0A3h
0A4h
0A6h
0B2h
—
—
—
—
—
—
—
—
CH32
C7
—
C7
—
C7
—
C7
—
—
—
—
—
MS
RHD7
CH8
CH16
CH24
—
CH32
CH8
CH16
CH24
—
CH32
CH8
CH31
C6
—
C6
—
C6
—
C6
—
—
—
—
PS2
RPBA6
RHD6
CH7
CH15
CH23
—
CH31
CH7
CH15
CH23
—
CH31
CH7
CH30
C5
—
C5
—
C5
—
C5
—
—
—
—
PS1
RPBA5
RHD5
CH6
CH14
CH22
—
CH30
CH6
CH14
CH22
—
CH30
CH6
CH29
C4
—
C4
—
C4
—
C4
—
—
—
—
PS0
RPBA4
RHD4
CH5
CH13
CH21
—
CH29
CH5
CH13
CH21
—
CH29
CH5
CH28
C3
—
C3
—
C3
—
C3
—
RRAI
LORC
LORC
—
RPBA3
RHD3
CH4
CH12
CH20
—
CH28
CH4
CH12
CH20
—
CH28
CH4
CH27
C2
—
C2
—
C2
—
C2
—
RAIS
LSP
—
—
RPBA2
RHD2
CH3
CH11
CH19
—
CH27
CH3
CH11
CH19
—
CH27
CH3
CH26
C1
—
C1
—
C1
—
C1
—
RLOS
LDN
V52LNK
RHWM
RPBA1
RHD1
CH2
CH10
CH18
—
CH26
CH2
CH10
CH18
—
CH26
CH2
CH25
C0
—
C0
—
C0
—
C0
—
RLOF
LUP
RDMA
RNE
RPBA0
RHD0
CH1
CH9
CH17
—
CH25
CH1
CH9
CH17
—
CH25(F-bit)
CH1
101 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0C9h
0CAh
RSI2
RSI3
0CBh
RSI4
0CCh
0CDh
0CEh
RGCCS1
RGCCS2
RGCCS3
0CFh
RGCCS4
0D0h
0D1h
0D2h
RCICE1
RCICE2
RCICE3
0D3h
RCICE4
CH16
CH24
—
CH32
CH8
CH16
CH24
—
CH32
CH8
CH16
CH24
—
CH15
CH23
—
CH31
CH7
CH15
CH23
—
CH31
CH7
CH15
CH23
—
CH14
CH22
—
CH30
CH6
CH14
CH22
—
CH30
CH6
CH14
CH22
—
CH13
CH21
—
CH29
CH5
CH13
CH21
—
CH29
CH5
CH13
CH21
—
CH12
CH200
—
CH28
CH4
CH12
CH20
—
CH28
CH4
CH12
CH20
—
CH11
CH19
—
CH27
CH3
CH11
CH19
—
CH27
CH3
CH11
CH19
—
CH10
CH18
—
CH26
CH2
CH10
CH18
—
CH26
CH2
CH10
CH18
—
CH9
CH17
—
CH25
CH1
CH9
CH17
—
CH25(F-bit)
CH1
CH9
CH17
—
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0D4h
0D5h
0D6h
RBPCS1
RBPCS2
RBPCS3
0D7h
RBPCS4
CH8
CH16
CH24
—
CH7
CH15
CH23
—
CH6
CH14
CH22
—
CH5
CH13
CH21
—
CH4
CH12
CH20
—
CH3
CH11
CH19
—
CH2
CH10
CH18
—
CH1
CH9
CH17
—
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
110h
111h
THC1
THBSE
113h
THC2
NOFS
TBSE8
TABT
TEOML
TBSE7
SBOC
THR
TBSE6
THCEN
THMS
TBSE5
THCS4
TFS
TBSE4
THCS3
TEOM
TBSE3
THCS2
TZSD
TBSE2
THCS1
TCRCD
TBSE1
THCS0
TABT
—
THCEN
THCS4
THCS3
THCS2
THCS1
THCS0
118h
119h
11Ah
SSIE1
SSIE2
SSIE3
11Bh
SSIE4
CH8
CH16
CH24
—
CH7
CH15
CH23
—
CH6
CH14
CH22
—
CH5
CH13
CH21
—
CH4
CH12
CH20
—
CH3
CH11
CH19
—
CH2
CH10
CH18
—
CH1
CH9
CH17
—
120h
121h
122h
123h
124h
125h
126h
127h
128h
129h
12Ah
12Bh
12Ch
12Dh
12Eh
12Fh
130h
131h
132h
133h
134h
TIDR1
TIDR2
TIDR3
TIDR4
TIDR5
TIDR6
TIDR7
TIDR8
TIDR9
TIDR10
TIDR11
TIDR12
TIDR13
TIDR14
TIDR15
TIDR16
TIDR17
TIDR18
TIDR19
TIDR20
TIDR21
CH32
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
C7
CH31
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
CH30
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
CH29
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
C4
CH28
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
C3
CH27
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
CH26
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
CH25
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
102 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
135h
136h
137h
TIDR22
TIDR23
TIDR24
C7
C7
C7
C6
C6
C6
C5
C5
C5
C4
C4
C4
C3
C3
C3
C2
C2
C2
C1
C1
C1
C0
C0
C0
138h
TIDR25
139h
TIDR26
13Ah
TIDR27
13Bh
TIDR28
13Ch
TIDR29
13Dh
TIDR30
13Eh
TIDR31
13Fh
TIDR32
140h
TS1
141h
TS2
142h
TS3
143h
TS4
144h
TS5
145h
TS6
146h
TS7
147h
TS8
148h
TS9
149h
TS10
14Ah
TS11
14Bh
TS12
14Ch
TS13
14Dh
TS14
—
—
—
—
—
—
—
—
C7
—
C6
—
C5
—
C4
—
C3
—
C2
—
C1
—
C0
—
C7
—
C6
—
C5
—
C4
—
C3
—
C2
—
C1
—
C0
—
C7
—
C6
—
C5
—
C4
—
C3
—
C2
—
C1
—
C0
—
C7
—
C7
—
C6
—
C6
—
C5
—
C5
—
C4
—
C4
—
C3
—
C3
—
C2
—
C2
—
C1
—
C1
—
C0
—
C0
—
C7
—
C6
—
C5
—
C4
—
C3
—
C2
—
C1
—
C0
—
C7
—
C6
—
C5
—
C4
—
C3
—
C2
—
C1
—
C0
—
C7
CH1-A
C6
CH1-B
C5
CH1-C
C4
CH1-D
C3
CH13-A
C2
CH13-B
C1
CH13-C
C0
CH13-D
0
CH2-A
0
CH2-B
0
CH2-C
0
CH2-D
X
CH14-A
Y
CH14-B
X
CH14-C
X
CH14-D
CH1-A
CH3-A
CH1-B
CH3-B
CH1-C
CH3-C
CH1-D
CH3-D
CH16-A
CH15-A
CH16-B
CH15-B
CH16-C
CH15-C
CH16-D
CH15-D
CH2-A
CH4-A
CH3-A
CH5-A
CH2-B
CH4-B
CH3-B
CH5-B
CH2-C
CH4-C
CH3-C
CH5-C
CH2-D
CH4-D
CH3-D
CH5-D
CH17-A
CH16-A
CH18-A
CH17-A
CH17-B
CH16-B
CH18-B
CH17-B
CH17-C
CH16-C
CH18-C
CH17-C
CH17-D
CH16-D
CH18-D
CH17-D
CH4-A
CH6-A
CH4-B
CH6-B
CH4-C
CH6-C
CH4-D
CH6-D
CH19-A
CH18-A
CH19-B
CH18-B
CH19-C
CH18-C
CH19-D
CH18-D
CH5-A
CH7-A
CH5-B
CH7-B
CH5-C
CH7-C
CH5-D
CH7-D
CH20-A
CH19-A
CH20-B
CH19-B
CH20-C
CH19-C
CH20-D
CH19-D
CH6-A
CH8-A
CH6-B
CH8-B
CH6-C
CH8-C
CH6-D
CH8-D
CH21-A
CH20-A
CH21-B
CH20-B
CH21-C
CH20-C
CH21-D
CH20-D
CH7-A
CH9-A
CH7-B
CH9-B
CH7-C
CH9-C
CH7-D
CH9-D
CH22-A
CH21-A
CH22-B
CH21-B
CH22-C
CH21-C
CH22-D
CH21-D
CH8-A
CH10-A
CH8-B
CH10-B
CH8-C
CH10-C
CH8-D
CH10-D
CH23-A
CH22-A
CH23-B
CH22-B
CH23-C
CH22-C
CH23-D
CH22-D
CH9-A
CH11-A
CH9-B
CH11-B
CH9-C
CH11-C
CH9-D
CH11-D
CH24-A
CH23-A
CH24-B
CH23-B
CH24-C
CH23-C
CH24-D
CH23-D
CH10-A
CH12-A
CH11-A
—
CH10-B
CH12-B
CH11-B
—
CH10-C
CH12-C
CH11-C
—
CH10-D
CH12-D
CH11-D
—
CH25-A
CH24-A
CH26-A
—
CH25-B
CH24-B
CH26-B
—
CH25-C
CH24-C
CH26-C
—
CH25-D
CH24-D
CH26-D
—
CH12-A
—
CH12-B
—
CH12-C
—
CH12-D
—
CH27-A
—
CH27-B
—
CH27-C
—
CH27-D
—
CH13-A
CH13-B
CH13-C
CH13-D
CH28-A
CH28-B
CH28-C
CH28-D
103 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
14Eh
TS15
14Fh
TS16
150h
151h
152h
TCICE1
TCICE2
TCICE3
153h
TCICE4
162h
T1TFDL
163h
T1TBOC
164h
165h
166h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
—
—
—
—
—
—
—
—
CH14-A
—
CH15-A
CH8
CH16
CH24
—
CH32
TFDL7
—
—
CH14-B
—
CH15-B
CH7
CH15
CH23
—
CH31
TFDL6
—
—
CH14-C
—
CH15-C
CH6
CH14
CH22
—
CH30
TFDL5
—
TBOC5
CH14-D
—
CH15-D
CH5
CH13
CH21
—
CH29
TFDL4
—
TBOC4
CH29-A
—
CH30-A
CH4
CH12
CH20
—
CH28
TFDL3
—
TBOC3
CH29-B
—
CH30-B
CH3
CH11
CH19
—
CH27
TFDL2
—
TBOC2
CH29-C
—
CH30-C
CH2
CH10
CH18
—
CH26
TFDL1
—
TBOC1
CH29-D
—
CH30-D
CH1
CH9
CH17
—
CH25
TFDL0
—
TBOC0
T1TSLC1
—
C8
—
C7
—
C6
—
C5
—
C4
—
C3
—
C2
—
C1
E1TAF
T1TSLC2
Si
M2
0
M1
0
S=0
1
S=1
1
S=0
0
C11
1
C10
1
C9
E1TNAF
T1TSLC3
E1TSiAF
Si
S=1
TSiF14
—
1
S4
TSiF12
—
A
S3
TSiF10
—
Sa4
S2
TSiF8
—
Sa5
S1
TSiF6
—
Sa6
A2
TSiF4
—
Sa7
A1
TSiF2
—
Sa8
M3
TSiF0
—
TsiF15
—
TSiF13
—
TSiF11
—
TSiF9
—
TSiF7
—
TSiF5
—
TSiF3
—
TSiF1
—
TRAF15
—
TRAF13
—
TRAF11
—
TRAF9
—
TRAF7
—
TRAF5
—
TRAF3
—
TRAF1
—
TSa4F15
—
TSa4F13
—
TSa4F11
—
TSa4F9
—
TSa4F7
—
TSa4F5
—
TSa4F3
—
TSa4F1
—
TSa5F15
—
TSa5F13
—
TSa5F11
—
TSa5F9
—
TSa5F7
—
TSa5F5
—
TSa5F3
—
TSa5F1
—
TSa6F15
—
TSa6F13
—
TSa6F11
—
TSa6F9
—
TSa6F7
—
TSa6F5
—
TSa6F3
—
TSa6F1
—
TSa7F13
—
TSa8F13
TFPT
TSa7F11
—
TSa8F11
—
TCPT
TSa7F9
—
TSa8F9
—
TSSE
TSa7F7
—
TSa8F7
—
GB7S
TSa7F5
—
TSa8F5
—
TB8ZS
TSa7F3
—
TSa8F3
SFTRST
TAIS
TSa7F1
—
TSa8F1
T1/E1
TRAI
167h
E1TSiNAF
168h
E1TRA
169h
E1TSa4
16Ah
E1TSa5
16Bh
E1TSa6
16Ch
E1TSa7
16Dh
E1TSa8
180h
TMMR
TCR1 (T1)
TSa7F15
—
TSa8F15
FRM_EN
TJC
TCR1 (E1)
TCR2 (T1)
TTPT
TFDLS
T16S
TSLC96
TG802
—
TSiS
FBCT2
TSA1
FBCT1
THDB3
TD4RM
TAIS
PDE
TCRC4
TB7ZS
TCR2 (E1)
AEBE
AAIS
ARA
Sa4S
Sa5S
Sa6S
Sa7S
Sa8S
ODF
ODM
TCSS1
TCSS0
MFRS
TFM
IBPV
TLOOP
ODF
ODM
TCSS1
TCSS0
MFRS
—
IBPV
CRC4R
TCLKINV
TSYNCINV
TSSYNCINV
TSCLKM
TSSM
TSIO
TSDW
TSM
181h
182h
183h
TCR3
184h
TIOCR
185h
TESCR
186h
TCR4
187h
188h
189h
THFC
TIBOC
TDS0SEL
INIT_DONE
TCLKINV
TSYNCINV
TSSYNCINV
TSCLKM
TSSM
TSIO
—
TSM
TDATFMT
—
TGCLKEN
—
——
—
TSZS
—
TESALGN
TRAIM
TESR
TAISM
TESMDM
TC1
TESE
TC0
—
—
—
—
—
—
—
—
—
—
—
—
IBS1
—
—
IBS0
—
—
IBOSEL
TCM4
—
IBOEN
TCM3
—
DA2
TCM2
TFLWM1
DA1
TCM1
TFLWM2
DA0
TCM0
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DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
18Ah
18Bh
TXPC
TBPBS
18Eh
TSYNCC
—
BPBSE8
—
—
BPBSE7
—
—
BPBSE6
—
—
BPBSE5
—
—
BPBSE4
—
TBPDIR
BPBSE3
TSEN
TBPFUS
BPBSE2
SYNCE
TBPEN
BPBSE1
RESYNC
190h
TLS1
191h
TLS2
192h
19Fh
TLS3
TIIR
1A0h
TIM1
1A1h
TIM2
1A2h
TIM3
1ACh
T1TCD1
ADh
T1TCD2
1B1h
1B3h
1B4h
1BBh
1C0h
1C1h
1C2h
TRTS2
TFBA
THF
TDS0M
TBCS1
TBCS2
TBCS3
1C3h
TBCS4
1C4h
1C5h
1C6h
TCBR1
TCBR2
TCBR3
1C7h
TCBR4
1C8h
1C9h
1CAh
THSCS1
THSCS2
THSCS3
1CBh
THSCS4
1CCh
1CDh
1CEh
TGCCS1
TGCCS2
TGCCS3
1CFh
TGCCS4
1D0h
1D1h
1D2h
PCL1
PCL2
PCL3
1D3h
PCL4
—
—
—
—
CRC4
TSEN
SYNCE
RESYNC
TESF
TESEM
TSLIP
TSLC96
TPDV
TMF
LOTCC
LOTC
TESF
TESEM
TSLIP
—
TAF
TMF
LOTCC
LOTC
—
—
—
TFDLE
TUDR
TMEND
TLWMS
TNFS
—
—
—
—
TUDR
TMEND
TLWMS
TNFS
—
—
TESF
—
—
TESEM
—
—
TSLIP
—
—
TSLC96
—
—
TPDV
—
TLS3
TMF
LOF
TLS2
LOTCC
LOFD
TLS1
LOTC
TESF
TESEM
TSLIP
—
TAF
TMF
LOTCC
LOTC
—
—
—
TFDLE
TUDR
TMEND
TLWMS
TNFS
—
—
—
—
TUDR
TMEND
TLWMS
TNFS
—
C7
—
C7
—
—
——
THD7
B1
CH8
CH16
CH24
—
—
C6
—
C6
—
—
TFBA6
THD6
B2
CH7
CH15
CH23
—
—
C5
—
C5
—
—
TFBA5
THD5
B3
CH6
CH14
CH22
—
—
C4
—
C4
—
—
TFBA4
THD4
B4
CH5
CH13
CH21
—
—
C3
—
C3
—
TEMPTY
TFBA3
THD3
B5
CH4
CH12
CH20
—
—
C2
—
C2
—
TFULL
TFBA2
THD2
B6
CH3
CH11
CH19
—
—
C1
—
C1
—
TLWM
TFBA1
THD1
B7
CH2
CH10
CH18
—
LOFD
C0
—
C0
—
TNF
TFBA0
THD0
B8
CH1
CH9
CH17
—
CH32
CH8
CH16
CH24
—
CH32
CH8
CH16
CH24
—
CH31
CH7
CH15
CH23
—
CH31
CH7
CH15
CH23
—
CH30
CH6
CH14
CH22
—
CH30
CH6
CH14
CH22
—
CH29
CH5
CH13
CH21
—
CH29
CH5
CH13
CH21
—
CH28
CH4
CH12
CH20
—
CH28
CH4
CH12
CH20
—
CH27
CH3
CH11
CH19
—
CH27
CH3
CH11
CH19
—
CH26
CH2
CH10
CH18
—
CH26
CH2
CH10
CH18
—
CH25
CH1
CH9
CH17
—
CH25:Fbit
CH1
CH9
CH17
—
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH8
CH16
CH24
—
CH7
CH15
CH23
—
CH6
CH14
CH22
—
CH5
CH13
CH21
—
CH4
CH12
CH20
—
CH3
CH11
CH19
—
CH2
CH10
CH18
—
CH1
CH9
CH17
—
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25(F-bit)
CH8
CH16
CH24
—
CH7
CH15
CH23
—
CH6
CH14
CH22
—
CH5
CH13
CH21
—
CH4
CH12
CH20
—
CH3
CH11
CH19
—
CH2
CH10
CH18
—
CH1
CH9
CH17
—
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
105 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1D4h
1D5h
1D6h
TBPCS1
TBPCS2
TBPCS3
CH8
CH16
CH24
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
CH1
CH9
CH17
1D7h
TBPCS4
—
—
—
—
—
—
—
—
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
*RLS6 is reserved for future use.
**Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode.
9.2.3
LIU Register Bit Map
Table 9-8. LIU Register Bit Map
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1000h
LTRCR
—
—
—
JADS
JAPS1
JAPS0
T1J1E1S
LSC
1001h
LTITSR
—
TIMPTOFF
TIMPL1
TIMPL0
—
L2
L1
L0
1002h
LMCR
TAIS
ATAIS
LLB
ALB
RLB
TPDE
RPDE
TE
1003h
LRSR
—
—
OEQ
UEQ
—
SCS
OCS
LOSS
1004h
LSIMR
JALTCIM
OCCIM
SCCIM
LOSCIM
JALTSIM
OCDIM
SCDIM
LOSDIM
1005h
LLSR
JALTC
OCC
SCC
LOSC
JALTS
OCD
SCD
LOSD
1006h
LRSL
RSL3
RSL2
RLS1
RLS0
—
—
—
—
1007h
LRISMR
RG703
RIMPOFF
RIMPM1
RIMPM0
RTR
RMONEN
RSMS1
RSMS0
9.2.4
BERT Register Bit Map
Table 9-9. BERT Register Bit Map
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1100h
BAWC
ACNT7
ACNT6
ACNT5
ACNT4
ACNT3
ACNT2
ACNT1
ACNT0
1101h
BRP1
RPAT7
RPAT6
RPAT5
RPAT4
RPAT3
RPAT2
RPAT1
RPAT0
1102h
BRP2
RPAT15
RPAT14
RPAT13
RPAT12
RPAT11
RPAT10
RPAT9
RPAT8
1103h
BRP3
RPAT23
RPAT22
RPAT21
RPAT20
RPAT19
RPAT18
RPAT17
RPAT16
1104h
BRP4
RPAT31
RPAT30
RPAT29
RPAT28
RPAT27
RPAT26
RPAT25
RPAT24
1105h
BC1
TC
TINV
RINV
PS2
PS1
PS0
LC
RESYNC
1106h
BC2
EIB2
EIB1
EIB0
SBE
RPL3
RPL2
RPL1
RPL0
1107h
BBC1
BBC7
BBC6
BBC5
BBC4
BBC3
BBC2
BBC1
BBC0
1108h
BBC2
BBC15
BBC14
BBC13
BBC12
BBC11
BBC10
BBC9
BBC8
1109h
BBC3
BBC23
BBC22
BBC21
BBC20
BBC19
BBC18
BBC17
BBC16
110Ah
BBC4
BBC31
BBC30
BBC29
BBC28
BBC27
BBC26
BBC25
BBC24
110Bh
BEC1
EC7
EC6
EC5
EC4
EC3
EC2
EC1
EC0
110Ch
BEC2
EC15
EC14
EC13
EC12
EC11
EC10
EC9
EC8
110Dh
BEC3
EC23
EC22
EC21
EC20
EC19
EC18
EC17
EC16
110Eh
BLSR
—
BBED
BBCO
BECO
BRA1
BRA0
BRLOS
BSYNC
110Fh
BSIM
—
BBED
BBCO
BECO
BRA1
BRA0
BRLOS
BSYNC
106 of 273
DS26524 Quad T1/E1/J1 Transceiver
9.3
Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit
descriptions are presented in this section.
Table 9-10. Global Register Set
ADDRESS
NAME
DESCRIPTION
R/W
0F0h
GTCR1
Global Transceiver Control Register 1
R/W
0F1h
GFCR
Global Framer Control Register
R/W
0F2h
GTCR2
Global Transceiver Control Register 2
R/W
0F3h
GTCCR
Global Transceiver Clock Control Register
R/W
0F4h
—
0F5h
GLSRR
Global LIU Software Reset Register
R/W
0F6h
GFSRR
Global Framer and BERT Software Reset Register
R/W
0F7h
—
0F8h
IDR
0F9h
Reserved
—
Reserved
—
Device Identification Register
R
GFISR
Global Framer Interrupt Status Register
R
0FAh
GBISR
Global BERT Interrupt Status Register
R
0FBh
GLISR
Global LIU Interrupt Status Register
R
0FCh
GFIMR
Global Framers Interrupt Mask Register
R/W
0FDh
GBIMR
Global BERT Interrupt Mask Register
R/W
0FEh
GLIMR
Global LIU Interrupt Mask Register
R/W
01Fh
—
Reserved
—
Note 1:
Reserved registers should only be written with all zeros.
Note 2:
The global registers are located in the framer address space. The corresponding address space for the other seven framers is
“Reserved,” and should be initialized with all zeros for proper operation.
107 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GTCR1
Global Transceiver Control Register 1
0F0h
6
—
0
5
RLOFLTS
0
4
GIBO
0
3
—
0
2
BWE
0
1
GCLE
0
0
GIPI
0
Bit 5: Receive Loss of Frame/Loss of Transmit Clock Indication Select (RLOFLTS).
0 = RLOF/LTCx pin indicates framer receive loss of frame
1 = RLOF/LTCx pin indicates framer loss of transmit clock
Bit 4: Global IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an external
wire-OR operation. Normally this bit should be set = 0 and the internal mux used.
0 = Use internal IBO mux
1 = Externally wire-OR TSERs and RSERs for IBO operation
Bit 2: Bulk Write Enable (BWE). When this bit is set, a port write to one of the quad ports is mapped into all four
ports. This applies to the framer, BERT, and LIU register sets. It must be cleared before performing a read
operation. This bit is useful for device initialization.
0 = Normal operation
1 = Bulk write is enabled
Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the
framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must
be cleared and set again to perform another counter latch.
Bit 0: Global Interrupt Pin Inhibit (GIPI).
0 = Normal operation. Interrupt pin (INTB) will toggle low on an unmasked interrupt condition.
1 = Interrupt inhibit. Interrupt pin (INTB) is forced high (inactive) when this bit is set.
108 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Description:
Register Address:
Bit #
Name
Default
GFCR
Global Framer Control Register
0F1h
7
IBOMS1
0
6
IBOMS0
0
5
BPCLK1
0
4
BPCLK0
0
3
RFLOSSFS
0
2
RFMSS
0
1
TCBCS
0
0
RCBCS
0
Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine the
configuration of the IBO (interleaved bus) multiplexer. These bits should be used in conjunction with the Rx and Tx
IBO control registers within each of the framer units. Additional information concerning the IBO multiplexer is given
in Section 8.8.2.
IBOMS1
0
0
1
1
IBOMS0
0
1
0
1
IBO MODE
IBO multiplexer disabled
2 devices on bus (4.096MHz)
4 devices on bus (8.192MHz)
8 devices on bus (16.384MHz)
Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on
the BPCLK pin.
BPCLK1
0
0
1
1
BPCLK0
0
1
0
1
BPCLK FREQUENCY
2.048MHz
4.096MHz
8.192MHz
16.384MHz
Bit 3: Receive Loss of Signal/Signaling Freeze Select (RLOSSFS). This bit controls the function of all four
AL/RSIGF/FLOS pins. The receive LOS is further selected between framer LOS and LIU LOS by GTCR2.2.
0 = AL/RSIGF/FLOS pin outputs RLOS[1:4] (receive loss)
1 = AL/RSIGF/FLOS pin outputs RSIGF[1:4] (receive-signaling freeze)
Bit 2: Receive Frame/Multiframe Sync Select (RFMSS). This bit controls the function of all four
RMSYNC/RFSYNC pins.
0 = RMSYNC/RFSYNC pin outputs RFSYNC[1:4] (receive frame sync)
1 = RMSYNC/RFSYNC pin outputs RMSYNC[1:4] (receive multiframe sync)
Bit 1: Transmit Channel Block/Clock Select (TCBCS). This bit controls the function of all four TCHBLK/CLK
pins.
0 = TCHBLK/CLK pin outputs TCHBLK[1:4] (transmit channel block)
1 = TCHBLK/CLK pin outputs TCHCLK[1:4] (transmit channel clock)
Bit 0: Receive Channel Block/Clock Select (RCBCS). This bit controls the function of all four RCHBLK/CLK pins.
0 = RCHBLK/CLK pin outputs RCHBLK[1:4] (receive channel block)
1 = RCHBLK/CLK pin outputs RCHCLK[1:4] (receive channel clock)
109 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GTCR2
Global Transceiver Control Register 2
0F2h
6
—
0
5
—
0
4
—
0
3
—
0
2
LOSS
0
1
TSSYNCIOSEL
0
0
—
0
Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pins can be driven with LIU loss. If reset, they
are driven by framer LOS. The selection of whether to drive AL/RSIGF/FLOS pins with LOS (analog or digital) or
signalling freeze is controlled by GFCR.2. This selection affects all ports.
Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL). If this bit is set to a 1, the TSSYNCIO is
an 8kHz output synchronous to the BPCLK. This “frame pulse” can be used in conjunction with the backplane clock
to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is
required for transmit synchronization and IBO operation.
110 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
GTCCR
Global Transceiver Clock Control Register
0F3h
Bit #
Name
Default
7
6
5
4
3
2
1
0
BPREFSEL3
BPREFSEL2
BPREFSEL1
BPREFSEL0
BFREQSEL
FREQSEL
MPS1
MPS0
0
0
0
0
0
0
0
0
Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock
source will be used for BPCLK generation. The BPCLK can be generated from the LIU recovered clock, an external
reference, or derivatives of MCLK input. This is shown in Table 9-11. See Figure 8-1 for additional information.
Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the
reference clock frequency used by the DS26524 backplane clock generation circuit. Note that the setting of this bit
should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock.
See Figure 8-1 for additional information.
0 = Backplane reference clock is 2.048MHz.
1 = Backplane reference clock is 1.544MHz.
Bit 2: Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, this bit selects the external MCLK
frequency of the signal input at the MCLK pin of the DS26524.
0 = The external master clock is 2.048MHz or multiple thereof.
1 = The external master clock is 1.544MHz or multiple thereof.
Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select
the external MCLK frequency of the signal input at the MCLK pin of the DS26524. This is shown in Table 9-12.
Table 9-11. Backplane Reference Clock Select
BPREFSEL3
BPREFSEL2
BPREFSEL1
BPREFSEL0
BFREQSEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
111 of 273
REFERENCE CLOCK
SOURCE
2.048MHz RCLK1
1.544MHz RCLK1
2.048MHz RCLK2
1.544MHz RCLK2
2.048MHz RCLK3
1.544MHz RCLK3
2.048MHz RCLK4
1.544MHz RCLK4
1.544MHz derived from MCLK.
(REFCLKIO is an output.)
2.048MHz derived from MCLK.
(REFCLKIO is an output.)
2.048MHz external clock input at REFCLKIO.
(REFCLKIO is an input.)
1.544MHz external clock input at REFCLKIO.
(REFCLKIO is an input.)
DS26524 Quad T1/E1/J1 Transceiver
Table 9-12. Master Clock Input Selection
FREQSEL
MPS1
MPS0
MCLK
(MHz ±50ppm)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2.048
4.096
8.192
16.384
1.544
3.088
6.176
12.352
112 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GLSRR
Global LIU Software Reset Register
0F5h
6
—
0
5
—
0
4
—
0
3
LSRST4
0
2
LSRST3
0
1
LSRST2
0
0
LSRST1
0
Bit 3: Channel 4 LIU Software Reset (LSRST4). LIU logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset LIU
Bit 2: Channel 3 LIU Software Reset (LSRST3). LIU logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset LIU
Bit 1: Channel 2 LIU Software Reset (LSRST2). LIU logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset LIU
Bit 0: Channel 1 LIU Software Reset (LSRST1). LIU logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset LIU
113 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GFSRR
Global Framer and BERT Software Reset Register
0F6h
6
—
0
5
—
0
4
—
0
3
FSRST4
0
2
FSRST3
0
1
FSRST2
0
0
FSRST1
0
Bit 3: Channel 4 Framer and BERT Software Reset (FSRST4). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset framer and BERT
Bit 2: Channel 3 Framer and BERT Software Reset (FSRST3). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset framer and BERT
Bit 1: Channel 2 Framer and BERT Software Reset (FSRST2). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset framer and BERT
Bit 0: Channel 1 Framer and BERT Software Reset (FSRST1). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset framer and BERT
114 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ID7
0
IDR
Device Identification Register
0F8h
6
ID6
1
5
ID5
1
4
ID4
0
3
ID3
0
2
ID2
0
1
ID1
0
0
ID0
1
Bits 7 to 3: Device ID (ID[7:3]). The upper five bits of the IDR are used to display the DS26524 ID.
Table 9-13. Device ID Codes in this Product Family
DEVICE
DS26528
DS26524
DS26522
DS26521
ID7
0
0
0
0
ID6
1
1
1
1
ID5
0
1
1
1
ID4
1
0
0
1
ID3
1
0
1
0
Bits 2 to 0: Silicon Revision Bits (ID[2:0]). The lower three bits of the IDR are used to display a sequential
number denoting the die revision of the chip. The initial silicon revision = “000,” and is incremented with each
silicon revision. This value is not the same as the two-character device revision on the top brand of the device. This
is due to the fact that portions of the device assembly other than the silicon may change, causing the device
revision increment on the brand without having a revision of the silicon. ID0 is the LSB of a decimal code that
represents the chip revision.
115 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GFISR
Global Framer Interrupt Status Register
0F9h
6
—
0
5
—
0
4
—
0
3
FIS4
0
2
FIS3
0
1
FIS2
0
0
FIS1
0
The GFISR register reports the framer interrupt status for each of the four T1/E1 framers. A logic one in the
associated bit location indicates a framer has set its interrupt signal.
Bit 3: Framer Interrupt Status 4 (FIS4).
0 = Framer 4 has not issued an interrupt.
1 = Framer 4 has issued an interrupt.
Bit 0: Framer Interrupt Status 3 (FIS3).
0 = Framer 3 has not issued an interrupt.
1 = Framer 3 has issued an interrupt.
Bit 0: Framer Interrupt Status 2 (FIS2).
0 = Framer 2 has not issued an interrupt.
1 = Framer 2 has issued an interrupt.
Bit 0: Framer Interrupt Status 1 (FIS1).
0 = Framer 1 has not issued an interrupt.
1 = Framer 1 has issued an interrupt.
116 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GBISR
Global BERT Interrupt Status Register
0FAh
6
—
0
5
—
0
4
—
0
3
BIS4
0
2
BIS3
0
1
BIS2
0
0
BIS1
0
The GBISR register reports the interrupt status for each of the four T1/E1 bit error-rate testers (BERTs). A logic one
in the associated bit location indicates a BERT has set its interrupt signal.
Bit 3: BERT Interrupt Status 4 (BIS4).
0 = BERT 4 has not issued an interrupt.
1 = BERT 4 has issued an interrupt.
Bit 2: BERT Interrupt Status 3 (BIS3).
0 = BERT 3 has not issued an interrupt.
1 = BERT 3 has issued an interrupt.
Bit 1: BERT Interrupt Status 2 (BIS2).
0 = BERT 2 has not issued an interrupt.
1 = BERT 2 has issued an interrupt.
Bit 0: BERT Interrupt Status 1 (BIS1).
0 = BERT 1 has not issued an interrupt.
1 = BERT 1 has issued an interrupt.
117 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GLISR
Global LIU Interrupt Status Register
0FBh
6
—
0
5
—
0
4
—
0
3
LIS4
0
2
LIS3
0
1
LIS2
0
0
LIS1
0
The GLISR register reports the LIU interrupt status for each of the four T1/E1 LIUs. A logic one in the associated bit
location indicates a LIU has set its interrupt signal.
Bit 3: LIU Interrupt Status 4 (LIS4).
0 = LIU 4 has not issued an interrupt.
1 = LIU 4 has issued an interrupt.
Bit 2: LIU Interrupt Status 3 (LIS3).
0 = LIU 3 has not issued an interrupt.
1 = LIU 3 has issued an interrupt.
Bit 1: LIU Interrupt Status 2 (LIS2).
0 = LIU 2 has not issued an interrupt.
1 = LIU 2 has issued an interrupt.
Bit 0: LIU Interrupt Status 1 (LIS1).
0 = LIU 1 has not issued an interrupt.
1 = LIU 1 has issued an interrupt.
118 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GFIMR
Global Framer Interrupt Mask Register
0FCh
6
—
0
5
—
0
4
—
0
Bit 3: Framer 4 Interrupt Mask (FIM4).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 2: Framer 3 Interrupt Mask (FIM3).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 1: Framer 2 Interrupt Mask (FIM2).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 0: Framer 1 Interrupt Mask (FIM1).
0 = Interrupt masked.
1 = Interrupt enabled.
119 of 273
3
FIM4
0
2
FIM3
0
1
FIM2
0
0
FIM1
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GBIMR
Global BERT Interrupt Mask Register
0FDh
6
—
0
5
—
0
4
—
0
Bit 3: BERT Interrupt Mask 4 (BIM4).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 2: BERT Interrupt Mask 3 (BIM3).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 1: BERT Interrupt Mask 2 (BIM2).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 0: BERT Interrupt Mask 1 (BIM1).
0 = Interrupt masked.
1 = Interrupt enabled.
120 of 273
3
BIM4
0
2
BIM3
0
1
BIM2
0
0
BIM1
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
GLIMR
Global LIU Interrupt Mask Register
0FEh
6
—
0
5
—
0
4
—
0
Bit 3: LIU Interrupt Mask 4 (LIM4).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 2: LIU Interrupt Mask 3 (LIM3).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 1: LIU Interrupt Mask 2 (LIM2).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 0: LIU Interrupt Mask 1 (LIM1).
0 = Interrupt masked.
1 = Interrupt enabled.
121 of 273
3
LIM4
0
2
LIM3
0
1
LIM2
0
0
LIM1
0
DS26524 Quad T1/E1/J1 Transceiver
9.4
Framer Register Definitions
See Table 9-3 for the complete framer register list.
9.4.1
Receive Register Definitions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RCRCD
0
RHC
Receive HDLC Control Register
010h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RHR
0
5
RHMS
0
4
RHCS4
0
3
RHCS3
0
2
RHCS2
0
1
RHCS1
0
0
RHCS0
0
Bit 7: Receive CRC-16 Display (RCRCD).
0 = Do not write received CRC-16 code to FIFO (default)
1 = Write received CRC-16 code to FIFO after last octet of packet
Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that
this bit is a acknowledged reset. The host should set this bit and the DS26524 will clear it once the reset operation
is complete. The DS26524 will complete the HDLC reset within two frames.
0 = Normal operation
1 = Reset receive HDLC controller and flush the receive FIFO
Bit 5: Receive HDLC Mapping Select (RHMS).
0 = Receive HDLC assigned to channels
1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode)
Bit 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to the
HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s selects
channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a receive HDLC reset
(RHR).
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BSE8
0
RHBSE
Receive HDLC Bit Suppress Register
011h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
BSE7
0
5
BSE6
0
4
BSE5
0
3
BSE4
0
2
BSE3
0
1
BSE2
0
0
BSE1
0
Bit 7: Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used.
Bit 6: Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used.
Bit 5: Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used.
Bit 4: Receive Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used.
Bit 3: Receive Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used.
Bit 2: Receive Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used.
Bit 1: Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used.
Bit 0: Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used.
123 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RDS0SEL
Receive Channel Monitor Select Register
012h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
RCM4
0
3
RCM3
0
2
RCM2
0
1
RCM1
0
0
RCM0
0
Bits 4 to 0: Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a 5-bit channel select that
determines which receive DS0 channel data will appear in the RDS0M register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RSIGC
Receive-Signaling Control Register
013h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
6
5
4
3
2
1
0
—
—
—
RFSA1
—
RSFF
RSFE
RSIE
—
—
—
CASMS
—
RSFF
RSFE
RSIE
0
0
0
0
0
0
0
0
Bit 4 (T1 Mode): Receive Force Signaling All Ones (RFSA1).
0 = do not force robbed bit signaling to all ones
1 = force signaling bits to all ones on a per-channel basis according to the T1RSAOI1:T1RSAOI3 registers.
Bit 4 (E1 Mode): CAS Mode Select (CASMS).
0 = The DS26524 will initiate a resync when two consecutive multiframe alignment signals have been
received with an error.
1 = The DS26524 will initiate a resync when two consecutive multiframe alignment signals have been
received with an error, or 1 multiframe has been received with all the bits in time slot 16 in state 0.
Alignment criteria is met when at least one bit in state 1 is present in the time slot 16 preceding the
multiframe alignment signal first detected (G.732 alternate criteria).
Bit 2: Receive-Signaling Force Freeze (RSFF). Freezes receive-side signaling at RSIG (and RSER if receivesignaling reinsertion is enabled); will override receive freeze enable (RFE).
0 = do not force a freeze event
1 = force a freeze event
Bit 1: Receive-Signaling Freeze Enable (RSFE).
0 = no freezing of receive-signaling data will occur
1 = allow freezing of receive-signaling data at RSIG (and RSER if receive-signaling reinsertion is enabled)
Bit 0: Receive-Signaling Integration Enable (RSIE).
0 = signaling changes of state reported on any change in selected channels
1 = signaling must be stable for three multiframes in order for a change of state to be reported
124 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
T1RCR2 (T1 Mode)
Receive Control Register 2
014h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
RSLC96
0
3
OOF2
0
2
OOF1
0
1
RAIIE
0
0
RD4RM
0
Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section 8.9.4.5 for SLC-96 details.
0 = SLC-96 synchronizer is disabled
1 = SLC-96 synchronizer is enabled
Bits 3 and 2: Out of Frame Select Bits (OOF[2:1]).
OOF2
0
0
1
1
OOF1
0
1
0
1
OUT OF FRAME CRITERIA
2/4 frame bits in error
2/5 frame bits in error
2/6 frame bits in error
2/6 frame bits in error
Bit 1: Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to
exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE will cause the RAI status from the DS26524
to be integrated for 200ms.
0=
RAI detects when 16 consecutive patterns of 00FF appear in the FDL.
RAI clears when 14 or fewer patterns of 00FF hex out of 16 possible appear in the FDL.
1=
RAI detects when the condition has been present for greater than 200ms.
RAI clears when the condition has been absent for greater than 200ms.
Bit 0: Receive-Side D4 Remote Alarm Select (RD4RM).
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
E1RSAIMR (E1 Mode Only)
Receive Sa-Bit Interrupt Mask Register
014h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
RSa4IM
0
3
RSa5IM
0
2
RSa6IM
0
1
RSa7IM
0
0
RSa8IM
0
Bit 4: Sa4 Change Detect Interrupt Mask (RSa4IM). This bit will enable the change detect interrupt for the Sa4
bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
0 = interrupt masked
1 = interrupt enabled
Bit 3: Sa5 Change Detect Interrupt Mask (RSa5IM). This bit will enable the change detect interrupt for the Sa5
bits. Any change of state of the Sa5 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
0 = interrupt masked
1 = interrupt enabled
Bit 2: Sa6 Change Detect Interrupt Mask (RSa6IM). This bit will enable the change detect interrupt for the Sa6
bits. Any change of state of the Sa6 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
0 = interrupt masked
1 = interrupt enabled
Bit 1: Sa7 Change Detect Interrupt Mask (RSa7IM). This bit will enable the change detect interrupt for the Sa7
bits. Any change of state of the Sa7 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
0 = interrupt masked
1 = interrupt enabled
Bit 0: Sa8 Change Detect Interrupt Mask (RSa8IM). This bit will enable the change detect interrupt for the Sa8
bits. Any change of state of the Sa8 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
0 = interrupt masked
1 = interrupt enabled
126 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RBR
0
T1RBOCC (T1 Mode Only)
Receive BOC Control Register
015h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
RBD1
0
4
RBD0
0
3
—
0
2
RBF1
0
1
RBF0
0
0
—
0
Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is
an acknowledged reset, that is, the host need only set the bit and the DS26524 will clear it once the reset operation
is complete (less than 250µs). Modifications to the RBF[1:0] and RBD[1:0] bits will not be applied to the BOC
controller until a BOC reset has been completed.
Bits 5 and 4: Receive BOC Disintegration Bits (RBD[1:0]). The BOC disintegration filter sets the number of
message bits that must be received without a valid BOC to set the BC bit indicating that a valid BOC is no longer
being received.
RBD1
RBD0
0
0
1
1
0
1
0
1
CONSECUTIVE MESSAGE BITS
FOR BOC CLEAR IDENTIFICATION
16
32
48
64 (See Note 1)
Bits 2 and 1: Receive BOC Filter Bits (RBF[1:0). The BOC filter sets the number of consecutive patterns that
must be received without error prior to an indication of a valid message.
RBF1
RBF0
0
0
1
1
0
1
0
1
CONSECUTIVE BOC CODES FOR
VALID SEQUENCE IDENTIFICATION
None
3
5
7 (See Note 1)
Note 1: The DS26524’s BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration
time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be
detected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
RIDR1 to RIDR32
Receive Idle Code Definition Registers 1 to 32
020h to 03Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
020h is for channel 1. Address 037h is for channel 24. Address 03Fh is for channel 32. RIDR1:RIDR24 are T1
mode only. RIDR25:RIDR32 are E1 mode only.
127 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
(MSB) 7
CH8
CH16
CH24
0
T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only)
Receive-Signaling All-Ones Insertion Registers 1 to 3
038h, 039h, 03Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
CH7
CH15
CH23
0
5
CH6
CH14
CH22
0
4
CH5
CH13
CH21
0
3
CH4
CH12
CH20
0
2
CH3
CH11
CH19
0
1
CH2
CH10
CH18
0
0 (LSB)
CH1
CH9
CH17
0
T1RSAOI1
T1RSAOI2
T1RSAOI3
Setting any of the CH[1:24] bits in the T1RSAOI1:T1RSAOI3 registers will cause signaling data to be replaced with
logic ones as reported on RSER. The RSIG signal will continue to report received signaling data. Note that this
feature must be enabled with control bit RSIGC.4.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
(MSB) 7
CH8
CH16
CH24
0
T1RDMWE1, T1RDMWE2, T1RDMWE3 (T1 Mode Only)
T1 Receive Digital Milliwatt Enable Registers 1 to 3
03Ch, 03Dh, 03Eh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
CH7
CH15
CH23
0
5
CH6
CH14
CH22
0
4
CH5
CH13
CH21
0
3
CH4
CH12
CH20
0
2
CH3
CH11
CH19
0
1
CH2
CH10
CH18
0
Bits 7 to 0: Receive Digital Milliwatt Enable for Channels 1 to 24 (CH[1:24]).
0 =do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with digital milliwatt code
128 of 273
0 (LSB)
CH1
CH9
CH17
0
T1RDMWE1
T1RDMWE2
T1RDMWE3
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RS1 to RS16
Receive-Signaling Registers 1 to 16
040h to 04Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
T1 Mode:
(MSB)
CH1-A
CH2-A
CH3-A
CH4-A
CH5-A
CH6-A
CH7-A
CH8-A
CH9-A
CH10-A
CH11-A
CH12-A
CH1-B
CH2-B
CH3-B
CH4-B
CH5-B
CH6-B
CH7-B
CH8-B
CH9-B
CH10-B
CH11-B
CH12-B
CH1-C
CH2-C
CH3-C
CH4-C
CH5-C
CH6-C
CH7-C
CH8-C
CH9-C
CH10-C
CH11-C
CH12-C
CH1-D
CH2-D
CH3-D
CH4-D
CH5-D
CH6-D
CH7-D
CH8-D
CH9-D
CH10-D
CH11-D
CH12-D
CH13-A
CH14-A
CH15-A
CH16-A
CH17-A
CH18-A
CH19-A
CH20-A
CH21-A
CH22-A
CH23-A
CH24-A
CH13-B
CH14-B
CH15-B
CH16-B
CH17-B
CH18-B
CH19-B
CH20-B
CH21-B
CH22-B
CH23-B
CH24-B
CH13-C
CH14-C
CH15-C
CH16-C
CH17-C
CH18-C
CH19-C
CH20-C
CH21-C
CH22-C
CH23-C
CH24-C
(LSB)
CH13-D
CH14-D
CH15-D
CH16-D
CH17-D
CH18-D
CH19-D
CH20-D
CH21-D
CH22-D
CH23-D
CH24-D
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
E1 Mode:
(MSB)
0
CH1-A
CH2-A
CH3-A
CH4-A
CH5-A
CH6-A
CH7-A
CH8-A
CH9-A
CH10-A
CH11-A
CH12-A
CH13-A
CH14-A
CH15-A
0
CH1-B
CH2-B
CH3-B
CH4-B
CH5-B
CH6-B
CH7-B
CH8-B
CH9-B
CH10-B
CH11-B
CH12-B
CH13-B
CH14-B
CH15-B
0
CH1-C
CH2-C
CH3-C
CH4-C
CH5-C
CH6-C
CH7-C
CH8-C
CH9-C
CH10-C
CH11-C
CH12-C
CH13-C
CH14-C
CH15-C
0
CH1-D
CH2-D
CH3-D
CH4-D
CH5-D
CH6-D
CH7-D
CH8-D
CH9-D
CH10-D
CH11-D
CH12-D
CH13-D
CH14-D
CH15-D
X
CH16-A
CH17-A
CH18-A
CH19-A
CH20-A
CH21-A
CH22-A
CH23-A
CH24-A
CH25-A
CH26-A
CH27-A
CH28-A
CH29-A
CH30-A
Y
CH16-B
CH17-B
CH18-B
CH19-B
CH20-B
CH21-B
CH22-B
CH23-B
CH24-B
CH25-B
CH26-B
CH27-B
CH28-B
CH29-B
CH30-B
X
CH16-C
CH17-C
CH18-C
CH19-C
CH20-C
CH21-C
CH22-C
CH23-C
CH24-C
CH25-C
CH26-C
CH27-C
CH28-C
CH29-C
CH30-C
(LSB)
X
CH16-D
CH17-D
CH18-D
CH19-D
CH20-D
CH21-D
CH22-D
CH23-D
CH24-D
CH25-D
CH26-D
CH27-D
CH28-D
CH29-D
CH30-D
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing
mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the framer will repeat the A
and B signaling data in the C and D bit locations. Therefore, when the framer is operated in D4 framing mode, the
user will need to retrieve the signaling bits every 1.5ms as opposed to 3ms for ESF mode. The receive-signaling
registers are frozen and not updated during a loss of sync condition. They will contain the most recent signaling
information before the “OOF” occurred.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
LCVCR1
Line Code Violation Count Register 1
050h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
LCVC14
0
7
LCVC15
0
5
LCVC13
0
4
LCVC12
0
3
LCVC11
0
2
LCVC10
0
1
LCVC9
0
0
LCVC8
0
Bits 7 to 0: Line Code Violation Counter Bits 15 to 8 (LCVC[15:8]). LCVC15 is the MSB of the 16-bit code
violation count.
Register Name:
Register Description:
Register Address:
LCVCR2
Line Code Violation Count Register 2
051h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
LCVC6
0
7
LCVC7
0
5
LCVC5
0
4
LCVC4
0
3
LCVC3
0
2
LCVC2
0
1
LCVC1
0
0
LCVC0
0
Bits 7 to 0: Line Code Violation Counter Bits 7 to 0 (LCVC[7:0]). LCVC0 is the LSB of the 16-bit code violation
count.
Register Name:
Register Description:
Register Address:
PCVCR1
Path Code Violation Count Register 1
052h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
PCVC14
0
7
PCVC15
0
5
PCVC13
0
4
PCVC12
0
3
PCVC11
0
2
PCVC10
0
1
PCVC9
0
0
PCVC8
0
Bits 7 to 0: Path Code Violation Counter Bits 15 to 8 (PCVC[15:8]). PCVC15 is the MSB of the 16-bit path code
violation count.
Register Name:
Register Description:
Register Address:
PCVCR2
Path Code Violation Count Register 2
053h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
PCVC6
0
7
PCVC7
0
5
PCVC5
0
4
PCVC4
0
3
PCVC3
0
2
PCVC2
0
1
PCVC1
0
0
PCVC0
0
Bits 7 to 0: Path Code Violation Counter Bits 0 to 7 (PCVC[7:0]). PCVC0 is the LSB of the 16-bit path code
violation count.
130 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
FOSCR1
Frames Out of Sync Count Register 1
054h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
FOS14
0
7
FOS15
0
5
FOS13
0
4
FOS12
0
3
FOS11
0
2
FOS10
0
1
FOS9
0
0
FOS8
0
Bits 7 to 0: Frames Out of Sync Counter Bits 15 to 8 (FOS[15:8]). FOS15 is the MSB of the 16-bit frames out of
sync count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FOS7
0
FOSCR2
Frames Out of Sync Count Register 2
055h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
FOS6
0
5
FOS5
0
4
FOS4
0
3
FOS3
0
2
FOS2
0
1
FOS1
0
0
FOS0
0
Bits 7 to 0: Frames Out of Sync Counter Bits 7 to 0 (FOS[7:0]). FOS0 is the LSB of the 16-bit frames out of
sync count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EB15
0
E1EBCR1 (E1 Mode Only)
E-Bit Count Register 1
056h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
EB14
0
5
EB13
0
4
EB12
0
3
EB11
0
2
EB10
0
1
EB9
0
0
EB8
0
Bits 7 to 0: E-Bit Counter Bits 15 to 8 (EB[15:8]). EB15 is the MSB of the 16-bit E-bit count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EB7
0
E1EBCR2 (E1 Mode Only)
E-Bit Count Register 2
057h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
EB6
0
5
EB5
0
4
EB4
0
3
EB3
0
2
EB2
0
Bits 7 to 0: E-Bit Counter Bits 7 to 0 (EB[7:0]). EB0 is the LSB of the 16-bit E-bit count.
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1
EB1
0
0
EB0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
B1
0
RDS0M
Receive DS0 Monitor Register
060h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
B2
0
5
B3
0
4
B4
0
3
B5
0
2
B6
0
1
B7
0
0
B8
0
Bits 7 to 0: Receive DS0 Channel Bits (B[1:8]). Receive channel data that has been selected by the Receive
Channel Monitor Select register (RDS0SEL). B8 is the LSB of the DS0 channel (last bit to be received).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FR7
0
E1RFRID (E1 Mode Only)
Receive Firmware Revision ID Register
061h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
FR6
0
5
FR5
0
4
FR4
0
3
FR3
0
2
FR2
0
1
FR1
0
0
FR0
0
Bits 7 to 0: Firmware Revision (FR[7:0]). This read-only register reports the current revision of the receive
firmware.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RFDL7
0
T1RFDL (T1 Mode)
Receive FDL Register
062h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RFDL6
0
5
RFDL5
0
4
RFDL4
0
3
RFDL3
0
2
RFDL2
0
1
RFDL1
0
0
RFDL0
0
2
CRC4SA
0
1
CASSA
0
0
FASSA
0
Note: This register has an alternate definition for E1 mode. See E1RRTS7.
Bit 7: Receive FDL Bit 7 (RFDL7). MSB of the received FDL code.
Bit 6: Receive FDL Bit 6 (RFDL6).
Bit 5: Receive FDL Bit 5 (RFDL5).
Bit 4: Receive FDL Bit 4 (RFDL4).
Bit 3: Receive FDL Bit 3 (RFDL3).
Bit 2: Receive FDL Bit 2 (RFDL2).
Bit 1: Receive FDL Bit 1 (RFDL1).
Bit 0: Receive FDL Bit 0 (RFDL0). LSB of the received FDL code.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CSC5
0
E1RRTS7 (E1 Mode)
Receive Real-Time Status Register 7
062h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
CSC4
0
5
CSC3
0
4
CSC2
0
3
CSC0
0
Note: This register has an alternate definition for T1 mode. See T1RFDL. All bits in this register are real-time (not latched).
Bits 7 to 3: CRC-4 Sync Counter Bits (CSC[5:2] and CSC0). The CRC-4 sync counter increments each time the
8ms CRC-4 multiframe search times out. The counter is cleared when the framer has successfully obtained
synchronization at the CRC-4 level. The counter can also be cleared by disabling the CRC-4 mode (RCR1.3 = 0).
This counter is useful for determining the amount of time the framer has been searching for synchronization at the
CRC-4 level. ITU-T G.706 suggests that if synchronization at the CRC-4 level cannot be obtained within 400ms,
then the search should be abandoned and proper action taken. The CRC-4 sync counter will saturate (not rollover).
CSC0 is the LSB of the 6-bit counter. (CSC1 is omitted to allow resolution to > 400ms using 5 bits.)
Bit 2: CRC-4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC-4 MF alignment
word.
Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.
Bit 0: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
T1RBOC (T1 Mode)
Receive BOC Register
063h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
—
0
6
—
0
5
RBOC5
0
4
RBOC4
0
3
RBOC3
0
2
RBOC2
0
1
RBOC1
0
0
RBOC0
0
Bit 5: BOC Bit 5 (RBOC5).
Bit 4: BOC Bit 4 (RBOC4).
Bit 3: BOC Bit 3 (RBOC3).
Bit 2: BOC Bit 2 (RBOC2).
Bit 1: BOC Bit 1 (RBOC1).
Bit 0: BOC Bit 0 (RBOC0).
The T1RBOC register always contains the last valid BOC received. The Receive FDL register (T1RFDL) reports
the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL
updates on multiframe boundaries and reports the six Fs bits in RFDL[5:0].
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
(MSB) 7
C8
M2
S=1
0
T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode)
Receive SLC-96 Data Link Registers 1 to 3
064h, 065h, 066h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C7
M1
S4
0
5
C6
S=0
S3
0
4
C5
S=1
S2
0
3
C4
S=0
S1
0
2
C3
C11
A2
0
1
C2
C10
A1
0
0 (LSB)
C1
C9
M3
0
T1RSLC1
T1RSLC2
T1RSLC3
Note: These registers have an alternate definition for E1 mode. See E1RAF, E1RNAF, and E1RSiAF.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
E1RAF (E1 Mode)
E1 Receive Align Frame Register
064h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
Si
0
6
0
0
5
0
0
4
1
0
Note: This register has an alternate definition for T1 mode. See T1RSLC1.
Bit 7: International Bit (Si).
Bit 6: Frame Alignment Signal Bit (0).
Bit 5: Frame Alignment Signal Bit (0).
Bit 4: Frame Alignment Signal Bit (1).
Bit 3: Frame Alignment Signal Bit (1).
Bit 2: Frame Alignment Signal Bit (0).
Bit 1: Frame Alignment Signal Bit (1).
Bit 0: Frame Alignment Signal Bit (1).
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3
1
0
2
0
0
1
1
0
0
1
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
E1RNAF (E1 Mode)
E1 Receive Non-Align Frame Register
065h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
Si
0
6
1
0
5
A
0
4
Sa4
0
3
Sa5
0
2
Sa6
0
1
Sa7
0
0
Sa8
0
2
SiF4
0
1
SiF2
0
0
SiF0
0
Note: This register has an alternate definition for T1 mode. See T1RSLC2.
Bit 7: International Bit (Si).
Bit 6: Frame Non-Alignment Signal Bit (1).
Bit 5: Remote Alarm (A).
Bit 4: Additional Bit 4 (Sa4).
Bit 3: Additional Bit 5 (Sa5).
Bit 2: Additional Bit 6 (Sa6).
Bit 1: Additional Bit 7 (Sa7).
Bit 0: Additional Bit 8 (Sa8).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SiF14
0
E1RSiAF (E1 Mode)
E1 Received Si Bits of the Align Frame Register
066h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
SiF12
0
5
SiF10
0
4
SiF8
0
Note: This register has an alternate definition for T1 mode. See T1RSLC3.
Bit 7: Si Bit of Frame 14 (SiF14).
Bit 6: Si Bit of Frame 12 (SiF12).
Bit 5: Si Bit of Frame 10 (SiF10).
Bit 4: Si Bit of Frame 8 (SiF8).
Bit 3: Si Bit of Frame 6 (SiF6).
Bit 2: Si Bit of Frame 4 (SiF4).
Bit 1: Si Bit of Frame 2 (SiF2).
Bit 0: Si Bit of Frame 0 (SiF0).
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3
SiF6
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SiF15
0
E1RSiNAF (E1 Mode Only)
Receive Si Bits of the Non-Align Frame Register
067h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
SiF13
0
5
SiF11
0
4
SiF9
0
3
SiF7
0
2
SiF5
0
1
SiF3
0
0
SiF1
0
2
RRAF5
0
1
RRAF3
0
0
RRAF1
0
Bit 7: Si Bit of Frame 15 (SiF15).
Bit 6: Si Bit of Frame 13 (SiF13).
Bit 5: Si Bit of Frame 11 (SiF11).
Bit 4: Si Bit of Frame 9 (SiF9).
Bit 3: Si Bit of Frame 7 (SiF7).
Bit 2: Si Bit of Frame 5 (SiF5).
Bit 1: Si Bit of Frame 3 (SiF3).
Bit 0: Si Bit of Frame 1 (SiF1).
Register Name:
Register Description:
Register Address:
E1RRA (E1 Mode Only)
Receive Remote Alarm Register
068h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RRAF13
0
7
RRAF15
0
5
RRAF11
0
4
RRAF9
0
Bit 7: Remote Alarm Bit of Frame 15 (RRAF15).
Bit 6: Remote Alarm Bit of Frame 13 (RRAF13).
Bit 5: Remote Alarm Bit of Frame 11 (RRAF11).
Bit 4: Remote Alarm Bit of Frame 9 (RRAF9).
Bit 3: Remote Alarm Bit of Frame 7 (RRAF7).
Bit 2: Remote Alarm Bit of Frame 5 (RRAF5).
Bit 1: Remote Alarm Bit of Frame 3 (RRAF3).
Bit 0: Remote Alarm Bit of Frame 1 (RRAF1).
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3
RRAF7
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa4F15
0
E1RSa4 (E1 Mode Only)
Receive Sa4 Bits Register
069h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RSa4F13
0
5
RSa4F11
0
4
RSa4F9
0
3
RSa4F7
0
2
RSa4F5
0
1
RSa4F3
0
0
RSa4F1
0
1
RSa5F3
0
0
RSa5F1
0
Bit 7: Sa4 Bit of Frame 15 (RSa4F15).
Bit 6: Sa4 Bit of Frame 13 (RSa4F13).
Bit 5: Sa4 Bit of Frame 11 (RSa4F11).
Bit 4: Sa4 Bit of Frame 9 (RSa4F9).
Bit 3: Sa4 Bit of Frame 7 (RSa4F7).
Bit 2: Sa4 Bit of Frame 5 (RSa4F5).
Bit 1: Sa4 Bit of Frame 3 (RSa4F3).
Bit 0: Sa4 Bit of Frame 1 (RSa4F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa5F15
0
E1RSa5 (E1 Mode Only)
Receive Sa5 Bits Register
06Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RSa5F13
0
5
RSa5F11
0
4
RSa5F9
0
Bit 7: Sa5 Bit of Frame 15 (RSa5F15).
Bit 6: Sa5 Bit of Frame 13 (RSa5F13).
Bit 5: Sa5 Bit of Frame 11 (RSa5F11).
Bit 4: Sa5 Bit of Frame 9 (RSa5F9).
Bit 3: Sa5 Bit of Frame 7 (RSa5F7).
Bit 2: Sa5 Bit of Frame 5 (RSa5F5).
Bit 1: Sa5 Bit of Frame 3 (RSa5F3).
Bit 0: Sa5 Bit of Frame 1 (RSa5F1).
138 of 273
3
RSa5F7
0
2
RSa5F5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa6F15
0
E1RSa6 (E1 Mode Only)
Receive Sa6 Bits Register
06Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RSa6F13
0
5
RSa6F11
0
4
RSa6F9
0
3
RSa6F7
0
2
RSa6F5
0
1
RSa6F3
0
0
RSa6F1
0
1
RSa7F3
0
0
RSa7F1
0
Bit 7: Sa6 Bit of Frame 15 (RSa6F15).
Bit 6: Sa6 Bit of Frame 13 (RSa6F13).
Bit 5: Sa6 Bit of Frame 11 (RSa6F11).
Bit 4: Sa6 Bit of Frame 9 (RSa6F9).
Bit 3: Sa6 Bit of Frame 7 (RSa6F7).
Bit 2: Sa6 Bit of Frame 5 (RSa6F5).
Bit 1: Sa6 Bit of Frame 3 (RSa6F3).
Bit 0: Sa6 Bit of Frame 1 (RSa6F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa7F15
0
E1RSa7 (E1 Mode Only)
Receive Sa7 Bits Register
06Ch + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RSa7F13
0
5
RSa7F11
0
4
RSa7F9
0
Bit 7: Sa7 Bit of Frame 15 (RSa7F15).
Bit 6: Sa7 Bit of Frame 13 (RSa7F13).
Bit 5: Sa7 Bit of Frame 11 (RSa7F11).
Bit 4: Sa7 Bit of Frame 9 (RSa7F9).
Bit 3: Sa7 Bit of Frame 7 (RSa7F7).
Bit 2: Sa7 Bit of Frame 5 (RSa7F5).
Bit 1: Sa7 Bit of Frame 3 (RSa7F3).
Bit 0: Sa7 Bit of Frame 1 (RSa7F1).
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3
RSa7F7
0
2
RSa7F5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa8F15
0
E1RSa8 (E1 Mode Only)
Receive Sa8 Bits Register
06Dh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RSa8F13
0
5
RSa8F11
0
4
RSa8F9
0
3
RSa8F7
0
2
RSa8F5
0
1
RSa8F3
0
0
RSa8F1
0
1
Sa7
0
0
Sa8
0
Bit 7: Sa8 Bit of Frame 15 (RSa8F15).
Bit 6: Sa8 Bit of Frame 13 (RSa8F13).
Bit 5: Sa8 Bit of Frame 11 (RSa8F11).
Bit 4: Sa8 Bit of Frame 9 (RSa8F9).
Bit 3: Sa8 Bit of Frame 7 (RSa8F7).
Bit 2: Sa8 Bit of Frame 5 (RSa8F5).
Bit 1: Sa8 Bit of Frame 3 (RSa8F3).
Bit 0: Sa8 Bit of Frame 1 (RSa8F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
SaBITS
Receive SaX Bits Register
06Eh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
Sa4
0
3
Sa5
0
2
Sa6
0
This register indicates the last received SaX bit. This can be used in conjunction with the RLS7 register to
determine which SaX bits have changed. The user can program which Sa bit positions should be monitored via the
E1RSAIMR register, and when a change is detected through an interrupt inRLS7.0, the user can determine which
bit has changed by reading this register and comparing it with previous known values.
Bit 4: Last Received Sa4 Bit (Sa4).
Bit 3: Last Received Sa5 Bit (Sa5).
Bit 2: Last Received Sa6 Bit (Sa6).
Bit 1: Last Received Sa7 Bit (Sa7).
Bit 0: Last Received Sa8 Bit (Sa8).
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
Sa6CODE
Received Sa6 Codeword Register
06Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
Sa6n
0
2
Sa6n
0
1
Sa6n
0
0
Sa6n
0
This register reports the received Sa6 codeword per ETS 300 233. The bits are monitored on a submultiframe
asynchronous basis, so the pattern reported could be one of multiple patterns that would represent a valid
codeword. The table below indicates which patterns reported in this register correspond to a given valid Sa6
codeword.
Bits 3 to 0: Sa6 Codeword Bit (Sa6n).
POSSIBLE REPORTED
VALID Sa6 CODE
PATTERNS
Sa6_8
1000, 0100, 0010, 0001
Sa6_A
1010, 0101
Sa6_C
110, 0110, 0011, 1001
Sa6_E
1110, 0111, 1011, 1101
Sa6_F
1111
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FRM_EN
0
RMMR
Receive Master Mode Register
080h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
INIT_DONE
0
5
—
0
4
—
0
3
—
0
2
—
0
1
SFTRST
0
0
T1/E1
0
Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE.
0 = Framer disabled—held in low-power state
1 = Framer enabled—all features active
Bit 6: Initialization Done (INIT_DONE). The user must set this bit once he has written the configuration registers.
The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the
DS26524 will check the FRM_EN bit and, if enabled, will begin operation based on the initial configuration.
Bit 1: Soft Reset (SFTRST). Level sensitive soft reset. Should be taken high then low to reset the receiver.
0 = Normal operation
1 = Reset the receiver
Bit 0: Receiver T1/E1 Mode Select (T1/E1). Sets operating mode for receiver only! This bit must be set to the
desired state before writing INIT_DONE.
0 = T1 operation
1 = E1 operation
141 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RCR1 (T1 Mode)
Receive Control Register 1
081h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RB8ZS
0
7
SYNCT
0
5
RFM
0
4
ARC
0
3
SYNCC
0
2
RJC
0
1
SYNCE
0
0
RESYNC
0
Note: This register has an alternate definition for E1 mode. See RCR1.
Bit 7: Sync Time (SYNCT).
0 = qualify 10 bits
1 = qualify 24 bits
Bit 6: Receive B8ZS Enable (RB8ZS).
0 = B8ZS disabled
1 = B8ZS enabled
Bit 5: Receive Frame Mode Select (RFM).
0 = ESF framing mode
1 = D4 framing mode
Bit 4: Auto Resync Criteria (ARC).
0 = resync on OOF or LOS event
1 = resync on OOF only
Bit 3: Sync Criteria (SYNCC).
In D4 Framing Mode:
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode:
0 = search for FPS pattern only
1 = search for FPS and verify with CRC-6
Bit 2: Receive Japanese CRC6 Enable (RJC).
0 = use ANSI:AT&T:ITU-T CRC-6 calculation (normal operation)
1 = use Japanese standard JT-G704 CRC-6 calculation
Bit 1: Sync Enable (SYNCE).
0 = auto resync enabled
1 = auto resync disabled
Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is
initiated. Must be cleared and set again for a subsequent resync.
142 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RCR1 (E1 Mode)
Receive Control Register 1
081h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RHDB3
0
7
—
0
5
RSIGM
0
4
RG802
0
3
RCRC4
0
2
FRC
0
1
SYNCE
0
0
RESYNC
0
Note: This register has an alternate definition for T1 mode. See RCR1.
Bit 6: Receive HDB3 Enable (RHDB3).
0 = HDB3 disabled
1 = HDB3 enabled (decoded per O.162)
Bit 5: Receive-Signaling Mode Select (RSIGM).
0 = CAS signaling mode
1 = CCS signaling mode
Bit 4: Receive G.802 Enable (RG802). See Figure 10-23 for details.
0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
Bit 3: Receive CRC-4 Enable (RCRC4).
0 = CRC-4 disabled
1 = CRC-4 enabled
Bit 2: Frame Resync Criteria (FRC).
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
Bit 1: Sync Enable (SYNCE).
0 = auto resync enabled
1 = auto resync disabled
Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is
initiated. Must be cleared and set again for a subsequent resync.
143 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
T1RIBCC (T1 Mode)
Receive In-Band Code Control Register
082h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
RUP2
0
4
RUP1
0
3
RUP0
0
Note: This register has an alternate definition for E1 mode. See E1RCR2.
Bits 5 to 3: Receive Up Code Length Definition Bits (RUP[2:0]).
RUP2
0
0
0
0
1
1
1
1
RUP1
0
0
1
1
0
0
1
1
RUP0
0
1
0
1
0
1
0
1
LENGTH SELECTED
1 bits
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
8 : 16 bits
Bits 2 to 0: Receive Down Code Length Definition Bits (RDN[2:0]).
RDN2
0
0
0
0
1
1
1
1
RDN1
0
0
1
1
0
0
1
1
RDN0
0
1
0
1
0
1
0
1
LENGTH SELECTED
1 bits
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
8 : 16 bits
144 of 273
2
RDN2
0
1
RDN1
0
0
RDN0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
E1RCR2 (E1 Mode)
Receive Control Register 2
082h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RSa7S
0
7
RSa8S
0
5
RSa6S
0
4
RSa5S
0
3
RSa4S
0
2
—
0
1
—
0
0
RLOSA
0
Note: This register has an alternate definition for T1 mode. See T1RIBCC.
Bit 7: Sa8 Bit Select (RSa8S). Set to one to have RLCLK pulse at the Sa8 bit position; set to zero to force RLCLK
low during Sa8 bit position.
Bit 6: Sa7 Bit Select (RSa7S). Set to one to have RLCLK pulse at the Sa7 bit position; set to zero to force RLCLK
low during Sa7 bit position.
Bit 5: Sa6 Bit Select (RSa6S). Set to one to have RLCLK pulse at the Sa6 bit position; set to zero to force RLCLK
low during Sa6 bit position.
Bit 4: Sa5 Bit Select (RSa5S). Set to one to have RLCLK pulse at the Sa5 bit position; set to zero to force RLCLK
low during Sa5 bit position.
Bit 3: Sa4 Bit Select (RSa4S). Set to one to have RLCLK pulse at the Sa4 bit position; set to zero to force RLCLK
low during Sa4 bit position.
Bit 0: Receive Loss of Signal Alternate Criteria (RLOSA). Defines the criteria for a loss-of-signal condition.
0 = LOS declared upon 255 consecutive zeros (125µs)
1 = LOS declared upon 2048 consecutive zeros (1ms)
145 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
IDF
0
RCR3
Receive Control Register 3
083h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
RSERC
0
4
—
0
3
—
0
2
—
0
1
PLB
0
0
FLB
0
Bit 7: Input Data Format (IDF).
0 = bipolar data is expected at RTIP and RRING (either AMI or B8ZS)
1 = NRZ data is expected at RTIP. The BPV counter will be disabled and RRING will be ignored by the
DS26524.
Bit 5: RSER Control (RSERC).
0 = allow RSER to output data as received under all conditions (normal operation)
1 = force RSER to one under loss of frame alignment conditions
Bit 1: Payload Loopback (PLB).
0 = loopback disabled
1 = loopback enabled
When PLB is enabled, the following will occur:
1) Data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of TCLK.
2) All the receive-side signals will continue to operate normally.
3) The TCHCLK and TCHBLK signals are forced low.
4) Data at the TSER, TDATA, and TSIG pins is ignored.
5) The TLCLK signal will become synchronous with RCLK instead of TCLK.
In a PLB situation, the DS26524 loops the 192 bits (248 for E1) of payload data (with BPVs corrected) from the
receive section back to the transmit section. The transmitter follows the frame alignment provided by the receiver.
The receive frame boundary is automatically fed into the transmit section, such that the transmit frame position is
locked to the receiver (i.e., TSYNC is sourced from RSYNC). The FPS framing pattern, CRC-6 calculation, and the
FDL bits (FAS word, Si, Sa, E-bits, and CRC-4 for E1) are not looped back. Rather, they are reinserted by the
DS26524 (i.e., the transmit section will modify the payload as if it was input at TSER).
Bit 0: Framer Loopback (FLB).
0 = loopback disabled
1 = loopback enabled
This loopback is useful in testing and debugging applications. In FLB, the DS26524 loops data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1) (T1 mode) An unframed all-ones code will be transmitted at TTIP and TRING.
(E1 mode) Normal data will be transmitted at TTIP and TRING.
2) Data at RTIP and RRING will be ignored.
3) All receive-side signals will take on timing synchronous with TCLK instead of RCLK.
4) Note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an
unstable condition.
146 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RIOCR
Receive I/O Configuration Register
084h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
6
5
4
RCLKINV
RCLKINV
RSYNCINV
RSYNCINV
H100EN
H100EN
RSCLKM
RSCLKM
0
0
0
0
3
RSMS
—
0
2
RSIO
RSIO
1
1
RSMS2
RSMS2
0
0
RSMS1
RSMS1
0
Bit 7: RCLK Invert (RCLKINV).
0 = no inversion
1 = invert RCLK as input
Bit 6: RSYNC Invert (RSYNCINV).
0 = no inversion
1 = invert RSYNC as either input or output
Bit 5: H.100 SYNC Mode (H100EN). See Section 8.8.3 for more information.
0 = normal operation
1 = RSYNC and TSSYNCIO signals are shifted
Bit 4: RSYSCLK Mode Select (RSCLKM).
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz or IBO enabled
Bit 3: RSYNC Multiframe Skip Control (RSMS) (T1 Mode Only). Useful in framing format conversions from D4 to
ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output
multiframe pulses.
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe
Bit 2: RSYNC I/O Select (RSIO). (Note: This bit must be set to zero when elastic store is disabled) The default
value for this bit is a logic 1 so that the default state of RSYNC is as an input.
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
Bit 1: RSYNC Mode Select 2 (RSMS2).
T1 Mode: RSYNC pin must be programmed in the output frame mode.
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
E1 Mode: RSYNC pin must be programmed in the output multiframe mode.
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC-4 multiframe boundaries
In E1 mode, RSMS2 also selects which multiframe signal is available at the RMSYNC pin, regardless of the
configuration for RSYNC. When RSMS2 = 0, RMSYNC outputs CAS multiframe boundaries; when RSMS2 = 1,
RMSYNC outputs CRC-4 multiframe boundaries.
Bit 0: RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In
input mode (elastic store must be enabled) multiframe mode is only useful when receive-signaling reinsertion is
enabled.
0 = frame mode
1 = multiframe mode
147 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RESCR
Receive Elastic Store Control Register
085h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
6
RDATFMT
RGCLKEN
0
0
5
—
0
4
RSZS
0
3
RESALGN
0
2
RESR
0
1
RESMDM
0
0
RESE
0
Bit 7: Receive Channel Data Format (RDATFMT).
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in 7 out of the 8 bits)
Bit 6: Receive Gapped Clock Enable (RGCLKEN).
0 = RCHCLK functions normally
1 = Enable gapped bit clock output on RCHCLK
Note: RGPCKEN and RDATFMT are not associated with the elastic store and are explained in the fractional
support section.
Bit 4: Receive Slip Zone Select (RSZS). This bit determines the minimum distance allowed between the elastic
store read and write pointers before forcing a controlled slip. This bit only applies during T1-to-E1 or E1-to-T1
conversion applications.
0 = force a slip at 9 bytes or less of separation (used for clustered blank channels)
1 = force a slip at 2 bytes or less of separation (used for distributed blank channels and minimum delay
mode)
Bit 3: Receive Elastic Store Align (RESALGN). Setting this bit from 0 to 1 forces the receive elastic store’s
write/read pointers to a minimum separation of half a frame. No action is taken if the pointer separation is already
greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed and the
data is disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again
for a subsequent align.
Bit 2: Receive Elastic Store Reset (RESR). Setting this bit from 0 to 1 forces the read pointer into the same frame
that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the
pointers within the slip zone (see bit 4), then an immediate slip occurs and the pointers move back to opposite
frames. Should be toggled after RSYSCLK has been applied and is stable. Do not leave this bit set HIGH.
Bit 1: Receive Elastic Store Minimum Delay Mode (RESMDM).
0 = elastic stores operate at full two-frame depth
1 = elastic stores operate at 32-bit depth
Bit 0: Receive Elastic Store Enable (RESE).
0 = elastic store is bypassed
1 = elastic store is enabled
148 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
1SECS
1SECS
0
ERCNT
Error-Counter Configuration Register
086h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
MCUS
MCUS
0
5
MECU
MECU
0
4
ECUS
ECUS
0
3
EAMS
EAMS
0
2
FSBE
—
0
1
MOSCRF
—
0
0
LCVCRF
LCVCRF
0
Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between
multiple ports. When ERCNT.3 = 0, setting this bit (on a specific framer) will update the framer’s error counters on
the transition of the one-second timer from framer 1. Note that this bit should always be clear for framer 1.
0 = use the one-second timer that is internal to the framer
1 = use the one-second timer from framer 1 to latch updates
Bit 6: Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be
used to allow the incoming LATCH_CNT signal to latch all counters.
0 = MECU is used to manually latch counters
1 = counters are latched on the rising edge of the LATCH_CNT signal
Bit 5: Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from 0 to 1
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The
user must wait a minimum of 250µs before reading the error count registers to allow for proper update.
Bit 4: Error Counter Update Select (ECUS).
T1 Mode:
0 = update error counters once a second
1 = update error counters every 42ms (333 frames)
E1 Mode:
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
Bit 3: Error Accumulation Mode Select (EAMS).
0 = automatic updating of error counters enabled. The state of ERCNT.4 determines accumulation time
(timed update)
1 = user toggling of ERCNT.5 determines accumulation time (manual update)
Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE) (T1 Mode Only).
0 = do not report bit errors in Fs-bit position; only Ft-bit position
1 = report bit errors in Fs-bit position as well as Ft-bit position
Bit 1: Multiframe Out of Sync Count Register Function Select (MOSCRF) (T1 Mode Only).
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
Bit 0: T1 Line Code Violation Count Register Function Select (LCVCRF).
0 = do not count excessive zeros
1 = count excessive zeros
149 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RHFC
Receive HDLC FIFO Control Register
087h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
Bits 1 and 0: Receive FIFO High Watermark Select (RFHWM[1:0]).
RFHWM1
RFHWM0
0
0
1
1
0
1
0
1
RECEIVE FIFO WATERMARK
(BYTES)
4
16
32
48
150 of 273
2
—
0
1
RFHWM1
0
0
RFHWM0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RIBOC
Receive Interleave Bus Operation Control Register
088h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
—
0
6
IBS1
0
5
IBS0
0
4
IBOSEL
0
3
IBOEN
0
2
DA2
0
1
DA1
0
Bits 6 and 5: IBO Bus Size Bits (IBS[1:0]). Indicates how many devices on the bus.
IBS1
0
0
1
1
IBS0
0
1
0
1
BUS SIZE
2 devices on bus (4.096MHz)
4 devices on bus (8.192MHz)
8 devices on bus (16.384MHz)
Reserved for future use
Bit 4: Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode.
0 = Channel Interleave
1 = Frame Interleave
Bit 3: Interleave Bus Operation Enable (IBOEN).
0 = interleave bus operation disabled
1 = interleave bus operation enabled
Bits 2 to 0: Device Assignment Bits (DA[2:0]).
DA2
0
0
0
0
1
1
1
1
DA1
0
0
1
1
0
0
1
1
DA0
0
1
0
1
0
1
0
1
DEVICE POSITION
1st device on bus
2nd device on bus
3rd device on bus
4th device on bus
5th device on bus
6th device on bus
7th device on bus
8th device on bus
151 of 273
0
DA0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
T1RSCC (T1 Mode Only)
In-Band Receive Spare Control Register
089h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
2
RSC2
0
1
RSC1
0
0
RSC0
0
1
RBPFUS
—
0
0
RBPEN
RBPEN
0
Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0]).
RSC2
RSC1
RSC0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LENGTH SELECTED
(BITS)
1
2
3
4
5
6
7
8:16
RXPC
Receive Expansion Port Control Register
08Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
6
5
4
—
—
—
—
—
—
—
—
0
0
0
0
3
—
—
0
2
RBPDIR
RBPDIR
0
Bit 2: Receive BERT Port Direction Control (RBPDIR).
0 = Normal (line) operation. Receive BERT port receives data from the receive framer.
1 = System (backplane) operation. Receive BERT port receives data from the transmit path. The transmit
path enters the receive BERT on the line side of the elastic store (if enabled).
Bit 1: Receive BERT Port Framed/Unframed Select (RBPFUS) (T1 Mode Only).
0 = The receive BERT will not clock data from the F-bit position (framed).
1 = The receive BERT will clock data from the F-bit position (unframed).
Bit 0: Receive BERT Port Enable (RBPEN).
0 = Receive BERT port is not active.
1 = Receive BERT port is active.
152 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RBPBS
Receive BERT Port Bit Suppress Register
08Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
BPBSE7
0
7
BPBSE8
0
5
BPBSE6
0
4
BPBSE5
0
3
BPBSE4
0
2
BPBSE3
0
1
BPBSE2
0
0
BPBSE1
0
Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being
used.
Bit 6: Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
Bit 5: Receive Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used.
Bit 4: Receive Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used.
Bit 3: Receive Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used.
Bit 2: Receive Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used.
Bit 1: Receive Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used.
Bit 0: Receive Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being
used.
153 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RLS1
Receive Latched Status Register 1
090h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RAISC
0
7
RRAIC
0
5
RLOSC
0
4
RLOFC
0
3
RRAID
0
2
RAISD
0
1
RLOSD
0
0
RLOFD
0
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a
RRAI condition has cleared.
Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC). Falling edge detect of RAIS. Set when a RAIS
condition has cleared.
Bit 5: Receive Loss of Signal Condition Clear (RLOSC). Falling edge detect of RLOS. Set when an RLOS
condition has cleared.
Bit 4: Receive Loss of Frame Condition Clear (RLOFC). Falling edge detect of RLOF. Set when an RLOF
condition has cleared.
Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID). Rising edge detect of RRAI. Set when a
remote alarm is received at RTIP and RRING.
Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD). Rising edge detect of RAIS.Set when an
unframed all-ones code is received at RTIP and RRING.
Bit 1: Receive Loss of Signal Condition Detect (RLOSD). Rising edge detect of RLOS. Set when 192
consecutive zeros have been detected at RTIP and RRING.
Bit 0: Receive Loss of Frame Condition Detect (RLOFD). Rising edge detect of RLOF. Set when the DS26524
has lost synchronized to the received data stream.
154 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPDV
0
RLS2 (T1 Mode)
Receive Latched Status Register 2
091h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
COFA
0
4
8ZD
0
3
16ZD
0
2
SEFE
0
1
B8ZS
0
0
FBE
0
Note: All bits in these register are latched. This register does not create interrupts. See RLS2 for E1 mode.
Bit 7: Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI
T1.403 requirements for pulse density.
Bit 5: Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or
multiframe alignment.
Bit 4: Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the
length of the string) have been received.
Bit 3: Sixteen Zero Detect Event (16ZD). Set when a string of at least 16 consecutive zeros (regardless of the
length of the string) have been received.
Bit 2: Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in
error.
Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RTIP and RRING
independent of whether the B8ZS mode is selected or not. Useful for automatically setting the line coding.
Bit 0: Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
155 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RLS2 (E1 Mode)
Receive Latched Status Register 2
091h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
CRCRC
0
7
—
0
5
CASRC
0
4
FASRC
0
3
RSA1
0
2
RSA0
0
1
RCMF
0
0
RAF
0
Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See RLS2 for T1 mode.
Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error.
Bit 5: CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are
received in error.
Bit 4: FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.
Bit 3: Receive-Signaling All-Ones Event (RSA1). Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 2: Receive-Signaling All-Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros.
Bit 1: Receive CRC-4 Multiframe Event (RCMF). Set on CRC-4 multiframe boundaries. This bit continues to be
set every 2ms on an arbitrary boundary if CRC-4 is disabled.
Bit 0: Receive Align Frame Event (RAF). Set approximately every 250µs to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LORCC
0
RLS3 (T1 Mode)
Receive Latched Status Register 3
092h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
LSPC
0
5
LDNC
0
4
LUPC
0
3
LORCD
0
2
LSPD
0
1
LDND
0
0
LUPD
0
Note: All bits in this register are latched and can create interrupts. See RLS3 for E1 mode.
Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when an LORC
condition was detected and then removed.
Bit 6: Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match
condition was detected and then removed.
Bit 5: Loop-Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down
condition was detected and then removed
Bit 4: Loop-Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up
condition was detected and then removed.
Bit 3: Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLK pin
has not transitioned for one channel time.
Bit 2: Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as
defined in the T1RSCD1:T1RSCD2 registers is being received.
Bit 1: Loop-Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loopdown code as defined in the T1RDNCD1:T1RDNCD2 register is being received.
Bit 0: Loop-Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop-up code
as defined in the T1RUPCD1:T1RUPCD2 register is being received.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LORCC
0
RLS3 (E1 Mode)
Receive Latched Status Register 3
092h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
V52LNKC
0
4
RDMAC
0
3
LORCD
0
2
—
0
1
V52LNKD
0
0
RDMAD
0
Note: All bits in this register are latched and can create interrupts. See RLS3 for T1 mode.
Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has
cleared (falling edge detect of LORC)
Bit 5: V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has
cleared (falling edge detect of V52LNK).
Bit 4: Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when an RDMA condition has
cleared (falling edge detect of RDMA).
Bit 3: Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLK pin has not
transitioned for one channel time (rising edge detect of LORC).
Bit 1: V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal.
(G.965). This is the rising edge detect of V52LNK.
Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit 6 of time slot 16 in
frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This
is the rising edge detect of RDMA.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RLS4
Receive Latched Status Register 4
093h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RESEM
0
7
RESF
0
5
RSLIP
0
4
—
0
3
RSCOS
0
2
1SEC
0
1
TIMER
0
0
RMF
0
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is
deleted.
Bit 6: Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a
frame is repeated.
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either
repeated or deleted a frame.
Bit 3: Receive-Signaling Change-of-State Event (RSCOS). Set when any channel selected by the ReceiveSignaling Change-of-State Interrupt Enable registers (RSCSE1:RSCSE3) changes signaling state.
Bit 2: One-Second Timer (1SEC). Set on every one-second interval based on RCLK.
Bit 1: Timer Event (TIMER). This status bit indicates that the performance monitor counters have been updated
and are available to be read by the host. The error counter update interval as determined by the settings in the
Error Counter Configuration register (ERCNT).
T1 Mode: Set on increments of one second or 42ms based on RCLK, or a manual latch event.
E1 Mode: Set on increments of one second or 62.5ms based on RCLK, or a manual latch event.
Bit 0: Receive Multiframe Event (RMF).
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
E1 Mode: Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is
available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.
159 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RLS5
Receive Latched Status Register 5 (HDLC)
094h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
ROVR
0
4
RHOBT
0
3
RPE
0
2
RPS
0
1
RHWMS
0
0
RNES
0
Note: All bits in this register are latched and can cause interrupts.
Bit 5: Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception
because the FIFO buffer is full.
Bit 4: Receive HDLC Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is the
first byte of a message.
Bit 3: Receive Packet-End Event (RPE). Set when the HDLC controller detects either the finish of a valid
message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC
checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when
read.
Bit 2: Receive Packet-Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a
latched bit and will be cleared when read.
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS). Set when the receive 64-byte FIFO crosses
the high watermark as defined by the Receive HDLC FIFO Control register (RHFC). Rising edge detect of RHWM.
Bit 0: Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from empty to not
empty (at least one byte has been put into the FIFO). Rising edge detect of RNE.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RLS7 (T1 Mode)
Receive Latched Status Register 7
096h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
RRAI-CI
0
4
RAIS-CI
0
3
RSLC96
0
2
RFDLF
0
1
BC
0
0
BD
0
Note: All bits in this register are latched and can create interrupts. See RLS7 for E1 mode.
Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver. This bit is
active in ESF framing mode only, and will set only if an RAI condition is being detected (RRTS1.3). When the host
reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1
seconds).
Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit
will set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host,
and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds).
Bit 3: Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the
Fs-bit stream, and the RSLCx registers have data available for retrieval. See Section 8.9.4.5 for more information.
Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit T1RFDL register is full. Useful for SLC-96
operation, or manual extraction of FDL data bits. See Section 8.9.5.4 for more information.
Bit 1: BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied).
Bit 0: BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RLS7 (E1 Mode)
Receive Latched Status Register 7
096h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
Sa6CD
0
0
SaXCD
0
Note: All bits in this register are latched and can create interrupts. See RLS7 for T1 mode.
Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit
positions.
Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled
SaX bits are selected by the E1RSAIMR register.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RSS1, RSS2, RSS3, RSS4
Receive-Signaling Status Registers 1 to 4
098h, 099h, 09Ah, 09Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1*
CH9
CH17*
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
RSS1
RSS2
RSS3
RSS4
(E1 Mode
Only)
Note: Status bits in this register are latched.
When a channel’s signaling data changes state, the respective bit in registers RSS1:RSS4 will be set and latched.
The RSCOS bit (RLS4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1:4.
The INTB signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read.
*Note that in E1 CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3
represents reserved bits and the distant multiframe alarm.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1RSCD1 (T1 Mode Only)
Receive Spare Code Definition Register 1
09Ch + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Note: Writing this register resets the detector’s integration period.
Bit 7: Receive Spare Code Definition Bit 7 (C7). First bit of the repeating pattern.
Bit 6: Receive Spare Code Definition Bit 6 (C6). A Don’t Care if a 1-bit length is selected.
Bit 5: Receive Spare Code Definition Bit 5 (C5). A Don’t Care if a 1- or 2-bit length is selected.
Bit 4: Receive Spare Code Definition Bit 4 (C4). A Don’t Care if a 1- to 3-bit length is selected.
Bit 3: Receive Spare Code Definition Bit 3 (C3). A Don’t Care if a 1- to 4-bit length is selected.
Bit 2: Receive Spare Code Definition Bit 2 (C2). A Don’t Care if a 1- to 5-bit length is selected.
Bit 1: Receive Spare Code Definition Bit 1 (C1). A Don’t Care if a 1- to 6-bit length is selected.
Bit 0: Receive Spare Code Definition Bit 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1RSCD2 (T1 Mode Only)
Receive Spare Code Definition Register 2
09Dh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Bit 7: Receive Spare Code Definition Bit 7 (C7). A Don’t Care if a 1- to 7-bit length is selected.
Bit 6: Receive Spare Code Definition Bit 6 (C6). A Don’t Care if a 1- to 7-bit length is selected.
Bit 5: Receive Spare Code Definition Bit 5 (C5). A Don’t Care if a 1- to 7-bit length is selected.
Bit 4: Receive Spare Code Definition Bit 4 (C4). A Don’t Care if a 1- to 7-bit length is selected.
Bit 3: Receive Spare Code Definition Bit 3 (C3). A Don’t Care if a 1- to 7-bit length is selected.
Bit 2: Receive Spare Code Definition Bit 2 (C2). A Don’t Care if a 1- to 7-bit length is selected.
Bit 1: Receive Spare Code Definition Bit 1 (C1). A Don’t Care if a 1- to 7-bit length is selected.
Bit 0: Receive Spare Code Definition Bit 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
163 of 273
0
C0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RIIR
Receive Interrupt Information Register
09Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RLS7
0
5
RLS6*
0
4
RLS5
0
3
RLS4
0
2
RLS3
0
1
RLS2**
0
0
RLS1
0
*RLS6 is reserved for future use.
**Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode.
The Receive Interrupt Information register (RIIR) indicates which of the DS26524 status registers are generating an
interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the receive status registers
is (are) causing the interrupt(s). The RIIR bits clear once the appropriate interrupt has been serviced and cleared,
as long as no additional, unmasked interrupt condition is present in the associated status register. Status bits that
have been masked via the Receive Interrupt Mask (RIMx) registers will also be masked from the RIIR register.
Register Name:
Register Description:
Register Address:
RIM1
Receive Interrupt Mask Register 1
0A0h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RAISC
0
7
RRAIC
0
5
RLOSC
0
4
RLOFC
0
3
RRAID
0
Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Receive Loss of Signal Condition Clear (RLOSC).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive Loss of Frame Condition Clear (RLOFC).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Receive Loss of Signal Condition Detect (RLOSD).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Loss of Frame Condition Detect (RLOFD).
0 = interrupt masked
1 = interrupt enabled
164 of 273
2
RAISD
0
1
RLOSD
0
0
RLOFD
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RIM2 (E1 Mode Only)
Receive Interrupt Mask Register 2
0A1h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
Bit 3: Receive-Signaling All-Ones Event (RSA1).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive-Signaling All-Zeros Event (RSA0).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Receive CRC-4 Multiframe Event (RCMF).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Align Frame Event (RAF).
0 = interrupt masked
1 = interrupt enabled
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3
RSA1
0
2
RSA0
0
1
RCMF
0
0
RAF
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LORCC
0
RIM3 (T1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
LSPC
0
5
LDNC
0
4
LUPC
0
Note: For E1 mode, see RIM3.
Bit 7: Loss of Receive Clock Condition Clear (LORCC).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Spare Code Detected Condition Clear (LSPC).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Loop-Down Code Detected Condition Clear (LDNC).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Loop-Up Code Detected Condition Clear (LUPC).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Loss of Receive Clock Condition Detect (LORCD).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Spare Code Detected Condition Detect (LSPD).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Loop-Down Code Detected Condition Detect (LDND).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Loop-Up Code Detected Condition Detect (LUPD).
0 = interrupt masked
1 = interrupt enabled
166 of 273
3
LORCD
0
2
LSPD
0
1
LDND
0
0
LUPD
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LORCC
0
RIM3 (E1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
V52LNKC
0
4
RDMAC
0
Note: For T1 mode, see RIM3.
Bit 7: Loss of Receive Clock Clear (LORCC).
0 = interrupt masked
1 = interrupt enabled
Bit 5: V5.2 Link Detected Clear (V52LNKC).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive Distant MF Alarm Clear (RDMAC).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Loss of Receive Clock Detect (LORCD).
0 = interrupt masked
1 = interrupt enabled
Bit 1: V5.2 Link Detect (V52LNKD).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Distant MF Alarm Detect (RDMAD).
0 = interrupt masked
1 = interrupt enabled
167 of 273
3
LORCD
0
2
—
0
1
V52LNKD
0
0
RDMAD
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RIM4
Receive Interrupt Mask Register 4
0A3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RESEM
0
7
RESF
0
5
RSLIP
0
4
—
0
Bit 7: Receive Elastic Store Full Event (RESF).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Receive Elastic Store Empty Event (RESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive-Signaling Change-of-State Event (RSCOS).
0 = interrupt masked
1 = interrupt enabled
Bit 2: One-Second Timer (1SEC).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Timer Event (TIMER).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Multiframe Event (RMF).
0 = interrupt masked
1 = interrupt enabled
168 of 273
3
RSCOS
0
2
1SEC
0
1
TIMER
0
0
RMF
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RIM5
Receive Interrupt Mask Register 5 (HDLC)
0A4h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
ROVR
0
4
RHOBT
0
3
RPE
0
Bit 5: Receive FIFO Overrun (ROVR).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive HDLC Opening Byte Event (RHOBT).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive Packet-End Event (RPE).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive Packet-Start Event (RPS).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive FIFO Not Empty Set Event (RNES).
0 = interrupt masked
1 = interrupt enabled
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2
RPS
0
1
RHWMS
0
0
RNES
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RIM7 (T1 Mode)
Receive Interrupt Mask Register 7 (BOC:FDL)
0A6h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
RRAI-CI
0
4
RAIS-CI
0
3
RSLC96
0
2
RFDLF
0
1
BC
0
0
BD
0
2
—
0
1
Sa6CD
0
0
SaXCD
0
Note: For E1 mode, see RIM7.
Bit 5: Receive RAI-CI (RRAI-CI).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive AIS-CI (RAIS-CI).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive SLC-96 (RSLC96).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive FDL Register Full (RFDLF).
0 = interrupt masked
1 = interrupt enabled
Bit 1: BOC Clear Event (BC).
0 = interrupt masked
1 = interrupt enabled
Bit 0: BOC Detect Event (BD).
0 = interrupt masked
1 = interrupt enabled
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RIM7 (E1 Mode)
Receive Interrupt Mask Register 7 (BOC:FDL)
A6h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
Note: For T1 mode, see RIM7.
Bit 1: Sa6 Codeword Detect. This bit will enable the interrupt generated when a valid codeword (per ETS 300
233) is detected in the Sa6 bits.
0 = interrupt masked
1 = interrupt enabled
Bit 0: SaX Change Detect. This bit will enable the interrupt generated when a change of state is detected in any of
the unmasked SaX bit positions. The masked or unmasked SaX bits are selected by the E1RSAIMR register.
0 = interrupt masked
1 = interrupt enabled
170 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RSCSE1, RSCSE2, RSCSE3, RSCSE4
Receive-Signaling Change of State Enable Registers 1 to 4
0A8h, 0A9h, 0AAh, 0Abh + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
RSCSE1
RSCSE2
RSCSE3
RSCSE4
(E1 Mode
Only)
Setting any of the CH[1:32] bits in the RSCSE1:RSCSE4 registers will cause RSCOS (RLS4.3) to be set when that
channel’s signaling data changes state.
171 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1RUPCD1 (T1 Mode Only)
Receive Up Code Definition Register 1
0ACh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
1
C1
0
0
C0
0
Note: Writing this register resets the detector’s integration period.
Bit 7: Receive Up Code Definition Bit 7 (C7). First bit of the repeating pattern.
Bit 6: Receive Up Code Definition Bit 6 (C6). A Don’t Care if a 1-bit length is selected.
Bit 5: Receive Up Code Definition Bit 5 (C5). A Don’t Care if a 1- or 2-bit length is selected.
Bit 4: Receive Up Code Definition Bit 4 (C4). A Don’t Care if a 1- to 3-bit length is selected.
Bit 3: Receive Up Code Definition Bit 3 (C3). A Don’t Care if a 1- to 4-bit length is selected.
Bit 2: Receive Up Code Definition Bit 2 (C2). A Don’t Care if a 1- to 5-bit length is selected.
Bit 1: Receive Up Code Definition Bit 1 (C1). A Don’t Care if a 1- to 6-bit length is selected.
Bit 0: Receive Up Code Definition Bit 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1RUPCD2 (T1 Mode Only)
Receive Up Code Definition Register 2
0ADh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
Bit 7: Receive Up Code Definition Bit 7 (C7). A Don’t Care if a 1- to 7-bit length is selected.
Bit 6: Receive Up Code Definition Bit 6 (C6). A Don’t Care if a 1- to 7-bit length is selected.
Bit 5: Receive Up Code Definition Bit 5 (C5). A Don’t Care if a 1- to 7-bit length is selected.
Bit 4: Receive Up Code Definition Bit 4 (C4). A Don’t Care if a 1- to 7-bit length is selected.
Bit 3: Receive Up Code Definition Bit 3 (C3). A Don’t Care if a 1- to 7-bit length is selected.
Bit 2: Receive Up Code Definition Bit 2 (C2). A Don’t Care if a 1- to 7-bit length is selected.
Bit 1: Receive Up Code Definition Bit 1 (C1). A Don’t Care if a 1- to 7-bit length is selected.
Bit 0: Receive Up Code Definition Bit 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1RDNCD1 (T1 Mode Only)
Receive Down Code Definition Register 1
0AEh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Note: Writing this register resets the detector’s integration period.
Bit 7: Receive Down Code Definition Bit 7 (C7). First bit of the repeating pattern.
Bit 6: Receive Down Code Definition Bit 6 (C6). A Don’t Care if a 1-bit length is selected.
Bit 5: Receive Down Code Definition Bit 5 (C5). A Don’t Care if a 1- or 2-bit length is selected.
Bit 4: Receive Down Code Definition Bit 4 (C4). A Don’t Care if a 1- to 3-bit length is selected.
Bit 3: Receive Down Code Definition Bit 3 (C3). A Don’t Care if a 1- to 4-bit length is selected.
Bit 2: Receive Down Code Definition Bit 2 (C2). A Don’t Care if a 1- to 5-bit length is selected.
Bit 1: Receive Down Code Definition Bit 1 (C1). A Don’t Care if a 1- to 6-bit length is selected.
Bit 0: Receive Down Code Definition Bit 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1RDNCD2 (T1 Mode Only)
Receive Down Code Definition Register 2
0AFh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Bit 7: Receive Down Code Definition Bit 7 (C7). A Don’t Care if a 1- to 7-bit length is selected.
Bit 6: Receive Down Code Definition Bit 6 (C6). A Don’t Care if a 1- to 7-bit length is selected.
Bit 5: Receive Down Code Definition Bit 5 (C5). A Don’t Care if a 1- to 7-bit length is selected.
Bit 4: Receive Down Code Definition Bit 4 (C4). A Don’t Care if a 1- to 7-bit length is selected.
Bit 3: Receive Down Code Definition Bit 3 (C3). A Don’t Care if a 1- to 7-bit length is selected.
Bit 2: Receive Down Code Definition Bit 2 (C2). A Don’t Care if a 1- to 7-bit length is selected.
Bit 1: Receive Down Code Definition Bit 1 (C1). A Don’t Care if a 1- to 7-bit length is selected.
Bit 0: Receive Down Code Definition Bit 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
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0
C0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RRTS1
Receive Real-Time Status Register 1
0B0h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
RRAI
0
2
RAIS
0
1
RLOS
0
0
RLOF
0
Note: All bits in this register are real-time (not latched).
Bit 3: Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RTIP and
RRING.
Bit 2: Receive Alarm Indication Signal Condition (RAIS). Set when an unframed all-ones code is received at
RTIP and RRING.
Bit 1: Receive Loss of Signal Condition (RLOS). Set when 192 consecutive zeros have been detected after the
B8ZS/HDB3 decoder.
Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26524 is not synchronized to the received
data stream.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RRTS3 (T1 Mode)
Receive Real-Time Status Register 3
0B2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
LORC
0
2
LSP
0
1
LDN
0
0
LUP
0
Note: All bits in this register are real-time (not latched). See RRTS3 for E1 mode.
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 2: Spare Code Detected Condition (LSP). Set when the spare code as defined in the T1RSCD1:T1RSCD2
registers is being received.
Bit 1: Loop-Down Code Detected Condition (LDN). Set when the loop-down code as defined in the
T1RDNCD1:T1RDNCD2 register is being received.
Bit 0: Loop-Up Code Detected Condition (LUP). Set when the loop-up code as defined in the
T1RUPCD1:T1RUPCD2 register is being received.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RRTS3 (E1 Mode)
Receive Real-Time Status Register 3
0B2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
LORC
0
2
—
0
1
V52LNK
0
0
RDMA
0
Note: All bits in this register are real-time (not latched). See RRTS3 for T1 mode.
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 1: V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal (G.965).
Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit 6 of time slot 16 in frame 0 has been set for
two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
RRTS5
Receive Real-Time Status Register 5 (HDLC)
0B4h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
PS2
0
5
PS1
0
4
PS0
0
3
—
0
2
—
0
1
RHWM
0
0
RNE
0
Note: All bits in this register are real time.
Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of
the receive FIFO.
PS2
0
PS1
0
PS0
0
PACKET STATUS
In Progress: End of message has not yet been reached.
0
0
1
Packet OK: Packet ended with correct CRC codeword.
0
1
0
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
0
1
1
Abort: Packet ended because an abort signal was detected (7 or more ones in a row).
1
0
0
Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond
the high watermark as defined by the Receive HDLC FIFO Control register (RHFC). This is a real-time bit.
Bit 0: Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte
available for a read. This is a real-time bit.
Register Name:
Register Description:
Register Address:
RHPBA
Receive HDLC Packet Bytes Available Register
0B5h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RPBA6
0
7
MS
0
5
RPBA5
0
4
RPBA4
0
3
RPBA3
0
2
RPBA2
0
1
RPBA1
0
0
RPBA0
0
Bit 7: Message Status (MS).
0 = Bytes indicated by RPBA[6:0] are the end of a message. Host must check the HDLC status register for
details.
1 = Bytes indicated by RPBA[6:0] are the beginning or continuation of a message. The host does not need
to check the HDLC status. The MS bit returns to a value of 1 when the Rx HDLC FIFO is empty.
Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RHD7
0
RHF
Receive HDLC FIFO Register
0B6h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
RHD6
0
5
RHD5
0
4
RHD4
0
3
RHD3
0
2
RHD2
0
1
RHD1
0
0
RHD0
0
Bit 7: Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte.
Bit 6: Receive HDLC Data Bit 6 (RHD6).
Bit 5: Receive HDLC Data Bit 5 (RHD5).
Bit 4: Receive HDLC Data Bit 4 (RHD4).
Bit 3: Receive HDLC Data Bit 3 (RHD3).
Bit 2: Receive HDLC Data Bit 2 (RHD2).
Bit 1: Receive HDLC Data Bit 1 (RHD1).
Bit 0: Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RBCS1, RBCS2, RBCS3, RBCS4
Receive Blank Channel Select Registers 1 to 4
0C0h, 0C1h, 0C2h, 0C3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
RBCS1
RBCS2
RBCS3
RBCS4
(E1 Mode
Only)
Bit 7 to 0: Receive Blank Channel Select for Channels 1 to 32 (CH[1:32]).
0 = Do not blank this channel (channel data is available on RSER)
1 = Data on RSER is forced to all ones for this channel
Note that when two or more sequential channels are chosen to be blanked, the receive-slip zone select bit should
be set to 0. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to 1,
which may provide a lower occurrence of slips in certain applications.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RCBR1, RCBR2, RCBR3, RCBR4
Receive Channel Blocking Registers 1 to 4
0C4h, 0C5h, 0C6h, 0C7h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
(F-bit)
0
0
0
0
0
0
0
0
RCBR1
RCBR2
RCBR3
RCBR4*
(E1 Mode
Only)
Bits 7 to 0: Receive Channel Blocking Control Bits for Channels 1 to 32 (CH[1:32]).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
*Note that RCBR4 has two functions:
When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking
signal for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the
RCHBLK signal will pulse high during the F-Bit time. In this mode, RCBR4.1:RCBR4.7 should be set to 0.
RCBR4.0 = 0, do not pulse RCHBLK during the F-bit.
RCBR4.0 = 1, pulse RCHBLK during the F-bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RSI1, RSI2, RSI3, RSI4
Receive-Signaling Reinsertion Enable Registers 1 to 4
0C8h, 0C9h, 0CAh, 0CBh + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
RSI1
RSI2
RSI3
RSI4
(E1 Mode
Only)
Setting any of the CH[1:24] bits in the RSI1:RSI3 registers causes signaling data to be reinserted for the associated
channel. RSI4 is used for 2.048MHz backplane operation.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RGCCS1, RGCCS2, RGCCS3, RGCCS4
Receive Gapped-Clock Channel Select Registers 1 to 4
0CCh, 0CDh, 0CEh, 0CFh + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
(F-bit)
0
0
0
0
0
0
0
0
RGCCS1
RGCCS2
RGCCS3
RGCCS4*
(E1 Mode
Only)
Bits 7 to 0: Receive Gapped Clock Channel Select Bits for Channels 1 to 32 (CH[1:32]).
0 = no clock is present on RCHCLK during this channel time
1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the
elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled.
*Note that RGCCS4 has two functions:
When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on
RCHCLK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is
generated on RCHCLK during the F-bit time:
RGCCS4.0 = 0, do not generate a clock during the F-bit.
RGCCS4.0 = 1, generate a clock during the F-bit.
In this mode, RGCCS4.1:RGCCS4.7 should be set to 0.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RCICE1, RCICE2, RCICE3, RCICE4
Receive Channel Idle Code Enable Registers 1 to 4
0D0h, 0D1h, 0D2h, 0D3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
Bits 7 to 0: Receive Channel Idle Code Insertion Control Bits for Channels 1 to 32 (CH[1:32]).
0 = do not insert data from the Idle Code Array into the receive data stream
1 = insert data from the Idle Code Array into the receive data stream
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RCICE1
RCICE2
RCICE3
RCICE4
(E1 Mode
Only)
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
RBPCS1, RBPCS2, RBPCS3, RBPCS4
Receive BERT Port Channel Select Registers 1 to 4
0D4h, 0D5h, 0D6h, 0D7h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
RBPCS1
RBPCS2
RBPCS3
RBPCS4
(E1 Mode
Only)
Bits 7 to 0: BERT Port Channel Select Receive Channels 1 to 32 (CH[1:32]).
0 = Do not enable the receive BERT clock for the associated channel time, or map the selected channel
data out of the receive BERT port.
1 = Enable the receive BERT clock for the associated channel time, and allow mapping of the selected
channel data out of the receive BERT port. Multiple or all channels may be selected simultaneously.
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DS26524 Quad T1/E1/J1 Transceiver
9.4.2
Transmit Register Definitions
Register Name:
Register Description:
Register Address:
THC1
Transmit HDLC Control Register 1
110h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TEOML
0
7
NOFS
0
5
THR
0
4
THMS
0
3
TFS
0
2
TEOM
0
1
TZSD
0
0
TCRCD
0
Bit 7: Number of Flags Select (NOFS).
0 = send one flag between consecutive messages
1 = send two flags between consecutive messages
Bit 6: Transmit End of Message and Loop (TEOML). To loop on a message, this bit should be set to a one just
before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the
user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message
will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop
by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new
message will start. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to the
end of all messages.
Bit 5: Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort
followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the
FIFO. This is an acknowledged reset, that is, the host need only to set the bit and the DS26524 will clear it once
the reset operation is complete. Total time for the reset is less than 250µs.
0 = Normal operation
1 = Reset transmit HDLC controller and flush the transmit FIFO
Bit 4: Transmit HDLC Mapping Select (THMS).
0 = Transmit HDLC assigned to channels
1 = Transmit HDLC assigned to FDL (T1 mode), Sa bits (E1 mode). This mode must be enabled with
TCR2.7.
Bit 3: Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before
the opening flags (7Eh).
0 = 7Eh
1 = FFh
Bit 2: Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet
is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a
2-byte CRC code to the end of the message.
Bit 1: Transmit Zero Stuffer Defeat (TZSD). The zero stuffer function automatically inserts a zero in the message
field (between the flags) after five consecutive ones to prevent the emulation of a flag or abort sequence by the
data pattern. The receiver automatically removes (destuffs) any zero after five ones in the message field.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Bit 0: Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message.
This bit can be used to disable the CRC function.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
THBSE
Transmit HDLC Bit Suppress Register
111h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TBSE7
0
7
TBSE8
0
5
TBSE6
0
4
TBSE5
0
3
TBSE4
0
2
TBSE3
0
1
TBSE2
0
0
TBSE1
0
Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used.
Bit 6: Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used.
Bit 5: Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used.
Bit 4: Transmit Bit 5 Suppress (TBSE5). Set to one to stop this bit from being used.
Bit 3: Transmit Bit 4 Suppress (TBSE4). Set to one to stop this bit from being used.
Bit 2: Transmit Bit 3 Suppress (TBSE3). Set to one to stop this bit from being used.
Bit 1: Transmit Bit 2 Suppress (TBSE2). Set to one to stop this bit from being used.
Bit 0: Transmit Bit 1 Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TABT
TABT
0
THC2
Transmit HDLC Control Register 2
113h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
SBOC
—
0
5
THCEN
THCEN
0
4
THCS4
THCS4
0
3
THCS3
THCS3
0
2
THCS2
THCS2
0
1
THCS1
THCS1
0
0
THCS0
THCS0
0
Bit 7: Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to
be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be
cleared and set again for a subsequent abort to be sent.
Bit 6: Send BOC (SBOC) (T1 Mode Only). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the T1TBOC
register.
Bit 5: Transmit HDLC Controller Enable (THCEN).
0 = Transmit HDLC controller is not enabled.
1 = Transmit HDLC controller is enabled.
Bits 4 to 0: Transmit HDLC Channel Select (THCS[4:0]). Determines which DSO channel will carry the HDLC
message if enabled. Changes to this value are acknowledged only upon a transmit HDLC controller reset (THR at
THC1.5).
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SiAF
0
E1TSACR (E1 Mode)
E1 Transmit Sa-Bit Control Register
114h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
SiNAF
0
5
RA
0
4
Sa4
0
3
Sa5
0
2
Sa6
0
Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF).
0 = do not insert data from the TSiAF register into the transmit data stream
1 = insert data from the TSiAF register into the transmit data stream
Bit 6: International Bit in Non-Align Frame Insertion Control Bit (SiNAF).
0 = do not insert data from the TSiNAF register into the transmit data stream
1 = insert data from the TSiNAF register into the transmit data stream
Bit 5: Remote Alarm Insertion Control Bit (RA).
0 = do not insert data from the TRA register into the transmit data stream
1 = insert data from the TRA register into the transmit data stream
Bit 4: Additional Bit 4 Insertion Control Bit (Sa4).
0 = do not insert data from the TSa4 register into the transmit data stream
1 = insert data from the TSa4 register into the transmit data stream
Bit 3: Additional Bit 5 Insertion Control Bit (Sa5).
0 = do not insert data from the TSa5 register into the transmit data stream
1 = insert data from the TSa5 register into the transmit data stream
Bit 2: Additional Bit 6 Insertion Control Bit (Sa6).
0 = do not insert data from the TSa6 register into the transmit data stream
1 = insert data from the TSa6 register into the transmit data stream
Bit 1: Additional Bit 7 Insertion Control Bit (Sa7).
0 = do not insert data from the TSa7 register into the transmit data stream
1 = insert data from the TSa7 register into the transmit data stream
Bit 0: Additional Bit 8 Insertion Control Bit (Sa8).
0 = do not insert data from the TSa8 register into the transmit data stream
1 = insert data from the TSa8 register into the transmit data stream
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1
Sa7
0
0
Sa8
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
SSIE1, SSIE2, SSIE3, SSIE4
Software-Signaling Insertion Enable Registers 1 to 4
118h, 119h, 11Ah, 11Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
Default
SSIE1
SSIE2
SSIE3
SSIE4
(E1 Mode
Only)
Bits 7 to 0: Software Signaling Insertion Enable for Channels 1 to 32 (CH[1:32]). These bits determine which
channels are to have signaling inserted form the transmit-signaling registers.
0 = do not source signaling data from the TS registers for this channel
1 = source signaling data from the TS registers for this channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
TIDR1 to TIDR32
Transmit Idle Code Definition Registers 1 to 32
120h to 13Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
120h is for channel 1, address 13Fh is for channel 32. TIDR1:TIDR24 are T1 mode. TIDR25:TIDR32 are E1 mode.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
T1 Mode:
Bit #
(MSB) 7
Name
CH1-A
CH2-A
CH3-A
CH4-A
CH5-A
CH6-A
CH7-A
CH8-A
CH9-A
CH10-A
CH11-A
CH12-A
TS1 to TS16
Transmit-Signaling Registers 1 to 16
140h to 14Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
CH1-B
CH2-B
CH3-B
CH4-B
CH5-B
CH6-B
CH7-B
CH8-B
CH9-B
CH10-B
CH11-B
CH12-B
5
CH1-C
CH2-C
CH3-C
CH4-C
CH5-C
CH6-C
CH7-C
CH8-C
CH9-C
CH10-C
CH11-C
CH12-C
4
CH1-D
CH2-D
CH3-D
CH4-D
CH5-D
CH6-D
CH7-D
CH8-D
CH9-D
CH10-D
CH11-D
CH12-D
3
CH13-A
CH14-A
CH15-A
CH16-A
CH17-A
CH18-A
CH19-A
CH20-A
CH21-A
CH22-A
CH23-A
CH24-A
2
CH13-B
CH14-B
CH15-B
CH16-B
CH17-B
CH18-B
CH19-B
CH20-B
CH21-B
CH22-B
CH23-B
CH24-B
1
CH13-C
CH14-C
CH15-C
CH16-C
CH17-C
CH18-C
CH19-C
CH20-C
CH21-C
CH22-C
CH23-C
CH24-C
0 (LSB)
CH13-D
CH14-D
CH15-D
CH16-D
CH17-D
CH18-D
CH19-D
CH20-D
CH21-D
CH22-D
CH23-D
CH24-D
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
4
0
CH1-D
CH2-D
CH3-D
CH4-D
CH5-D
CH6-D
CH7-D
CH8-D
CH9-D
CH10-D
CH11-D
CH12-D
CH13-D
CH14-D
CH15-D
3
X
CH16-A
CH17-A
CH18-A
CH19-A
CH20-A
CH21-A
CH22-A
CH23-A
CH24-A
CH25-A
CH26-A
CH27-A
CH28-A
CH29-A
CH30-A
2
Y
CH16-B
CH17-B
CH18-B
CH19-B
CH20-B
CH21-B
CH22-B
CH23-B
CH24-B
CH25-B
CH26-B
CH27-B
CH28-B
CH29-B
CH30-B
1
X
CH16-C
CH17-C
CH18-C
CH19-C
CH20-C
CH21-C
CH22-C
CH23-C
CH24-C
CH25-C
CH26-C
CH27-C
CH28-C
CH29-C
CH30-C
0 (LSB)
X
CH16-D
CH17-D
CH18-D
CH19-D
CH20-D
CH21-D
CH22-D
CH23-D
CH24-D
CH25-D
CH26-D
CH27-D
CH28-D
CH29-D
CH30-D
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
Note: In D4 framing mode, the C and D bits are not used.
E1 Mode:
Bit #
(MSB) 7
Name
0
CH1-A
CH2-A
CH3-A
CH4-A
CH5-A
CH6-A
CH7-A
CH8-A
CH9-A
CH10-A
CH11-A
CH12-A
CH13-A
CH14-A
CH15-A
6
0
CH1-B
CH2-B
CH3-B
CH4-B
CH5-B
CH6-B
CH7-B
CH8-B
CH9-B
CH10-B
CH11-B
CH12-B
CH13-B
CH14-B
CH15-B
5
0
CH1-C
CH2-C
CH3-C
CH4-C
CH5-C
CH6-C
CH7-C
CH8-C
CH9-C
CH10-C
CH11-C
CH12-C
CH13-C
CH14-C
CH15-C
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TCICE1, TCICE2, TCICE3, TCICE4
Transmit Channel Idle Code Enable Registers 1 to 4
150h, 151h, 152h, 153h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
TCICE1
TCICE2
TCICE3
TCICE4
(E1 Mode
Only)
The Transmit Channel Idle Code Enable registers (TCICE1:TCICE4) are used to determine which of the 24 T1
channels (or 32 E1 channels) from the backplane should be overwritten with the code placed in the Transmit Idle
Code Definition register (TIDR1:TIDR32).
Bits 7 to 0: Transmit Channels 1 to 32 Code Insertion Control Bits (CH[1:32]).
0 = do not insert data from the Idle Code Array into the transmit data stream
1 = insert data from the Idle Code Array into the transmit data stream
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FR7
0
TFRID
Transmit Firmware Revision ID Register
161h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
FR6
0
5
FR5
0
4
FR4
0
3
FR3
0
2
FR2
0
1
FR1
0
0
FR0
0
Bits 7 to 0: Firmware Revision (FR[7:0]). This read-only register reports the transmitter firmware revision.
Register Name:
Register Description:
Register Address:
T1TFDL (T1 Mode)
Transmit FDL Register
162h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TFDL6
0
7
TFDL7
0
5
TFDL5
0
4
TFDL4
0
3
TFDL3
0
2
TFDL2
0
1
TFDL1
0
0
TFDL0
0
Note: Also used to insert Fs framing pattern in D4 framing mode.
The Transmit FDL register (T1TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a
byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are
used.
Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code.
Bit 6: Transmit FDL Bit 6 (TFDL6).
Bit 5: Transmit FDL Bit 5 (TFDL5).
Bit 4: Transmit FDL Bit 4 (TFDL4).
Bit 3: Transmit FDL Bit 3 (TFDL3).
Bit 2: Transmit FDL Bit 2 (TFDL2).
Bit 1: Transmit FDL Bit 1 (TFDL1).
Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the transmit FDL code.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
T1TBOC (T1 Mode Only)
Transmit BOC Register
163h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
TBOC5
0
4
TBOC4
0
3
TBOC3
0
Bit 5: Transmit BOC Bit 5 (TBOC5). MSB of the transmit BOC code.
Bit 4: Transmit BOC Bit 4 (TBOC4).
Bit 3: Transmit BOC Bit 3 (TBOC3).
Bit 2: Transmit BOC Bit 2 (TBOC2).
Bit 1: Transmit BOC Bit 1 (TBOC1).
Bit 0: Transmit BOC Bit 0 (TBOC0). LSB of the transmit BOC code.
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2
TBOC2
0
1
TBOC1
0
0
TBOC0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode)
Transmit SLC-96 Data Link Registers 1 to 3
164h, 165h, 166h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
6
C7
M1
S4
0
Default
(MSB) 7
C8
M2
S=1
0
5
C6
S=0
S3
0
4
C5
S=1
S2
0
3
C4
S=0
S1
0
2
C3
C11
A2
0
1
C2
C10
A1
0
0 (LSB)
C1
C9
M3
0
T1TSLC1
T1TSLC2
T1TSLC3
Note: See E1TAF, E1TNAF, and E1TSiAF for E1 modes.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
E1TAF (E1 Mode)
Transmit Align Frame Register
164h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
Si
0
6
0
0
5
0
0
4
1
1
3
1
1
2
0
0
1
1
1
0
1
1
2
Sa6
0
1
Sa7
0
0
Sa8
0
Bit 7: International Bit (Si).
Bit 6: Frame Alignment Signal Bit (0).
Bit 5: Frame Alignment Signal Bit (0).
Bit 4: Frame Alignment Signal Bit (1).
Bit 3: Frame Alignment Signal Bit (1).
Bit 2: Frame Alignment Signal Bit (0).
Bit 1: Frame Alignment Signal Bit (1).
Bit 0: Frame Alignment Signal Bit (1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
E1TNAF (E1 Mode)
Transmit Non-Align Frame Register
165h + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
Si
0
6
1
1
5
A
0
4
Sa4
0
Bit 7: International Bit (Si).
Bit 6: Frame Non-Alignment Signal Bit (1).
Bit 5: Remote Alarm (Used to Transmit the Alarm) (A).
Bit 4: Additional Bit 4 (Sa4).
Bit 3: Additional Bit 5 (Sa5).
Bit 2: Additional Bit 6 (Sa6).
Bit 1: Additional Bit 7 (Sa7).
Bit 0: Additional Bit 8 (Sa8).
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3
Sa5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
E1TSiAF (E1 Mode)
Transmit Si Bits of the Align Frame Register
166h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TSiF12
0
7
TSiF14
0
5
TSiF10
0
4
TSiF8
0
3
TSiF6
0
2
TSiF4
0
1
TSiF2
0
0
TSiF0
0
1
TSiF3
0
0
TSiF1
0
Bit 7: Si Bit of Frame 14 (TSiF14).
Bit 6: Si Bit of Frame 12 (TSiF12).
Bit 5: Si Bit of Frame 10 (TSiF10).
Bit 4: Si Bit of Frame 8 (TSiF8).
Bit 3: Si Bit of Frame 6 (TSiF6).
Bit 2: Si Bit of Frame 4 (TSiF4).
Bit 1: Si Bit of Frame 2 (TSiF2).
Bit 0: Si Bit of Frame 0 (TSiF0).
Register Name:
Register Description:
Register Address:
E1TSiNAF (E1 Mode Only)
Transmit Si Bits of the Non-Align Frame Register
167h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TSiF13
0
7
TSiF15
0
5
TSiF11
0
4
TSiF9
0
Bit 7: Si Bit of Frame 15 (TSiF15).
Bit 6: Si Bit of Frame 13 (TSiF13).
Bit 5: Si Bit of Frame 11 (TSiF11).
Bit 4: Si Bit of Frame 9 (TSiF9).
Bit 3: Si Bit of Frame 7 (TSiF7).
Bit 2: Si Bit of Frame 5 (TSiF5).
Bit 1: Si Bit of Frame 3 (TSiF3).
Bit 0: Si Bit of Frame 1 (TSiF1).
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3
TSiF7
0
2
TSiF5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
E1TRA (E1 Mode Only)
Transmit Remote Alarm Register
168h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TRAF13
0
7
TRAF15
0
5
TRAF11
0
4
TRAF9
0
3
TRAF7
0
2
TRAF5
0
1
TRAF3
0
0
TRAF1
0
1
TSa4F3
0
0
TSa4F1
0
Bit 7: Remote Alarm Bit of Frame 15 (TRAF15).
Bit 6: Remote Alarm Bit of Frame 13 (TRAF13).
Bit 5: Remote Alarm Bit of Frame 11 (TRAF11).
Bit 4: Remote Alarm Bit of Frame 9 (TRAF9).
Bit 3: Remote Alarm Bit of Frame 7 (TRAF7).
Bit 2: Remote Alarm Bit of Frame 5 (TRAF5).
Bit 1: Remote Alarm Bit of Frame 3 (TRAF3).
Bit 0: Remote Alarm Bit of Frame 1 (TRAF1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa4F15
0
E1TSa4 (E1 Mode Only)
Transmit Sa4 Bits Register
169h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TSa4F13
0
5
TSa4F11
0
4
TSa4F9
0
Bit 7: Sa4 Bit of Frame 15 (TSa4F15).
Bit 6: Sa4 Bit of Frame 13 (TSa4F13).
Bit 5: Sa4 Bit of Frame 11 (TSa4F11).
Bit 4: Sa4 Bit of Frame 9 (TSa4F9).
Bit 3: Sa4 Bit of Frame 7 (TSa4F7).
Bit 2: Sa4 Bit of Frame 5 (TSa4F5).
Bit 1: Sa4 Bit of Frame 3 (TSa4F3).
Bit 0: Sa4 Bit of Frame 1 (TSa4F1).
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3
TSa4F7
0
2
TSa4F5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa5F15
0
E1TSa5 (E1 Mode Only)
Transmit Sa5 Bits Register
16Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TSa5F13
0
5
TSa5F11
0
4
TSa5F9
0
3
TSa5F7
0
2
TSa5F5
0
1
TSa5F3
0
0
TSa5F1
0
1
TSa6F3
0
0
TSa6F1
0
Bit 7: Sa5 Bit of Frame 15 (TSa5F15).
Bit 6: Sa5 Bit of Frame 13 (TSa5F13).
Bit 5: Sa5 Bit of Frame 11 (TSa5F11).
Bit 4: Sa5 Bit of Frame 9 (TSa5F9).
Bit 3: Sa5 Bit of Frame 7 (TSa5F7).
Bit 2: Sa5 Bit of Frame 5 (TSa5F5).
Bit 1: Sa5 Bit of Frame 3 (TSa5F3).
Bit 0: Sa5 Bit of Frame 1 (TSa5F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa6F15
0
E1TSa6 (E1 Mode)
Transmit Sa6 Bits Register
16Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TSa6F13
0
5
TSa6F11
0
4
TSa6F9
0
Bit 7: Sa6 Bit of Frame 15 (TSa6F15).
Bit 6: Sa6 Bit of Frame 13 (TSa6F13).
Bit 5: Sa6 Bit of Frame 11 (TSa6F11).
Bit 4: Sa6 Bit of Frame 9 (TSa6F9).
Bit 3: Sa6 Bit of Frame 7 (TSa6F7).
Bit 2: Sa6 Bit of Frame 5 (TSa6F5).
Bit 1: Sa6 Bit of Frame 3 (TSa6F3).
Bit 0: Sa6 Bit of Frame 1 (TSa6F1).
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3
TSa6F7
0
2
TSa6F5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa7F15
0
E1TSa7 (E1 Mode Only)
Transmit Sa7 Bits Register
16Ch + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TSa7F13
0
5
TSa7F11
0
4
TSa7F9
0
3
TSa7F7
0
2
TSa7F5
0
1
TSa7F3
0
0
TSa7F1
0
1
TSa8F3
0
0
TSa8F1
0
Bit 7: Sa7 Bit of Frame 15 (TSa7F15).
Bit 6: Sa7 Bit of Frame 13 (TSa7F13).
Bit 5: Sa7 Bit of Frame 11 (TSa7F11).
Bit 4: Sa7 Bit of Frame 9 (TSa7F9).
Bit 3: Sa7 Bit of Frame 7 (TSa7F7).
Bit 2: Sa7 Bit of Frame 5 (TSa7F5).
Bit 1: Sa7 Bit of Frame 3 (TSa7F3).
Bit 0: Sa7 Bit of Frame 1 (TSa7F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa8F15
0
E1TSa8 (E1 Mode Only)
Transmit Sa8 Bits Register
16Dh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TSa8F13
0
5
TSa8F11
0
4
TSa8F9
0
Bit 7: Sa8 Bit of Frame 15 (TSa8F15).
Bit 6: Sa8 Bit of Frame 13 (TSa8F13).
Bit 5: Sa8 Bit of Frame 11 (TSa8F11).
Bit 4: Sa8 Bit of Frame 9 (TSa8F9).
Bit 3: Sa8 Bit of Frame 7 (TSa8F7).
Bit 2: Sa8 Bit of Frame 5 (TSa8F5).
Bit 1: Sa8 Bit of Frame 3 (TSa8F3).
Bit 0: Sa8 Bit of Frame 1 (TSa8F1).
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3
TSa8F7
0
2
TSa8F5
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FRM_EN
0
TMMR
Transmit Master Mode Register
180h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
INIT_DONE
0
5
—
0
4
—
0
3
—
0
2
—
0
1
SFTRST
0
0
T1/E1
0
Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE.
0 = Framer disabled—held in low-power state
1 = Framer enabled—all features active
Bit 6: Initialization Done (INIT_DONE). The user must set this bit once he has written the configuration registers.
The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the
DS26524 will check the FRM_EN bit and, if enabled will begin operation based on the initial configuration.
Bit 1: Soft Reset (SFTRST). Level sensitive-soft reset. Should be taken high then low to reset the transceiver.
0 = Normal operation
1 = Reset the transceiver
Bit 0: Transmitter T1/E1 Mode Select (T1/E1). Sets operating mode for transmitter only! This bit must be written
with the desired value prior to setting INIT_DONE.
0 = T1 operation
1 = E1 operation
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TJC
0
TCR1 (T1 Mode)
Transmit Control Register 1
181h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TFPT
0
5
TCPT
0
4
TSSE
0
3
GB7S
0
2
TB8ZS
0
1
TAIS
0
0
TRAI
0
Note: See TCR1 for E1 mode.
Bit 7: Transmit Japanese CRC-6 Enable (TJC).
0 = use ANSI/AT&T:ITU-T CRC-6 calculation (normal operation)
1 = use Japanese standard JT-G704 CRC-6 calculation
Bit 6: Transmit F-Bit Pass Through (TFPT).
0 = F-bits sourced internally
1 = F-bits sampled at TSER
Bit 5: Transmit CRC Pass Through (TCPT).
0 = source CRC-6 bits internally
1 = CRC-6 bits sampled at TSER during F-bit time
Bit 4: Transmit Software-Signaling Enable (TSSE). This function is enabled by TB7ZS (TCR2.0).
0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx
registers still define which channels are to have B7 stuffing performed.
1 = source signaling data as enabled by the SSIEx registers.
Bit 3: Global Bit 7 Stuffing (GB7S). This function is enabled by TB7ZS (TCR2.0).
0 = allow the SSIEx registers to determine which channels containing all zeros are to be bit 7 stuffed
1 = force bit 7 stuffing in all zero-byte channels of that port, regardless of how the SSIEx registers are
programmed
Bit 2: Transmit B8ZS Enable (TB8ZS).
0 = B8ZS disabled
1 = B8ZS enabled
Bit 1: Transmit Alarm Indication Signal (TAIS).
0 = transmit data normally
1 = transmit an unframed all-ones code at TPOS and TNEG
Bit 0: Transmit Remote Alarm Indication (TRAI).
0 = do not transmit remote alarm
1 = transmit remote alarm
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TTPT
0
TCR1 (E1 Mode)
Transmit Control Register 1
181h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
T16S
0
5
TG802
0
4
TSiS
0
3
TSA1
0
2
THDB3
0
1
TAIS
0
Note: See TCR1 for T1 mode.
Bit 7: Transmit Time Slot 0 Pass Through (TTPT).
0 = FAS bits/Sa bits/remote alarm sourced internally from the E1TAF and E1TNAF registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
Bit 6: Transmit Time Slot 16 Data Select (T16S). See Section 8.9.4 on software signaling.
0 = time slot 16 determined by the SSIEx and THSCS1:THSCS4 registers
1 = source time slot 16 from TS1:TS16 registers
Bit 5: Transmit G.802 Enable (TG802). See Section 10.4.
0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
Bit 4: Transmit International Bit Select (TSiS).
0 = sample Si bits at TSER pin
1 = source Si bits from E1TAF and E1TNAF registers (in this mode, TCR1.7 must be set to 0)
Bit 3: Transmit-Signaling All Ones (TSA1).
0 = normal operation
1 = force time slot 16 in every frame to all ones
Bit 2: Transmit HDB3 Enable (THDB3).
0 = HDB3 disabled
1 = HDB3 enabled
Bit 1: Transmit AIS (TAIS).
0 = transmit data normally
1 = transmit an unframed all-ones code at TPOS and TNEG
Bit 0: Transmit CRC-4 Enable (TCRC4).
0 = CRC-4 disabled
1 = CRC-4 enabled
195 of 273
0
TCRC4
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
TCR2 (T1 Mode)
Transmit Control Register 2
182h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TSLC96
0
7
TFDLS
0
5
—
0
4
FBCT2
0
3
FBCT1
0
2
TD4RM
0
1
PDE
0
0
TB7ZS
0
Note: See TCR2 for E1 mode.
Bit 7: TFDL Register Select (TFDLS).
0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6)
1 = source FDL or Fs bits from the internal HDLC controller
Bit 6: Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the
SLC-96 alignment pattern and data from the T1TSLC1:T1TSLC3 registers. See Section 8.9.4.4 for details.
0 = SLC-96 insertion disabled
1 = SLC-96 insertion enabled
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 2: Transmit D4 RAI Select (TD4RM).
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12
Bit 1: Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data
streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive zeros
and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the
transmit and receive data streams are reported in the TLS1.3 and RLS2.7 bits, respectively. When this bit is set to
one, the DS26524 will force the transmitted stream to meet this requirement no matter the content of the
transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS-encoded data streams cannot
violate the pulse density requirements.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS).
0 = no stuffing occurs
1 = force bit 7 to a one as determined by the GB7S bit at TCR1.3
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
AEBE
0
TCR2 (E1 Mode)
Transmit Control Register 2
182h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
AAIS
0
5
ARA
0
4
Sa4S
0
3
Sa5S
0
2
Sa6S
0
1
Sa7S
0
Note: See TCR2 for T1 mode.
Bit 7: Automatic E-Bit Enable (AEBE).
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
Bit 6: Automatic AIS Generation (AAIS).
0 = disabled
1 = enabled
Bit 5: Automatic Remote Alarm Generation (ARA).
0 = disabled
1 = enabled
Bit 4: Sa4 Bit Select (Sa4S). Set to one to source the Sa4 bit; set to zero to not source the Sa4 bit.
Bit 3: Sa5 Bit Select (Sa5S). Set to one to source the Sa5 bit; set to zero to not source the Sa5 bit.
Bit 2: Sa6 Bit Select (Sa6S). Set to one to source the Sa6 bit; set to zero to not source the Sa6 bit
Bit 1: Sa7 Bit Select (Sa7S). Set to one to source the Sa7 bit; set to zero to not source the Sa7 bit.
Bit 0: Sa8 Bit Select (Sa8S). Set to one to source the Sa8 bit; set to zero to not source the Sa8 bit.
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0
Sa8S
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ODF
ODF
0
TCR3
Transmit Control Register 3
183h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
ODM
ODM
0
5
TCSS1
TCSS1
0
4
TCSS0
TCSS0
0
3
MFRS
MFRS
0
2
TFM
—
0
1
IBPV
IBPV
0
0
TLOOP
CRC4R
0
Bit 7: Output Data Format (ODF).
0 = bipolar data at TTIP and TRING
1 = NRZ data at TTIP; TRING = 0
Bit 6: Output Data Mode (ODM).
0 = pulses at TTIP and TRING are one full TCLK period wide
1 = pulses at TTIP and TRING are 1/2 TCLK period wide
Bits 5 and 4: Transmit Clock Source Select 1 and 0 (TCSS[1:0]).
TCSS1
TCSS0
TRANSMIT CLOCK SOURCE
0
0
0
1
The TCLK pin is always the source of transmit clock.
Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after
one channel time.
1
0
Reserved
1
1
Use the signal present at RCLK as the transmit clock. The TCLK pin is ignored.
Bit 3: Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe
boundary.
0 = Normal operation. Transmit multiframe boundary is determined by line-side counters referenced to
TSYNC when TSYNC is an input. Free-running when TSYNC is an output.
1 = Pass-forward operation. Transmit multiframe boundary determined by system-side counters referenced
to TSSYNCIO (input mode 3), which is then passed forward to the line-side clock domain. This mode can
only be used when the transmit elastic store is enabled with a synchronous backplane (i.e., no frame slips
allowed). This mode must be used to allow transmit hardware-signaling insertion while the transmit elastic
store is enabled.
Bit 2: Transmit Frame Mode Select (TFM) (T1 Mode Only).
0 = ESF framing mode
1 = D4 framing mode
Bit 1: Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single bipolar violation (BPV) to be inserted into
the transmit data stream. Once this bit has been toggled from 0 to 1, the device waits for the next occurrence of
three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be
inserted.
Bit 0 (T1 Mode): Transmit Loop Code Enable (TLOOP). See Section 8.9.15 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as defined in registers T1TCD1 and T1TCD2
Bit 0 (E1 Mode): CRC-4 Recalculate (CRC4R).
0 = transmit CRC-4 generation and insertion operates in normal mode
1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TCLKINV
TCLKINV
0
TIOCR
Transmit I/O Configuration Register
184h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
5
TSYNCINV
TSYNCINV
TSSYNCINV
TSSYNCINV
0
0
4
TSCLKM
TSCLKM
0
3
TSSM
TSSM
0
2
TSIO
TSIO
0
1
TSDW
—
0
0
TSM
TSM
0
Bit 7: TCLK Invert (TCLKINV).
0 = No inversion
1 = Invert
Bit 6: TSYNC Invert (TSYNCINV).
0 = No inversion
1 = Invert
Bit 5: TSSYNCIO Invert (TSSYNCINV) (Input Mode Only).
0 = No inversion
1 = Invert
Bit 4: TSYSCLK Mode Select (TSCLKM).
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048/4.096/8.192MHz or IBO enabled (see Section 8.8.2 for details on IBO function)
Bit 3: TSSYNCIO Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNCIO pin.
0 = frame mode
1 = multiframe mode
Bit 2: TSYNC I/O Select (TSIO).
0 = TSYNC is an input
1 = TSYNC is an output
Bit 1: TSYNC Double-Wide (TSDW) (T1 Mode Only). (Note: This bit must be set to zero when TSM = 1 or when
TSIO = 0.)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
Bit 0: TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin.
0 = frame mode
1 = multiframe mode
199 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TDATFMT
0
TESCR
Transmit Elastic Store Control Register
185h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
TGCLKEN
0
5
—
0
4
TSZS
0
3
TESALGN
0
2
TESR
0
1
TESMDM
0
0
TESE
0
Note: Bits 7 and 6 are used for fractional backplane support. See Section 8.8.5.
Bit 7: Transmit Channel Data Format (TDATFMT).
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in 7 out of the 8 bits)
Bit 6: Transmit Gapped-Clock Enable (TGCLKEN).
0 = TCHCLK functions normally
1 = enable gapped bit clock output on TCHCLK
Bit 4: Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic
store read and write pointers before forcing a controlled slip. This bit is only applies during T1-to-E1 or E1-to-T1
conversion applications.
0 = force a slip at 9 bytes or less of separation (used for clustered blank channels)
1 = force a slip at 2 bytes or less of separation (used for distributed blank channels)
Bit 3: Transmit Elastic Store Align (TESALGN). Setting this bit from 0 to 1 will force the transmit elastic store’s
write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be
executed and the data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align.
Bit 2: Transmit Elastic Store Reset (TESR). Setting this bit from 0 to 1 will force the read pointer into the same
frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place
the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to
opposite frames. Should be toggled after TSYSCLK has been applied and is stable. Do not leave this bit set HIGH.
Bit 1: Transmit Elastic Store Minimum-Delay Mode (TESMDM).
0 = elastic stores operate at full two-frame depth
1 = elastic stores operate at 32-bit depth
Bit 0: Transmit Elastic Store Enable (TESE).
0 = elastic store is bypassed
1 = elastic store is enabled
200 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TCR4 (T1 Mode Only)
Transmit Control Register 4
186h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
TRAIM
0
2
TAISM
0
1
TC1
0
0
TC0
0
Bits 3: Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame
mode only.
0 = transmit normal RAI upon activation with TCR1.0
1 = transmit RAI-CI (T1.403) upon activation with TCR1.0
Bits 2: Transmit AIS Mode (TAISM). Determines the pattern sent when TAIS (TCR1.1) is activated.
0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1
1 = transmit AIS-CI (T1.403) upon activation with TCR1.1
Bits 1 and 0: Transmit Code Length Definition Bits (TC[1:0]).
TC1
TC0
0
0
1
1
0
1
0
1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
LENGTH SELECTED
(BITS)
5
6:3
7
16 : 8 : 4 : 2 : 1
THFC
Transmit HDLC FIFO Control Register
187h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
Bits 1 and 0: Transmit HDLC FIFO Low Watermark Select (TFLWM[1:2]).
TFLWM1
TFLWM2
0
0
1
1
0
1
0
1
TRANSMIT FIFO WATERMARK
(BYTES)
4
16
32
48
201 of 273
2
—
0
1
TFLWM1
0
0
TFLWM2
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TIBOC
Transmit Interleave Bus Operation Control Register
188h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
IBS1
0
5
IBS0
0
4
IBOSEL
0
3
IBOEN
0
2
DA2
0
1
DA1
0
0
DA0
0
Bits 6 and 5: IBO Bus Size (IBS[1:0]). Indicates how many devices are on the bus.
IBS1
0
0
1
1
IBS0
0
1
0
1
BUS SIZE
2 devices on bus
4 devices on bus
8 devices on bus
Reserved for future use
Bit 4: Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode.
0 = Channel Interleave
1 = Frame Interleave
Bit 3: Interleave Bus Operation Enable (IBOEN).
0 = Interleave Bus Operation disabled
1 = Interleave Bus Operation enabled
Bits 2 to 0: Device Assignment Bits (DA[2:0]).
DA2
0
0
0
0
1
1
1
1
DA1
0
0
1
1
0
0
1
1
DA0
0
1
0
1
0
1
0
1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
DEVICE POSITION
1st device on bus
2nd device on bus
3rd device on bus
4th device on bus
5th device on bus
6th device on bus
7th device on bus
8th device on bus
TDS0SEL
Transmit DS0 Channel Monitor Select Register
189h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
TCM4
0
3
TCM3
0
2
TCM2
0
1
TCM1
0
0
TCM0
0
Bits 4 to 0: Transmit Channel Monitor Bits (TCM[4:0]). TCM0 is the LSB of a 5-bit channel select that
determines which transmit channel data will appear in the TDS0M register. Channels 1 to 32 are represented by a
5-bit BCD code from 0 to 31. TCM[4:0] = all zeros selects channel 1, TCM[4:0] = 11111 selects channel 32.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TXPC
Transmit Expansion Port Control Register
18Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
2
TBPDIR
0
1
TBPFUS
0
0
TBPEN
0
Bit 2: Transmit BERT Port Direction Control (TBPDIR).
0 = Normal (line) operation. Transmit BERT port sources data into the transmit path.
1 = System (backplane) operation. Transmit BERT port sources data into the receive path (RDATA). In this
mode the data out of the transmit BERT is muxed into the receive path at RDATA (the line side of the
elastic store).
Bit 1: Transmit BERT Port Framed/Unframed Select (TBPFUS).
0 = The transmit BERT will not clock data into the F-bit position (framed)
1 = The transmit BERT will clock data into the F-bit position (unframed)
Bit 0: Transmit BERT Port Enable (TBPEN).
0 = Transmit BERT port is not active
1 = Transmit BERT port is active
203 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BPBSE8
0
TBPBS
Transmit BERT Port Bit Suppress Register
18Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
BPBSE7
0
5
BPBSE6
0
4
BPBSE5
0
3
BPBSE4
0
2
BPBSE3
0
1
BPBSE2
0
0
BPBSE1
0
Bit 7: Transmit Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being
used.
Bit 6: Transmit Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
Bit 5: Transmit Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used.
Bit 4: Transmit Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used.
Bit 3: Transmit Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used.
Bit 2: Transmit Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used.
Bit 1: Transmit Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used.
Bit 0: Transmit Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being
used.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
—
0
TSYNCC
Transmit Synchronizer Control Register
18Eh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
—
0
5
—
—
0
4
—
—
0
3
—
CRC4
0
2
TSEN
TSEN
0
1
SYNCE
SYNCE
0
0
RESYNC
RESYNC
0
Bit 3: CRC-4 Enable (CRC4) (E1 Mode Only).
0 = Do not search for the CRC-4 multiframe word
1 = Search for the CRC-4 multiframe word
Bit 2: Transmit Synchronizer Enable (TSEN).
0 = Transmit synchronizer disabled
1 = Transmit synchronizer enabled
Bit 1: Sync Enable (SYNCE).
0 = auto resync enabled
1 = auto resync disabled
Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the transmit-side framer
is initiated. Must be cleared and set again for a subsequent resync.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
TLS1
Transmit Latched Status Register 1
190h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
6
TESEM
TESEM
0
Default
7
TESF
TESF
0
5
TSLIP
TSLIP
0
4
TSLC96
—
0
3
TPDV
TAF
0
2
TMF
TMF
0
1
LOTCC
LOTCC
0
0
LOTC
LOTC
0
Note: All bits in this register are latched and can cause interrupts.
Bit 7: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is
deleted.
Bit 6: Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a
frame is repeated.
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either
repeated or deleted a frame.
Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only). When enabled by TCR2.6, this bit will set
once per SLC-96 multiframe (72 frames) to alert the host that new data may be written to the T1TSLC1:T1TSLC3
registers. See Section 8.9.4.4 for more information.
Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not
meet the ANSI T1.403 requirements for pulse density.
Bit 3 (E1 Mode): Transmit Align Frame Event (TAF). Set every 250µs to alert the host that the E1TAF and
E1TNAF registers need to be updated.
Bit 2: Transmit Multiframe Event (TMF). In T1 mode, this bit is set every 1.5ms on D4 MF boundaries or every
3ms on ESF MF boundaries. In E1 operation, this but is set every 2ms (regardless if CRC-4 is enabled) on transmit
multiframe boundaries. Used to alert the host that signaling data needs to be updated.
Bit 1: Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has
been sensed at the TCLK pin).
Bit 0: Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for approximately
3 clock periods. Will force the LOTC bit high if enabled. This bit can be cleared by the host even if the condition is
still present. LOTC will remain high while the condition exists, even if the host has cleared the status bit. If enabled
by TIM1.0, the INTB pin will transition low when this bit is set, and transition high when this bit is cleared (if no other
unmasked interrupt conditions exist).
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
—
0
TLS2
Transmit Latched Status Register 2 (HDLC)
191h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
—
0
5
—
—
0
4
TFDLE
—
0
3
TUDR
TUDR
0
2
TMEND
TMEND
0
1
TLWMS
TLWMS
0
0
TNFS
TNFS
0
Note: All bits in this register are latched and can create interrupts.
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL register has shifted out all 8
bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or
BOC controller circuits.
Bit 3: Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the
TMEND bit set. An abort is automatically sent.
Bit 2: Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a
message.
Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO
empties beyond the low watermark as defined by the transmit low watermark bit (TLWM), rising edge detect of
TLWM.
Bit 0: Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty
byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TLS3
Transmit Latched Status Register 3 (Synchronizer)
192h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
LOF
0
0
LOFD
0
Note: Some bits in this register are latched and can create interrupts.
Bit 1: Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync
pattern in the incoming data stream.
Bit 0: Loss of Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is
searching for the sync pattern in the incoming data stream.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TIIR
Transmit Interrupt Information Register
19Fh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
—
0
2
TLS3
0
1
TLS2
0
0
TLS1
0
The Transmit Interrupt Information register provides an indication of which status registers are generating an
interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers
are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt
has been serviced and cleared.
Bit 2: Transmit Latched Status Register 3 Interrupt Status (TLS3).
0 = no interrupt pending
1 = interrupt pending
Bit 1: Transmit Latched Status Register 2 Interrupt Status (TLS2).
0 = no interrupt pending
1 = interrupt pending
Bit 0: Transmit Latched Status Register 1 Interrupt Status (TLS1).
0 = no interrupt pending
1 = interrupt pending
207 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
TIM1
Transmit Interrupt Mask Register 1
1A0h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
6
TESEM
TESEM
0
Default
7
TESF
TESF
0
5
TSLIP
TSLIP
0
4
TSLC96
—
0
3
TPDV
TAF
0
Bit 7: Transmit Elastic Store Full Event (TESF).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Transmit Elastic Store Empty Event (TESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only).
0 = interrupt masked
1 = interrupt enabled
Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV).
0 = interrupt masked
1 = interrupt enabled
Bit 3 (E1 Mode): Transmit Align Frame Event (TAF).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Transmit Multiframe Event (TMF).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Loss of Transmit Clock Clear Condition (LOTCC).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Loss of Transmit Clock Condition (LOTC).
0 = interrupt masked
1 = interrupt enabled
208 of 273
2
TMF
TMF
0
1
LOTCC
LOTCC
0
0
LOTC
LOTC
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
—
0
TIM2
Transmit Interrupt Mask Register 2 (HDLC)
1A1h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
—
0
5
—
—
0
4
TFDLE
—
0
3
TUDR
TUDR
0
2
TMEND
TMEND
0
1
TLWMS
TLWMS
0
0
TNFS
TNFS
0
1
—
0
0
LOFD
0
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Transmit FIFO Underrun Event (TUDR).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Transmit Message End Event (TMEND).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Transmit FIFO Not Full Set Condition (TNFS).
0 = interrupt masked
1 = interrupt enabled
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TIM3
Transmit Interrupt Mask Register 3 (Synchronizer)
1A2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
Bit 0: Loss of Frame Synchronization Detect (LOFD).
0 = interrupt masked
1 = interrupt enabled
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3
—
0
2
—
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1TCD1 (T1 Mode Only)
Transmit Code Definition Register 1
1ACh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bit 7: Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern.
Bit 6: Transmit Code Definition Bit 6 (C6).
Bit 5: Transmit Code Definition Bit 5 (C5).
Bit 4: Transmit Code Definition Bit 4 (C4).
Bit 3: Transmit Code Definition Bit 3 (C3).
Bit 2: Transmit Code Definition Bit 2 (C2). A Don’t Care if a 5-bit length is selected.
Bit 1: Transmit Code Definition Bit 1 (C1). A Don’t Care if a 5- or 6-bit length is selected.
Bit 0: Transmit Code Definition Bit 0 (C0). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
C7
0
T1TCD2 (T1 Mode Only)
Transmit Code Definition Register 2
1ADh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
C6
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Bit 7: Transmit Code Definition Bit 7 (C7). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 6: Transmit Code Definition Bit 6 (C6). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 5: Transmit Code Definition Bit 5 (C5). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 4: Transmit Code Definition Bit 4 (C4). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 3: Transmit Code Definition Bit 3 (C3). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 2: Transmit Code Definition Bit 2 (C2). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 1: Transmit Code Definition Bit 1 (C1). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Bit 0: Transmit Code Definition Bit 0 (C0). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
210 of 273
0
C0
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TRTS2
Transmit Real-Time Status Register 2 (HDLC)
1B1h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
—
0
3
TEMPTY
0
2
TFULL
0
1
TLWM
0
0
TNF
0
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties
beyond the low watermark as defined by the transmit low watermark bits (TLWM).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte
available.
Register Name:
Register Description:
Register Address:
TFBA
Transmit HDLC FIFO Buffer Available
1B3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
TFBA6
0
7
—
0
5
TFBA5
0
4
TFBA4
0
3
TFBA3
0
2
TFBA2
0
1
TFBA1
0
0
TFBA0
0
1
THD1
0
0
THD0
0
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA[6:0]). TFBA0 is the LSB.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
THD7
0
THF
Transmit HDLC FIFO Register
1B4h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
THD6
0
5
THD5
0
4
THD4
0
3
THD3
0
Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte.
Bit 6: Transmit HDLC Data Bit 6 (THD6).
Bit 5: Transmit HDLC Data Bit 5 (THD5).
Bit 4: Transmit HDLC Data Bit 4 (THD4).
Bit 3: Transmit HDLC Data Bit 3 (THD3).
Bit 2: Transmit HDLC Data Bit 2 (THD2).
Bit 1: Transmit HDLC Data Bit 1 (THD1).
Bit 0: Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte.
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2
THD2
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TDS0M
Transmit DS0 Monitor Register
1BBh + (200h x n): where n = 0 to 3, for Ports 1 to 4
7
B1
0
6
B2
0
5
B3
0
4
B4
0
3
B5
0
2
B6
0
1
B7
0
0
B8
0
Bits 7 to 0: Transmit DS0 Channel Bits (B[1:8]). Transmit channel data that has been selected by the Transmit
DS0 Channel Monitor Select register (TDS0SEL). B8 is the LSB of the DS0 channel (last bit to be transmitted).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TBCS1, TBCS2, TBCS3, TBCS4
Transmit Blank Channel Select Registers 1 to 4
1C0h, 1C1h, 1C2h, 1C3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
TBCS1
TBCS2
TBCS3
TBCS4
(E1 Mode
Only)
Bits 7 to 0: Transmit Blank Channel Select for Channels 1 to 32 (CH[1:32]).
0 = transmit TSER data from this channel
1 = ignore TSER data from this channel
Note that when two or more sequential channels are chosen to be ignored, the receive slip zone select bit should
be set to zero. If the ignore channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to
one, which may provide a lower occurrence of slips in certain applications.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TCBR1, TCBR2, TCBR3, TCBR4
Transmit Channel Blocking Registers 1 to 4
1C4h, 1C5h, 1C6h, 1C7h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB)
CH8
CH16
CH24
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
(LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
(F-bit)
0
0
0
0
0
0
0
0
TCBR1
TCBR2
TCBR3
TCBR4*
(E1 Mode
Only)
Bits 7 to 0: Transmit Channel Blocking Channels 1 to 32 Control Bits (CH[1:32]).
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
*Note that TCBR4 has two functions:
When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking
signal for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the
TCHBLK signal will pulse high during the F-bit time:
TCBR4.0 = 0: Do not pulse TCHBLK during the F-bit.
TCBR4.0 = 1: Pulse TCHBLK during the F-bit.
In this mode, TCBR4.1 to TCBR4.7 should be set to 0.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
THSCS1, THSCS2, THSCS3, THSCS4
Transmit Hardware-Signaling Channel Select Registers 1 to 4
1C8h, 1C9h, 1CAh, 1CBh + (200h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
Default
THSCS1
THSCS2
THSCS3
THSCS4*
(E1 Mode
Only)
Bits 7 to 0: Transmit Hardware-Signaling Channel Select for Channels 1 to 32 (CH[1:32]). These bits
determine which channels have signaling data inserted from the TSIG pin into the TSER PCM data.
0 = do not source signaling data from the TSIG pin for this channel
1 = source signaling data from the TSIG pin for this channel
*Note that THSCS4 is only used in 2.048MHz backplane applications.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TGCCS1, TGCCS2, TGCCS3, TGCCS4
Transmit Gapped-Clock Channel Select Registers 1 to 4
1CCh, 1CDh, 1CEh, 1CFh + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB)
CH8
CH16
CH24
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
(LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
(F-bit)
0
0
0
0
0
0
0
0
TGCCS1
TGCCS2
TGCCS3
TGCCS4*
(E1 Mode
Only)
Bits 7 to 0: Transmit Gapped-Clock Channel Select Channels 1 to 32 (CH[1:32]).
0 = no clock is present on TCHCLK during this channel time
1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLK if the
elastic store is disabled, and synchronous with TSYSCLK if the elastic store is enabled.
*Note that TGCCS4 has two functions:
When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on
TCHCLK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is
generated on TCHCLK during the F-bit time:
TGCCS4.0 = 0: Do not generate a clock during the F-bit
TGCCS4.0 = 1: Generate a clock during the F-bit
In this mode, TGCCS4.1 to TGCCS4.7 should be set to 0.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
PCL1, PCL2, PCL3, PCL4
Per-Channel Loopback Enable Registers 1 to 4
1D0h, 1D1h, 1D2h, 1D3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB)
CH8
CH16
CH24
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
(LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
PCL1
PCL2
PCL3
PCL4
(E1 Mode
Only)
Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH[1:32]).
0 = loopback disabled
1 = enable loopback; source data from the corresponding receive channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TBPCS1, TBPCS2, TBPCS3, TBPCS4
Transmit BERT Port Channel Select Registers 1 to 4
1D4h, 1D5h, 1D6h, 1D7h + (200h x n): where n = 0 to 3, for Ports 1 to 4
(MSB) 7
CH8
CH16
CH24
6
CH7
CH15
CH23
5
CH6
CH14
CH22
4
CH5
CH13
CH21
3
CH4
CH12
CH20
2
CH3
CH11
CH19
1
CH2
CH10
CH18
0 (LSB)
CH1
CH9
CH17
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
0
0
0
0
0
0
0
0
TBPCS1
TBPCS2
TBPCS3
TBPCS4
(E1 Mode
Only)
Setting any of the CH[1:32] bits in the TBPCS1:TBPCS4 registers will enable the transmit BERT clock for the
associated channel time, and allow mapping of the selected channel data out of the receive BERT port. Multiple or
all channels can be selected simultaneously.
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DS26524 Quad T1/E1/J1 Transceiver
9.5
LIU Register Definitions
Table 9-14. LIU Register Set
ADDRESS
NAME
DESCRIPTION
R/W
1000h
LTRCR
LIU Transmit Receive Control Register
R/W
1001h
LTITSR
LIU Transmit Impedance and Pulse Shape Selection Register
R/W
1002h
LMCR
LIU Maintenance Control Register
R/W
1003h
LRSR
LIU Real Status Register
1004h
LSIMR
LIU Status Interrupt Mask Register
R/W
1005h
LLSR
LIU Latched Status Register
R/W
1006h
LRSL
LIU Receive Signal Level Register
1007h
LRISMR
1008h–101Fh
—
R
R
LIU Receive Impedance and Sensitivity Monitor Register
R/W
Reserved
—
Note: Reserved registers should only be written with all zeros.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
LTRCR
LIU Transmit Receive Control Register
1000h + (20h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
—
0
4
JADS
0
3
JAPS1
0
2
JAPS0
0
1
T1J1E1S
0
0
LSC
0
Bit 4: Jitter Attenuator Depth Select (JADS).
0 = Jitter attenuator FIFO depth set to 128 bits.
1 = Jitter attenuator FIFO depth set to 32 bits. Use for delay-sensitive applications.
Bits 3 and 2: Jitter Attenuator Position Select 1 and 0 (JAPS[1:0]). These bits are used to select the position of
the jitter attenuator.
JAPS1
0
0
1
1
JAPS0
0
1
0
1
FUNCTION
Jitter attenuator is in the receive path.
Jitter attenuator is in the transmit path.
Jitter attenuator is not used.
Jitter attenuator is not used.
Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation.
0 = E1
1 = T1 or J1
Bit 0: LOS Criteria Selection (LCS). This bit is used for LIU LOS selection criteria.
E1 Mode:
0 = G.775
1 = ETS 300 233
T1/J1 Mode:
0 = T1.231
1 = T1.231
216 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
LTITSR
LIU Transmit Impedance and Pulse Shape Selection Register
1001h + (20h x n): where n = 0 to 3, for Ports 1 to 4
6
TIMPTOFF
0
5
TIMPL1
0
4
TIMPL0
0
3
—
0
2
L2
0
1
L1
0
0
L0
0
Bit 6: Transmit Impedance Off (TIMPTOFF).
0 = Enable transmit terminating impedance.
1 = Disable transmit terminating impedance.
Bits 5 and 4: Transmit Load Impedance 1 and 0 (TIMPL[1:0]). These bits are used to select the transmit load
impedance. These must be set to match the cable impedance. Even if the internal load impedance is turned off (via
TIMPTOFF); the external cable impedance must be specified for optimum operation. For J1 applications, use
110Ω. See Table 9-15.
Bits 2 to 0: Line Build-Out Select 2 to 0 (L[2:0]). Used to select the transmit waveshape. The waveshape has a
voltage level and load impedance associated with it once the T1/J1 or E1 selection is made by settings in the
LTRCR register. See Table 9-16.
Table 9-15. Transmit Load Impedance Selection
TIMPL1
0
0
1
1
TIMPL0
0
1
0
1
IMPEDANCE SELECTION
75Ω
100Ω
110Ω
120Ω
Table 9-16. Transmit Pulse Shape Selection
NOMINAL
VOLTAGE
2.37V
3.0V
L2
L1
L0
MODE
IMPEDANCE
0
0
0
0
0
1
E1
E1
75Ω
120Ω
L2
L1
L0
MODE
CABLE LENGTH
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
DSX-1/0dB CSU, 0ft–133ft ABAM 100Ω
DSX-1, 133ft–266ft ABAM 100Ω
DSX-1, 266ft–399ft ABAM 100Ω
DSX-1, 399ft–533ft ABAM 100Ω
DSX-1, 533ft–655ft ABAM 100Ω
-7.5dB CSU
-15dB CSU
-22.5dB CSU
217 of 273
MAX
ALLOWED
CABLE LOSS
0.6dB
1.2dB
1.8dB
2.4dB
3.0dB
—
—
—
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TAIS
0
LMCR
LIU Maintenance Control Register
1002h + (20h x n): where n = 0 to 3, for Ports 1 to 4
6
ATAIS
0
5
LLB
0
4
ALB
0
3
RLB
0
2
TPDE
0
1
RPDE
0
0
TE
0
Bit 7: Transmit AIS (TAIS). Alarm Indication Signal (AIS) is sent using MCLK as the reference clock. The transmit
data coming from the framer is ignored.
0 = TAIS is disabled.
1 = Output an unframed all-ones pattern (AIS) at TTIP and TRING.
Bit 6: Automatic Transmit AIS (ATAIS).
0 = ATAIS is disabled.
1 = Automatically transmit AIS on the occurrence of an LIU LOS.
Bit 5: Local Loopback (LLB). See Section 8.11.5.2 for operational details.
0 = LLB is disabled.
1 = LLB is enabled.
Bit 4: Analog Loopback (ALB). See Section 8.11.5.1 for operational details.
0 = ALB is disabled.
1 = ALB is enabled.
Bit 3: Remote Loopback (RLB). See Section 8.11.5.3 for operational details.
0 = Remote loopback is disabled.
1 = Remote loopback is enabled.
In this loopback, received data passes all the way through the receive LIU and is then transmitted back
through the transmit side of the LIU. Data will continue to pass through the receive-side framer of the
DS26524 as it would normally and the data from the transmit side of the framer will be ignored.
Bit 2: Transmit Power-Down Enable (TPDE).
0 = Transmitter power enabled.
1 = Transmitter powered down. TTIP/TRING outputs are high impedance.
Bit 1: Receiver Power-Down Enable (RPDE).
0 = Receiver power enabled.
1 = Receiver powered down.
Bit 0: Transmit Enable (TE). This function is overridden by the TXENABLE pin.
0 = TTIP/TRING outputs are high impedance.
1 = TTIP/TRING outputs enabled.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
LRSR
LIU Real Status Register
1003h + (20h x n): where n = 0 to 3, for Ports 1 to 4
6
—
0
5
OEQ
0
4
UEQ
0
3
—
0
2
SCS
0
1
OCS
0
0
LOSS
0
Bit 5: Over Equalized (OEQ). The equalizer is over equalized. This can happen if there is very large unexpected
resistive loss. This could result if monitor mode is used and the device is not placed in monitor mode. This indicator
provides more qualitative information to the receive loss indicators.
Bit 4: Under Equalized (UEQ). The equalizer is under equalized. A signal with a very high resistive gain is being
applied. This indicator provides more qualitative information to the receive loss indicators.
Bit 2: Short-Circuit Status (SCS). A real-time bit that is set when the LIU detects that the TTIP and TRING
outputs are short-circuited. The load resistance must be 25Ω (typically) or less for short-circuit detection.
Bit 1: Open-Circuit Status (OCS). A real-time bit that is set when the LIU detects that the TTIP and TRING
outputs are open-circuited.
Bit 0: Loss-of-Signal Status (LOSS). A real-time bit that is set when the LIU detects a LOS condition at RTIP and
RRING.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
LSIMR
LIU Status Interrupt Mask Register
1004h + (20h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
OCCIM
0
7
JALTCIM
0
5
SCCIM
0
4
LOSCIM
0
3
JALTSIM
0
Bit 7: Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 6: Open-Circuit Clear Interrupt Mask (OCCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 5: Short-Circuit Clear Interrupt Mask (SCCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 4: Loss of Signal Clear Interrupt Mask (LOSCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 3: Jitter Attenuator Limit Trip Set Interrupt Mask (JALTSIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 2: Open-Circuit Detect Interrupt Mask (OCDIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 1: Short-Circuit Detect Interrupt Mask (SCDIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 0: Loss of Signal Detect Interrupt Mask (LOSDIM).
0 = Interrupt masked.
1 = Interrupt enabled.
220 of 273
2
OCDIM
0
1
SCDIM
0
0
LOSDIM
0
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
JALTC
0
LLSR
LIU Latched Status Register
1005h + (20h x n): where n = 0 to 3, for Ports 1 to 4
6
OCC
0
5
SCC
0
4
LOSC
0
3
JALTS
0
2
OCD
0
1
SCD
0
0
LOSD
0
Note: All bits in this register are latched and can create interrupts.
Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a jitter attenuator limit trip condition
was detected and then removed.
Bit 6: Open-Circuit Clear (OCC). This latched bit is set when an open-circuit condition was detected at TTIP and
TRING and then removed.
Bit 5: Short-Circuit Clear (SCC). This latched bit is set when a short-circuit condition was detected at TTIP and
TRING and then removed.
Bit 4: Loss of Signal Clear (LOSC). This latched bit is set when a loss-of-signal condition was detected at RTIP
and RRING and then removed.
Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator limit trip condition
is detected.
Bit 2: Open-Circuit Detect (OCD). This latched bit is set when an open-circuit condition is detected at TTIP and
TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).
Bit 1: Short-Circuit Detect (SCD). This latched bit is set when a short-circuit condition is detected at TTIP and
TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).
Bit 0: Loss of Signal Detect (LOSD). This latched bit is set when an LOS condition is detected at RTIP and
RRING.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LRSL
LIU Receive Signal Level Register
1006h + (20h x n): where n = 0 to 3, for Ports 1 to 4
7
RSL3
0
6
RSL2
0
5
RLS1
0
4
RLS0
0
3
—
0
2
—
0
1
—
0
0
—
0
Bits 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in Table 9-17. Note
that the range of signal levels reported the RSL[3:0] is limited by the Equalizer Gain Limit (EGL) in short-haul
applications.
Table 9-17. Receive Level Indication
RSL3
RSL2
RSL1
RSL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RECEIVE LEVEL (dB)
T1
> -2.5
-2.5 to -5
-5 to -7.5
-7.5 to -10
-10 to -12.5
-12.5 to -15
-15 to -17.5
-17.5 to -20
-20 to -23
-23 to -26
-26 to -29
-29 to -32
-32 to -36
< -36
—
—
222 of 273
E1
> -2.5
-2.5 to -5
-5 to -7.5
-7.5 to -10
-10 to -12.5
-12.5 to -15
-15 to -17.5
-17.5 to -20
-20 to -23
-23 to -26
-26 to -29
-29 to -32
-32 to -36
-36 to -40
-40 to -44
< -44
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
LRISMR
LIU Receive Impedance and Sensitivity Monitor Register
1007h + (20h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RIMPOFF
0
7
RG703
0
5
RIMPM1
0
4
RIMPM0
0
3
RTR
0
2
RMONEN
0
1
RSMS1
0
0
RSMS0
0
Bit 7: Receive G.703 Clock Enable (RG703). If this bit is set, the receiver expects a 2.048MHz or 1.544MHz
clock from the RTIP/RRING, based on the selection of T1 (1.544) or E1 (2.048) mode in the LTRCR register.
Bit 6: Receive Impedance Termination Off (RIMPOFF).
0 = Receive terminating impedance match is enabled.
1 = Receive terminating impedance match is disabled.
Bits 5 and 4: Receive Impedance Match 1 and 0 (RIMPM[1:0]). These bits are used to select the receive
impedance match value. These must be set according to the cable impedance. Even if the internal receive match
impedance is turned off (RIMPOFF); the external cable impedance must be specified for optimum operation by
RIMPM1 to 0. See Table 9-18.
Bit 3: Receiver Turns Ratio (RTR).
0 = Receive transformer turns ratio is 1:1.
1 = Receive transformer turns ratio is 2:1. This option should only be used in short-haul applications.
Bit 2: Receiver Monitor Mode Enable (RMONEN).
0 = Disable receive monitor mode.
1 = Enable receive monitor mode. Resistive gain is added with the maximum sensitivity. The receiver
sensitivity is determined by RSMS1 and RSMS0.
Bits 1 and 0: Receiver Sensitivity/Monitor Gain Select 1 and 0 (RSMS[1:0]). These bits are used to select the
receiver sensitivity level and additional gain in monitoring applications. The monitor mode (RMONEN) adds
resistive gain to compensate for the signal loss caused by the isolation resistors. See Table 9-19 and Table 9-20.
Table 9-18. Receive Impedance Selection
RIMPM[1:0]
RECEIVE IMPEDANCE
SELECTED (Ω)
00
01
10
11
75
100
110
120
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DS26524 Quad T1/E1/J1 Transceiver
Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled
RMONEN
RSMS[1:0]
0
0
0
0
00
01
10
11
RECEIVER
MONITOR MODE
GAIN (dB)
0
0
0
0
RECEIVER SENSITIVITY
(MAX CABLE LOSS
ALLOWED) (dB)
12
18
30
36 for T1; 43 for E1
Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled
RMONEN
RSMS[1:0]
1
1
1
1
00
01
10
11
RECEIVER
MONITOR MODE
GAIN (dB)
14
20
26
32
RECEIVER SENSITIVITY
(MAX CABLE LOSS
ALLOWED) (dB)
30
22.5
17.5
12
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DS26524 Quad T1/E1/J1 Transceiver
9.6
BERT Register Definitions
Table 9-21. BERT Register Set
ADDR
NAME
DESCRIPTION
R/W
1100h
BAWC
BERT Alternating Word Count Rate Register
1101h
BRP1
BERT Repetitive Pattern Set Register 1
R/W
1102h
BRP2
BERT Repetitive Pattern Set Register 2
R/W
1103h
BRP3
BERT Repetitive Pattern Set Register 3
R/W
1104h
BRP4
BERT Repetitive Pattern Set Register 4
R/W
1105h
BC1
BERT Control Register 1
R/W
1106h
BC2
BERT Control Register 2
R/W
1107h
BBC1
BERT Bit Count Register 1
R
1108h
BBC2
BERT Bit Count Register 2
R
1109h
BBC3
BERT Bit Count Register 3
R
110Ah
BBC4
BERT Bit Count Register 4
R
110Bh
BEC1
BERT Error Count Register 1
R
110Ch
BEC2
BERT Error Count Register 2
R
110Dh
BEC3
BERT Error Count Register 3
R
110Eh
BLSR
BERT Latched Status Register
R
110Fh
BSIM
BERT Status Interrupt Mask Register
R
R/W
Register Name:
Register Description:
Register Address:
BAWC
BERT Alternating Word Count Rate Register
1100h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
ACNT6
0
7
ACNT7
0
5
ACNT5
0
4
ACNT4
0
3
ACNT3
0
2
ACNT2
0
1
ACNT1
0
0
ACNT0
0
Bits 7 to 0: Alternating Word Count Rate Bits 7 to 0 (ACNT[7:0]). When the BERT is programmed in the
alternating word mode, the words will repeat for the count loaded into this register, then flip to the other word and
again repeat for the number of times loaded into this register. ACNT0 is the LSB of the 8-bit alternating word count
rate counter.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
BRP1
BERT Repetitive Pattern Set Register 1
1101h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RPAT6
0
7
RPAT7
0
5
RPAT5
0
4
RPAT4
0
3
RPAT3
0
2
RPAT2
0
1
RPAT1
0
0
RPAT0
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]). RPAT0 is the LSB of the 32-bit repetitive
pattern.
Register Name:
Register Description:
Register Address:
BRP2
BERT Repetitive Pattern Set Register 2
1102h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RPAT14
0
7
RPAT15
0
5
RPAT13
0
4
RPAT12
0
3
RPAT11
0
2
RPAT10
0
1
RPAT9
0
0
RPAT8
0
1
RPAT17
0
0
RPAT16
0
1
RPAT25
0
0
RPAT24
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 15 to 8 (RPAT[15:8]).
Register Name:
Register Description:
Register Address:
BRP3
BERT Repetitive Pattern Set Register 3
1103h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RPAT22
0
7
RPAT23
0
5
RPAT21
0
4
RPAT20
0
3
RPAT19
0
2
RPAT18
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 23 to 16 (RPAT[23:16]).
Register Name:
Register Description:
Register Address:
BRP4
BERT Repetitive Pattern Set Register 4
1104h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
RPAT30
0
7
RPAT31
0
5
RPAT29
0
4
RPAT28
0
3
RPAT27
0
2
RPAT26
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 31 to 24 (RPAT[31:24]). RPAT31 is the MSB of the 32-bit
repetitive pattern.
226 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TC
0
BC1
BERT Control Register 1
1105h + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
TINV
0
5
RINV
0
4
PS2
0
3
PS1
0
2
PS0
0
1
LC
0
0
RESYNC
0
Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to
be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be
cleared and set again for subsequent loads.
Bit 6:Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 5:Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bits 4 to 2: Pattern Select Bits 2 to 0 (PS[2:0]). These bits select data pattern used by the transmit and receive
circuits. See Table 9-22.
Table 9-22. BERT Pattern Select
PS2
PS1
PS0
PATTERN DEFINITION
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
1
1
1
Pseudorandom 2E7-1
Pseudorandom 2E11-1
Pseudorandom 2E15-1
Pseudorandom Pattern QRSS. A 220 - 1 pattern with 14 consecutive zero restriction.
Repetitive Pattern
Alternating Word Pattern
Modified 55 Octet (Daly) Pattern. The Daly pattern is a repeating 55 octet pattern that is
byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance
for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25
(November 1993).
Pseudorandom 2E-9-1
Bit 1: Load Bit and Error Counter (LC). A low-to-high transition latches the current bit and error counts into the
registers BBC1, BBC2, BBC3, BBC4 and BEC1, BEC2, and BEC3, and clears the internal count. This bit should be
toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set
again for subsequent loads.
Bit 0: Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes
to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
227 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
BC2
BERT Control Register 2
1106h + (10h x n): where n = 0 to 3, for Ports 1 to 4
7
EIB2
0
6
EIB1
0
5
EIB0
0
4
SBE
0
3
RPL3
0
2
RPL2
0
1
RPL1
0
0
RPL0
0
Bits 7 to 5: Error Insert Bits 2 to 0 (EIB[2:0]). Will automatically insert bit errors at the prescribed rate into the
generated data pattern. Can be used for verifying error detection features. See Table 9-23.
Table 9-23. BERT Error Insertion Rate
EIB2
EIB1
EIB0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ERROR RATE INSERTED
No errors automatically inserted
10E-1
10E-2
10E-3
10E-4
10E-5
10E-6
10E-7
Bit 4: Single Bit Error Insert (SBE). A low-to-high transition will create a single bit error. Must be cleared and set
again for a subsequent bit error to be inserted.
Bits 3 to 0: Repetitive Pattern Length Select 3 to 0 (RPL[3:0]). RPL0 is the LSB and RPL3 is the MSB of a
nibble that describes how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are
ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns fewer than
17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal
to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30
(1101). See Table 9-24.
Table 9-24. BERT Repetitive Pattern Length Select
LENGTH
(BITS)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RPL3
RPL2
RPL1
RPL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
228 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BBC7
0
BBC1
BERT Bit Count Register 1
1107h + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
BBC6
0
5
BBC5
0
4
BBC4
0
3
BBC3
0
2
BBC2
0
1
BBC1
0
0
BBC0
0
Bits 7 to 0: BERT Bit Counter Bits 7 to 0 (BBC[7:0]). BBC0 is the LSB of the 32-bit counter.
Register Name:
Register Description:
Register Address:
BBC2
BERT Bit Count Register 2
1108h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
BBC14
0
7
BBC15
0
5
BBC13
0
4
BBC12
0
3
BBC11
0
2
BBC10
0
1
BBC9
0
0
BBC8
0
1
BBC17
0
0
BBC16
0
1
BBC25
0
0
BBC24
0
Bits 7 to 0: BERT Bit Counter Bits 15 to 8 (BBC[15:8]).
Register Name:
Register Description:
Register Address:
BBC3
BERT Bit Count Register 3
1109h + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
BBC22
0
7
BBC23
0
5
BBC21
0
4
BBC20
0
3
BBC19
0
2
BBC18
0
Bits 7 to 0: BERT Bit Counter Bits 23 to 16 (BBC[23:16]).
Register Name:
Register Description:
Register Address:
BBC4
BERT Bit Count Register 4
110Ah + (10h x n): where n = 0 to 3, for Ports 1 to 4
Bit #
Name
Default
6
BBC30
0
7
BBC31
0
5
BBC29
0
4
BBC28
0
3
BBC27
0
2
BBC26
0
Bits 7 to 0: BERT Bit Counter Bits 31 to 24 (BBC[31:24]). BBC31 is the MSB of the 32-bit counter.
229 of 273
DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EC7
0
BEC1
BERT Error Count Register 1
110Bh + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
EC6
0
5
EC5
0
4
EC4
0
3
EC3
0
2
EC2
0
1
EC1
0
0
EC0
0
1
EC9
0
0
EC8
0
1
EC17
0
0
EC16
0
Bits 7 to 0: Error Counter Bits 7 to 0 (EC[7:0]). EC0 is the LSB of the 24-bit counter.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EC15
0
BEC2
BERT Error Count Register 2
110Ch + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
EC14
0
5
EC13
0
4
EC12
0
3
EC11
0
2
EC10
0
Bits 7 to 0: Error Counter Bits 15 to 8 (EC[15:8]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EC23
0
BEC3
BERT Error Count Register 3
110Dh + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
EC22
0
5
EC21
0
4
EC20
0
3
EC19
0
2
EC18
0
Bits 7 to 0: Error Counter Bits 23 to 16 (EC[23:16]). EC23 is the MSB of the 24-bit counter.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
BLSR
BERT Latched Status Register
110Eh + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
BBED
0
5
BBCO
0
4
BECO
0
3
BRA1
0
2
BRA0
0
1
BRLOS
0
0
BSYNC
0
Note: All bits in this register are latched and can create interrupts.
Bit 6: BERT Bit-Error-Detected Event (BBED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 5: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows.
Bit 4: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows.
Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit that is set when 32 consecutive ones are
received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit that is set when 32 consecutive zeros are
received.
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS). A latched bit that is set whenever the
receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32
consecutive bit positions.
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DS26524 Quad T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
BSIM
BERT Status Interrupt Mask Register
110Fh + (10h x n): where n = 0 to 3, for Ports 1 to 4
6
BBED
0
5
BBCO
0
4
BECO
0
3
BRA1
0
Bit 6: BERT Bit-Error-Detected Event (BBED).
0 = interrupt masked
1 = interrupt enabled
Bit 5: BERT Bit Counter Overflow Event (BBCO).
0 = interrupt masked
1 = interrupt enabled
Bit 4: BERT Error Counter Overflow Event (BECO).
0 = interrupt masked
1 = interrupt enabled
Bit 3: BERT Receive All-Ones Condition (BRA1).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 2: BERT Receive All-Zeros Condition (BRA0).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS)
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 0: BERT in Synchronization Condition (BSYNC).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
232 of 273
2
BRA0
0
1
BRLOS
0
0
BSYNC
0
DS26524 Quad T1/E1/J1 Transceiver
10.
FUNCTIONAL TIMING
10.1
T1 Receiver Functional Timing Diagrams
Figure 10-1. T1 Receive-Side D4 Timing
1
FRAME#
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
RFSYNC
RSYNC 1
RSYNC 2
RSYNC
3
NOTE 1: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0).
NOTE 2: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1).
NOTE 3: RSYNC IN THE MULTIFRAME MODE (RIOCR.0 = 1).
Figure 10-2. T1 Receive-Side ESF Timing
FRAME#
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
1
RSYNC
RFSYNC
RSYNC
RSYNC
2
3
NOTE 1: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0).
NOTE 2: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1).
NOTE 3: RSYNC IN THE MULTIFRAME MODE (RIOCR.0 = 1).
233 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)
RCLK
CHANNEL 23
RSER
CHANNEL 24
CHANNEL 1
LSB
LSB MSB
F
MSB
RSYNC
RFSYNC
RSIG
CHANNEL 23
A
B C/A D/B
CHANNEL 24
A
B C/A D/B
CHANNEL 1
A
RCHCLK
RCHBLK1
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
RSYSCLK
CHANNEL 23
RSER
CHANNEL 24
CHANNEL 1
LSB
LSB MSB
F
MSB
RSYNC1
RMSYNC
2
RSYNC
RSIG
CHANNEL 23
A
B C/A D/B
CHANNEL 24
A
B C/A D/B
RCHCLK
RCHBLK
3
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
234 of 273
CHANNEL 1
A
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RSYSCLK
RSER
RSYNC
1
CHANNEL 31
CHANNEL 32
CHANNEL 1
LSB
LSB MSB
2
RMSYNC
3
RSYNC
RSIG
A
CHANNEL 31
B C/A D/B
A
CHANNEL 32
B C/A D/B
RCHCLK
RCHBLK
4
NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO ONE.
NOTE 2: RSYNC IS IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE-SIDE ELASTIC STORE.
235 of 273
CHANNEL 1
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode
RSYNC
RSER1
FR1 CH 32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
RSIG1
FR1 CH132
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
RSER2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
RSIG2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
RSER3
FR4
Ch32
FR5
Ch32
FR6
Ch32
FR7
Ch32
FR0
Ch1
FR1
Ch1
FR2
Ch1
FR3
Ch1
FR4
Ch1
FR5
Ch1
FR6
Ch1
FR7
Ch1
FR0
Ch2
FR1
Ch2
FR2
Ch2
FR3
Ch2
FR4
Ch2
FR5
Ch2
FR6
Ch2
FR7
Ch2
RSIG3
FR4
Ch32
FR5
Ch32
FR6
Ch32
FR7
Ch32
FR0
Ch1
FR1
Ch1
FR2
Ch1
FR3
Ch1
FR4
Ch1
FR5
Ch1
FR6
Ch1
FR7
Ch1
FR0
Ch2
FR1
Ch2
FR2
Ch2
FR3
Ch2
FR4
Ch2
FR5
Ch2
FR6
Ch2
FR7
Ch2
BIT DETAIL
SYSCLK
RSYNC4
Framer 3, Channel 32
RSER
Framer 0, Channel 1
LSB MSB
Framer 3, Channel 32
RSIG
A
B
C/A D/B
Framer 1, Channel 1
LSB MSB
Framer 0, Channel 1
A
B
LSB MSB
Framer 1, Channel 1
C/A D/B
A
B
C/A D/B
A
B
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. 16.384 MHz bus configuration.
4. RSYNC is in the input mode (RIOCR.2 = 0).
5. Shows system implementation with multiple DS26528 cores driving the backplane.
6. Though not shown, RCHCLK continues to mark the channel LSB for the framers active period.
7. Though not shown, RCHBLK continues to mark the blocked channels for the framers active period.
236 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode
RSYNC
RSER1
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
RSIG1
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
RSER2
FR2 CH1-32
FR3 CH1-32 FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
RSIG2
FR2 CH1-32
FR3 CH1-32
FR1 CH1-32
RSER3
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
FR0
Ch1-32 Ch1-32
FR1
Ch1-32
FR2
Ch1-32
RSIG3
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR0 CH1-32
FR0
Ch1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32
FR0 CH1-32 FR1 CH1-32
FR2 CH1-32 FR3 CH1-32
FR3
Ch1-32
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR0
Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR3
Ch1-32
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR3
Ch1-32
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR0
Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR3
Ch1-32
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
BIT DETAIL
SYSCLK
RSYNC4
Framer 3, Channel 32
RSER
Framer 0, Channel 1
LSB MSB
Framer 3, Channel 32
RSIG
A
B
C/A D/B
Framer 0, Channel 2
LSB MSB
Framer 0, Channel 1
A
B
LSB MSB
Framer 0, Channel 2
C/A D/B
A
B
C/A D/B
A
B
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. 16.384 MHz bus configuration.
4. RSYNC is in the input mode (RIOCR.2 = 0).
5. Shows system implementation with multiple DS26528 cores driving the backplane.
6. Though not shown, RCHCLK continues to mark the channel LSB for the framers active period.
7. Though not shown, RCHBLK continues to mark the blocked channels for the framers active period.
237 of 273
DS26524 Quad T1/E1/J1 Transceiver
10.2
T1 Transmitter Functional Timing Diagrams
Figure 10-8. T1 Transmit-Side D4 Timing
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
1
TSYNC
TSSYNC
2
TSYNC
3
TSYNC
NOTE 1: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0).
NOTE 2: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1).
NOTE 3: TSYNC IN THE MULTIFRAME MODE (TIOCR.0 = 1).
Figure 10-9. T1 Transmit-Side ESF Timing
FRAME#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5
TSYNC1
TSSYNC
TSYNC
2
3
TSYNC
NOTE 1: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0).
NOTE 2: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1).
NOTE 3: TSYNC IN THE MULTIFRAME MODE (TIOCR.0 = 1).
238 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)
TCLK
CHANNEL 1
TSER
LSB
F
CHANNEL 2
MSB
LSB MSB
LSB MSB
TSYNC1
TSYNC2
CHANNEL 1
TSIG
D/B
A
B
CHANNEL 2
C/A
D/B
A
B
C/A
D/B
TCHCLK
TCHBLK 3
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TIOCR.2 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (TIOCR.2 = 0).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
TSYSCLK
CHANNEL 23
CHANNEL 24
LSB MSB
TSER
CHANNEL 1
LSB
F MSB
TSSYNC
CHANNEL 23
TSIG
A
B
CHANNEL 24
C/A D/B
A
TCHCLK
TCHBLK 1
NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
239 of 273
B
CHANNEL 1
C/A D/B
A
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
TSYSCLK
CHANNEL 31
TSER
1
CHANNEL 32
CHANNEL 1
LSB F3
LSB MSB
TSSYNC
CHANNEL 31
TSIG
A
B
CHANNEL 32
C/A D/B
A
B
CHANNEL 1
C/A D/B
A
TCHCLK
TCHBLK 2
NOTE 1: TSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1.
NOTE 3: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE
ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1. (NORMALLY THE TRANSMIT-SIDE FORMATTER
OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS THROUGH THE F-BIT
POSITION).
240 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode
TSYNC
TSER1
FR1 CH 32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
TSIG1
FR1 CH132
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
TSER2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
TSIG2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
TSER3
FR4
Ch32
FR5
Ch32
FR6
Ch32
FR7
Ch32
FR0
Ch1
FR1
Ch1
FR2
Ch1
FR3
Ch1
FR4
Ch1
FR5
Ch1
FR6
Ch1
FR7
Ch1
FR0
Ch2
FR1
Ch2
FR2
Ch2
FR3
Ch2
FR4
Ch2
FR5
Ch2
FR6
Ch2
FR7
Ch2
TSIG3
FR4
Ch32
FR5
Ch32
FR6
Ch32
FR7
Ch32
FR0
Ch1
FR1
Ch1
FR2
Ch1
FR3
Ch1
FR4
Ch1
FR5
Ch1
FR6
Ch1
FR7
Ch1
FR0
Ch2
FR1
Ch2
FR2
Ch2
FR3
Ch2
FR4
Ch2
FR5
Ch2
FR6
Ch2
FR7
Ch2
BIT DETAIL
SYSCLK
TSYNC4
Framer 3, Channel 32
TSER
Framer 0, Channel 1
LSB MSB
Framer 3, Channel 32
TSIG
A
B
C/A D/B
Framer 1, Channel 1
LSB MSB
Framer 0, Channel 1
A
B
LSB MSB
Framer 1, Channel 1
C/A D/B
A
B
C/A D/B
A
B
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. 16.384 MHz bus configuration.
4. TSYNC is in the input mode (TIOCR.2 = 0).
5. Though not shown, TCHCLK continues to mark the channel LSB for the framers active period.
6. Though not shown, TCHBLK continues to mark the blocked channels for the framers active period.
241 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode
TSYNC
TSER1
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
TSIG1
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
TSER2
FR2 CH1-32
FR3 CH1-32 FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
TSIG2
FR2 CH1-32
FR3 CH1-32
FR1 CH1-32
TSER3
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
FR0
Ch1-32 Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR3
FR4
Ch1-32 Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR0
Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR3
Ch1-32
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
TSIG3
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR3
FR4
Ch1-32 Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR0
Ch1-32
FR1
Ch1-32
FR2
Ch1-32
FR3
Ch1-32
FR4
Ch1-32
FR5
Ch1-32
FR6
Ch1-32
FR7
Ch1-32
FR0 CH1-32
FR0
Ch1-32
FR3 CH1-32
FR2 CH1-32 FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32 FR3 CH1-32
FR0 CH1-32 FR1 CH1-32
FR2 CH1-32 FR3 CH1-32
BIT DETAIL
SYSCLK
TSYNC4
Framer 3, Channel 32
TSER
Framer 0, Channel 1
LSB MSB
Framer 3, Channel 32
TSIG
A
B
C/A D/B
Framer 0, Channel 2
LSB MSB
Framer 0, Channel 1
A
B
LSB MSB
Framer 0, Channel 2
C/A D/B
A
B
C/A D/B
A
B
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. 16.384 MHz bus configuration.
4. TSYNC is in the input mode (TIOCR.2 = 0).
5. Though not shown, TCHCLK continues to mark the channel LSB for the framers active period.
6. Though not shown, TCHBLK continues to mark the blocked channels for the framers active period.
242 of 273
DS26524 Quad T1/E1/J1 Transceiver
10.3
E1 Receiver Functional Timing Diagrams
Figure 10-15. E1 Receive-Side Timing
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RFSYNC
RSYNC 1
RSYNC
2
NOTE 1: RSYNC IN FRAME MODE (RIOCR.0 = 0).
NOTE 2: RSYNC IN MULTIFRAME MODE (RIOCR.0 = 1).
NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled)
RCLK
CHANNEL 32
CHANNEL 1
RSER
LSB
Si
1
A
CHANNEL 2
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
RSYNC
RFSYNC
CHANNEL 32
RSIG
A
B
CHANNEL 1
C
D
CHANNEL 2
A
B
Note 3
RCHCLK
RCHBLK
1
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 2: SHOWN IS A RNAF FRAME BOUNDARY.
NOTE 3. RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
243 of 273
1
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
RSYSCLK
CHANNEL 23/31
1
RSER
CHANNEL 24/32
CHANNEL 1/2
LSB
LSB MSB
F
MSB
RSYNC2
RMSYNC
3
RSYNC
RCHCLK
4
RCHBLK
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS
MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE).
NOTE 2: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNC IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RSYSCLK
CHANNEL 31
RSER
CHANNEL 32
LSB MSB
CHANNEL 1
LSB MSB
1
RSYNC
RMSYNC
RSYNC
2
RSIG
A
CHANNEL 31
C
B
D
A
CHANNEL 32
C
B
D
CHANNEL 1
Note 4
RCHCLK
RCHBLK
3
NOTE 1: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 2: RSYNC IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
244 of 273
DS26524 Quad T1/E1/J1 Transceiver
10.4
E1 Transmitter Functional Timing Diagrams
Figure 10-19. E1 Transmit-Side Timing
FRAME#
14 15 16 1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
1
TSYNC
TSSYNC
TSYNC
2
NOTE 1: TSYNC IN FRAME MODE (TIOCR.0 = 0).
NOTE 2: TSYNC IN MULTIFRAME MODE (TIOCR.0 = 1).
NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC-4 MF BEGIN WITH THE TAF FRAME.
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)
TCLK
CHANNEL 1
TSER
LSB
Si
1
CHANNEL 2
A Sa4 Sa5 Sa6 Sa7 Sa8 MSB
LSB MSB
TSYNC1
TSYNC2
CHANNEL 1
TSIG
CHANNEL 2
D
A
B
C
D
TCHCLK
TCHBLK 3
NOTE 1: TSYNC IN THE OUTPUT MODE (TIOCR.2 = 1).
NOTE 2: TSYNC IN THE INPUT MODE (TIOCR.2 = 0).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 4: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT
FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000).
NOTE 5: SHOWN IS A TNAF FRAME BOUNDARY.
245 of 273
9 10
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
TSYSCLK
CHANNEL 23
1
CHANNEL 24
LSB MSB
TSER
CHANNEL 1
LSB
F
MSB
TSSYNC
TCHCLK
TCHBLK
2
NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
TSYSCLK
CHANNEL 31
TSER
TSYNC
CHANNEL 32
LSB MSB
1
TSIG
CHANNEL 32
C
A
B
D
CHANNEL 31
C
A
B
D
TCHCLK
TCHBLK
CHANNEL 1
LSB MSB
2
NOTE 1: TSYNC IN THE INPUT MODE (TIOCR.2 = 0).
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
246 of 273
CHANNEL 1
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-23. E1 G.802 Timing
TS #
31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2
RSYNC
TSYNC
RCHCLK
TCHCLK
RCHBLK
TCHBLK
RCLK / RSYSCLK
TCLK / TSYSCLK
CHANNEL 25
RSER / TSER
CHANNEL 26
LSB MSB
RCHCLK / TCHCLK
RCHBLK / TCHBLK
NOTE: RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH
25, AND BIT 1 OF TIME SLOT 26.
247 of 273
DS26524 Quad T1/E1/J1 Transceiver
11.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V
Supply Voltage (VDD) Range with Respect to VSS…………………………………………………………..-0.3V to +3.63V
Operating Temperature Range
Commercial (DS26524G)...…………………………………………………………….………………0°C to +70°C
Industrial (DS26524GN)…………………………………………………………….……..-40°C to +85°C (Note 1)
Storage Temperature Range...………………………………………………………………………………-55°C to +125°C
Soldering Temperature………………………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
Note 1:
Specifications to -40°C are guaranteed by design and not production tested.
Table 11-1. Recommended DC Operating Conditions
(TA = -40°C to +85°C for DS26524GN.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 1
VIH
2.0
5.5
V
Logic 0
VIL
-0.3
+0.8
V
Supply
VDD
3.135
3.3
3.465
V
MIN
TYP
MAX
UNITS
Table 11-2. Capacitance
(TA = +25°C)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CONDITIONS
CIN
7
pF
COUT
7
pF
Table 11-3. Recommended DC Operating Conditions
(VDD = 3.135V to 3.465V, TA = -40°C to +85°C for DS26524GN.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
260
450
mA
-10.0
+10.0
µA
-500.0
+10.0
µA
+10.0
µA
Supply Current at 3.3V
IDD
(Notes 2, 3)
Input Leakage
IIL
Pullup Pin Input Leakage
IILP
Tri-State Output Leakage
IOL
-10.0
Output Voltage (Io = -1.6mA)
VOH
2.4
Output Voltage (Io = +0.4mA)
VOL
(Note 4)
V
0.4
Note 2:
RCLK1-n = TCLK1-n = 2.048MHz.
Note 3:
Max power dissipation is measured with both ports transmitting an all-ones data pattern with a transmitter load of 100Ω.
Note 4:
Pullup pins include DIGIOEN, JTRST, JTMS, and JTDI.
248 of 273
V
DS26524 Quad T1/E1/J1 Transceiver
11.1
Thermal Characteristics
Table 11-4. Thermal Characteristics
PARAMETER
CONDITIONS
DS26524G
MIN
TYP
MAX
0
+70
-40
+85
Ambient Temperature (Note 1)
UNITS
°C
DS26524GN
Junction Temperature
+125
Theta-JA (θJA) in Still Air for 256-Pin TE-CSBGA
(Note 2)
+17.5
°C
°C/W
Note 1:
The package is mounted on a four-layer JEDEC standard test board.
Note 2:
Theta-JA (θJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test
board.
11.2
Line Interface Characteristics
Table 11-5. Transmitter Characteristics
PARAMETER
SYMBOL
CONDITIONS
Output Mark Amplitude
Vm
E1 75Ω
E1 120Ω
T1 100Ω
J1 110Ω
Output Zero Amplitude
Vs
(Note 1)
Transmit Amplitude Variation with
Supply
MIN
TYP
MAX
UNITS
2.13
2.70
2.40
2.40
2.37
3.00
3.00
3.00
2.61
3.30
3.60
3.60
V
-0.3
+0.3
V
-1
+1
%
MAX
UNITS
43
dB
Table 11-6. Receiver Characteristics
PARAMETER
Cable Attenuation
SYMBOL
CONDITIONS
MIN
TYP
Attn
192
192
2048
24
192
192
Allowable Zeros Before Loss
(Note 1)
Allowable Ones Before Loss
(Note 2)
Note 1:
192 zeros for T1 and T1.231 Specification Compliance. 192 zeros for E1 and G.775 Specification Compliance. 2048 zeros for
ETS 300 233 compliance.
Note 2:
24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETS 300 233.
249 of 273
DS26524 Quad T1/E1/J1 Transceiver
12.
AC TIMING CHARACTERISTICS
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus
signals.
12.1
Microprocessor Bus AC Characteristics
Table 12-1. AC Characteristics—Microprocessor Bus Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26524GN.) (Note 1) (See Figure 12-1, Figure 12-2,
Figure 12-3, and Figure 12-4.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for A[12:0] Valid to CSB
Active
t1
0
ns
Setup Time for CSB Active to Either RDB,
or WRB Active
t2
0
ns
Delay Time from Either RDB or DSB
Active to D[7:0] Valid
t3
Hold Time from Either RDB or WRB
Inactive to CSB Inactive
t4
0
Hold Time from CSB or RDB or DSB
Inactive to D[7:0] Tri-State
t5
5
Wait Time from WRB Active to Latch Data
t6
40
ns
Data Setup Time to WRB Inactive
t7
10
ns
Data Hold Time from WRB Inactive
t8
2
ns
Address Hold from WRB Inactive
t9
0
ns
Write Access to Subsequent Write/Read
Access Delay Time
t10
80
ns
(Note 2)
(Note 2)
Note 1:
The timing parameters in this table are guaranteed by design (GBD).
Note 2:
If supplying a 1.544MHz MCLK, the FREQSEL bit must be set to meet this timing.
250 of 273
125
ns
ns
20
ns
DS26524 Quad T1/E1/J1 Transceiver
Figure 12-1. Intel Bus Read Timing (BTS = 0)
t9
A[12:0]
Address Valid
Data Valid
D[7:0]
t5
WRB
t1
CSB
t2
t4
t3
RDB
t10
Figure 12-2. Intel Bus Write Timing (BTS = 0)
t9
A[12:0]
Address Valid
D[7:0]
t7
t8
RDB
t1
CSB
t2
t6
WRB
t4
t10
251 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 12-3. Motorola Bus Read Timing (BTS = 1)
t9
Address Valid
A[12:0]
Data Valid
D[7:0]
t5
RWB
t1
CSB
t2
t4
t3
DSB
t10
Figure 12-4. Motorola Bus Write Timing (BTS = 1)
t9
A[12:0]
Address Valid
D[7:0]
t7
t8
RWB
t1
CSB
t2
t6
DSB
t4
t10
252 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 12-2. Receiver AC Characteristics
(VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26524GN.) (Note 1) (See Figure 12-5, Figure 12-6, and
Figure 12-7.)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 2)
(Note 3)
TYP
MAX
648
488
UNITS
RCLK Period
tCP
RCLK Pulse Width
tCH
tCL
RSYSCLK Period
tSP
RSYSCLK Pulse Width
tSH
tSL
125
125
60
60
30
30
RSYNC Setup to RSYSCLK Falling
tSU
20
RSYNC Pulse Width
tPW
50
Delay RCLK to RSER, RSIG Valid
tD1
50
ns
tD2
50
ns
tD3
50
ns
tD4
50
ns
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC
Delay RSYSCLK to RSER, RSIG
Valid
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC
(Note 4)
(Note 5)
Note 1:
The timing parameters in this table are guaranteed by design (GBD).
Note 2:
T1 Mode.
Note 3:
E1 Mode.
Note 4:
RSYSCLK = 1.544MHz.
Note 5:
RSYSCLK = 2.048MHz.
253 of 273
ns
ns
648
488
ns
ns
tSH - 5
ns
ns
DS26524 Quad T1/E1/J1 Transceiver
Figure 12-5. Receive Framer Timing—Backplane (T1 Mode)
RCLK
t D1
F-BIT
RSER/RSIG
t D2
RCHCLK
t D2
RCHBLK
t D2
RFSYNC/RMSYNC
t D2
RSYNC 1
NOTE 1: RSYNC IS IN THE OUTPUT MODE.
NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED.
254 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 12-6. Receive-Side Timing, Elastic Store Enabled (T1 Mode)
t SL
RSYSCLK
t SH
t SP
t D3
SEE NOTE 3
RSER/RSIG
t D4
RCHCLK
t
D4
RCHBLK
t
D4
RMSYNC
t D4
1
RSYNC
t HD
t SU
RSYNC2
NOTE 1: RSYNC IS IN THE OUTPUT MODE.
NOTE 2: RSYNC IS IN THE INPUT MODE.
NOTE 3: F-BIT WHEN RIOCR.4 = 0, MSB OF TS0 WHEN RIOCR.4 = 1.
Figure 12-7. Receive Framer Timing—Line Side
t CL
t CH
RCLK
tCP
t SU
RTIP, RRING
t HD
255 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 12-3. Transmit AC Characteristics
(VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26524GN.) (Note 1) (See Figure 12-8, Figure 12-9,
Figure 12-10, and Figure 12-11.)
PARAMETER
SYMBOL
CONDITIONS
(Note 2)
(Note 3)
MIN
TCLK Period
tCP
TCLK Pulse Width
tCH
tCL
TSYSCLK Period
tSP
TSYSCLK Pulse Width
tSH
tSL
125
125
60
60
30
30
TSYNC or TSSYNCIO Setup to TCLK
or TSYSCLK falling
tSU
20
TSYNC or TSSYNCIO Pulse Width
tPW
TSSYNCIO Pulse Width (Notes 7, 8)
tPW
(Note 4)
(Note 5)
(Note 6)
TYP
648
488
MAX
UNITS
ns
ns
648
448
ns
ns
tCH - 5
or
tSH - 5
50
488
244
122
61
ns
ns
ns
TSER, TSIG Setup to TCLK,
TSYSCLK Falling
TSER, TSIG Hold from TCLK,
TSYSCLK Falling
Delay TCLK to TCHBLK, TCHCLK,
TSYNC
tSU
20
ns
tHD
20
ns
tD2
50
ns
Delay TSYSCLK to TCHCLK, TCHBLK
tD3
50
ns
Delay BPCLK to TSSYNCIO (Note 7)
tD5
5
ns
Note 1:
The timing parameters in this table are guaranteed by design (GBD).
Note 2:
T1 Mode.
Note 3:
E1 Mode.
Note 4:
RSYSCLK = 1.544MHz.
Note 5:
RSYSCLK = 2.048MHz.
Note 6:
TSSYNCIO configured as an input (GTCR2.1 = 0).
Note 7:
TSSYNCIO configured as an output (GTCR2.1 = 1).
Note 8:
Varies depending on the frequency of BPCLK.
256 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 12-8. Transmit Formatter Timing—Backplane
t CP
t CL
t CH
TCLK
t D1
TESO
t SU
TSER/TSIG
t HD
t D2
TCHCLK
t D2
TCHBLK
t D2
TSYNC1
t SU
t HD
TSYNC2
NOTE 1: TSYNC IS IN THE OUTPUT MODE.
NOTE 2: TSYNC IS IN THE INPUT MODE.
NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
NOTE 5: NO RELATIONSHIP BETWEEN TCHCLK AND TCHBLK AND THE OTHER SIGNALS IS IMPLIED.
257 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 12-9. Transmit Formatter Timing, Elastic Store Enabled
t SP
t SL
t SH
TSYSCLK
t SU
TSER
t D3
t HD
TCHCLK
t D3
TCHBLK
t HD
t SU
TSSYNC
NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
Figure 12-10. BPCLK Timing
BPC LK
tD 5
T SSYN C IO 1
N otes:
1. TS S Y NC IO is configured as an O utput (G TC R 2.TS S Y N IO S E L = 1)
Figure 12-11. Transmit Formatter Timing—Line Side
t CP
t CL
TCLK
TTIP, TRING
t D3
258 of 273
t CH
DS26524 Quad T1/E1/J1 Transceiver
12.2
JTAG Interface Timing
Table 12-4. JTAG Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26524GN.) (See Figure 12-12.)
PARAMETER
SYMBOL
JTCLK Clock Period
CONDITIONS
MIN
t1
JTCLK Clock High:Low Time
t2:t3
(Note 1)
50
TYP
MAX
UNITS
1000
ns
500
ns
JTCLK to JTDI, JTMS Setup Time
t4
5
ns
JTCLK to JTDI, JTMS Hold Time
t5
2
ns
JTCLK to JTDO Delay
t6
2
50
ns
JTCLK to JTDO High-Impedance Delay
t7
2
50
ns
JTRST Width Low Time
t8
100
Note 1:
Clock can be stopped high or low.
Figure 12-12. JTAG Interface Timing Diagram
t1
t2
t3
JTCLK
t4
t5
JTDI, JTMS, JTRST
t6
t7
JTDO
t8
JTRST
259 of 273
ns
DS26524 Quad T1/E1/J1 Transceiver
12.3
System Clock AC Characteristics
Table 12-5. System Clock AC Charateristics
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.544
REF_CLK Frequency
MHz
2.048
REF_CLK Duty Cycle
Gapped Clock Frequency
40
(Note 1)
Gapped Clock Duty Cycle
Note 1:
43
40
The gapped clock is output on the RCHCLK pin when RESCR.6 = 1.
260 of 273
45
60
%
60
MHz
60
%
DS26524 Quad T1/E1/J1 Transceiver
13.
JTAG BOUNDARY SCAN AND TEST ACCESS PORT
The DS26524 IEEE 1149.1 design supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Table 13-1. The DS26524
contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions for details.
Figure 13-1. JTAG Functional Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
MUX
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
VDD
10kΩ
VDD
OUTPUT ENABLE
VDD
10kΩ
10kΩ
JTDI
SELECT
JTMS
JTCLK
JTRST
261 of 273
JTDO
DS26524 Quad T1/E1/J1 Transceiver
13.1
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
See Figure 13-2.
13.1.1 Test-Logic-Reset
Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE
instruction. All system logic of the device operates normally.
13.1.2 Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test
registers remain idle.
13.1.3 Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the
Capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller
to the Select-IR-Scan state.
13.1.4 Capture-DR
Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not
call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current
value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is LOW, or it goes to the
Exit1-DR state if JTMS is HIGH.
13.1.5 Shift-DR
The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one
stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is
not placed in the serial path, it maintains its previous state.
13.1.6 Exit1-DR
While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-DR
state.
13.1.7 Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain
their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS
HIGH puts the controller in the Exit2-DR state.
13.1.8 Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and
terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state.
13.1.9 Update-DR
A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
13.1.10
Select-IR-Scan
All test registers retain their previous state. The instruction register remains unchanged during this state. With
JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence
for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-LogicReset state.
262 of 273
DS26524 Quad T1/E1/J1 Transceiver
13.1.11
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Exit1IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the Shift-IR state.
13.1.12
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one
stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers,
remains at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the Exit1-IR
state. A rising edge on JTCLK with JTMS LOW keeps the controller in the Shift-IR state while moving data one
stage thorough the instruction shift register.
13.1.13
Exit1-IR
A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-IR state. If JTMS is HIGH on the rising
edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
13.1.14
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK puts the
controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is LOW during a rising edge on
JTCLK.
13.1.15
Exit2-IR
A rising edge on JTCLK with JTMS LOW puts the controller in the Update-IR state. The controller loops back to
Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
13.1.16
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of
JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising
edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller
enters the Select-DR-Scan state.
263 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 13-2. TAP Controller State Diagram
1
Test Logic
Reset
0
0
Run Test/
Idle
1
Select
DR-Scan
1
Select
IR-Scan
0
1
0
1
Capture DR
Capture IR
0
Shift DR
0
Shift IR
0
1
Exit IR
Pause IR
0
1
0
Exit2 DR
1
0
Exit2 IR
1
1
Update DR
Update IR
1
1
0
264 of 273
1
0
0
Pause DR
0
1
1
Exit DR
1
0
0
DS26524 Quad T1/E1/J1 Transceiver
13.2
Instruction Register
The instruction register contains a shift register as well as a latched parallel output, and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial
output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the
controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift
register to the instruction parallel output. Instructions supported by the DS26524 and its respective operational
binary codes are shown in Table 13-1.
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE:PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
010
111
000
011
100
001
13.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into the
boundary scan register via JTDI using the Shift-DR state.
13.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s normal
operation.
13.2.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will
sample all digital inputs into the boundary scan register.
13.2.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
13.2.5 HIGHZ
All digital outputs of the device will be placed in a high-impedance state. The BYPASS register will be connected
between JTDI and JTDO.
13.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
ID code will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
265 of 273
DS26524 Quad T1/E1/J1 Transceiver
13.3
JTAG ID Codes
Table 13-2. ID Code Structure
REVISION
ID[31:28]
DEVICE CODE
ID[27:12]
MANUFACTURER’S CODE
ID[11:1]
REQUIRED
ID[0]
DS26528
Consult factory
0000000000110111
00010100001
1
DS26524
Consult factory
0000000000111001
00010100001
1
DEVICE
13.4
Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included with the DS26524 design. This test register is the identification register and
is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
13.4.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells,
and is n bits in length. See Table 13-3 for all the cell bit locations and definitions.
13.4.2 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which
provides a short path between JTDI and JTDO.
13.4.3 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Table 13-3. Boundary Scan Control Bits
CELL#
NAME
TYPE
0
—
controlr
1
rser(1)
output3
2
—
controlr
CONTROL
CELL
CELL#
NAME
TYPE
20
rchblk_clk(2)
output3
21
rchblk_clk(2)
observe_only
22
—
controlr
0
3
rm_rfsync(1)
output3
23
rsig(2)
output3
4
rm_rfsync(1)
observe_only
2
24
rsig(2)
observe_only
5
—
controlr
25
—
controlr
6
rsync(1)
output3
26
rlf_ltc(2)
output3
7
rsync(1)
observe_only
27
—
controlr
28
al_rsigf_flos(2)
output3
29
—
controlr
5
8
—
controlr
9
tsig(1)
output3
10
tsig(1)
observe_only
30
rser(2)
output3
11
—
controlr
31
—
controlr
12
tsync(1)
output3
32
rm_rfsync(2)
output3
13
tsync(1)
observe_only
33
rm_rfsync(2)
observe_only
14
tser(1)
observe_only
34
—
controlr
15
tclk(1)
observe_only
35
rsync(2)
output3
16
—
controlr
36
rsync(2)
observe_only
8
11
17
tchblk_clk(1)
output3
37
—
controlr
18
tchblk_clk(1)
observe_only
16
38
tsig(2)
output3
19
—
controlr
39
tsig(2)
observe_only
266 of 273
CONTROL
CELL
19
22
25
27
29
31
34
37
DS26524 Quad T1/E1/J1 Transceiver
CELL#
NAME
TYPE
40
—
controlr
CONTROL
CELL
CELL#
NAME
TYPE
82
—
controlr
41
tsync(2)
output3
83
rm_rfsync(7)
output3
42
tsync(2)
observe_only
84
rm_rfsync(7)
observe_only
43
tser(2)
observe_only
85
—
controlr
44
tclk(2)
observe_only
86
rser(7)
output3
45
—
controlr
46
tchblk_clk(2)
output3
47
tchblk_clk(2)
48
49
40
87
—
controlr
88
al_rsigf_flos(7)
output3
observe_only
89
—
controlr
mclk
observe_only
90
rlf_ltc(7)
output3
—
controlr
91
—
controlr
45
50
refclkio
output3
92
rsig(7)
output3
51
refclkio
observe_only
49
93
rsig(7)
observe_only
52
—
controlr
94
—
controlr
53
bpclk
output3
95
rchblk_clk(7)
output3
54
a(12)
observe_only
96
rchblk_clk(7)
observe_only
55
a(11)
observe_only
97
—
controlr
56
a(10)
observe_only
98
tchblk_clk(8)
output3
57
digio_en
observe_only
99
tchblk_clk(8)
observe_only
58
a(9)
observe_only
100
tclk(8)
observe_only
59
a(8)
observe_only
101
tser(8)
observe_only
60
a(7)
observe_only
102
—
controlr
61
a(6)
observe_only
103
tsync(8)
output3
62
a(5)
observe_only
104
tsync(8)
observe_only
63
a(4)
observe_only
105
—
controlr
64
a(3)
observe_only
106
tsig(8)
output3
65
a(2)
observe_only
107
tsig(8)
observe_only
66
a(1)
observe_only
108
—
controlr
67
a(0)
observe_only
109
rsync(8)
output3
68
—
controlr
110
rsync(8)
observe_only
52
69
tchblk_clk(7)
output3
111
—
controlr
70
tchblk_clk(7)
observe_only
68
112
rm_rfsync(8)
output3
71
tclk(7)
observe_only
113
rm_rfsync(8)
observe_only
72
tser(7)
observe_only
114
—
controlr
73
—
controlr
115
rser(8)
output3
74
tsync(7)
output3
116
—
controlr
75
tsync(7)
observe_only
73
117
al_rsigf_flos(8)
output3
76
—
controlr
118
—
controlr
77
tsig(7)
output3
119
rlf_ltc(8)
output3
78
tsig(7)
observe_only
120
—
controlr
79
—
controlr
121
rclk(8)
output3
80
rsync(7)
output3
122
rclk(8)
observe_only
81
rsync(7)
observe_only
123
—
controlr
76
79
267 of 273
CONTROL
CELL
82
85
87
89
91
94
97
102
105
108
111
114
116
118
120
DS26524 Quad T1/E1/J1 Transceiver
CONTROL
CELL
123
CELL#
NAME
TYPE
CELL#
NAME
TYPE
124
rclk(7)
output3
166
tsig(6)
observe_only
125
rclk(7)
observe_only
167
—
controlr
126
—
controlr
168
tsync(6)
output3
127
rsig(8)
output3
169
tsync(6)
observe_only
128
rsig(8)
observe_only
170
tser(6)
observe_only
171
tclk(6)
observe_only
172
—
controlr
126
129
—
controlr
130
rchblk_clk(8)
output3
131
rchblk_clk(8)
observe_only
173
tchblk_clk(6)
output3
132
—
controlr
174
tchblk_clk(6)
observe_only
133
rclk(6)
output3
175
—
controlr
134
rclk(6)
observe_only
176
rchblk_clk(5)
output3
135
—
controlr
177
rchblk_clk(5)
observe_only
136
rclk(5)
output3
178
—
controlr
137
rclk(5)
observe_only
179
rsig(5)
output3
138
resetb
observe_only
180
rsig(5)
observe_only
139
txen_b
observe_only
181
—
controlr
140
bts
observe_only
182
rlf_ltc(5)
output3
141
rsysclk
observe_only
183
—
controlr
142
—
controlr
184
al_rsigf_flos(5)
output3
143
tssyncio
output3
185
—
controlr
144
tssyncio
observe_only
186
rser(5)
output3
145
tsysclk
observe_only
187
—
controlr
146
—
controlr
188
rm_rfsync(5)
output3
147
rchblk_clk(6)
output3
189
rm_rfsync(5)
observe_only
148
rchblk_clk(6)
observe_only
190
—
controlr
149
—
controlr
191
rsync(5)
output3
150
rsig(6)
output3
192
rsync(5)
observe_only
151
rsig(6)
observe_only
193
—
controlr
152
—
controlr
194
tsig(5)
output3
153
rlf_ltc(6)
output3
195
tsig(5)
observe_only
154
—
controlr
196
—
controlr
155
al_rsigf_flos(6)
output3
197
tsync(5)
output3
156
—
controlr
198
tsync(5)
observe_only
157
rser(6)
output3
199
tser(5)
observe_only
200
tclk(5)
observe_only
201
—
controlr
129
132
135
142
146
149
152
154
156
158
—
controlr
159
rm_rfsync(6)
output3
160
rm_rfsync(6)
observe_only
202
tchblk_clk(5)
output3
161
—
controlr
203
tchblk_clk(5)
observe_only
158
161
CONTROL
CELL
167
172
175
178
181
183
185
187
190
193
196
201
162
rsync(6)
output3
204
—
controlr
163
rsync(6)
observe_only
205
intb
output3
204
164
—
controlr
206
d(7)
output3
220
165
tsig(6)
output3
207
d(7)
observe_only
164
268 of 273
DS26524 Quad T1/E1/J1 Transceiver
CELL#
NAME
TYPE
208
d(6)
output3
209
d(6)
observe_only
210
d(5)
output3
211
d(5)
observe_only
212
d(4)
output3
213
d(4)
observe_only
214
d(3)
output3
215
d(3)
observe_only
216
d(2)
output3
217
d(2)
observe_only
CONTROL
CELL
220
CELL#
NAME
TYPE
250
rsig(4)
output3
251
rsig(4)
observe_only
252
—
controlr
253
rchblk_clk(4)
output3
254
rchblk_clk(4)
observe_only
220
220
220
220
220
255
—
controlr
256
tchblk_clk(3)
output3
257
tchblk_clk(3)
observe_only
258
tclk(3)
observe_only
259
tser(3)
observe_only
218
d(1)
output3
260
—
controlr
219
d(1)
observe_only
261
tsync(3)
output3
220
—
controlr
262
tsync(3)
observe_only
221
d(0)
output3
263
—
controlr
222
d(0)
observe_only
264
tsig(3)
output3
223
rdb_dsb
observe_only
265
tsig(3)
observe_only
224
wrb_rwb
observe_only
266
—
controlr
225
csb
observe_only
267
rsync(3)
output3
226
—
controlr
268
rsync(3)
observe_only
227
tchblk_clk(4)
output3
269
—
controlr
228
tchblk_clk(4)
observe_only
270
rm_rfsync(3)
output3
229
tclk(4)
observe_only
271
rm_rfsync(3)
observe_only
230
tser(4)
observe_only
272
—
controlr
231
—
controlr
273
rser(3)
output3
220
226
232
tsync(4)
output3
274
—
controlr
233
tsync(4)
observe_only
275
al_rsigf_flos(3)
output3
234
—
controlr
276
—
controlr
235
tsig(4)
output3
277
rlf_ltc(3)
output3
236
tsig(4)
observe_only
278
—
controlr
237
—
controlr
238
rsync(4)
output3
239
rsync(4)
240
231
234
279
rsig(3)
output3
280
rsig(3)
observe_only
observe_only
281
—
controlr
—
controlr
282
rchblk_clk(3)
output3
241
rm_rfsync(4)
output3
283
rchblk_clk(3)
observe_only
242
rm_rfsync(4)
observe_only
284
—
controlr
243
—
controlr
285
rclk(4)
output3
244
rser(4)
output3
286
rclk(4)
observe_only
245
—
controlr
287
—
controlr
246
al_rsigf_flos(4)
output3
247
—
controlr
248
rlf_ltc(4)
output3
249
—
controlr
237
240
243
245
247
269 of 273
288
rclk(3)
output3
289
rclk(3)
observe_only
290
—
controlr
291
rclk(2)
output3
CONTROL
CELL
249
252
255
260
263
266
269
272
274
276
278
281
284
287
290
DS26524 Quad T1/E1/J1 Transceiver
CELL#
NAME
TYPE
292
rclk(2)
observe_only
293
—
controlr
294
rclk(1)
output3
295
rclk(1)
296
—
CONTROL
CELL
CELL#
NAME
TYPE
299
—
controlr
300
rsig(1)
output3
301
rsig(1)
observe_only
observe_only
302
—
controlr
controlr
303
rlf_ltc(1)
output3
297
rchblk_clk(1)
output3
298
rchblk_clk(1)
observe_only
293
296
270 of 273
304
—
controlr
305
al_rsigf_flos(1)
output3
CONTROL
CELL
299
302
304
DS26524 Quad T1/E1/J1 Transceiver
14.
PIN CONFIGURATION
Figure 14-1. Pin Configuration—256-Ball TE-CSBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
TTIP1
TTIP1
TRING1
RSYNC1
TCHBLK/
CLK1
TSIG2
REFCLKIO
A11
A7
A1
DVSS
N.C.
DVSS
N.C.
N.C.
N.C.
B
ATVDD1
ATVSS1
TRING1
TSYNC1
RCHBLK/
CLK2
RSYNC2
MCLK
A10
A8
A2
DVSS
N.C.
DVSS
N.C.
ATVSS8
ATVDD8
C
RTIP1
RRING1
AL/
RSIGF/
FLOS1
RMSYNC1/
RFSYNC1
TCLK1
A12
A6
A0
DVSS
N.C.
DVSS
N.C.
N.C.
N.C.
D
ARVDD1
ARVSS1
RLF/
LTC1
RSIG1
TSIG1
RSER2
TCLK2
DIGIOEN
A5
N.C.
N.C.
DVSS
DVSS
N.C.
ARVSS8
ARVDD8
E
ARVDD2
ARVSS2
RLF/
LTC2
RCHBLK/
CLK1
RSER1
RSIG2
TSER2
BPCLK
A4
DVSS
N.C.
N.C.
N.C.
N.C.
ARVSS7
ARVDD7
F
RTIP2
RRING2
AL/
RSIGF/
FLOS2
RCLK1
JTCLK
TSER1
TSYNC2
A9
A3
DVSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
G
ATVDD2
ATVSS2
TRING2
RCLK2
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
N.C.
N.C.
ATVSS7
ATVDD7
H
TTIP2
TTIP2
TRING2
JTDI
DVDDIO
DVDDIO
ACVDD
DVDD
DVDD
DVDDIO
DVDDIO
DVSS
DVSS
N.C.
N.C.
N.C.
J
TTIP3
TTIP3
TRING3
JTDO
DVSSIO
DVSSIO
ACVSS
DVSS
DVSS
DVSSIO
DVSSIO
RESETB
N.C.
N.C.
N.C.
N.C.
K
ATVDD3
ATVSS3
TRING3
JTMS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
N.C.
N.C.
ATVSS6
ATVDD6
L
RTIP3
RRING3
AL/
RSIGF/
FLOS3
RCLK3
JTRST
RCHBLK/ TCHBLK/
CLK3
CLK3
TCLK4
D1
DVSS
DVSS
N.C.
N.C.
N.C.
M
ARVDD3
ARVSS3
RLF/
LTC3
RCLK4
RSIG3
TSYNC3
TSYNC4
RDB/
DSB
D5
DVSS
N.C.
N.C.
BTS
N.C.
ARVSS6
ARVDD6
N
ARVDD4
ARVSS4
RLF/
LTC4
RSER3
RSYNC3
RSER4
TSER4
D0
D6
DVSS
DVSS
N.C.
TSSYNCIO
N.C.
ARVSS5
ARVDD5
P
RTIP4
RRING4
AL/
RSIGF/
FLOS4
RMSYNC3/
RFSYNC3
TCLK3
D2
N.C.
N.C.
N.C.
DVSS
TSYSCLK
N.C.
N.C.
N.C.
R
ATVDD4
ATVSS4
TRING4
TSER3
RSIG4
TSIG4
WRB/
RWB
D4
INTB
DVSS
N.C.
DVSS
N.C.
N.C.
ATVSS5
ATVDD5
T
TTIP4
TTIP4
TRING4
TSIG3
RCHBLK/
CLK4
RSYNC4
CSB
D3
D7
DVSS
N.C.
DVSS
N.C.
N.C.
N.C.
N.C.
RMSYNC2/ TCHBLK/
RFSYNC2
CLK2
RMSYNC4/ TCHBLK/
RFSYNC4
CLK4
271 of 273
RSYSCLK TXENABLE
DS26524 Quad T1/E1/J1 Transceiver
15.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information.)
15.1
256-Ball TE-CSBGA (56-G6028-001)
272 of 273
DS26524 Quad T1/E1/J1 Transceiver
16.
DOCUMENT REVISION HISTORY
REVISION
DATE
102106
012307
060607
112907
DESCRIPTION
PAGES
CHANGED
New product release.
—
Corrected TSYNC1 ball (from B1 to B4).
Corrected RSYNC3 and RSYNC4 (previously said RSYNC2 for both).
Corrected DVDD balls—previous revision stated “G5, G12” but this is “G5–G12.”
Figure 8-11: In Note 4, changed S2/S3 to S3/S4 and changed S4/S5 to S5/S6;
added Note 6.
Added commercial temperature range devices (DS26524G and DS26524G+) to
Ordering Information table.
Added commercial temperature range to Absolute Maximum Ratings and added
“for DS26524GN” to the temp range for Table 11-1, Table 11-3, Table 12-1, Table
12-2, Table 12-3, and Table 12-4.
In Table 11-4, added commercial temperature range to Ambient Temperature.
Elaborated on pin descriptions for TCLK, TCHCLK, and RCHCLK.
In the Absolute Maximum Ratings section, added GBD note for cold test (Note 1).
20
21
24
72
1
248, 250,
253, 256,
259
249
20, 22
248
273 of 273
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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