DS2762
High-Precision Li+ Battery Monitor With Alerts
www.maxim-ic.com
FEATURES
GENERAL DESCRIPTION
The DS2762 high-precision Li+ battery monitor is a
data-acquisition, information-storage, and safetyprotection device tailored for cost-sensitive battery
pack applications. This low-power device integrates
precise
temperature,
voltage,
and
current
measurement, nonvolatile (NV) data storage, and Li+
protection into the small footprint of either a TSSOP
package or flip-chip package. The DS2762 is a key
component in applications including remaining
capacity estimation, safety monitoring, and batteryspecific data storage.
§
Li+ Safety Circuit
Overvoltage Protection
Overcurrent/Short-Circuit Protection
Undervoltage Protection
Host Alerted When Accumulated Current or
Temperature Exceeds User-Selectable Limits
0V Battery Recovery Charge
Available in Two Configurations:
Internal 25mW Sense Resistor
External User-Selectable Sense Resistor
Current Measurement
12-Bit Bidirectional Measurement
Internal Sense Resistor Configuration:
0.625mA LSB and ±1.9A Dynamic Range
External Sense Resistor Configuration:
15.625mV LSB and ±64mV Dynamic Range
Current Accumulation:
Internal Sense Resistor: 0.25mAhr LSB
External Sense Resistor: 6.25mVhr LSB
Voltage Measurement with 4.88mV Resolution
Temperature Measurement Using Integrated
Sensor with 0.125°C Resolution
System Power Management and Control
Feature Support
32 Bytes of Lockable EEPROM
16 Bytes of General-Purpose SRAM
®
Dallas 1-Wire Interface with Unique 64-Bit
Device Address
Low-Power Consumption:
Active Current: 60mA typ, 90mA max
Sleep Current: 1mA typ, 2mA max
§
§
§
§
PIN CONFIGURATIONS
TOP VIEW
CC
1
16
PLS
2
15
VDD
DC
3
2
14
PIO
SNS
4
13
VSS
SNS
5
12
VSS
SNS
6
11
VSS
DQ
7
10
PS
IS2
8
9
IS1
VIN
TSSOP
1
2
3
CC
SNS
PROBE
VIN
VSS
PROBE
VDD
§
§
§
§
§
§
4
A
SNS
PLS DC
§
DQ
B
§
C
IS2
IS1
PS
PIO
VSS
D
E
F
FLIP CHIP
(top view – bumps on bottom)
1-Wire is registered trademark of Dallas Semiconductor.
APPLICATIONS
PDAs
Cell Phones/Smartphones
Digital Cameras
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
DS2762BE+
-20°C to +70°C
16 TSSOP
Selector Guide appears at end of data sheet, for additional
options.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 010906
DS2762 High-Precision Li+ Battery Monitor With Alerts
ABSOLUTE MAXIMUM RATINGS
Voltage Range on PLS and CC Pin, Relative to VSS
Voltage Range on PIO Pin, Relative to VSS
Voltage Range on Any Other Pin, Relative to VSS
Continuous Internal Sense Resistor Current
Pulsed Internal Sense Resistor Current
Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to +18V
-0.3V to +12V
-0.3V to +6V
±2.5A
±50A for VDD
(charger connected)
Overcurrent, Charge
VIS > VOC
Overcurrent, Discharge
VIS < -VOC
tOCD
DC high
VPLS > VDD - VTP
(4)
Short Circuit
VSNS > VSC
tSCD
DC high
VPLS > VDD - VTP
(4)
VIS = VIS1 - VIS2. Logic high = VPLS for CC and VDD for DC. All voltages are with respect to VSS. ISNS references current delivered from pin SNS.
Note 1:
If VDD < 2.2V, release is delayed until the recovery charge current (IRC) passed from PLS to VDD charges the battery and allows VDD
to exceed 2.2V.
Note 2:
For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: ISNS > IOC for charge
Note 3:
With test current ITST flowing from PLS to VSS (pulldown on PLS).
Note 4:
With test current ITST flowing from VDD to PLS (pullup on PLS).
direction and ISNS < -IOC for discharge direction.
Overvoltage. If the cell voltage on VIN exceeds the overvoltage threshold, VOV, for a period longer than overvoltage
delay, tOVD, the DS2762 shuts off the external charge FET and sets the OV flag in the protection register. When the
cell voltage falls below charge enable threshold VCE, the DS2762 turns the charge FET back on (unless another
protection condition prevents it). Discharging remains enabled during overvoltage, and the DS2762 re-enables the
charge FET before VIN < VCE if a discharge current of -80mA (VIS ≤ -2mV) or less is detected.
Undervoltage. If the voltage of the cell drops below undervoltage threshold, VUV, for a period longer than
undervoltage delay, tUVD, the DS2762 shuts off the charge and discharge FETs, sets the UV flag in the protection
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DS2762 High-Precision Li+ Battery Monitor With Alerts
register, and enters sleep mode. The DS2762 provides a current-limited (IRC) recovery charge path from PLS to
VDD to gently charge severely depleted cells. The recovery path is enabled when 0 £ VDD < 3V (typ). Once VDD
reaches 3V (typ), the DS2762 returns to normal operation, awaiting connection of a charger to turn on the charge
FET and pull out of sleep mode.
Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (VIS = VIS1 - VIS2) is the
filtered voltage drop across the current-sense resistor. If VIS exceeds overcurrent threshold VOC for a period longer
than overcurrent delay tOCD, the DS2762 shuts off both external FETs and sets the COC flag in the protection
register. The charge current path is not re-established until the voltage on the PLS pin drops below VDD - VTP. The
DS2762 provides a test current of value ITST from PLS to VSS to pull PLS down to detect the removal of the
offending charge current source.
Overcurrent, Discharge Direction. If VIS is less than -VOC for a period longer than tOCD, the DS2762 shuts off the
external discharge FET and sets the DOC flag in the protection register. The discharge current path is not reestablished until the voltage on PLS rises above VDD - VTP. The DS2762 provides a test current of value ITST from
VDD to PLS to pull PLS up to detect the removal of the offending low-impedance load.
Short Circuit. If the voltage on the SNS pin with respect to VSS exceeds short-circuit threshold VSC for a period
longer than short-circuit delay tSCD, the DS2762 shuts off the external discharge FET and sets the DOC flag in the
protection register. The discharge current path is not re-established until the voltage on PLS rises above VDD - VTP.
The DS2762 provides a test current of value ITST from VDD to PLS to pull PLS up to detect the removal of the short
circuit.
Figure 3. Li+ Protection Circuitry Example Waveforms
VOV
VCE
VCELL
VUV
CHARGE
VOC
0
-VOC
-VSC
VIS
DISCHARGE
(NOTE 1)
CC
DC
tOVD
tOVD
tSCD
VPLS
tOCD
tOCD
VSS
tUVD
VDD
VSS
ACTIVE
SLEEP
MODE
INACTIVE
NOTE 1: TO ALLOW THE DEVICE TO REACT QUICKLY TO SHORT CIRCUITS, DETECTION OCCURS ON THE SNS PIN RATHER THAN ON THE
FILTERED IS1 AND IS2 PINS. THE ACTUAL SHORT-CIRCUIT DETECT CONDITION IS VSNS > VSC.
Summary. All of the protection conditions described above are ORed together to affect the CC and DC outputs.
DC = (Undervoltage) or (Overcurrent, Either Direction) or (Short Circuit) or (Protection Register Bit DE = 0)
or (Sleep Mode)
CC = (Overvoltage) or (Undervoltage) or (Overcurrent, Charge Direction) or (Protection Register bit CE = 0)
or (Sleep Mode)
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DS2762 High-Precision Li+ Battery Monitor With Alerts
CURRENT MEASUREMENT
In active mode, the DS2762 continually measures the current flow into and out of the battery by measuring the
voltage drop across a current-sense resistor. The DS2762 is available in two configurations: 1) internal 25mW
current-sense resistor and 2) external user-selectable sense resistor. In either configuration, the DS2762 considers
the voltage difference between pins IS1 and IS2 (VIS = VIS1 - VIS2) to be the filtered voltage drop across the sense
resistor. A positive VIS value indicates current is flowing into the battery (charging), while a negative VIS value
indicates current is flowing out of the battery (discharging).
VIS is measured with a signed resolution of 12 bits. The current register is updated in two’s-complement format
every 88ms with an average of 128 readings. Currents outside the register range are reported at the range limit.
Figure 4 shows the format of the current register.
For the internal sense resistor configuration, the DS2762 maintains the current register in units of amps, with a
resolution of 0.625mA and full-scale range of no less than ±1.9A (see Note 7 on IFS spec for more details). The
DS2762 automatically compensates for internal sense resistor process variations and temperature effects when
reporting current.
For the external sense resistor configuration, the DS2762 writes the measured VIS voltage to the current register,
with a 15.625mV resolution and a full-scale ±64mV range.
Figure 4. Current Register Format
MSB—Address 0E
S
11
2
10
2
9
2
8
2
7
2
LSB—Address 0F
6
2
MSb
5
4
2
2
LSb
MSb
3
2
2
2
1
2
0
2
X
X
X
LSb
Units: 0.625mA for Internal Sense Resistor
15.625mV for External Sense Resistor
CURRENT ACCUMULATOR
The current accumulator facilitates remaining capacity estimation by tracking the net current flow into and out of the
battery. Current flow into the battery increments the current accumulator while current flow out of the battery
decrements it. Data is maintained in the current accumulator in two’s-complement format. Figure 5 shows the
format of the current accumulator.
When the internal sense resistor is used, the DS2762 maintains the current accumulator in units of amp-hours, with
a 0.25mAhrs resolution and full-scale ±8.2Ahrs range. When using an external sense resistor, the DS2762
maintains the current accumulator in units of volt-hours, with a 6.25mVhrs resolution and a full-scale ±205mVhrs
range.
The current accumulator is a read/write register that can be altered by the host system as needed.
Figure 5. Current Accumulator Format
MSB—Address 10
S
MSb
14
2
13
2
12
2
11
2
10
2
LSB—Address 11
9
2
8
7
2
2
LSb
MSb
6
2
5
2
4
2
3
2
2
2
1
2
0
2
LSb
Units: 0.25mAhrs for Internal Sense Resistor
6.25mVhrs for External Sense Resistor
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DS2762 High-Precision Li+ Battery Monitor With Alerts
CURRENT OFFSET COMPENSATION
Current measurement and current accumulation are internally compensated for offset on a continual basis
minimizing error resulting from variations in device temperature and voltage. Additionally, a constant bias can be
used to alter any other sources of offset. This bias resides in EEPROM address 33h in two’s-complement format
and is subtracted from each current measurement. The current offset bias is applied to the internal and external
sense resistor configurations. The factory default for the current offset bias is 0.
Figure 6. Current Offset Bias
Address 33
6
S
5
2
4
2
2
3
2
2
1
2
0
2
2
MSb
LSb
Units: 0.625mA for Internal Sense Resistor
15.625mV for External Sense Resistor
VOLTAGE MEASUREMENT
The DS2762 continually measures the voltage between pins VIN and VSS over a 0 to 4.75V range. The voltage
register is updated in two’s-complement format every 3.4ms with a 4.88mV resolution. Voltages above the
maximum register value are reported as the maximum value. Figure 7 shows the voltage register format.
Figure 7. Voltage Register Format
MSB—Address 0C
S
9
2
8
2
7
2
6
2
5
2
LSB—Address 0D
4
2
MSb
3
2
2
2
LSb
MSb
1
2
0
2
X
X
X
X
X
LSb
Units: 4.88mV
TEMPERATURE MEASUREMENT
The DS2762 uses an integrated temperature sensor to continually measure battery temperature. Temperature
measurements are placed in the temperature register every 220ms in two’s-complement format with a 0.125°C
resolution over a ±127°C range. Figure 8 shows the temperature register format.
Figure 8. Temperature Register Format
MSB—Address 18
S
MSb
9
2
8
2
7
2
6
2
5
2
LSB—Address 19
4
2
3
2
2
2
LSb
MSb
1
2
0
2
X
X
X
X
X
LSb
Units: 0.125°C
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DS2762 High-Precision Li+ Battery Monitor With Alerts
PROGRAMMABLE I/O
To use the PIO pin as described in this section, the IE bit (bit 2) of the Status Register must be set to 0.
To use the PIO pin as an output, write the desired output value to the PIO bit in the special feature register. Writing
a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to VSS. Writing a 1 to the PIO bit disables the
output driver, allowing the PIO pin to be pulled high or used as an input. To sense the value on the PIO pin, read
the PIO bit. The DS2762 turns off the PIO output driver and sets the PIO bit high when in sleep mode or when DQ
is low for more than 2s, regardless of the state of the PMOD bit.
ALARM COMPARATORS
The PIO pin can be programmed as an interrupt output (active low) to alert the host system of critical events. To
use the Interrupt feature, the Interrupt Enable (IE) bit (bit 2) of the Status Register must be set to a 1. Interrupt
threshold values can be programmed by the user in the designated SRAM memory registers in the formats and
locations found in Figure 9. Since these thresholds are located in SRAM memory, they must be reprogrammed if a
loss of power to the DS2762 occurs. The PIO line will go low to interrupt the system host and indicate that one of
the following events has occurred:
·
·
·
·
Accumulated Current ³ Current Accumulator Interrupt High Threshold
Accumulated Current £ Current Accumulator Interrupt Low Threshold
Temperature ³ Temperature Interrupt High Threshold
Temperature £ Temperature Interrupt Low Threshold
The host may then poll the DS2762 to determine which threshold has been met or exceeded.
Figure 9. Interrupt Threshold Register Formats
Current Accumulator Interrupt High Threshold
MSB—Address 80
S
14
2
13
2
12
2
11
2
10
2
LSB—Address 81
9
2
MSb
8
7
2
2
LSb
MSb
6
2
5
2
4
2
3
2
2
2
1
2
0
2
LSb
Units: 0.25mAhrs for Internal Sense Resistor
6.25mVhrs for External Sense Resistor
Current Accumulator Interrupt Low Threshold
MSB—Address 82
S
MSb
14
2
13
2
12
2
11
2
10
2
LSB—Address 83
9
2
8
7
2
2
LSb
MSb
6
2
5
2
4
2
3
2
2
2
1
2
0
2
LSb
Units: 0.25mAhrs for Internal Sense Resistor
6.25mVhrs for External Sense Resistor
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DS2762 High-Precision Li+ Battery Monitor With Alerts
Temperature Interrupt High Threshold
Address 84
S
6
2
5
4
2
2
3
2
2
2
1
2
MSb
0
2
LSb
Units: 1.0°C
Temperature Alarm Low Threshold
Address 85
S
6
2
5
2
4
2
3
2
MSb
2
2
1
2
0
2
LSb
Units: 1.0°C
POWER SWITCH INPUT
The DS2762 provides a power control function that uses the discharge protection FET to gate battery power to the
system. The PS pin, internally pulled to VDD through a 1mA current source, is continuously monitored for a lowimpedance connection to VSS. If the DS2762 is in sleep mode, the detection of a low on the PS pin causes the
device to transition into active mode, turning on the discharge FET. If the DS2762 is already in active mode, activity
on PS has no effect other than the latching of its logic low level in the PS bit in the special feature register. The
reading of a 0 in the PS bit should be immediately followed by writing a 1 to the PS bit to ensure that a subsequent
low forced on the PS pin is latched into the PS bit.
MEMORY
The DS2762 has a 256-byte linear address space with registers for instrumentation, status, and control in the lower
32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining address space. All
EEPROM memory is general purpose except addresses 30h, 31h, and 33h, which should be written with the
default values for the protection register, status register, and current offset register, respectively. All SRAM memory
is general purpose. When the MSB of any two-byte register is read, both the MSB and LSB are latched and held for
the duration of the read data command to prevent updates during the read and ensure synchronization between
the two register bytes. For consistent results, always read the MSB and the LSB of a two-byte register during the
same read data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to
be verified by the host system before being copied to EEPROM. All reads and writes to/from EEPROM memory
actually access the shadow RAM. In unlocked EEPROM blocks, the write data command updates shadow RAM. In
locked EEPROM blocks, the write data command is ignored. The copy data command copies the contents of
shadow RAM to EEPROM in an unlocked block of EEPROM but has no effect on locked blocks. The recall-data
command copies the contents of a block of EEPROM to shadow RAM regardless of whether the block is locked or
not.
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DS2762 High-Precision Li+ Battery Monitor With Alerts
Table 2. Memory Map
ADDRESS (HEX)
DESCRIPTION
READ/WRITE
00
01
02–06
07
08
09–0B
0C
0D
0E
0F
Protection Register
Status Register
Reserved
EEPROM Register
Special Feature Register
Reserved
Voltage Register MSB
Voltage Register LSB
Current Register MSB
Current Register LSB
R/W
R
10
11
12–17
18
19
1A–1F
20–2F
30–3F
40–7F
80
Accumulated Current Register MSB
Accumulated Current Register LSB
Reserved
Temperature Register MSB
Temperature Register LSB
Reserved
EEPROM, block 0
EEPROM, block 1
Reserved
SRAM (Optional Accumulated Current Interrupt
High Threshold MSB)
SRAM (Optional Accumulated Current Interrupt
High Threshold LSB)
SRAM (Optional Accumulated Current Interrupt
Low Threshold MSB)
SRAM (Optional Accumulated Current Interrupt
Low Threshold LSB)
SRAM (Optional Temperature Interrupt High
Threshold)
SRAM (Optional Temperature Interrupt Low
Threshold)
SRAM
Reserved
R/W
R/W
81
82
83
84
85
86-8F
90–FF
R/W
R/W
R
R
R
R
R
R
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give conditional
control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when corresponding
protection conditions occur and remain set until cleared by the host system. The default values of the CE and DE
bits of the protection register are stored in lockable EEPROM in the corresponding bits in address 30h. A recall
data command for EEPROM block 1 recalls the default values into CE and DE. Figure 10 shows the format of the
protection register. The function of each bit is described in detail in the following paragraphs.
Figure 10. Protection Register Format
ADDRESS 00
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OV
UV
COC
DOC
CC
DC
CE
DE
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DS2762 High-Precision Li+ Battery Monitor With Alerts
OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage condition.
This bit must be reset by the host system.
UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an undervoltage
condition. This bit must be reset by the host system.
COC—Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a chargedirection overcurrent condition. This bit must be reset by the host system.
DOC—Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a dischargedirection overcurrent condition. This bit must be reset by the host system.
CC—CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.
DC—DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE—Charge Enable. Writing a 0 to this bit disables charging (CC output high, external charge FET off) regardless
of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the presence of any
protection conditions. The DS2762 automatically sets this bit to 1 when it transitions from sleep mode to active
mode.
DE—Discharge Enable. Writing a 0 to this bit disables discharging (DC output high, external discharge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to override by the presence
of any protection conditions. The DS2762 automatically sets this bit to 1 when it transitions from sleep mode to
active mode.
STATUS REGISTER
The default values for the status register bits are stored in lockable EEPROM in the corresponding bits of address
31h. A recall data command for EEPROM block 1 recalls the default values into the status register bits. The format
of the status register is shown in Figure 11. The function of each bit is described in detail in the following
paragraphs.
Figure 11. Status Register Format
ADDRESS 01
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
PMOD
RNAOP
SWEN
IE
X
X
X—Reserved Bits.
PMOD—Sleep Mode Enable. A value of 1 in this bit enables the DS2762 to enter sleep mode when the DQ line
goes low for greater than 2s and to leave sleep mode when the DQ line goes high. A value of 0 disables DQrelated transitions into and out of sleep mode. This bit is read-only. The desired default value should be set in bit 5
of address 31h. The factory default is 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address command to
33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should be set in bit 4 of
address 31h. The factory default is 0.
SWEN—SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP command. If
set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of address 31h. This bit is
read-only. The factory default is 0.
IE—Interrupt Enable. A value of 1 in this bit location enables the PIO pin to be used as an interrupt to the host
system when either the user-programmed thresholds for Accumulated Current and Temperature are met or
exceeded. If set to 0, the PIO pin performs as noted in the PIO section. This bit is read-only. The desired default
value should be set in bit 2 of address 31h. The factory default is 0.
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DS2762 High-Precision Li+ Battery Monitor With Alerts
EEPROM REGISTER
The format of the EEPROM register is shown in Figure 12. The function of each bit is described in detail in the
following paragraphs.
Figure 12. EEPROM Register Format
ADDRESS 07
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EEC
LOCK
X
X
X
X
BL1
BL0
EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress. While this
bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data may be written to unlocked
EEPROM blocks.
LOCK—EEPROM Lock Enable. When this bit is 0, the lock command is ignored. Writing a 1 to this bit enables the
lock command. After the lock command is executed, the LOCK bit is reset to 0. The factory default is 0.
BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 30 to 3F) is
locked (read-only) while a 0 indicates block 1 is unlocked (read/write).
BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20 to 2F) is
locked (read-only) while a 0 indicates block 0 is unlocked (read/write).
X—Reserved Bits.
SPECIAL FEATURE REGISTER
The format of the special feature register is shown in Figure 13. The function of each bit is described in detail in the
following paragraphs.
Figure 13. Special Feature Register Format
ADDRESS 08
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PS
PIO
MSTR
X
X
X
X
X
PS—PS Pin Latch. This bit latches a low state on the PS pin, and is cleared only by writing a 1 to this location.
Writing this bit to a 1 immediately upon reading of a 0 value is recommended.
PIO—PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.
MSTR—SWAP Master Status Bit. This bit indicates whether a device has been selected through the SWAP
command. Selection of this device through the SWAP command and the appropriate net address results in setting
this bit, indicating that this device is the master. A 0 signifies that this device is not the master.
X—Reserved Bits.
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DS2762 High-Precision Li+ Battery Monitor With Alerts
1-Wire BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-Wire bus
with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2762 is a slave device.
The bus master is typically a microprocessor in the host system. The discussion of this bus system consists of four
topics: 64-bit net address, hardware configuration, transaction sequence, and 1-Wire signaling.
64-BIT NET ADDRESS
Each DS2762 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first eight bits are
the 1-Wire family code (30h for DS2762). The next 48 bits are a unique serial number. The last eight bits are a
cyclic redundancy check (CRC) of the first 56 bits (see Figure 14). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2762 to communicate through the 1-Wire protocol detailed in the 1-Wire
Bus System section of this data sheet.
Figure 14. 1-Wire Net Address Format
8-BIT CRC
8-BIT FAMILY
CODE (30H)
LSb
48-BIT SERIAL NUMBER
MSb
CRC GENERATION
The DS2762 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure error-free
transmission of the address, the host system can compute a CRC value from the first 56 bits of the address and
compare it to the CRC from the DS2762. The host system is responsible for verifying the CRC value and taking
action as a result. The DS2762 does not compare CRC values and does not prevent a command sequence from
proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a
very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in
Figure 15, or it can be generated in software. Additional information about the Dallas 1-Wire CRC is available in
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch
Memory Products (www.maxim-ic.com/appnoteindex).
In the circuit in Figure 15, the shift register bits are initialized to 0. Then, starting with the least significant bit of the
family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial
number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value.
Figure 15. 1-Wire CRC Generation Block Diagram
INPUT
MSb
XOR
XOR
LSb
XOR
18 of 25
DS2762 High-Precision Li+ Battery Monitor With Alerts
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the
appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain
or tri-state output drivers. The DS2762 used an open-drain output driver as part of the bidirectional interface
circuitry shown in Figure 16. If a bidirectional pin is not available on the bus master, separate output and input pins
can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the value of
this resistor should be approximately 5kW. The idle state for the 1-Wire bus is high. If, for any reason, a bus
transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. If the
bus is left low for more than 120ms, slave devices on the bus begin to interpret the low period as a reset pulse,
effectively terminating the transaction.
Figure 16. 1-Wire Bus Interface Circuitry
BUS MASTER
VPULLUP
(2.0V to 5.5V)
DS2762 1-Wire PORT
4.7kW
Rx
Rx
1mA
(typ)
Tx
Rx = RECEIVE
Tx = TRANSMIT
Tx
100W
MOSFET
TRANSACTION SEQUENCE
The protocol for accessing the DS2762 through the 1-Wire port is as follows:
§
§
§
§
Initialization
Net Address Command
Function Command
Transaction/Data
The sections that follow describe each of these steps in detail.
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the
bus master, followed by a presence pulse simultaneously transmitted by the DS2762 and any other slaves on the
bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For
more details, see the 1-Wire Signaling section.
19 of 25
DS2762 High-Precision Li+ Battery Monitor With Alerts
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each ROM command is followed by the 8-bit
opcode for that command in square brackets. Figure 17 presents a transaction flowchart of the net address
commands.
Read Net Address [33h or 39h]. This command allows the bus master to read the DS2762’s 1-Wire net address.
This command can only be used if there is a single slave on the bus. If more than one slave is present, a data
collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The
RNAOP bit in the status register selects the opcode for this command, with RNAOP = 0 indicating 33h, and
RNAOP = 1 indicating 39h.
Match Net Address [55h]. This command allows the bus master to specifically address one DS2762 on the 1-Wire
bus. Only the addressed DS2762 responds to any subsequent function command. All other slave devices ignore
the function command and wait for a reset pulse. This command can be used with one or more slave devices on
the bus.
Skip Net Address [CCh]. This command saves time when there is only one DS2762 on the bus by allowing the
bus master to issue a function command without specifying the address of the slave. If more than one slave device
is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at
the same time.
Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the
1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple threestep routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master
performs this simple three-step routine on each bit location of the net address. After one complete pass through all
64 bits, the bus master knows the address of one device. The remaining devices can then be identified on
®
additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive
discussion of a net address search, including an actual example (www.maxim-ic.com/iButtonBook).
SWAP [AAh]. SWAP is a ROM level command specifically intended to aid in distributed multiplexing applications
and is described specifically with regards to power control using the 27xx series of products. The term power
control refers to the ability of the DS2762 to control the flow of power into or out the battery pack using control pins
DC and CC. The SWAP command is issued followed by the net address. The effect is to cause the addressed
device to enable power to or from the system while simultaneously (break-before-make) deselecting and powering
down (SLEEP) all other packs. This switching sequence is controlled by a timing pulse issued on the DQ line
following the net address. The falling edge of the pulse is used to disable power with the rising edge enabling
power flow by the selected device. The DS2762 recognizes a SWAP command, device address, and timing pulse
only if the SWEN bit is set.
FUNCTION COMMANDS
After successfully completing one of the net address commands, the bus master can access the features of the
DS2762 with any of the function commands described in the following paragraphs and summarized in Table 3. The
name of each function is followed by the 8-bit opcode for that command in square brackets.
Read Data [69h, XX]. This command reads data from the DS2762 starting at memory address XX. The LSb of the
data in address XX is available to be read immediately after the MSb of the address has been entered. Because
the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX
+ 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read
beyond address FFh, the DS2762 outputs logic 1 until a reset pulse occurs. Addresses labeled “Reserved” in the
memory map contain undefined data. The read data command can be terminated by the bus master with a reset
pulse at any bit boundary.
iButton is a registered trademark of Dallas Semiconductor.
20 of 25
DS2762 High-Precision Li+ Battery Monitor With Alerts
Write Data [6Ch, XX]. This command writes data to the DS2762 starting at memory address XX. The LSb of the
data to be stored at address XX can be written immediately after the MSb of address has been entered. Because
the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XX
+ 1 can be written immediately after the MSb to be stored at address XX. If the bus master continues to write
beyond address FFh, the DS2762 ignores the data. Writes to read-only addresses, reserved addresses and locked
EEPROM blocks are ignored. Incomplete bytes are not written. Writes to unlocked EEPROM blocks are to shadow
RAM rather than EEPROM. See the Memory section for more details.
Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 16-byte EEPROM
block containing address XX. Copy data commands that address locked blocks are ignored. While the copy data
command is executing, the EEC bit in the EEPROM register is set to 1 and writes to EEPROM addresses are
ignored. Reads and writes to non-EEPROM addresses can still occur while the copy is in progress. The copy data
command execution time, tEEC, is 2ms typical and starts after the last address bit is transmitted.
Recall Data [B8h, XX]. This command recalls the contents of the 16-byte EEPROM block containing address XX
to shadow RAM.
Lock [6Ah, XX]. This command locks (write-protects) the 16-byte block of EEPROM memory containing memory
address XX. The LOCK bit in the EEPROM register must be set to l before the lock command is executed. If the
LOCK bit is 0, the lock command has no effect. The lock command is permanent; a locked block can never be
written again.
Table 3. Function Commands
COMMAND
FUNCTION
COMMAND
PROTOCOL
BUS STATE AFTER
COMMAND PROTOCOL
BUS DATA
Read Data
Reads data from memory
starting at address XX
69h, XX
Master Rx
Up to 256 bytes of
data
Write Data
Writes data to memory
starting at address XX
6Ch, XX
Master Tx
Up to 256 bytes of
data
48h, XX
Bus idle
None
B8h, XX
Bus idle
None
6Ah, XX
Bus idle
None
Copy Data
Recall Data
Lock
Copies shadow RAM data to
EEPROM block containing
address XX
Recalls EEPROM block
containing address XX to
shadow RAM
Permanently locks the block
of EEPROM
containing address XX
21 of 25
DS2762 High-Precision Li+ Battery Monitor With Alerts
Figure 17. Net Address Command Flow Chart
MASTER Tx
RESET PULSE
DS2762 Tx
PRESENCE PULSE
MASTER Tx
NET ADDRESS
COMMAND
33h / 39h
READ
NO
55h
MATCH
YES
NO
YES
AAh
SWAP
YES
MASTER Tx
BIT 0
DS2762 Tx
FAMILY CODE
1 BYTE
NO
F0h
SEARCH
DS2762 Tx BIT 0
DS2762 Tx BIT 0
NO
CCh
SKIP
YES
YES
MASTER TX
BIT 0
MASTER TX
FUNCTION
COMMAND
MASTER Tx BIT 0
DS2762 Tx
SERIAL NUMBER
6 BYTES
BIT 0
MATCH ?
DS2762 Tx
CRC
1 BYTE
NO
NO
YES
BIT 0
MATCH ?
NO
YES
MASTER TX
BIT 1
BIT 0
MATCH ?
YES
MASTER TX
BIT 1
DS2762 Tx BIT 1
DS2762 Tx BIT 1
MASTER Tx BIT 1
BIT 1
MATCH ?
YES
MASTER TX
BIT 63
NO
NO
BIT 1
MATCH ?
NO
YES
BIT 1
MATCH ?
YES
MASTER TX
BIT 63
DS2762 Tx BIT 63
DS2762 Tx BIT 63
MASTER Tx BIT 63
MASTER TX
FUNCTION
COMMAND
YES
NO
BIT 63
MATCH ?
NO
22 of 25
BIT 63
MATCH ?
YES
FALLING EDGE
OF DQ
RISING EDGE
OF DQ
DS2762 TO
SLEEP MODE
DS2762 TO
ACTIVE MODE
NO
DS2762 High-Precision Li+ Battery Monitor With Alerts
I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2762
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data.
The bus master initiates all these types of signaling except the presence pulse.
The initialization sequence required to begin any communication with the DS2762 is shown in Figure 18. A
presence pulse following a reset pulse indicates that the DS2762 is ready to accept a net address command. The
bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and goes into receive mode
(Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin,
the DS2762 waits for tPDH and then transmits the presence pulse for tPDL.
Figure 18. 1-Wire Initialization Sequence
tRSTL
tRSTH
tPDH
tPDL
PACK+
DQ
PACKLINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
DS2762 ACTIVE LOW
BOTH BUS MASTER AND
DS2762 ACTIVE LOW
RESISTOR PULLUP
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be tSLOT (60ms to 120ms)
in duration with a 1ms minimum recovery time, tREC, between cycles. The DS2762 samples the 1-Wire bus line
between 15ms and 60ms after the line falls. If the line is high when sampled, a write 1 occurs. If the line is low when
sampled, a write 0 occurs (Figure 19). For the bus master to generate a write 1 time slot, the bus line must be
pulled low and then released, allowing the line to be pulled high within 15ms after the start of the write time slot. For
the host to generate a write 0 time slot, the bus line must be pulled low and held low for the duration of the writetime slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1ms and then release it to allow the DS2762 to present valid
data. The bus master can then sample the data tRDV (15ms) from the start of the read-time slot. By the end of the
read-time slot, the DS2762 releases the bus line and allows it to be pulled high by the external pullup resistor. All
read-time slots must be tSLOT (60ms to 120ms) in duration with a 1ms minimum recovery time, tREC, between cycles.
See Figure 19 for more information.
23 of 25
DS2762 High-Precision Li+ Battery Monitor With Alerts
Figure 19. 1-Wire Write- and Read-Time Slots
WRITE 0 SLOT
WRITE 1 SLOT
tSLOT
tLOW0
tLOW1
tSLOT
tREC
PACK+
DQ
PACKDS2762 SAMPLE WINDOW
MIN
TYP
MAX
15ms
15ms
DS2762 SAMPLE WINDOW
MIN
TYP
MAX
>1ms
30ms
15ms
READ 0 SLOT
15ms
30ms
READ 1 SLOT
tSLOT
tSLOT
tREC
PACK+
DQ
PACK–
>1ms
MASTER SAMPLE WINDOW
tRDV
MASTER SAMPLE WINDOW
tRDV
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
DS2762 ACTIVE LOW
BOTH BUS MASTER AND
DS2762 ACTIVE LOW
RESISTOR PULLUP
Figure 20. Swap Command Timing
tSWL
DQ
tSWOFF
CC, DC
tSWON
CC, DC
24 of 25
DS2762 High-Precision Li+ Battery Monitor With Alerts
SELECTOR GUIDE
PART
DS2762AE+
DS2762BE+
DS2762AE+T&R
DS2762BE+T&R
DS2762AE+025
DS2762BE+025
DS2762AE+025/T&R
DS2762BE+025/T&R
DS2762AX-025/T&R
DS2762BX-025/T&R
DS2762AX/T&R
DS2762BX/T&R
DS2762AE
DS2762BE
DS2762AE/T&R
DS2762BE/T&R
DS2762AE-025
DS2762BE-025
DS2762AE-025/T&R
DS2762BE-025/T&R
MARKING
DS2762A
DS2762B
DS2762A
DS2762B
2762A25
2762B25
2762A25
2762B25
DS2762AR
DS2762BR
DS2762A
DS2762B
DS2762A
DS2762B
DS2762A
DS2762B
2762A25
2762B25
2762A25
2762B25
DESCRIPTION
TSSOP, External Sense Resistor, 4.275V VOV, Lead-Free
TSSOP, External Sense Resistor, 4.35V VOV, Lead-Free
DS2762AE+ on Tape-and-Reel, Lead-Free
DS2762BE+ on Tape-and-Reel, Lead-Free
TSSOP, 25mW Sense Resistor, 4.275V VOV, Lead-Free
TSSOP, 25mW Sense Resistor, 4.35V VOV, Lead-Free
DS2762AE+025 in Tape-and-Reel, Lead-Free
DS2762BE+025 in Tape-and-Reel, Lead-Free
Flip-Chip, 25mW Sense Resistor, Tape-and-Reel, 4.275V VOV
Flip-Chip, 25mW Sense Resistor, Tape-and-Reel, 4.35V VOV
Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.275V VOV
Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.35V VOV
TSSOP, External Sense Resistor, 4.275V VOV
TSSOP, External Sense Resistor, 4.35V VOV
DS2762AE on Tape-and-Reel
DS2762BE on Tape-and-Reel
TSSOP, 25mW Sense Resistor, 4.275V VOV
TSSOP, 25mW Sense Resistor, 4.35V VOV
DS2762AE-025 in Tape-and-Reel
DS2762BE-025 in Tape-and-Reel
Note: Additional VOV options are available, contact Maxim/Dallas Semiconductor sales.
PACKAGE INFORMATION
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products · Printed USA
25 of 25
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