DS2764AE+025

DS2764 High-Precision Li+ Battery Monitor with 2-Wire Interface www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS2764 high-precision Li+ battery monitor is a data-acquisition, information-storage, and safetyprotection device tailored for cost-sensitive battery pack applications. This low-power device integrates precise temperature, voltage, and current measurement, nonvolatile (NV) data storage, and Li+ protection into the small footprint of either a TSSOP package or flip-chip package. The DS2764 is a key component in applications requiring remaining capacity estimation, safety monitoring, and batteryspecific data storage.     PIN CONFIGURATIONS TOP VIEW  CC 1 16 VIN PLS 2 15 VDD DC 3 2 14 SCL SNS 4 13 VSS SNS 5 12 VSS SNS 6 11 VSS PS 7 10 SDA IS2 8 9 IS1      TSSOP 1 2 3  4 A SNS PLS DC IS2 CC SNS PROBE PS VIN VSS PROBE IS1 VDD SCL SDA VSS Li+ Safety Circuit Overvoltage Protection Overcurrent/Short-Circuit Protection Undervoltage Protection 0V Battery Recovery Charge Available in Two Configurations: Internal 25m Sense Resistor External User-Selectable Sense Resistor Current Measurement 12-Bit Bidirectional Measurement Internal Sense Resistor Configuration: 0.625mA LSB and ±1.9A Dynamic Range External Sense Resistor Configuration: 15.625V LSB and ±64mV Dynamic Range Current Accumulation: Internal Sense Resistor: 0.25mAhr LSB External Sense Resistor: 6.25Vhr LSB Voltage Measurement with 4.88mV Resolution Temperature Measurement Using Integrated Sensor with 0.125°C Resolution 40 Bytes of Lockable EEPROM Option for Unique 64-bit ID Industry 2-Wire Interface with Programmable Slave Address Low-Power Consumption: Active Current: 60A typ, 90A max Sleep Current: 1A typ, 2A max APPLICATIONS B PDAs Cell Phones/Smartphones Digital Cameras C D ORDERING INFORMATION E F FLIP CHIP (TOP VIEWBUMPS ON BOTTOM) PART TEMP RANGE PIN-PACKAGE DS2764BE+ -20°C to +70°C 16 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. Selector Guide appears at end of data sheet, for additional options. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 20 011806 DS2764 High-Precision Li+ Battery Monitor with 2-Wire Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on PLS and CC Pins, Relative to VSS Voltage Range on Any Other Pin, Relative to VSS Continuous Internal Sense Resistor Current Pulsed Internal Sense Resistor Current Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3V to +18V -0.3V to +6V 2.5A 50A for VOV tOVD CC high Undervoltage VIN < VUV tUVD CC, DC high, Sleep Mode Overcurrent, Charge VIS > VOC(2) tOCD CC, DC high VPLS < VDD - VTP (3) Overcurrent, Discharge VIS < -VOC(2) tOCD DC high VPLS > VDD - VTP (4) Short Circuit VSNS > VSC tSCD DC high VPLS > VDD - VTP (4) VIN < VCE, or VIS ≤ -2mV VPLS > VDD (1) (charger connected) VIS = VIS1 - VIS2. Logic high = VPLS for CC and VDD for DC. All voltages are with respect to VSS. ISNS references current delivered from pin SNS. Note 1: If VDD < 2.2V, release is delayed until the recovery charge current passed from PLS to VDD charges the battery and allows VDD to exceed 2.2V. Note 2: For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: ISNS > IOC for charge Note 3: With test current ITST flowing from PLS to VSS (pulldown on PLS). Note 4: With test current ITST flowing from VDD to PLS (pullup on PLS). direction and ISNS < -IOC for discharge direction. Overvoltage. If the cell voltage on VIN exceeds the overvoltage threshold, VOV, for a period longer than overvoltage delay, tOVD, the DS2764 shuts off the external charge FET and sets the OV flag in the protection register. When the cell voltage falls below charge enable threshold VCE, the DS2764 turns the charge FET back on (unless another protection condition prevents it). Discharging remains enabled during overvoltage, and the DS2764 re-enables the charge FET before VIN < VCE if a discharge current of -80mA (VIS ≤ -2mV) or less is detected. Undervoltage. If the voltage of the cell drops below undervoltage threshold, VUV, for a period longer than undervoltage delay, tUVD, the DS2764 shuts off the charge and discharge FETs, sets the UV flag in the protection register, and enters sleep mode. The DS2764 provides a recovery charge path from PLS to VDD to power the DS2764 by the charger when the cell is severely depleted. Once the DS2764 regains power it will enter active mode of operation and allow full charging of the cell. The recovery charge path is disabled when the cell voltage is above 3.0V to prevent cell overcharge through the PLS pin. 9 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (VIS = VIS1 - VIS2) is the filtered voltage drop across the current-sense resistor. If VIS exceeds overcurrent threshold VOC for a period longer than overcurrent delay tOCD, the DS2764 shuts off both external FETs and sets the COC flag in the protection register. The charge current path is not re-established until the voltage on the PLS pin drops below VDD - VTP. The DS2764 provides a test current of value ITST from PLS to VSS to pull PLS down to detect the removal of the offending charge current source. Overcurrent, Discharge Direction. If VIS is less than -VOC for a period longer than tOCD, the DS2764 shuts off the external discharge FET and sets the DOC flag in the protection register. The discharge current path is not reestablished until the voltage on PLS rises above VDD - VTP. The DS2764 provides a test current of value ITST from VDD to PLS to pull PLS up to detect the removal of the offending low-impedance load. Short Circuit. If the voltage on the SNS pin with respect to VSS exceeds short-circuit threshold VSC for a period longer than short-circuit delay tSCD, the DS2764 shuts off the external discharge FET and sets the DOC flag in the protection register. The discharge current path is not re-established until the voltage on PLS rises above VDD - VTP. The DS2764 provides a test current of value ITST from VDD to PLS to pull PLS up to detect the removal of the short circuit. Figure 4. Li+ Protection Circuitry Example Waveforms VOV VCE VCELL VUV CHARGE VOC 0 -VOC -VSC VIS DISCHARGE (NOTE 1) CC DC tOVD tOVD tSCD VPLS tOCD tOCD VSS tUVD VDD VSS ACTIVE MODE SLEEP NOTE 1: TO ALLOW THE DEVICE TO REACT QUICKLY TO SHORT CIRCUITS, DETECTION OCCURS ON THE SNS PIN RATHER THAN ON THE FILTERED IS1 AND IS2 PINS. THE ACTUAL SHORT-CIRCUIT DETECT CONDITION IS VSNS > VSC. Summary. All of the protection conditions described above are OR’ed together to affect the CC and DC outputs. DC = (Undervoltage) or (Overcurrent, Either Direction) or (Short Circuit) or (Protection Register Bit DE = 0) or (Sleep Mode) CC = (Overvoltage and VIS ≥ -2mV) or (Undervoltage) or (Overcurrent, Charge Direction) or (Protection Register bit CE = 0) or (Sleep Mode) Soft Startup. The discharge protection FET is turned on slowly when the DS2764 enters Active mode from Sleep. The soft startup reduces the inrush current that normally occurs when a battery pack is inserted into an un-powered host system. Soft Startup does not reduce inrush currents if the DS2764 is already in Active mode when the battery pack is connected to the un-powered system. 10 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface CURRENT MEASUREMENT In active mode, the DS2764 continually measures the current flow into and out of the battery by measuring the voltage drop across a current-sense resistor. The DS2764 is available in two configurations: 1) internal 25m current-sense resistor and 2) external user-selectable sense resistor. In either configuration, the DS2764 considers the voltage difference between pins IS1 and IS2 (VIS = VIS1 - VIS2) to be the filtered voltage drop across the sense resistor. A positive VIS value indicates current is flowing into the battery (charging), while a negative VIS value indicates current is flowing out of the battery (discharging). VIS is measured with a signed resolution of 12 bits. The current register is updated in two’s-complement format every 88ms with an average of 128 readings. Current measurements outside the register range are reported at the range limit. Each measurement is internally compensated for offset on a continual basis minimizing error resulting from variations in device temperature and voltage. Figure 5 shows the format of the current register. For the internal sense resistor configuration, the DS2764 maintains the current register in units of amps, with a resolution of 0.625mA and full-scale range of no less than 1.9A (see Note 7 on IFS spec for more details). The DS2764 automatically compensates for internal sense resistor process variations and temperature effects when reporting current. For the external sense resistor configuration, the DS2764 writes the measured VIS voltage to the current register, with a 15.625V resolution and a full-scale 64mV range. Figure 5. Current Register Format MSB—Address 0E S 211 210 29 28 27 LSB—Address 0F 26 MSb 25 24 LSb MSb 23 22 21 20 X X X LSb Units: 0.625mA for Internal Sense Resistor 15.625V for External Sense Resistor CURRENT ACCUMULATOR The current accumulator facilitates remaining capacity estimation by tracking the net current flow into and out of the battery. Current flow into the battery increments the current accumulator while current flow out of the battery decrements it. Data is maintained in the current accumulator in two’s-complement format. Figure 6 shows the format of the current accumulator. When the internal sense resistor is used, the DS2764 maintains the current accumulator in units of amp-hours, with a 0.25mAhrs resolution and full-scale 8.2Ahrs range. When using an external sense resistor, the DS2764 maintains the current accumulator in units of volt-hours, with a 6.25Vhrs resolution and a full-scale 205mVhrs range. The current accumulator is a read/write register that can be altered by the host system as needed. Figure 6. Current Accumulator Format MSB—Address 10 S MSb 214 213 212 211 210 LSB—Address 11 29 28 27 LSb MSb 26 25 24 23 22 21 20 LSb Units: 0.25mAhrs for Internal Sense Resistor 6.25Vhrs for External Sense Resistor 11 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface CURRENT OFFSET COMPENSATION The current measurement and current accumulation are internally compensated for offset on a continual basis minimizing error resulting from variations in device temperature and voltage. Additionally, the Current Offset Bias register is a user programmable constant bias that can be used to alter the offset of the Current and Accumulated current registers. User programmed bias values can be used to correct for offset errors after final assembly of the module or pack. An offset value can be purposely chosen to bias current accumulation in the discharge polarity to ensure a pessimistic accounting of A level standby currents. The Current Offset Bias value resides in EEPROM address 33h in two’s-complement format and is subtracted from current measurements during the accumulation process. The Current Offset Bias is applied to the internal and external sense resistor configurations. The factory default for EEPROM address 33h is 0. Figure 7. Current Offset Bias Address 33 26 S 25 24 23 22 21 MSb 20 LSb Units: 0.625mA for Internal Sense Resistor 15.625V for External Sense Resistor VOLTAGE MEASUREMENT The DS2764 continually measures the voltage between pins VIN and VSS over a 0 to 4.75V range. The voltage register is updated in two’s-complement format every 3.4ms with a 4.88mV resolution. Voltages above the maximum register value are reported as the maximum value. Figure 8 shows the voltage register format. Figure 8. Voltage Register Format MSB—Address 0C S 29 28 27 26 25 LSB—Address 0D 24 MSb 23 22 LSb MSb 21 20 X X X X X LSb Units: 4.88mV TEMPERATURE MEASUREMENT The DS2764 uses an integrated temperature sensor to continually measure battery temperature. Temperature measurements are placed in the temperature register every 220ms in two’s-complement format with a 0.125°C resolution over a 127°C range. Figure 9 shows the temperature register format. Figure 9. Temperature Register Format MSB—Address 18 S MSb 29 28 27 26 25 LSB—Address 19 24 23 22 LSb MSb 21 20 X X X X X LSb Units: 0.125C 12 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface POWER SWITCH INPUT The DS2764 provides a power control function that uses the discharge protection FET to gate battery power to the system. The PS pin, internally pulled to VDD through a 1A current source, is continuously monitored for a lowimpedance connection to VSS. If the DS2764 is in sleep mode, the detection of a low on the PS pin causes the device to transition into active mode, turning on the discharge FET. If the DS2764 is already in active mode, activity on PS has no effect on the FET control. The host system has the option of monitoring activity on the PS pin by reading the PS bit in the Special Feature Register. The PS bit latches a 0 value when a logic low occurs on the PS pin regardless of the operating mode of the DS2764. If the host intends to monitor future PS pin events, it must write a 1 to the PS bit to ensure that a subsequent low forced on the PS pin is latched into the PS bit. The PS bit value has no effect on operation of the DS2764 and can be ignored if PS pin monitoring is not required. MEMORY The DS2764 has a 256-byte linear address space. Registers for instrumentation, status, and control are mapped in the lower 32 bytes, with lockable EEPROM blocks and the unique ROM ID occupying portions of the remaining address space. The Function Command Register occupies location FEh. All EEPROM memory is general purpose except byte addresses 31h, 32h and 33h, which should be written with the default values for the Status register, 2Wire slave address and Current Offset register, respectively. When reading two-byte registers, (Current, ACR, Voltage and Temperature), the MSB should be read first. When the MSB of two-byte registers is read, the MSB and LSB are latched simultaneously and held for the duration of the Read Data transaction. This prevents register updates during the read and ensures synchronization between the MSB and LSB of two byte register values. For consistent results, always read the MSB and the LSB of a two-byte register during the same Read Data transaction. EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to be verified by the host system before being copied to EEPROM. The Read Data and Write Data protocols to/from EEPROM memory addresses access the shadow RAM. The Recall Data function command transfers data from the EEPROM to the shadow RAM. The Copy Data function command transfers data from the shadow RAM to the EEPROM and requires tEEC to complete programming of the EEPROM cells. In unlocked EEPROM blocks, writing data updates shadow RAM. In locked EEPROM blocks, attempts to write data are ignored. The Copy Data function command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM but has no effect on locked blocks. The Recall Data function command copies the contents of a block of EEPROM to shadow RAM regardless of whether the block is locked or not. Figure 10. EEPROM Access via Shadow RAM Copy EEPROM Serial Interface Write Read Shadow RAM 13 of 20 Recall DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface Table 2. Memory Map ADDRESS (HEX) 00 01 02–06 07 08 09–0B 0C 0D 0E 0F 10 11 12–17 18 19 1A–1F 20–2F 30–3F 40–47 50–EF F0–F7 F8–FD FE FF DESCRIPTION READ/WRITE Protection Register Status Register Reserved EEPROM Register Special Feature Register Reserved Voltage Register MSB Voltage Register LSB Current Register MSB Current Register LSB Accumulated Current Register MSB Accumulated Current Register LSB Reserved Temperature Register MSB Temperature Register LSB Reserved EEPROM, block 0 EEPROM, block 1 EEPROM, block 2 Reserved Unique ID Reserved Function Command Register Reserved R/W R R/W R/W R R R R R/W R/W R R R/W* R/W* R/W* R+ W * Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only. + Unique 64 bit ID is a factory option available by special order. Units with IDs do not allow access to block 2 of user EEPROM PROTECTION REGISTER The protection register consists of flags that indicate protection circuit status and switches that give conditional control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when corresponding protection conditions occur and remain set until cleared by the host system. The default values of the CE and DE bits of the protection register are stored in lockable EEPROM in the corresponding bits in address 30h. A recall data command for EEPROM block 1 recalls the default values into CE and DE. Figure 11 shows the format of the protection register. The function of each bit is described in detail in the following paragraphs. Figure 11. Protection Register Format ADDRESS 00 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OV UV COC DOC CC DC CE DE OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage condition. This bit must be reset by the host system. UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an undervoltage condition. This bit must be reset by the host system. COC—Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a chargedirection overcurrent condition. This bit must be reset by the host system. DOC—Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a dischargedirection overcurrent condition. This bit must be reset by the host system. 14 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface CC—CC Pin Mirror. This read-only bit mirrors the state of the CC output pin. DC—DC Pin Mirror. This read-only bit mirrors the state of the DC output pin. CE—Charge Enable. Writing a 0 to this bit disables charging (CC output high, external charge FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the presence of any protection conditions. The DS2764 automatically sets this bit to 1 when it transitions from sleep mode to active mode. DE—Discharge Enable. Writing a 0 to this bit disables discharging (DC output high, external discharge FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to override by the presence of any protection conditions. The DS2764 automatically sets this bit to 1 when it transitions from sleep mode to active mode. STATUS REGISTER The read-only Status register shows the status of bits which enable or disable selected functions of the DS2764. Functions are enabled or disabled by programming a default value for the corresponding bits in lockable EEPROM address 31h. After writing the desired value to 31h, the Copy Data and Recall Data commands for EEPROM block 1 are required to transfer the default values into the status register bits and activate the selected functions. The selected functions become the default mode of the DS2764 since a recall from block 1 occurs on power-up. The format of the Status register is shown in Figure 12. Figure 12. Status Register Format ADDRESS 01 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X PMOD X X X X X X—Reserved Bits. PMOD—Sleep Mode Enable. A value of 1 in this bit enables the DS2764 to enter sleep mode when the bus is low for greater than 2s and to leave sleep mode when the SCL OR SDA line goes high. A value of 0 disables busrelated transitions into and out of sleep mode. This bit is read-only. The desired default value should be set in bit 5 of address 31h. The factory default is 0. EEPROM REGISTER The format of the EEPROM register is shown in Figure 13. The function of each bit is described in detail in the following paragraphs. Figure 13. EEPROM Register Format ADDRESS 07 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EEC LOCK X X X BL2 BL1 BL0 EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data or Lock function command is in progress. While this bit is high, writes to EEPROM addresses are ignored and Copy Data and Lock function commands cannot be issued. A 0 in this bit indicates that data may be written to unlocked EEPROM blocks. LOCK—EEPROM Lock Enable. When this bit is 0, the Lock function command is ignored. Writing a 1 to this bit enables the Lock function command. After the Lock function command is executed, the LOCK bit is reset to 0. The factory default is 0. 15 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface BL2—EEPROM Block 2 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 2 (addresses 40 to 47) is locked (read-only) while a 0 indicates block 2 is unlocked (read/write). The special order unique 64-bit ID device does not support EEPROM Block 2. BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 30 to 3F) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write). BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20 to 2F) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write). X—Reserved Bits. SPECIAL FEATURE REGISTER The format of the special feature register is shown in Figure 14. The function of each bit is described in detail in the following paragraphs. Figure 14. Special Feature Register Format ADDRESS 08 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PS X X X X X SAWE X PSPS Pin Latch. This bit latches a low state on the PS pin with a 0 value. The bit is cleared only by writing a 1 to this location. See the Power Switch Input section. SAWESlave Address Write Enable. This bit must be set to 1 before the 2-wire slave address in location 0x32 can be modified. SAWE should be written back to 0 after writing the slave address. Power up default is 0. XReserved Bits. PROGRAMMABLE SLAVE ADDRESS The 2-Wire slave address of the DS2764 is stored in lockable EEPROM block 1, address 32h. Programming the slave address requires a write to set the SAWE bit in the Special Feature register, followed by a write to 32h with the desired slave address. The new slave address value is effective following the write to 32h, and must be used to address the DS2764 on subsequent bus transactions. The slave address value is not stored to EEPROM until a Copy EEPROM block 1 command is executed. Prior to executing the Copy command, power cycling the DS2764 restores the original slave address value. The data format of the slave address value in address 32h is shown in Figure 15. Figure 15. Slave Address Format ADDRESS 32 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 A6 A5 A4 A3 A2 A1 A0 X A6 to A0—Slave Address. 0110100b. A6-A0 contains the 7-bit slave address of the DS2764. X—Reserved Bits. 16 of 20 The factory default is DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface 2-WIRE BUS SYSTEM The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multimaster system. Up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. The 2-wire interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional communication between the DS2764 slave device and a master device at speeds up to 100kHz. The DS2764’s SDA pin operates bi-directionally, that is, when the DS2764 receives data, SDA operates as an input, and when the DS2764 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up. The DS2764 always operates as a slave device, receiving and transmitting data under the control of a master device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and STOP bits which begin and end each transaction. Bit Transfer One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any change in SDA when SCL is high is interpreted as a START or STOP control signal. Bus Idle The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high when the bus is idle. The STOP condition is the proper method to return the bus to the idle state. START and STOP Conditions The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one transaction and begin another without returning the bus to the idle state. In multi-master systems, a Repeated START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities in which the SDA transitions when SCL is high. Acknowledge Bits Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the master and the DS2764 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re-attempt communication. Data Order A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is followed by the Acknowledge bit. DS2764 registers composed of multi-byte values are ordered most significant byte (MSB) first. The MSB of multi-byte registers is stored on even data memory addresses. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a Slave Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2764 continuously monitors for a START condition followed by its slave address. When the DS2764 receives a slave address that matches the value in its Programmable Slave Address register, it responds with an Acknowledge bit during the clock period following the R/W bit. The 7-bit Programmable Slave Address register is factory programmed to 0110100. The slave address can be re-programmed, refer to the Programmable Slave Address section for details. Read/Write Bit The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0 selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read transaction, with the following bytes being read from the stave by the master. 17 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface Bus Timing The DS2764 is compatible with any bus timing up to 100kHz. No special configuration is required to operate at any speed. 2-Wire Command Protocols The command protocols involve several transaction formats. The simplest format consists of the master writing the START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2764. More complex formats such as the Write Data, Read Data and Function command protocols write data, read data and execute device specific operations. All bytes in each command format require the slave or host to return an Acknowledge bit before continuing with the next byte. Each function command definition outlines the required transaction format. The following key applies to the transaction formats. Table 3. 2-Wire Protocol Key KEY S SAddr FCmd MAddr Data A N DESCRIPTION START bit Slave Address (7-bit) Function Command byte Memory Address byte Data byte written by master Acknowledge bit - Master No Acknowledge - Master KEY Sr W R P Data A N DESCRIPTION Repeated START R/W bit = 0 R/W bit = 1 STOP bit Data byte returned by slave Acknowledge bitSlave No AcknowledgeSlave Basic Transaction Formats Write: S SAddr W A MAddr A Data0 A P A write transaction transfers one or more data bytes to the DS2764. The data transfer begins at the memory address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction, except for the Acknowledge cycles. Read: S SAddr W A MAddr A Sr SAddr R A Data0 N P Write Portion Read Portion A read transaction transfers one or more bytes from the DS2764. Read transactions are composed of two parts, a write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write portion communicates the starting point for the read operation. The read portion follows immediately, beginning with a Repeated START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2764 beginning with the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2764 throughout the transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding to the last byte it requires with a No Acknowledge. This signals the DS2764 that control of SDA is to remain with the master following the Acknowledge clock. Write Data Protocol The write data protocol is used to write to register and shadow RAM data to the DS2764 starting at memory address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by sending a STOP or Repeated START after receiving the last acknowledge bit. S SAddr W A MAddr A Data0 A Data1 A … DataN A P The msb of the data to be stored at address MAddr can be written immediately after the MAddr byte is acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is received by the DS2764, the msb of the data at address MAddr + 1 is can be written immediately after the acknowledgement of the data at address MAddr. If the bus master continues an auto-incremented write transaction beyond address 4Fh, the DS2764 ignores the data. Data is also ignored on writes to read-only addresses and reserved addresses, locked EEPROM blocks as well as a write that auto increments to the Function Command register (address FEh). Incomplete bytes and bytes that are Not Acknowledged by the DS2764 are not written to memory. As noted in the Memory Section, writes to unlocked EEPROM blocks modify the shadow RAM only. 18 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface Read Data Protocol The Read Data protocol is used to read register and shadow RAM data from the DS2764 starting at memory address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data from MAddr + 1 and DataN represents the last byte read by the master. S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A … DataN N P Data is returned beginning with the most significant bit (msb) of the data in MAddr. Because the address is automatically incremented after the least significant bit (lsb) of each byte is returned, the msb of the data at address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If the bus master continues to read beyond address FFh, the DS2764 outputs data values of FFh. Addresses labeled “Reserved” in the memory map return undefined data. The bus master terminates the read transaction at any byte boundary by issuing a No Acknowledge followed by a STOP or Repeated START. Function Command Protocol The Function Command protocol executes a device specific operation by writing one of the function command values (FCmd) to memory address FEh. Table 4 lists the DS2764 FCmd values and describes the actions taken by each. A one byte write protocol is used to transmit the function command, with the MAddr set to FEh and the data byte set to the desired FCmd value. Additional data bytes are ignored. Data read from memory address FEh is undefined. S SAddr W A MAddr=0FEh A FCmd A P Table 4. Function Commands FUNCTION COMMAND Copy Data Recall Data TARGET EEPROM BLOCK FCMD VALUE 0 42h 1 44h 2 48h 0 1 2 B2h B4h B8h 0 63h 1 66h 2 6Ah Lock DESCRIPTION This command copies the shadow RAM to the target EEPROM block. Copy Data commands that target locked blocks are ignored. While the Copy Data command is executing, the EEC bit in the EEPROM register is set to 1, and Write Data commands with MAddr set to any address within the target block are ignored. Read Data and Write Data commands with MAddr set outside the target block are processed while the copy is in progress. The Copy Data command execution time, tEEC, is 2ms typical and starts after the FCMD byte is acknowledged. Subsequent Copy or Lock commands must be delayed until the EEPROM programming cycle completes. This command recalls the contents of the targeted EEPROM block to its shadow RAM. This command locks (write-protects) the targeted EEPROM block. The LOCK bit in the EEPROM register must be set to 1 before the lock command is executed. If the LOCK bit is 0, the lock command has no effect. The lock command is permanent; a locked block can never be written again. The Lock command execution time, tEEC, is 2ms typical and starts after the FCMD byte is acknowledged. Subsequent Copy or Lock commands must be delayed until the EEPROM programming cycle completes. Note: EEPROM block 2 is not supported on special order devices with unique IDs. 19 of 20 DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface 64-BIT UNIQUE ID The DS2764 can be special ordered with a unique, factory-programmed ID that is 64 bits in length. The first eight bits are the product family code (B0h for DS2764). The next 48 bits are a unique 40-bit serial number followed by 0x64h. The last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 16). The 64-bit ID can be read as 8 bytes starting at memory address F0h. The 64-bit ID is read only. Figure 16. 64-BIT ID FORMAT 8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (B0h) msb lsb SELECTOR GUIDE PART MARKING DS2764AE+ DS2764BE+ DS2764AE+T&R DS2764BE+T&R DS2764AE+025* DS2764BE+025* DS2764AE+025/T&R* DS2764BE+025/T&R* DS2764AX-025/T&R* DS2764BX-025/T&R* DS2764AX/T&R* DS2764BX/T&R* DS2764A DS2764B DS2764A DS2764B 2764A25 2764B25 2764A25 2764B25 DS2764AR DS2764BR DS2764A DS2764B PACKAGE INFORMATION TSSOP, External Sense Resistor, 4.275V VOV TSSOP, External Sense Resistor, 4.35V VOV DS2764AE+ on Tape-and-Reel DS2764BE+ on Tape-and-Reel TSSOP, 25m Sense Resistor, 4.275V VOV TSSOP, 25m Sense Resistor, 4.35V VOV DS2764AE+025 in Tape-and-Reel DS2764BE+025 in Tape-and-Reel Flip-Chip, 25m Sense Resistor, Tape-and-Reel, 4.275V VOV Flip-Chip, 25m Sense Resistor, Tape-and-Reel, 4.35V VOV Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.275V VOV Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.35V VOV *Denotes option available at a future date; contact factory for availability. +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. Note 1: Additional VOV options are available, contact the factory. Note 2: To order devices with the unique 64-bit ID option, contact the factory. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. 20 of 20