DS28E25G+T

ABRIDGED DATA SHEET Evaluation Kit Available Design Resources Tools and Models Support Click here to ask an associate for production status of specific part numbers. DS28E25 DeepCover Secure Authenticator with 1-Wire SHA-256 and 4Kb User EEPROM General Description DeepCover™ embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible. The DeepCover Secure Authenticator (DS28E25) combines crypto-strong, bidirectional, secure challengeand-response authentication functionality with an implementation based on the FIPS 180-3-specified Secure Hash Algorithm (SHA-256). A 4Kb user-programmable EEPROM array provides nonvolatile storage of application data and additional protected memory holds a readprotected secret for SHA-256 operations and settings for user memory control. Each device has its own guaranteed unique 64-bit ROM identification number (ROM ID) that is factory programmed into the chip. This unique ROM ID is used as a fundamental input parameter for cryptographic operations and also serves as an electronic serial number within the application. A bidirectional security model enables two-way authentication between a host system and slave-embedded DS28E25. Slave-to-host authentication is used by a host system to securely validate that an attached or embedded DS28E25 is authentic. Hostto-slave authentication is used to protect DS28E25 user memory from being modified by a nonauthentic host. The SHA-256 message authentication code (MAC), which the DS28E25 generates, is computed from data in the user memory, an on-chip secret, a host random challenge, and the 64-bit ROM ID. The DS28E25 communicates over the single-contact 1-Wire® bus at overdrive speed. The communication follows the 1-Wire protocol with the ROM ID acting as node address in the case of a multiple-device 1-Wire network. Features ● Symmetric Key-Based Bidirectional Secure Authentication Model Based on SHA-256 ● Dedicated Hardware-Accelerated SHA Engine for Generating SHA-256 MACs ● Strong Authentication with a High Bit Count, UserProgrammable Secret, and Input Challenge ● 4096 Bits of User EEPROM Partitioned Into 16 Pages of 256 Bits ● User-Programmable and Irreversible EEPROM Protection Modes Including Authentication, Write and Read Protect, and OTP/EPROM Emulation ● Unique, Factory-Programmed 64-Bit Identification Number ● Single-Contact 1-Wire Interface Communicates with Host at Up to 76.9kbps ● Operating Range: 3.3V ±10%, -40°C to +85°C ● Low-Power 5µA (typ) Standby ● ±8kV Human Body Model ESD Protection (typ) ● 2-Pin SFN, 2-Pin TO-92, 6-Pin TDFN, and 6-Pin TSOC Packages Typical Application Circuit 3V RP (I2C PORT) SLPZ Authentication of Network-Attached Appliances Printer Cartridge ID/Authentication Reference Design License Management System Intellectual Property Protection Sensor/Accessory Authentication and Calibration Secure Feature Setting for Configurable Systems Key Generation and Exchange for Cryptographic Systems RP = 1.1kΩ MAXIMUM I2C BUS CAPACITANCE 320pF VCC DS2465 µC Applications ● ● ● ● ● ● ● SDA SCL IO 1-Wire LINE DS28E25 Ordering Information appears at end of data sheet. DeepCover is a trademark and 1-Wire is a registered trademark of Maxim Integrated Products, Inc. 219-0019; Rev 4; 6/21 ©  2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2021 Analog Devices, Inc. All rights reserved. ABRIDGED DATA SHEET DS28E25 DeepCover Secure Authenticator with 1-Wire SHA-256 and 4Kb User EEPROM ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND.......................................-0.5V to 4.0V IO Sink Current...................................................................20mA Operating Temperature Range ........................... -40°C to +85°C Junction Temperature.......................................................+150°C Storage Temperature Range............................. -55°C to +125°C Lead Temperature (soldering, 10s) TO-92, TSOC, TDFN....................................................+300°C Soldering Temperature (reflow) TO-92............................................................................+250°C TSOC, TDFN................................................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.63 V IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.97 1-Wire Pullup Resistance RPUP VPUP = 3.3V ± 10% (Note 3) 300 Input Capacitance Input Load Current CIO IL 1500 (Notes 4, 5) 1500 IO pin at VPUP Ω pF 5 19.5 0.65 x VPUP µA VTL (Notes 6, 7) Input Low Voltage VIL (Notes 2, 8) Low-to-High Switching Threshold VTH (Notes 6, 9) 0.75 x VPUP V Switching Hysteresis VHY (Notes 6, 10) 0.3 V Output Low Voltage VOL IOL = 4mA (Note 11) Recovery Time tREC RPUP = 1500Ω (Notes 2, 12) 5 µs Time-Slot Duration tSLOT (Notes 2, 13) 13 µs High-to-Low Switching Threshold V 0.3 0.4 V V IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time tRSTL (Note 2) 48 80 µs Reset High Time tRSTH (Note 14) 48 Presence-Detect Sample Time tMSP (Notes 2, 15) 8 10 µs Write-Zero Low Time tW0L (Notes 2, 16) 8 16 µs Write-One Low Time tW1L (Notes 2, 16) 0.25 2 µs tRL (Notes 2, 17) 0.25 2-d µs tMSR (Notes 2, 17) tRL + d 2 µs 1 mA 10 ms 100 ms µs IO PIN: 1-Wire WRITE IO PIN: 1-Wire READ Read Low Time Read Sample Time EEPROM Programming Current IPROG VPUP = 3.63V (Notes 5, 18) Programming Time for a 32-Bit Segment or Page Protection tPRD Programming Time for the Secret tPRS Write/Erase Cycling Endurance NCY TA = +85°C (Notes 21, 22) Data Retention tDR TA = +85°C (Notes 23, 24, 25) www.analog.com Refer to the full data sheet. 100k — 10 Years Analog Devices │  2 ABRIDGED DATA SHEET DS28E25 DeepCover Secure Authenticator with 1-Wire SHA-256 and 4Kb User EEPROM ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 mA 3 ms SHA-256 ENGINE Computation Current ICSHA Computation Time tCSHA Refer to the full data sheet. Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 5: Guaranteed by design and/or characterization only; not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic-zero is detected. Note 8: The voltage on IO must be less than or equal to VILMAX at all times when the master is driving IO to a logic-zero level. Note 9: Voltage above which, during a rising edge on IO, a logic-one is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E25 present. The power-up presence detect pulse could be outside this interval, but will be complete within 2ms after power-up. Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during the programming interval or SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V. Note 19: Refer to the full data sheet. Note 20: Refer to the full data sheet. Note Note Note Note 21: Write-cycle endurance is tested in compliance with JESD47G. 22: Not 100% production tested; guaranteed by reliability monitor sampling. 23: Data retention is tested in compliance with JESD47G. 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-term storage at elevated temperatures is not recommended. Note 26: Refer to the full data sheet. www.analog.com Analog Devices │  3 ABRIDGED DATA SHEET DS28E25 DeepCover Secure Authenticator with 1-Wire SHA-256 and 4Kb User EEPROM Pin Configurations BOTTOM VIEW TOP VIEW 1 2 + DS28E25 GND GND DS28E25 1 IO 2 N.C. 3 DS28E25 6 N.C. N.C. 1 5 N.C. IO 2 4 N.C. GND 3 TSOC SFN (6mm x 6mm x 0.9mm) + 6 N.C. 28E25 ymrrF IO TOP VIEW 5 N.C. 4 N.C. EP TDFN (3mm × 3mm) NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE. SIDE VIEW FRONT VIEW IO 1 N.C. 2 GND 3 1 2 3 TO-92 Pin Descriptions PIN NAME SFN TO-92 TSOC TDFN-EP 2 3 1 3 GND 1 1 2 2 IO — 2 3, 4, 5, 6 1, 4, 5, 6 N.C. — — — — EP www.analog.com FUNCTION Ground Reference 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor. Not Connected Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. Analog Devices │  4 ABRIDGED DATA SHEET DS28E25 DeepCover Secure Authenticator with 1-Wire SHA-256 and 4Kb User EEPROM Note to readers: This document is an abridged version of the full data sheet. Additional device information is available only in the full version of the data sheet. To request the full data sheet, go to www.maximintegrated.com/DS28E25 and click on Request Full Data Sheet. Ordering Information PART TEMP RANGE Package Information PIN-PACKAGE DS28E25G+T -40°C to +85°C 2 SFN (2.5k pcs) DS28E25+ -40°C to +85°C 2 TO-92 DS28E25P+ -40°C to +85°C 6 TSOC DS28E25P+T -40°C to +85°C 6 TSOC (4k pcs) DS28E25Q+T -40°C to +85°C 6 TDFN-EP* (2.5k pcs) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. www.analog.com For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 2 SFN G266N+1 21-0390 — 2 TO-92 Q2+1 21-0249 — 6 TSOC D6+1 21-0382 90-0321 6 TDFN-EP T633+2 21-0137 90-0058 Analog Devices │  43 ABRIDGED DATA SHEET DS28E25 DeepCover Secure Authenticator with 1-Wire SHA-256 and 4Kb User EEPROM Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 7/12 Initial release 1 8/12 Replaced the Typical Application Circuit; added the TO-92 package to the Features, Absolute Maximum Ratings, Pin Configurations, Pin Descriptions, Ordering Information, and Package Information sections 2 11/12 Changed title of data sheet 3 12/12 Defined the EEPROM tPRD and added tPRS parameters in the Electrical Characteristics table, thereby updating Figures 7a, 7b, 7e, 7f, 7g, 7h, and the 1-Wire Communication Examples ; data retention parameter specified at TA = +85°C 4 6/21 Updated Electrical Characteristics table DESCRIPTION — 1, 2, 4, 42 1–44 2, 3, 24, 25, 28–31, 39–43 2 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.Specifications subject to change without notice. No license is granted by implicationor otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective owners. w w w . a n a l o g . c o m Analog Devices │  44