DS3101GN

19-4596; Rev 4; 5/09 DEMO KIT AVAILABLE DS3101 Stratum 2/3E/3 Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 2, 3E, 3 4E and 4 requirements of GR-1244, GR-253, G.812 Types I - IV, G.813 and G.8262. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3101 devices can be configured in a master/slave arrangement for timing card equipment protection.  The DS3101 registers and I/O pins are backward compatible with Semtech’s ACS8520 and ACS8530 timing card ICs. The DS3101 is functionally equivalent to a DS3100 without integrated BITS transceivers.   APPLICATIONS SONET/SDH ADMs, MSPPs, and MSSPs Digital Cross-Connects DSLAMs Service Provider Routers FUNCTIONAL DIAGRAM  TIMING FROM LINE CARDS AND BITS/SSU RECEIVERS 14 (VARIOUS RATES) DS3101 SONET/SDH SYNCHRONIZATION IC 11 TIMING TO LINE CARDS AND BITS/SSU TRANSMITTERS (VARIOUS RATES)   Synchronization Subsystem for Stratum 2, 3E, 3, 4E, and 4, SMC, SEC and EEC - Meets Requirements of GR-1244 Stratum 2 - 4, GR-253, G.812 Types I - IV, G.813 and G.8262 - Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator - Programmable Bandwidth, 0.5mHz to 70Hz - Hitless Reference Switching on Loss of Input - Phase Build-Out and Transient Absorption - Locks To and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261 14 Input Clocks - 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz - Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz - Two 64kHz Composite Clock Receivers - Continuous Input Clock Quality Monitoring - Separate 2/4/8kHz Frame Sync Input 11 Output Clocks - Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz - Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz - One 64kHz Composite Clock Transmitter - One 1.544MHz/2.048MHz Output Clock - Two Sync Pulses: 8kHz and 2kHz - Output Clock Rates Include 2kHz, 8kHz, NxDS1, NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz, 38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz, 125MHz, 155.52MHz, 311.04MHz Internal Compensation for Master Clock Oscillator Frequency Accuracy Processor Interface: 8-Bit Parallel or SPI Serial 1.8V Operation with 3.3V I/O (5V Tolerant) ORDERING INFORMATION LOCAL TCXO OR OCXO PART DS3101GN DS3101GN+ CONTROL STATUS TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 256 CSBGA (17mm)2 256 CSBGA (17mm)2 +Denotes a lead(Pb)-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 150 DS3101 TABLE OF CONTENTS 1. STANDARDS COMPLIANCE ................................................................................................6 2. BLOCK DIAGRAM.................................................................................................................7 3. APPLICATION EXAMPLE .....................................................................................................8 4. DETAILED DESCRIPTION ....................................................................................................8 5. DETAILED FEATURES .......................................................................................................10 5.1 5.2 5.3 5.4 5.5 5.6 5.7 T0 DPLL FEATURES ....................................................................................................................10 T4 DPLL FEATURES ....................................................................................................................10 INPUT CLOCK FEATURES..............................................................................................................10 OUTPUT CLOCK FEATURES ..........................................................................................................11 REDUNDANCY FEATURES .............................................................................................................11 COMPOSITE CLOCK I/O FEATURES ...............................................................................................11 GENERAL FEATURES ...................................................................................................................11 6. PIN DESCRIPTIONS............................................................................................................12 7. FUNCTIONAL DESCRIPTION .............................................................................................18 7.1 7.2 7.3 7.4 OVERVIEW...................................................................................................................................18 DEVICE IDENTIFICATION AND PROTECTION....................................................................................19 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION ...........................................................19 INPUT CLOCK CONFIGURATION.....................................................................................................20 7.4.1 7.4.2 7.5 INPUT CLOCK QUALITY MONITORING ............................................................................................23 7.5.1 7.5.2 7.5.3 7.5.4 7.6 Priority Configuration .................................................................................................................... 25 Automatic Selection Algorithm ..................................................................................................... 25 Forced Selection........................................................................................................................... 26 Ultra-Fast Reference Switching.................................................................................................... 26 External Reference Switching Mode ............................................................................................ 26 Output Clock Phase Continuity During Reference Switching....................................................... 27 DPLL ARCHITECTURE AND CONFIGURATION .................................................................................27 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.7.8 7.7.9 7.7.10 7.7.11 7.7.12 7.7.13 7.8 Frequency Monitoring................................................................................................................... 23 Activity Monitoring ........................................................................................................................ 23 Selected Reference Activity Monitoring........................................................................................ 24 Composite Clock Inputs................................................................................................................ 24 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ..................................................................25 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 Signal Format Configuration......................................................................................................... 20 Frequency Configuration .............................................................................................................. 22 T0 DPLL State Machine ............................................................................................................... 27 T4 DPLL State Machine ............................................................................................................... 30 Bandwidth..................................................................................................................................... 31 Damping Factor ............................................................................................................................ 32 Phase Detectors ........................................................................................................................... 32 Loss of Phase Lock Detection...................................................................................................... 33 Phase Monitor and Phase Build-Out ............................................................................................ 34 Input to Output Phase Adjustment ............................................................................................... 35 Phase Recalibration ..................................................................................................................... 35 Frequency and Phase Measurement ........................................................................................... 35 Input Wander and Jitter Tolerance ............................................................................................... 36 Jitter and Wander Transfer........................................................................................................... 36 Output Jitter and Wander ............................................................................................................. 37 OUTPUT CLOCK CONFIGURATION .................................................................................................38 7.8.1 Signal Format Configuration......................................................................................................... 39 19-4596; Rev 4; 5/09 2 of 150 DS3101 7.8.2 7.9 Frequency Configuration .............................................................................................................. 39 EQUIPMENT REDUNDANCY CONFIGURATION .................................................................................48 7.9.1 7.9.2 7.9.3 Master-Slave Pin Feature............................................................................................................. 49 Master-Slave Output Clock Phase Alignment .............................................................................. 49 Master-Slave Frame and Multiframe Alignment with the SYNC2K Pin........................................ 50 7.10 COMPOSITE CLOCK RECEIVERS AND TRANSMITTER ......................................................................52 7.10.1 IC1 and IC2 Receivers ................................................................................................................. 53 7.10.2 OC8 Transmitter ........................................................................................................................... 53 7.11 MICROPROCESSOR INTERFACES ..................................................................................................55 7.11.1 Parallel Interface Modes............................................................................................................... 55 7.11.2 SPI Interface Mode....................................................................................................................... 55 7.12 RESET LOGIC ..............................................................................................................................57 7.13 POWER-SUPPLY CONSIDERATIONS ..............................................................................................58 7.14 INITIALIZATION .............................................................................................................................58 8. REGISTER DESCRIPTIONS ...............................................................................................59 8.1 8.2 8.3 8.4 STATUS BITS ...............................................................................................................................59 CONFIGURATION FIELDS ..............................................................................................................59 MULTIREGISTER FIELDS ...............................................................................................................59 REGISTER DEFINITIONS ...............................................................................................................60 9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN....................................................125 9.1 9.2 9.3 9.4 JTAG DESCRIPTION ..................................................................................................................125 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION............................................................126 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ....................................................................128 JTAG TEST REGISTERS .............................................................................................................129 10. ELECTRICAL CHARACTERISTICS..................................................................................130 10.1 10.2 10.3 10.4 10.5 10.6 DC CHARACTERISTICS ...............................................................................................................130 INPUT CLOCK TIMING .................................................................................................................134 OUTPUT CLOCK TIMING .............................................................................................................134 PARALLEL INTERFACE TIMING ....................................................................................................135 SPI INTERFACE TIMING ..............................................................................................................138 JTAG INTERFACE TIMING...........................................................................................................139 11. PIN ASSIGNMENTS ..........................................................................................................140 12. PACKAGE INFORMATION ...............................................................................................145 12.1 256-PIN CSBGA (17MM X 17MM) ..............................................................................................145 13. THERMAL INFORMATION................................................................................................146 14. GLOSSARY .......................................................................................................................147 15. ACRONYMS AND ABBREVIATIONS ...............................................................................148 16. TRADEMARK ACKNOWLEDGEMENTS ..........................................................................148 17. DATA SHEET REVISION HISTORY..................................................................................149 19-4596; Rev 4; 5/09 3 of 150 DS3101 LIST OF FIGURES Figure 2-1. DS3101 Block Diagram ............................................................................................................................. 7 Figure 3-1. Typical Application Example ..................................................................................................................... 8 Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 28 Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 31 Figure 7-3. Typical MTIE for T0 DPLL Output ........................................................................................................... 37 Figure 7-4. Typical TDEV for T0 DPLL Output .......................................................................................................... 38 Figure 7-5. DPLL Block Diagram ............................................................................................................................... 40 Figure 7-6. OC10 8kHz Options ................................................................................................................................ 48 Figure 7-7. GR-378 Composite Clock Pulse Mask.................................................................................................... 54 Figure 7-8. SPI Clock Polarity and Phase Options.................................................................................................... 56 Figure 7-9. SPI Bus Transactions.............................................................................................................................. 57 Figure 9-1. JTAG Block Diagram............................................................................................................................. 125 Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 127 Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 131 Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 132 Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 133 Figure 10-4. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 136 Figure 10-5. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 137 Figure 10-6. SPI Interface Timing Diagram ............................................................................................................. 138 Figure 10-7. JTAG Timing Diagram......................................................................................................................... 139 Figure 11-1. DS3101 Pin Assignment—Left Half .................................................................................................... 143 Figure 11-2. DS3101 Pin Assignment—Right Half.................................................................................................. 144 19-4596; Rev 4; 5/09 4 of 150 DS3101 LIST OF TABLES Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 12 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 13 Table 6-3. Global Pin Descriptions ............................................................................................................................ 14 Table 6-4. Parallel Interface Pin Descriptions ........................................................................................................... 15 Table 6-5. SPI Bus Mode Pin Descriptions ............................................................................................................... 16 Table 6-6. JTAG Interface Pin Descriptions .............................................................................................................. 16 Table 6-7. General-Purpose I/O Pin Descriptions ..................................................................................................... 16 Table 6-8. Power-Supply Pin Descriptions ................................................................................................................ 17 Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements..................................................................................... 19 Table 7-2. Input Clock Capabilities ............................................................................................................................ 21 Table 7-3. Locking Frequency Modes ....................................................................................................................... 22 Table 7-4. Default Input Clock Priorities .................................................................................................................... 25 Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32 Table 7-6. T0 Adaptation for T4 Phase Measurement Mode .................................................................................... 36 Table 7-7. Output Clock Capabilities ......................................................................................................................... 38 Table 7-8. Digital1 and Digital2 Frequencies............................................................................................................. 41 Table 7-9. APLL Frequency to Output Frequencies (T0 and T4) .............................................................................. 42 Table 7-10. T0 APLL Frequency to T0 Path Configuration ....................................................................................... 42 Table 7-11. T4 APLL Frequency to T4 Path Configuration ....................................................................................... 43 Table 7-12. OC1 to OC7 Output Frequency Selection .............................................................................................. 44 Table 7-13. Possible Frequencies for OC1 to OC7 ................................................................................................... 44 Table 7-14. Equipment Redundancy Methodology ................................................................................................... 48 Table 7-15. Composite Clock Variations ................................................................................................................... 52 Table 7-16. GR-378 Composite Clock Interface Specification .................................................................................. 54 Table 7-17. G.703 Synchronization Interfaces Specification..................................................................................... 54 Table 7-18. Microprocessor Interface Modes ............................................................................................................ 55 Table 8-1. Top-Level Memory Map............................................................................................................................ 59 Table 8-2. Register Map ............................................................................................................................................ 60 Table 9-1. JTAG Instruction Codes ......................................................................................................................... 128 Table 9-2. JTAG ID Code ........................................................................................................................................ 129 Table 10-1. Recommended DC Operating Conditions ............................................................................................ 130 Table 10-2. DC Characteristics................................................................................................................................ 130 Table 10-3. CMOS/TTL Pins ................................................................................................................................... 131 Table 10-4. LVDS Pins ............................................................................................................................................ 131 Table 10-5. LVPECL Pins........................................................................................................................................ 132 Table 10-6. AMI Composite Clock Pins ................................................................................................................... 133 Table 10-7. Recommended External Components for Output Clock OC8.............................................................. 133 Table 10-8. Input Clock Timing................................................................................................................................ 134 Table 10-9. Input Clock to Output Clock Delay ....................................................................................................... 134 Table 10-10. Output Clock Phase Alignment, Frame Sync Alignment Mode......................................................... 134 Table 10-11. Parallel Interface Timing..................................................................................................................... 135 Table 10-12. SPI Interface Timing ........................................................................................................................... 138 Table 10-13. JTAG Interface Timing........................................................................................................................ 139 Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 140 Table 13-1. Thermal Properties, Natural Convection .............................................................................................. 146 19-4596; Rev 4; 5/09 5 of 150 DS3101 1. STANDARDS COMPLIANCE Table 1-1. Applicable Telecom Standards SPECIFICATION SPECIFICATION TITLE ANSI T1.101 T1.102 TIA/EIA-644-A ETSI Synchronization Interface Standard, 1999 Digital Hierarchy—Electrical Interfaces, 1993 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 EN 300 417-6-1 EN 300 462-3-1 EN 300 462-5-1 IEEE IEEE 1149.1 ITU-T G.781 G.783 G.812 G.813 G.823 G.824 G.825 G.8262 TELCORDIA GR-253-CORE GR-378-CORE GR-1244-CORE Transmission and Multiplexing (TM); Generic Requirements of Transport Functionality of Equipment; Part 6-1: Synchronization Layer Functions, v1.1.3 (1999-05) Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks; Part 3-1: The Control of Jitter and Wander within Synchronization Networks, v1.1.1 (1998-05) Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks; Part 5-1: Timing Characteristics of Slave Clocks Suitable for Operation in Synchronous Digital Hierarchy (SDH) Equipment, v1.1.1 (1998-05) Standard Test Access Port and Boundary-Scan Architecture, 1990 Synchronization Layer Functions (06/1999) ITU G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks (10/2000 plus Amendment 1 06/2002 and Corrigendum 2 03/2003) Timing Requirements of Slave Clocks Suitable for Use as Node Clocks in Synchronization Networks (06/1998) Timing characteristics of SDH equipment slave clocks (SEC) (03/2003) The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps Hierarchy (03/2000) The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps Hierarchy (03/2000) The Control of Jitter and Wander within Digital Networks which are Based on the Synchronous Digital Hierarchy (SDH) (03/2000) Timing characteristics of synchronous Ethernet equipment slave clock (EEC) (08/2007) SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000 Generic Requirements for Timing Signal Generators, Issue 2, February 1999 Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000 19-4596; Rev 4; 5/09 6 of 150 DS3101 2. BLOCK DIAGRAM Figure 2-1. DS3101 Block Diagram CC Rx IC2A IC1 IC2 IC3 IC4 IC5 POS/NEG IC6 POS/NEG IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 Input Clock Selector, Divider and Monitor 19-4596; Rev 4; 5/09 Output Clock Synthesizer and Selector DS3101 OC1 OC2 OC3 OC4 OC5 OC6 POS/NEG OC7 POS/NEG CC Tx Master Clock Generator Microprocessor Port (8-bit Parallel or SPI Serial) and HW Control and Status Pins WDT WDT JTAG OC8 POS/NEG OC9 OC10 OC11 T0 DPLL HIZ RST IFSEL[2:0] CS WR / R/W RD / DS ALE A[8:0] AD7 / CPOL AD6 / CPHA AD[5:3] AD2 / SCLK AD1 / SDI AD0 / SDO RDY INTREQ MASTSLV SONSDH SRCSW SRFAIL GPIO[4:1] JTRST JTMS JTCLK JTDI JTDO T4 DPLL CC Rx SYNC2K IC1A REFCLK TCXO or OCXO 7 of 150 DS3101 3. APPLICATION EXAMPLE Figure 3-1. Typical Application Example activty and frequency monitoring, select highest priority valid input Backplane create derived DS1 or E1/2048 kHz clock from 19.44 MHz frequency locked to line clock create DS1/E1 frames, insert SSMs, transmit DS1, E1 or 2048 kHz sync signal Timing Card (1 of 2) micro controller N DS3100 Monitor, Divider, Selector BITS Tx T4 DPLL T4 APLL to BITS/SSU BITS Tx TCXO or OCXO N DS1, E1 or 2048 kHz T0 APLL T0 DPLL Monitor, Divider, Selector typically 19.44 MHz point-to-point or multidrop buses BITS Rx from BITS/SSU BITS Rx DS1, E1 or 2048 kHz N Identical to Timing Card 1 N clock/data recovery, equalizer, framer, extract SSMs Timing Card (2 of 2) Stratum 2, 3E, or 3: jitter/wander filtering, hitless switching, phase adjust, holdover Line Card (1 of N) divide line clock down to backplane rate, send to timing cards Line Card (N of N) DPLL select best system clock, hitless switching, basic holdover 4. APLL to port SERDES clock multiplication, jitter cleanup DETAILED DESCRIPTION Figure 2-1 illustrates the blocks described in this section and how they relate to one another. Section 5 provides a detailed feature list. The DS3101 is a highly integrated timing card IC for systems with SONET/SDH ports. At the core of this device are two digital phase-locked loops (DPLLs) labeled T0 and T4 1. DPLL technology makes uses of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to implement PLLs that are precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process variations. The DS3101’s DPLLs are digitally configurable for input and output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. Both DPLLs can directly lock to many common telecom frequencies and also can lock at 8kHz to any multiple of 8kHz up to 155.52MHz. The DPLLs can also tolerate and filter significant amounts of jitter and wander. 1 These names are adapted from output ports of the SETS function specified in ITU and ETSI standards such as ETSI EN 300 462-2-1. 19-4596; Rev 4; 5/09 8 of 150 DS3101 The T0 DPLL is responsible for generating the system clocks used to time the outgoing traffic interfaces of the system (SONET/SDH, synchronous Ethernet, etc.). To perform this role in a variety of systems with diverse performance requirements, the T0 DPLL has a sophisticated feature set and is highly configurable. T0 can automatically transition among free-run, locked and holdover states all without software intervention. In free-run, T0 generates a stable, low-noise clock with the same frequency accuracy as the external oscillator connected to the REFCLK pin. With software calibration the DS3101 can even improve the accuracy to within ±0.02 ppm. When an input reference has been validated, T0 transitions to the locked state in which its output clock accuracy is equal to the accuracy of the input reference. While in the locked state, T0 acquires a high-accuracylong-term average frequency value to use as the holdover frequency. When its selected reference fails, T0 can very quickly detect the failure and enter the holdover state to avoid affecting its output clock. From holdover it can automatically switch to the next highest priority input reference, again without affecting its output clock (hitless switching). Switching among input references can be either revertive or nonrevertive. When all input references are lost, T0 stays in holdover in which it generates a stable low-noise clock with initial frequency accuracy equal to its stored holdover value and drift performance determined by the quality of the external oscillator. With a suitable local oscillator the T0 DPLL provides holdover performance suitable for all applications up to and including Stratum 2. T0 can also perform phase build-outs and fine-granularity output clock phase adjustments. The T4 DPLL has a much less demanding role to play and therefore is much simpler than T0. Often T4 is used as a frequency converter to create a derived DS1- or E1-rate clock (frequency locked to an incoming SONET/SDH port) to be sent to a nearby BITS Timing Signal Generator (TSG, Telcordia terminology) or Synchronization Supply Unit (SSU, ITU-T terminology). In other cases T4 is phase-locked to T0 and used as a frequency converter to produce additional output clock rates for use within the system, such as NxDS1, NxE1, NxDS2, DS3, E3, or 125MHz for synchronous Ethernet. T4 can also be configured as a measuring tool to measure the frequency of an input reference or the phase difference between two input references. At the front end of both the T0 and T4 DPLLs is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This block continuously monitors as many as 14 different input clocks of various frequencies for activity and frequency accuracy. In addition, ICSDM maintains separate input clock priority tables for the T0 and T4 DPLLs and can automatically select and provide the highest priority valid clock to each DPLL without any software intervention. The ICSDM block can also divide the selected clock down to 8kHz if required by the DPLL. In addition to digital clock signals from system line cards, the DS3101 can also directly receive up to two 64kHz composite clock signals on its IC1A and IC2A pins. These signals typically come from a nearby BITS Timing Signal Generator or SSU to provide external timing to the system. The Output Clock Synthesizer and Selector (OCSS) block shown in Figure 2-1 contains the T0 output APLL, the T4 output APLL, clock divider logic, and additional output DFS blocks. The T0 and T4 APLLs multiply the clock rates from the DPLLs by four and simulataneously attenuate jitter. Using the different settings of the T0 and T4 DPLLs and the output divider logic, the DS3101 can produce more than 60 different output frequencies including common SONET/SDH, PDH and synchronous Ethernet rates plus 2kHz and 8kHz frame pulses. In addition to creating digital clock signals for use within the system, the DS3101 can also directly transmit one composite clock signal on its OC8 pin. This signal typically conveys the recovered timing from one SONET/SDH port to a nearby BITS timing-signal generator or SSU which in turn distributes timing to the whole central office. The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus the free-run and holdover stability of the DS3101-based timing card is entirely a function of the stability of the external oscillator, the performance of which can be selected to match the application: TCXO, OCXO, double-oven OCXO, etc. The 12.8MHz clock from the external oscillator is multiplied by sixteen by the Master Clock Generator block to create the 204.8MHz master clock used by the rest of the device. Since every block on the device depends on the master clock and therefore the local oscillator clock for proper operation, the master clock generator has a watchdog timer (WDT) function that can be used to signal a local microprocessor in the event of a local oscillator clock failure. The DS3101 also has several features to support master/slave timing card redundancy and protection. Two DS3101 devices on redundant cards can be configured to maintain the same priority tables, choose the same input references, and generate output clocks and frame syncs with the same frequency and phase. 19-4596; Rev 4; 5/09 9 of 150 DS3101 5. DETAILED FEATURES 5.1 T0 DPLL Features                   5.2           5.3        High-resolution DPLL plus low-jitter output APLL Sophisticated state machine automatically transitions between free-run, locked, and holdover states Revertive or nonrevertive reference selection algorithm Programmable bandwidth in 18 steps from 0.5mHz to 70Hz Separately configurable acquisition bandwidth and locked bandwidth Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 Multiple phase detectors: phase/frequency, early/late, and multicycle Phase/frequency locking (±360° capture) or nearest-edge phase locking (±180° capture) Multicycle phase detection and locking (up to ±8191UI) improves jitter tolerance and lock time Phase build-out in response to input phase transients (1 to 3.5μs) Phase build-out in response to reference switching Less than 5ns output clock phase transient during phase build-out Output phase adjustment up to ±200ns in 6ps steps with respect to selected input reference High-resolution frequency and phase measurement Holdover frequency averaging with 8- or 110-minute intervals APLL frequency options suitable for N x 19.44MHz, N x DS1, and N x E1 Low-jitter frame sync (8kHz) and multiframe sync (2kHz) outputs on OC10 and OC11 2kHz and 8kHz clocks available on OC1 through OC7 with programmable polarity and pulse width T4 DPLL Features High-resolution DPLL plus low-jitter output APLL Programmable bandwidth: 18Hz, 35Hz, or 70Hz Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 Multiple phase detectors: phase/frequency, early/late, and multicycle Phase/frequency locking (±360° capture) or nearest-edge phase locking (±180° capture) Multicycle phase detection and locking (up to ±8191UI) improves jitter tolerance and lock time APLL frequency options suitable for N x 19.44MHz, N x DS1, N x E1, DS3, E3, 6312kHz, and N x 62.5MHz (for Gigabit Ethernet) 2kHz and 8kHz clocks available on OC1 through OC7 with programmable polarity and pulse width Can operate independently or locked to T0 DPLL Phase detector can be used to measure phase difference between two input clocks Input Clock Features 14 input clocks 10 programmable-frequency CMOS/TTL input clocks accept any multiple of 8kHz up to 125MHz Two LVDS/LVPECL/CMOS/TTL input clocks accept any multiple of 8kHz up to 125MHz plus 155.52MHz Two 64kHz composite clock receivers (AMI format) that can also be configured as programmable-frequency CMOS/TTL input clocks if needed All 14 input clocks are constantly monitored by programmable frequency monitors and activity monitors Fast activity monitor can disqualify the selected reference after two missing clock cycles Separate 2/4/8kHz sync input 19-4596; Rev 4; 5/09 10 of 150 DS3101 5.4         5.5     5.6       5.7     Output Clock Features 11 output clocks Five programmable-frequency CMOS/TTL output clocks drive any internally produced clock up 77.76MHz Two programmable-frequency LVDS output clocks drive any internally produced clock up to 311.04MHz Two sync pulses, 2kHz and 8kHz, can be disciplined by a 2kHz or 8kHz sync input One 1.544MHz/2.048MHz output clock One 64kHz composite clock output (AMI format) Output clock rates include 2kHz, 8kHz, NxDS1, NxDS2, DS3, NxE1, E3, 19.44MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, 125.0MHz, 155.52MHz, and 311.04MHz Outputs at even divisors of 311.04MHz have less than 0.5ns peak-to-peak output jitter Redundancy Features Devices on redundant timing cards can be configured for master/slave operation Clocks and frame syncs can be cross-wired between devices to ensure that slave always tracks master Master/slave mode pin can auto-configure slave to track master with no phase build-out and wider bandwidth Input clock priority tables can easily be kept synchronized between master and slave Composite Clock I/O Features Two composite clock receivers and one composite clock transmitter (all AMI format) Compliant with Telcordia GR-378 composite clock, G.703 centralized clock, and G.703 Appendix II.1 Japanese synchronization interfaces Configurable for 50% or 5/8 duty cycle, 1V or 3V pulse amplitude, and 110Ω/120Ω/133Ω termination Received signals are monitored for LOS, AMI violations, presence/absence of the 8 kHz component, and presence/absence of the 400Hz component (for G.703 Appendix II.1 option b) Transmitter can generate or suppress the 8kHz component and/or the 400 Hz component (for G.703 Appendix II.1 option b) Composite clock receiver inputs can be configured as programmable-frequency CMOS/TTL inputs if composite clock support is not needed General Features Operates from a single external 12.800MHz local oscillator (TCXO or OCXO) On-chip local oscillator watchdog circuit Microprocessor interface can be 8-bit parallel (Intel or Motorola, multiplexed or nonmultiplexed) or SPI serial Register set can be write-protected 19-4596; Rev 4; 5/09 11 of 150 DS3101 6. PIN DESCRIPTIONS Table 6-1. Input Clock Pin Descriptions PIN NAME(1) TYPE(2) H1 REFCLK I P6 IC1A I A10 IC1 IPD P7 IC2A I B10 IC2 IPD C10 IC3 IPD Input Clock 3. CMOS/TTL. Programmable frequency (default 8kHz). A11 IC4 IPD Input Clock 4. CMOS/TTL. Programmable frequency (default 8kHz). B5 IC5POS A5 IC5NEG B4 IC6POS A4 IC6NEG B11 IC7 IPD Input Clock 7. CMOS/TTL. Programmable frequency (default 19.44MHz). C11 IC8 IPD Input Clock 8. CMOS/TTL. Programmable frequency (default 19.44MHz). A12 IC9 IPD Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44MHz). B12 IC10 IPD Input Clock 10. CMOS/TTL. Programmable frequency (default 19.44MHz). A13 IC11 IPD Input Clock 11. CMOS/TTL. Programmable frequency (default 19.44MHz in master mode, 6.48MHz in slave mode). C12 IC12 IPD Input Clock 12. CMOS/TTL. Programmable frequency (default 1.544/2.048MHz). B13 IC13 IPD Input Clock 13. CMOS/TTL. Programmable frequency (default 1.544/2.048MHz). A14 IC14 IPD Input Clock 14. CMOS/TTL. Programmable frequency (default 1.544/2.048MHz). B14 SYNC2K IPD Frame Sync Input. 2kHz, 4kHz, or 8kHz. IA, IA IA, IA 19-4596; Rev 4; 5/09 FUNCTION Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local oscillator (TCXO or OCXO). See Section 7.3. Input Clock 1 AMI. AMI 64kHz composite clock. Enabled when MCR5:IC1SF = 0. See Section 7.10.1, Table 10-6, and Figure 10-3. Input Clock 1. CMOS/TTL. Programmable frequency (default 8kHz). Enabled when MCR5:IC1SF = 1. See Section 7.10.1. Input Clock 2 AMI. AMI 64kHz composite clock. Enabled when MCR5:IC2SF = 0. See Section 7.10.1, Table 10-6, and Figure 10-3. Input Clock 2. CMOS/TTL. Programmable frequency (default 8kHz). Enabled when MCR5:IC2SF = 1. See Section 7.10.1. Input Clock 5. LVDS/LVPECL. Programmable frequency (default 19.44MHz LVDS). LVDS: See Table 10-4 and Figure 10-1. LVPECL: See Table 10-5 and Figure 10-2. CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS. Input Clock 6. LVDS/LVPECL. Programmable frequency (default 19.44MHz LVPECL). LVDS: See Table 10-4 and Figure 10-1. LVPECL: See Table 10-5 and Figure 10-2. CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS. 12 of 150 DS3101 Table 6-2. Output Clock Pin Descriptions PIN NAME(1) TYPE(2) C6 OC1 O3 Output Clock 1. CMOS/TTL. Programmable frequency (default 6.48MHz). A7 OC2 O3 Output Clock 2. CMOS/TTL. Programmable frequency (default 38.88MHz). B7 OC3 O3 Output Clock 3. CMOS/TTL. Programmable frequency (default 19.44MHz). C7 OC4 O3 Output Clock 4. CMOS/TTL. Programmable frequency (default 38.88MHz). A8 OC5 O3 Output Clock 5. CMOS/TTL. Programmable frequency (default 77.76MHz). B3 OC6POS O3 Output Clock 6. LVDS. Programmable frequency (default 38.88MHz LVDS). See Table 10-4 and Figure 10-1. O3 Output Clock 7. LVDS. Programmable frequency (default 19.44MHz LVDS). See Table 10-4 and Figure 10-1. O3 Output Clock 8. AMI. 64kHz composite clock. See Section 7.10.2, Table 10-6, and Figure 10-3. A3 OC6NEG C2 OC7POS C1 OC7NEG C8 OC8POS FUNCTION B8 OC8NEG A9 OC9 O3 Output Clock 9. CMOS/TTL. 1.544/2.048MHz. B9 OC10 O3 Output Clock 10. CMOS/TTL. 8kHz frame sync or clock. C9 OC11 O3 Output Clock 11. CMOS/TTL. 2kHz multiframe sync or clock. 19-4596; Rev 4; 5/09 13 of 150 DS3101 Table 6-3. Global Pin Descriptions PIN NAME(1) TYPE(2) FUNCTION B6 RST IPU Active-Low Reset. When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as RST is low. RST should be held low for at least two REFCLK cycles. R14 HIZ IPU Acitve-Low High-Z Enable Input. The JTRST pin must be low to activate this function. 0 = Put all output pins in a high-impedance state 1 = Normal operation N1 IFSEL0 N2 IFSEL1 P1 IFSEL2 R11 MASTSLV IPD IPU Microprocessor Interface Select. During reset, the value on these pins is latched into the IFSEL field of the IFCR register. See Section 7.11. 010 = Intel bus mode (multiplexed) 011 = Intel bus mode (nonmultiplexed) 100 = Motorola mode (nonmultiplexed) 101 = SPI mode (address and data transmitted LSB first) 110 = Motorola mode (multiplexed) 111 = SPI mode (address and data transmitted MSB first) 000, 001 = {unused value} Master/Slave Select Input. Sets the state of the MASTSLV bit in the MCR3 register. 0 = slave mode 1 = master mode M3 SONSDH IPD SONET/SDH Frequency Select Input. Sets the reset-default state of the SONSDH bit in MCR3, the DIG1SS and DIG2SS bits in MCR6, and the OC9SON bit in T4CR1. 0 = SDH rates (N x 2.048MHz) 1 = SONET rates (N x 1.544MHz) M2 SRCSW IPD Source Switching. Fast source switching control input. See Section 7.6.5. J2 SRFAIL O3 SRFAIL Status. When MCR10:SRFPIN = 1, this pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the system a very fast indication of the failure of the current reference. When MCR10:SRFPIN = 0, SRFAIL is disabled (low). C5 WDT IA Watchdog Timer. Analog node for the REFCLK watchdog timer. Connect to a resistor (R) to VDDIO and a capacitor (C) to ground. Suggested values are R = 20kΩ and C = 0.01μF. See Section 7.3. 19-4596; Rev 4; 5/09 14 of 150 DS3101 Table 6-4. Parallel Interface Pin Descriptions Note: These pins are active in Intel and Motorola bus modes. See Section 7.11.1 for functional description and Section 10.4 for timing specifications. PIN NAME(1) TYPE(2) FUNCTION K14 ALE IPD Address Latch Enable. This signal controls the address latch. In nonmultiplexed bus modes, the address is latched from A[8:0]. In these modes, ALE is typically wired high to make the latch transparent. In multiplexed bus modes, the address is latched from A[8] and AD[7:0]. J16 CS IPU Active-Low Chip Select. This pin must be asserted (low) to read or write internal registers. J15 WR/R/W IPU J14 RD/DS IPU E16 F15 G14 F16 G15 H14 G16 H15 H16 C14 D14 E14 C15 D15 C16 D16 E15 A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] B15 RDY A15 INTREQ 19-4596; Rev 4; 5/09 Active-Low Write Enable or Read/Active-Low Write Select. For Intel bus modes, WR is asserted to write internal registers. For Motorola bus modes, R/W = 1 indicates a read and R/W = 0 indicates a write. Active-Low Read Enable or Active-Low Data Strobe. For the Intel-style interface modes, RD is asserted (low) to read internal registers. For the Motorola-style interface modes, the falling edge of DS enables data output on AD[7:0] during reads while the rising edge of DS latches data from AD[7:0] during writes. IPD Address Bus. In nonmultiplexed bus modes, these inputs specify the address of the internal register to be accessed. In multiplexed bus modes, the address is specified on A[8] and AD[7:0], while A[7:0] are not used and should be wired high or low. I/O Address/Data Bus. In both multiplexed and nonmultiplexed bus modes, these pins are an 8-bit data bus. In multiplexed bus modes, these pins also convey the lower 8 bits of the register address. O Active-Low Ready/Data Acknowledge. This pin is asserted when the device has completed a read or write operation. O Interrupt Request. The behavior of this pin is configured in the INTCR register. Polarity can be active high or active low. Drive action can be push-pull or open drain. The pin can also be configured as a general-purpose output if the interrupt request function is not needed. 15 of 150 DS3101 Table 6-5. SPI Bus Mode Pin Descriptions Note: These pins are active in SPI interface modes. See Section 7.11.2 for functional description and Section 10.5 for timing specifications. PIN NAME(1) TYPE(2) FUNCTION J16 CS IPU Active-Low Chip Select. This pin must be asserted to read or write internal registers. C16 SCLK I Serial Clock. SCLK is always driven by the SPI bus master. D16 SDI I Serial Data Input. The SPI bus master transmits data to the device on this pin. E15 SDO O Serial Data Output. The device transmits data to the SPI bus master on this pin. D14 CPHA I Clock Phase. See Section Figure 7-8. 0 = data is latched on the leading edge of the SCLK pulse 1 = data is latched on the trailing edge of the SCLK pulse C14 CPOL I Clock Polarity. See Section Figure 7-8. 0 = SCLK is normally low and pulses high during bus transactions 1 = SCLK is normally high and pulses low during bus transactions O Interrupt Request. The behavior of this pin is configured in the INTCR register. Polarity can be active high or active low. Drive action can be push-pull or open drain. The pin can also be configured as a general-purpose output if the interrupt request function is not needed. A15 INTREQ Table 6-6. JTAG Interface Pin Descriptions Note: See Section 9 for functional description and Section 10.6 for timing specifications. PIN NAME(1) TYPE(2) T8 JTRST IPU R8 JTCLK I JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, JTCLK can be held low or high. R9 JTDI IPU JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If not used, JTDI can be held low or high. P9 JTDO O JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling edge of JTCLK. If not used, leave floating. T9 JTMS IPU JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If not used, connect to VDDIO or leave floating. FUNCTION Active-Low JTAG Test Reset. Asynchronously resets the test access port (TAP) controller. If not used, JTRST can be held low or high. Table 6-7. General-Purpose I/O Pin Descriptions PIN NAME(1) TYPE(2) E2 GPIO1 I/O F3 GPIO2 I/O H2 GPIO3 I/O J1 GPIO4 I/O 19-4596; Rev 4; 5/09 FUNCTION General-Purpose I/O Pin 1. GPCR:GPIO1D configures this pin as an input or an output. GPCR:GPIO1O specifies the output value. GPSR:GPIO1 indicates the state of the pin. General-Purpose I/O Pin 2. GPCR:GPIO2D configures this pin as an input or an output. GPCR:GPIO2O specifies the output value. GPSR:GPIO2 indicates the state of the pin. General-Purpose I/O Pin 3. GPCR:GPIO3D configures this pin as an input or an output. GPCR:GPIO3O specifies the output value. GPSR:GPIO3 indicates the state of the pin. General-Purpose I/O Pin 4. GPCR:GPIO4D configures this pin as an input or an output. GPCR:GPIO4O specifies the output value. GPSR:GPIO4 indicates the state of the pin. 16 of 150 DS3101 Table 6-8. Power-Supply Pin Descriptions PIN NAME(1) TYPE(2) VDD P Core Power Supply. 1.8V ±10% VDDIO P I/O Power Supply. 3.3V ±10% FUNCTION D6, D8, D9, D11, E6, E11, F4, F5, F12, F13, H4, H13, J4, J13, L4, L5, L12, L13, M6, M11, N6, N8, N9, N11 B1, B16, D7, D10, E7–E10, G4, G5, G12, G13, H5, H12, J5, J12, K4, K5, K12, K13, M7–M10, N7, N10, R1, R16 A1, A16, D4, D5, D12, D13, E4, E5, E12, E13, F6–F11, G6–G11, H6–H11, J6–J11, K6–K11, L6–L11, M4, M5, M12, M13, N4, N5, N12, N13, T1, T16 A6 VSS P Ground Reference VDD_ICDIFF P Power Supply for LVDS Inputs (IC5 and IC6). 3.3V ±10% C4 VSS_ICDIFF P Return for LVDS Inputs (IC5 and IC6) B2 VDD_OC6 P Power Supply for LVDS Output OC6. 1.8V ±10% A2 VSS_OC6 P Return for LVDS Output OC6 C3 VDD_OC7 P Power Supply for LVDS Output OC7. 1.8V ±10% D3 VSS_OC7 P Return for LVDS Output OC7 D1 AVDD_PLL1 P Power Supply for T0 Output APLL. 1.8V ±10% D2 AVSS_PLL1 P Return for T0 Output APLL E1 AVDD_PLL2 P Power Supply for T4 Output APLL. 1.8V ±10% E3 AVSS_PLL2 P Return for T4 Output APLL. F1 AVDD_PLL3 P Power Supply for T0 Feedback APLL. 1.8V ±10% G2 AVSS_PLL3 P Return for T0 Feedback APLL G1 AVDD_PLL4 P Power Supply for Master Clock Generator APLL. 1.8V ±10% P Return for Master Clock Generator APLL — Connect to VSS — No Connection G3 AVSS_PLL4 TM1 R13 TM2 T15 C13, F2, F14, H3, J3, K1, K2, K3, K15, K16, L1, L2, L3, L14, L15, L16, M1, M14, M15, M16, N3, N14, N15, N16, P2–P5, P8, P10–P16, R2–R7, R10, R12, R15, T2–T7, T10–T14 N.C. Note 1: All pin names with an overbar (e.g., CS) are active low. Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description. I = input pin O = output pin IA = analog input pin OA = analog output pin (can be placed in a high-impedance state) IPD = input pin with internal 50kΩ pulldown O3 = output pin that can tri-stated (i.e., placed in a high-impedance state) P = power-supply pin IPU = input pin with internal 50kΩ pullup to approx. 2.2V I/O = input/output pin Note 3: Note 4: All digital pins are I/O pins in JTAG mode. When ramping power supplies up or down, the voltage on any 1.8V power supply pin must not exceed the voltage on any 3.3V powersupply pin. 19-4596; Rev 4; 5/09 17 of 150 DS3101 7. FUNCTIONAL DESCRIPTION 7.1 Overview The DS3101 has 14 input clocks and 11 output clocks,. There are two separate DPLL paths in the device: the highperformance T0 path and the simpler T4 path. See Figure 2-1. Two of the 14 input clocks are 64kHz composite clock receivers (by default), two are LVDS/LVPECL, and 10 are CMOS/TTL (5V tolerant). The composite clock receivers can be converted to CMOS/TTL inputs as needed. The CMOS/TTL inputs can accept signals from 2kHz to 125MHz. The LVDS/LVPECL pins can accept clock signals up to 155.52MHz. Each input clock can be monitored continually for activity and/or frequency. Frequency can be compared to both a hard limit and a soft limit. Inputs outside the hard limit are declared invalid, while inputs inside the hard limit but outside the soft limit are merely flagged. Each input can be marked unavailable or given a priority number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special modes, the highest priority valid input is automatically selected as the reference for each path. Both the T0 and T4 DPLLs can directly lock to many common telecom frequencies, including, but not limited to 8kHz, DS1, E1, 19.44MHz, and 38.88MHz. The DPLLs can also lock to any multiple of 8kHz up to 125MHz. The T0 DPLL is the high-performance path with all the features for node timing synchronization. The T4 DPLL is a simpler auxiliary path typically used to provide derived DS1s, E1s, or other synchronization signals to an external BITS/SSU. The two paths can be operated independently or locked together. Both DPLLs have these features:  Automatic reference selection based on input quality and priority  Optional manual reference selection/forcing  Configurable quality thresholds for each input  Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor  Ability to lock to several common telecom frequencies plus multiples of 8kHz up to 155.52MHz  Frequency conversion between input and output using digital frequency synthesis  Combined performance of a stable, consistent digital PLL and a low-jitter analog output PLL The T0 DPLL has these additional features not available in the T4 DPLL:  A full state machine for automatic transitions among free-run, locked, and holdover states  Nonrevertive reference switching mode  Phase build-out for reference switching (“hitless”) and for phase hits on the selected reference  Output vs. input phase offset control  18 bandwidth selections from 0.5mHz to 70Hz (vs. three selections for the T4 path)  Noise rejection circuitry for low-frequency references  Optional software control over holdover frequency  Output phase alignment to input frame sync signal  Several frequency averaging methods for acquiring the holdover frequency The T4 DPLL has these additional features not available in the T0 DPLL:  Optional mode to lock to the T0 DPLL  Optional mode to measure the phase difference between two input clocks  Ability to generate DS3, E3, 6312kHz, and N x 62.5MHz (Gigabit Ethernet) frequencies Typically the internal state machine controls the T0 DPLL, but manual control by system software is also available. The T4 DPLL has a simpler state machine that software cannot directly control. In either DPLL, however, software can override the DPLL logic using manual reference selection. The T0 DPLL always operates at 77.76MHz, regardless of the output frequencies selected for the output clock pins. The T4 DPLL can operate at any of several frequencies in order to support generation of frequencies such as 19-4596; Rev 4; 5/09 18 of 150 DS3101 44.736MHz (DS3) and 34.368MHz (E3). When the T4 DPLL is locked to the T0 DPLL, it locks to an 8kHz signal from T0 to ensure synchronization of all possible T4 frequencies, which are always multiples of 8kHz. The outputs of the T0 and T4 DPLLs are connected to high-speed APLLs that multiply the DPLL clock rate and filter DPLL output jitter. The outputs of the APLLs are divided down to make a wide variety of possible frequencies available at the output clock pins. All or some of the output frequencies of the T0 DPLL can be synchronized to an input 2kHz, 4kHz, or 8kHz sync signal (SYNC2K pin). This synchronization to a low-frequency input enables, among other things, two redundant timing cards to maintain output phase alignment with one another. Seven of the output clocks can be configured for a variety of different frequencies from either the T0 DPLL or the T4 DPLL. One output clock is a 64kHz composite clock transmitter (AMI format), one is 1544kHz or 2048kHz, one is 8kHz, and one is 2kHz. Of the seven multifrequency outputs, five are CMOS/TTL and two are LVDS. Altogether more than 60 output frequencies are possible, ranging from 2kHz to 311.04MHz. 7.2 Device Identification and Protection The 16-bit read-only ID field in the ID1 and ID2 registers is set to 0C1Dh = 3101 decimal. The device revision can be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The register set can be protected from inadvertent writes using the PROT register. 7.3 Local Oscillator and Master Clock Configuration The T0 and T4 DPLL paths operate from a 204.8MHz master clock. The master clock is synthesized from a 12.800MHz clock originating from a local oscillator attached to the REFCLK pin. The stability of the T0 DPLL in holdover is equivalent to the stability of the local oscillator. Selection of an appropriate local oscillator is, therefore, of crucial importance if the telecom standards listed in Table 1-1 are to be met. TCXOs can be used in less stringent cases, but OCXOs are required in the most demanding applications. Even OCXOs may need to be shielded to avoid slow frequency changes due to ambient temperature fluctuations and drift. Careful evaluation of the local oscillator component is necessary to ensure proper performance. Contact Maxim at www.maxim-ic.com/support for recommended oscillators. For reference, the Telcordia GR-1244-CORE stability requirements for Stratum 2, Stratum 3E and Stratum 3 are listed in Table 7-1. Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements PARAMETER Temperature STRATUM 2 n/a Drift (non-temp) ± 1 x 10-10/day STRATUM 3E ± 10 x 10-9 ± 1.16 x 10-14/sec (± 1 x 10-9/day) STRATUM 3 ± 280 x 10-9 ± 4.63 x 10-13/sec (± 40 x 10-9/day) Note: Refer to GR-1244-CORE for additional details. The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because the DS3101 can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the local oscillator clock. The MCLKFREQ field in registers MCLK1 and MCLK2 specifies the frequency adjustment to be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps. 19-4596; Rev 4; 5/09 19 of 150 DS3101 The DS3101 implements a stand-alone watchdog circuit that causes an interrupt on the INTREQ pin when the local oscillator attached to the REFCLK pin is significantly off frequency. The watchdog interrupt is not maskable, but is subject to the INTCR register settings. When the watchdog circuit activates, reads of any and all registers in the device will return 00h to indicate the failure. In response to the activation of the INTREQ pin or during periodic polling, if system software ever reads 00h from the ID registers (which are hard-coded to 0C1Dh = 3101 decimal) then it can conclude that the local oscillator attached to that DS3101 has failed. For proper operation of the watchdog timer, connect the WDT pin to a resistor (R) to VDDIO and a capacitor (C) to ground. Suggested values are R = 20kΩ and C = 0.01μF. 7.4 Input Clock Configuration The DS3101 has 14 input clocks: IC1 to IC14. Table 7-2 provides summary information about each clock, including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller. 7.4.1 Signal Format Configuration Inputs with CMOS/TTL signal format accept both TTL and 3.3V CMOS levels. One key configuration bit that affects the available frequencies is the SONSDH bit in MCR3. When SONSDH = 1 (SONET mode), the 1.544MHz frequency is available. When SONSDH = 0 (SDH mode), the 2.048MHz frequency is available. During reset, the default value of this bit is latched from the SONSDH pin. Input clocks IC5 and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using the proper set of external components. The recommended LVDS termination is shown in Figure 10-1, and the LVDS electrical specifications are listed in Table 10-4. The recommended LVPECL termination is shown in Figure 10-2, and the LVPECL electrical specifications are listed in Table 10-5. To configure these differential inputs to accept singleended CMOS/TTL signals, use a voltage-divider to bias the ICxNEG pin to approximately 1.4V and connect the single-ended signal to the ICxPOS pin. If IC5 or IC6 is not used it should be configured for LVDS and left floating (one input is internally pulled high and the other internally pulled low). (See also MCR5:IC5SF and IC6SF.) By default, input clocks IC1 and IC2 are 64kHz composite clock receivers (see Section 7.10). The composite clock signal is a 64kHz AMI clock with an embedded 8kHz clock indicated by deliberate bipolar violations (BPVs) every 8 clock cycles. The 8kHz component is the clock that is forwarded to the DPLLs. The AMI composite clock electrical specifications are shown in Table 10-6, and the recommended external components are shown in Figure 10-3. IC1 and IC2 can be configured as standard CMOS/TTL inputs (identical to IC3) by setting MCR5:IC1SF = 1 or MCR5:IC2SF = 1, respectively. 19-4596; Rev 4; 5/09 20 of 150 DS3101 Table 7-2. Input Clock Capabilities INPUT CLOCK IC1 IC2 SIGNAL FORMATS AMI or CMOS/TTL(3) AMI or CMOS/TTL(3) FREQUENCIES 64kHz composite clock or up to 125MHz 64kHz composite clock or up to 125MHz DEFAULT FREQUENCY 8kHz 8kHz IC3 CMOS/TTL Up to 125MHz(1) 8kHz IC4 CMOS/TTL Up to 125MHz 8kHz Up to 155.52MHz(2) 19.44MHz Up to 155.52MHz 19.44MHz IC5 IC6 LVDS/LVPECL or CMOS/TTL LVDS/LVPECL or CMOS/TTL IC7 CMOS/TTL Up to 125MHz 19.44MHz IC8 CMOS/TTL Up to 125MHz 19.44MHz IC9 CMOS/TTL Up to 125MHz 19.44MHz IC10 CMOS/TTL Up to 125MHz 19.44MHz IC11 CMOS/TTL Up to 125MHz IC12 CMOS/TTL Up to 125MHz IC13 CMOS/TTL Up to 125MHz IC14 CMOS/TTL Up to 125MHz Note 1: Master mode (MASTSLV = 1): 19.44MHz Slave mode (MASTSLV = 0): 6.48MHz SONET mode (SONSDH = 1): 1.544MHz SDH mode (SONSDH = 0): 2.048MHz SONET mode (SONSDH = 1): 1.544MHz SDH mode (SONSDH = 0): 2.048MHz SONET mode (SONSDH = 1): 1.544MHz SDH mode (SONSDH = 0): 2.048MHz Available frequencies for CMOS/TTL input clocks are 2kHz, 4kHz, 8kHz, 1.544MHz (SONET mode), 2.048MHz (SDH mode), 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 38.88MHz, 51.84MHz, 77.76MHz, and N x 8kHz for 2 ≤ N ≤ 15,625. Note 2: Available frequencies for LVDS/LVPECL input clocks include all CMOS/TTL frequencies in Note 1 plus 155.52MHz. Note 3: Signal formats for IC1 and IC2 are controlled by MCR5:IC1SF and IC2SF, respectively. 19-4596; Rev 4; 5/09 21 of 150 DS3101 7.4.2 Frequency Configuration Input clock frequencies are configured in the FREQ field of the ICR registers. The DIVN and LOCK8K bits of these same registers specify the locking frequency mode, as shown in Table 7-3. Table 7-3. Locking Frequency Modes DIVN LOCK8K 0 0 1 0 1 X 7.4.2.1 LOCKING FREQUENCY MODE Direct lock mode LOCK8K mode DIVN mode Direct Lock Mode In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the corresponding ICR register. Direct lock mode can only be used for input clocks with these specific frequencies: 2kHz, 4kHz, 8kHz, 1.544MHz, 2.048MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 38.88MHz, 51.84MHz, 77.76MHz, and 155.52MHz. For the 155.52MHz case, the input clock is internally divided by two, and the DPLL direct-locks at 77.76 MHz. The T0 DPLL can direct-lock to all the specific input frequencies listed above, and so can the T4 DPLL when configured for 77.76MHz operation (see Section 7.8.2.2). When configured for non-77.76MHz operation, the T4 DPLL can direct-lock to any of the specific frequencies listed above from 2kHz to 6.48MHz, but for the specific frequencies of 19.44MHz and higher, the input must be configured for LOCK8K or DIVN mode. MTIE may be somewhat lower in direct lock mode because the higher frequencies allow more frequent phase updates. 7.4.2.2 LOCK8K Mode In LOCK8K mode, an internal divider is configured to divide the selected reference down to 8kHz. The DPLLs lock to the 8kHz output of the divider. LOCK8K mode can only be used for input clocks with these frequencies: 8kHz, 1.544MHz, 2.048MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 38.88MHz, 51.84MHz, 77.76MHz, and 155.52MHz. LOCK8K mode is enabled for a particular input clock by setting the LOCK8K bit in the corresponding ICR register. LOCK8K mode gives a greater tolerance to input jitter because it uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be configured using the 8KPOL bit in the TEST1 register. For 2kHz and 4kHz clocks, the LOCK8K bit is ignored and direct-lock mode is used. 7.4.2.3 DIVN Mode In DIVN mode, the internal divider is configured from the value stored in the DIVN registers. The DIVN value must be chosen so that when the selected reference is divided by DIVN+1 the output clock is 8kHz. The DPLLs lock to the 8kHz output of the divider. DIVN mode can only be used for input clocks whose frequency is an integer multiple of 8 kHz and less than or equal to 155.52MHz. The DIVN register field can range from 1 to 19,439 inclusive. The same DIVN+1 factor is used for all input clocks configured for DIVN mode. When DIVN = 1 in an ICR register, the FREQ field of that register is ignored. Note that although DIVN divider is able to divide down clock rates has as high as 155.52MHz (DIVN = 19,439), the CMOS/TTL inputs are only rated for a maximum clock rate of 125MHz (DIVN = 15,624). 19-4596; Rev 4; 5/09 22 of 150 DS3101 7.5 Input Clock Quality Monitoring Each input clock is continuously monitored for frequency accuracy and activity. Frequency monitoring is described in Section 7.5.1, while activity monitoring is described in Sections 7.5.2 and 7.5.3. Any input clock that has a frequency out-of-band alarm or activity alarm is automatically declared invalid. The valid/invalid state of each input clock is reported in the corresponding real-time status bit in register VALSR1 or VALSR2. When the valid/invalid state of a clock changes, the corresponding latched status bit is set in register MSR1 or MSR2, and an interrupt request occurs if the corresponding interrupt enable bit is set in registers IER1 or IER2. Input clocks marked invalid cannot be selected as the reference for either DPLL. If the T4 DPLL does not have any valid input clocks available, the T4NOIN status bit is set to 1 in MSR3. 7.5.1 Frequency Monitoring The DS3101 monitors the frequency of each input clock and invalidates any clock whose frequency is outside of specified limits. Two frequency limits can be specified: a soft limit and a hard limit. For all input clocks except the T0 DPLL’s selected reference, these limits are specified in the ILIMIT register. For the T0 DPLL’s selected reference the limits are specified in the SRLIMIT register. When the frequency of an input clock is greater than or equal to the soft limit, the corresponding SOFT alarm bit is set to 1 in the ISR registers. The soft limit is only for monitoring; triggering it does not invalidate the clock. When the frequency of an input clock is greater than or equal to the hard limit, the corresponding HARD alarm bit is set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. Monitoring according to the hard and soft limits is enabled/disabled using the HARDEN and SOFTEN bits in the MCR10 register. Both the ILIMIT and SRLIMIT registers have a default soft limit of ±11.43ppm and a default hard limit of ±15.24ppm. Limits can be set from ±3.81ppm to ±60.96ppm in 3.81ppm steps. Both the SOFT and HARD alarm limits have hysteresis as required by GR-1244. Frequency monitoring is only done on an input clock when the clock does not have an activity alarm. 5 15 Frequency measurement can be done with respect to the internal 204.8MHz master clock or the 77.76MHz T0 DPLL output, as specified by the FMONCLK bit in MCR10. Measured frequency can be read from any frequency monitor by specifying the input clock in the FMEASIN field of MCR11 and reading the frequency from the FMEAS register. 7.5.2 Activity Monitoring Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully between events and no alarm is declared. When events occur close enough together, the accumulator increments faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the alarm clear threshold. The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 through 3) in the BUCKET field of the ICR registers. Each leaky bucket configuration has programmable size, alarm declare threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers at addresses 50h through 5Fh. Activity monitoring is divided into 128ms intervals. The accumulator is incremented once for each 128ms interval in which the input clock is inactive for more than two cycles (more than four cycles for 155.52MHz input clocks). Thus the “fill” rate of the bucket is at most 1 unit per 128ms, or approximately 8 units/second. During each period of 1, 2, 4 or 8 intervals (programmable), the accumulator decrements if no irregularities occur. Thus the “leak” rate of the bucket is approximately 8, 4, 2, or 1 units/second. A leak is prevented when a fill event occurs in the same interval. When the value of an accumulator reaches the alarm threshold (LBxU register), the corresponding ACT alarm bit is set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. When the value of an accumulator reaches the alarm clear threshold (LBxL register), the activity alarm is cleared by clearing the clock’s ACT bit. The accumulator cannot increment past the size of the bucket specified in the LBxS register. The decay rate of the accumulator is specified in the LBxD register. The values stored in the leaky bucket configuration registers must have the following relationship at all times: LBxS ≥ LBxU > LBxL. 15 19-4596; Rev 4; 5/09 23 of 150 DS3101 When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the “x” in “LbxU” is the leaky bucket configuration number, 0 to 3). The minimum time to clear an activity alarm in seconds is [2LBxD x (LBxS - LBxL) / 8]. For example, assume LBxU = 8, LBxL = 1, LBxS = 10, and LBxD = 0. The minimum time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity alarm would be [20 x (10 - 1) / 8 = 1.125 seconds]. For input clocks IC1 and IC2 configured in composite clock mode, if MCR5:BITERR = 1, then the accumulator is also incremented whenever a violation of the one-BPV-in-eight pattern is detected. 7.5.3 Selected Reference Activity Monitoring The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference can cause unwanted jitter, wander or frequency offset on the output clocks. When anomalies occur on the selected reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from the reference until the reference is available again. By design, the regular input clock activity monitor (Section 7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity monitor that detects inactivity within approximately two missing reference clock cycles (within approximately four missing cycles for 155.52MHz references). When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the selected reference and sets the SRFAIL bit in MSR2. The setting of the SRFAIL bit can cause an interrupt request on the INTREQ pin if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin follows the state of the SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference switch (see Section 7.6.4). When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-of-lock during no-activity events. If the selected reference becomes available again before any alarms are declared by the activity monitor or frequency monitor, then the T0 DPLL continues to track the selected reference using nearest-edge locking (±180°) to avoid cycle slips. When NALOL = 1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 state machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt request if enabled. If the selected reference becomes available again before any alarms are declared by the activity monitor or frequency monitor, then the T0 DPLL tracks the selected reference using phase/frequency locking (±360°) until phase lock is reestablished. When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If NALOL = 1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an interrupt request if enabled. 7.5.4 Composite Clock Inputs When input clocks IC1 and IC2 are configured for composite clock mode (MCR5:IC1SF = 0 and MCR5:IC2SF = 0), they are also monitored for various defects (AMI error, LOS, etc.) See Section 7.10.1 for further details. 19-4596; Rev 4; 5/09 24 of 150 DS3101 7.6 7.6.1 Input Clock Priority, Selection, and Switching Priority Configuration During normal operation, the selected reference for the T0 DPLL and the selected reference for the T4 DPLL are chosen automatically based on the priority rankings assigned to the input clocks in the input priority registers (IPR1 to IPR7). Each of these seven registers has priority fields for two input clocks. When T4T0 = 0 in the MCR11 register, the IPR registers specify the input clock priorities for the T0 DPLL. When T4T0 = 1, the IPR registers specify the input clock priorities for the T4 DPLL. The default input clock priorities, for both PLLs, are shown in Table 7-4. Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks. Table 7-4. Default Input Clock Priorities INPUT CLOCK IC1 IC2 IC3 IC4 IC5 IC6 IC7 Note 1: 7.6.2 DEFAULT PRIORITY 2 3 4 5 6 7 8 INPUT CLOCK IC8 IC9 IC10 IC11 IC12 IC13 IC14 DEFAULT PRIORITY 9 10 11 12 or 1 (1) 13 14 15 During reset, the default priority for IC11 is set to 12 in the master device and set to 1 in the slave device. Devices are configured as master and slave by the value of the MASTSLV pin. (The state of the MASTSLV pin is mirrored in the MASTSLV bit of the MCR3 register.) See Section 7.9. Automatic Selection Algorithm The real-time valid/invalid state of each input clock is maintained in the VALSR1 and VALSR2 registers. The selected reference can be marked invalid for phase, frequency or activity. Other input clocks can be invalidated for frequency or activity. The reference selection algorithm for each DPLL chooses the highest-priority valid input clock to be the selected reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table of valid inputs. The top three entries in this table and the selected reference are displayed in the PTAB1 and PTAB2 registers. When T4T0 = 0 in the MCR11 register, these registers indicate the highest priority input clocks for the T0 DPLL. When T4T0 = 1, they indicate the highest priority input clocks for the T4 path. If two or more input clocks are given the same priority number then those inputs are prioritized among themselves using a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid then the next equal-priority clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is inherently nonrevertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equal-priority inputs have the highest priority. An important input to the selection algorithm for T0 DPLL is the REVERT bit in the MCR3 register. In revertive mode (REVERT = 1), if an input clock with a higher priority than the selected reference becomes valid, the higherpriority reference immediately becomes the selected reference. In nonrevertive mode (REVERT = 0), the higherpriority reference does not immediately become the selected reference but does become the highest-priority reference in the priority table (REF1 field in the PTAB1 register). (The selection algorithm always switches to the highest-priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For many applications, nonrevertive mode is preferred for the T0 DPLL because it minimizes disturbances on the output clocks due to reference switching. The T4 DPLL always operates in revertive mode. In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under software control. The validation of the new higher priority clock sets the corresponding status bit in the MSR1 or 19-4596; Rev 4; 5/09 25 of 150 DS3101 MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. System software can then respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive the switchover to the higher priority clock. In most systems redundant timing cards are required, with one functioning as the master and the other as the slave. In such systems the priority tables of the master and slave must match. The DS3101’s register set makes it easy for the slave’s priority table to track the master’s table. At system start-up, the same priorities must be assigned to the input clocks, for both DPLLs, in the master and slave devices. During operation, if an input clock becomes valid or invalid in one device (master or slave), the change is flagged in that device’s MSR1 or MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. The real-time valid/invalid state of the input clocks can then be read from that device’s VALSR1 and VALSR2 registers. Once the nature of the state change is understood, the control bits of the other device’s VALCR1 and VALCR2 registers can be manipulated to mark clocks invalid in the other device as well. 7.6.3 Forced Selection The T0FORCE field in the MCR2 register and the T4FORCE field in the MCR4 register provide a way to force a specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 1 to 14 specify the input clock to be the forced selection. Internally forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT = 1) the forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority input is listed as the third-highest priority (PTAB2:REF3). 7.6.4 Ultra-Fast Reference Switching By default, disqualification of the selected reference and switchover to another reference occurs when the activity monitor’s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects approximately two missing clock cycles it declares the reference failed by forcing the leaky bucket accumulator to its upper threshold (see Section 7.5.2) and initiates reference switching. This is in addition to setting the SRFAIL bit in MSR2 and optionally generating an interrupt request, as described in Section 7.5.3. When ultra-fast switching occurs, the T0 DPLL transitions to the prelocked 2 state, which allows switching to occur faster by bypassing the Loss-of-Lock state. The device should be in non-revertive mode when ultra-fast switching is enabled. If the device is in revertive mode, ultra-fast switching could cause excessive reference switching when the highest priority input is intermittent. 7.6.5 External Reference Switching Mode In the external reference switching mode, the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by setting the EXTSW bit to 1 in the MCR10 register. In this mode, if the SRCSW pin is high, the device is forced to lock to input IC3 (if the priority of IC3 is nonzero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the selected input has a valid reference signal. If the SRCSW pin is low the device is forced to lock to input IC4 (if the priority of IC4 is non-zero in IPR2) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a valid reference signal. During reset the default value of the EXTSW bit is latched from the SRCSW pin. If external reference switching mode is enabled during reset, the default frequency tolerance (DLIMIT registers) is configured to ±80ppm rather than the normal default of ±9.2ppm. In external reference switching mode the device is simply a clock switch, and the DPLL is forced to lock onto the selected reference whether it is valid or not. Unlike forced reference selection (Section 7.6.3) this mode controls the PTAB1:SELREF field directly and is therefore not affected by the state of the MCR3:REVERT bit. During external reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2 and REF3 fields in the PTAB registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the automatic selection logic. External reference switching mode only affects the T0 DPLL. 19-4596; Rev 4; 5/09 26 of 150 DS3101 7.6.6 Output Clock Phase Continuity During Reference Switching If phase build out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than ±30ppm then the device always complies with the GR-1244-CORE requirement that the rate of phase change must be less than 81ns per 1.326ms during reference switching. 7.7 DPLL Architecture and Configuration Both the T0 and T4 paths of the device are digital PLLs (DPLLs) with analog PLLs (APLLs) at the output stage. This architecture combines the benefits of both PLL types. Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature and voltage, and (2) flexible behavior that is easily programmed via configuration registers. DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS, a high-speed master clock (204.8MHz) is multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master clock is then digitally divided down to the desired output frequency. Since the resolution of the DFS process is one master clock cycle or 4.88ns, the DFS output clock has jitter of up to 1 master clock UI (4.88ns) pk-pk. The analog PLLs filter the jitter from the DPLLs, reducing the 4.88ns pk-pk jitter to 0.5ns pk-pk and 60ps RMS, typical, measured broadband (10Hz to 1GHz). The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input frequency, pull-in/hold-in range, loop frequency, output frequency, input-to-output phase offset, phase build-out, and more. No knowledge of loop equations or gain parameters is required to configure and operate the device. No external components are required for the DPLLs or the APLLs except the high-quality local oscillator connected to the REFCLK pin. The T0 path is the main path through the device, and the T0 DPLL has a full free-run/locked/holdover state machine and full programmability. The T4 path is a simpler frequency converter/synthesis path, lacking the low bandwidth settings, phase build-out, phase adjustment controls, and holdover state found in the T0 DPLL. 7.7.1 T0 DPLL State Machine The T0 DPLL has three main timing modes: locked, holdover, and free-run. The control state machine for the T0 DPLL has states for each timing mode as well as three temporary states: prelocked, prelocked 2, and loss-of-lock. The state transition diagram is shown in Figure 7-1. Descriptions of each state are given in the paragraphs below. During normal operation the state machine controls state transitions. When necessary, however, the state can be forced using the T0STATE field of the MCR1 register. Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register. 7.7.1.1 Free-Run State Free-run mode is the reset default state. In free-run, all output clocks are derived from the 12.800MHz local oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock (see Section 7.3). The state machine transitions from free-run to the prelocked state when at least one input clock is valid. 7.7.1.2 Prelocked State The prelocked state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the selected reference. If phase lock is achieved during this period then the state machine transitions to locked mode. If the DPLL fails to lock to the selected reference within the phase-lock time-out period specified by PHLKTO then a phase lock alarm is raised (corresponding LOCK bit set in the ISR register), invalidating the input (ICn bit goes low in VALSR registers). If another input clock is valid then the state machine re-enters the prelocked state and tries to lock to the alternate input clock. If no other input clocks are valid then the state machine transitions back to the free-run state. In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock timeout period, then the state machine re-enters the prelocked state and tries to lock the higher priority input. If a 19-4596; Rev 4; 5/09 27 of 150 DS3101 phase-lock timeout period longer than 100 seconds is required for locking (such as 700 seconds for Stratum 3E or 1000 seconds for Stratum 2 applications), the PHLKTO register must be configured accordingly. Figure 7-1. T0 DPLL State Transition Diagram Free-Run select ref (001) Reset (selected reference invalid OR out of lock >100s) AND no valid input clock [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher-priority input)] AND valid input clock available Pre-locked wait for 100s) AND OR out of lock >100s] AND Pre-locked 2 Loss-of-Lock no valid input clock available valid input clock available wait for 100s) AND no valid input clock available all input clocks evaluated at least one input valid Note 2: An input clock is valid when it has no activity alarm, no hard frequency limit alarm, and no phase lock alarm (see the VALSR registers and the ISR registers). All input clocks are continuously monitored for activity and frequency. Note 3: Only the selected reference is monitored for loss of lock. Note 4: Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds. Note 5: To simply the diagram, the phase-lock timeout period is always shown as 100s, which is the default value of the PHLKTO register. Longer or shorter timeout periods can be specified as needed by writing the appropriate value to the PHLKTO register. 19-4596; Rev 4; 5/09 28 of 150 DS3101 7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the DPLL has locked to the selected reference for at least one second (see Section 7.7.6). In the locked state, the output clocks track the phase and frequency of the selected reference. While in the locked state, if the selected reference is so impaired that an activity alarm or a hard frequency limit alarm is raised (corresponding ACT or HARD bit set in the ISR register), then the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine immediately transitions to either the prelocked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid). If loss-of-lock is declared while in the locked state, the state machine transitions to the loss-of-lock state. 7.7.1.4 Loss-of-Lock State When the loss-of-lock detectors (see Section 7.7.6) indicate loss-of-phase lock, the state machine immediately transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds (default value of PHLKTO register) to regain phase lock. If phase lock is regained during that period, the state machine transitions back to the locked state. If, during the phase-lock timeout period specified by PHLKTO, the selected reference is so impaired that an activity alarm or a hard frequency limit alarm is raised (corresponding ACT or HARD bit set in the ISR registers), then the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine immediately transitions to either the prelocked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid). If phase lock cannot be regained by the end of the phase-lock timeout period, then a phase lock alarm is raised (corresponding LOCK bit set in the ISR registers), the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine transitions to either the prelocked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid). 7.7.1.5 Prelocked 2 State The prelocked and prelocked 2 states are similar. The prelocked 2 state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the new selected reference. If phase lock is achieved during this period, then the state machine transitions to locked mode. If the DPLL fails to lock to the new selected reference within the phase-lock timeout period specified by PHLKTO, then a phase lock alarm is raised (corresponding LOCK bit set in the ISR registers), invalidating the input (ICn bit goes low in VALSR registers). If another input clock is valid, the state machine re-enters the prelocked 2 state and tries to lock to the alternate input clock. If no other input clocks are valid, the state machine transitions to the holdover state. In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock timeout period, the state machine re-enters the prelocked 2 state and tries to lock to the higher priority input. If a phase-lock timeout period longer than 100 seconds is required for locking (such as 700 seconds for Stratum 3E or 1000 seconds for Stratum 2 applications), then the PHLKTO register must be configured accordingly. 7.7.1.6 Holdover State The device reaches the holdover state when it declares its selected reference invalid and has no other valid input clocks available. During holdover the T0 DPLL is not phase locked to any input clock but instead generates its output frequency from stored frequency information, typically the averaged frequency of the DPLL when it was in the locked state. The device can be configured for manual or automatic holdover as described in the following subsections. When at least one input clock has been declared valid the state machine immediately transitions from holdover to the prelocked 2 state and tries to lock to the highest priority valid clock. 7.7.1.6.1 Automatic Holdover For automatic holdover (MANHO = 0 in MCR3), the device can be further configured for instantaneous mode or averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current frequency at the moment of entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2 and FREQ3 registers when MCR11:T4T0 = 0). The FREQ field is the DPLL’s integral path and therefore is an average 19-4596; Rev 4; 5/09 29 of 150 DS3101 frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not used to minimize the effect of recent phase disturbances on the holdover frequency. In averaged mode (AVG = 1 in HOCR3), the holdover frequency is set to an internally averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged. The FAST bit in HOCR3 determines the period of this averaging. When FAST = 1 the frequency is averaged for a period of approximately 8 minutes. When FAST = 0 (slow), the frequency is averaged for a period of approximately 110 minutes. The T0 DPLL indicates that it has acquired valid holdover values by setting the FHORDY and SHORDY status bits in VALSR2 (real-time status) and MSR4 (latched status). If FAST = 0 and the T0 DPLL must enter holdover before the 110-minute average is available, then the 8-minute average is used, if available. Otherwise the instantaneous value from the integral path is used. If FAST = 1 and the T0 DPLL must enter holdover before the 8-minute average is available, then the instantaneous value is used. 7.7.1.6.2 Manual Holdover For manual holdover (MANHO = 1 in MCR3), the holdover frequency is set by the HOFREQ field in the HOCR1, HOCR2 and HOCR3 registers. The HOFREQ field has the same size and format as the current frequency field (FREQ[18:0] in the FREQ1, FREQ2, and FREQ3 registers). If desired, software can, during locked operation, read the current frequency from FREQ, filter or average it over time, and then write the resulting holdover frequency to HOFREQ. The FREQ field is derived from the DPLL’s integral path, and thus can be considered an average frequency with a rate of change inversely proportional to the DPLL bandwidth. To combine internal averaging with additional software filtering, the HOFREQ field can be configured to read out the internally averaged frequency when RDAVG = 1 in the HOCR3 register. This averaged value can be read from HOFREQ regardless of the current holdover mode. The FAST bit in HOCR3 specifies whether the value read is from the fast averager or the slow averager. 7.7.1.7 Mini-Holdover When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the DPLL enters mini-holdover mode, with a mini-holdover frequency as specified by the MINIHO field of HOCR3. Miniholdover lasts until the selected reference returns or a new input clock has been chosen as the selected reference or the state machine enters the holdover state. Note that when the T0 DPLL is configured for manual holdover (MCR3:MANHO = 1), mini-holdover is also configured for manual holdover and HOCR3:MINIHO is ignored. 7.7.2 T4 DPLL State Machine The T4 DPLL has a simpler state machine than the T0 DPLL, as shown in Figure 7-2. The T4 DPLL states are similar to the equivalent states of the T0 DPLL. Note that the T4 DPLL only operates in revertive switching mode. 19-4596; Rev 4; 5/09 30 of 150 DS3101 Figure 7-2. T4 DPLL State Transition Diagram Reset Free-Run all input clocks evaluated at least one input valid selected reference invalid AND valid input clock available Pre-locked loss-of-lock on selected reference selected reference invalid AND valid input clock available 7.7.3 selected reference invalid AND no valid input clock available phase-locked to selected reference Locked selected reference invalid AND no valid input clock available Bandwidth The bandwidth of the T4 DPLL is configured in the T4BW register to be 18Hz, 35Hz, or 70Hz. This bandwidth value is used for both acquisition and locked mode. The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 0.5mHz to 70Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW = 1, the T0 DPLL uses the T0ABW bandwidth during acquisition (not phase locked) and the T0LBW bandwidth when phase locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition and when phase locked. When LIMINT = 1 in the MCR9 register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. 19-4596; Rev 4; 5/09 31 of 150 DS3101 7.7.4 Damping Factor The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register, while the damping factor the T4 DPLL is configured in the DAMP field of the T4CR2 register. The reset default damping factors for both DPLLs are chosen to give a maximum wander gain peak of approximately 0.1dB. Available settings are a function of DPLL bandwidth (configured in the T4BW, T0ABW, and T0LBW registers). See Table 7-5. Table 7-5. Damping Factors and Peak Jitter/Wander Gain BANDWIDTH 0.5mHz to 4Hz 8Hz 18 Hz 35 Hz 70 Hz 7.7.5 DAMP[2:0] VALUE 1, 2, 3, 4, 5 1 2, 3, 4, 5 1 2 3, 4, 5 1 2 3 4, 5 1 2 3 4 5 DAMPING FACTOR 5 2.5 5 1.2 2.5 5 1.2 2.5 5 10 1.2 2.5 5 10 20 GAIN PEAK (dB) 0.1 0.2 0.1 0.4 0.2 0.1 0.4 0.2 0.1 0.06 0.4 0.2 0.1 0.06 0.03 Phase Detectors Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are available in both the T0 and T4 DPLLs:  Phase/frequency detector (PFD)  Early/late phase detector (PD2) for fine resolution  Multicycle phase detector (MCPD) for large input jitter tolerance These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle phase detector detects and remembers phase differences of many cycles (up to 8191UI). The phase detectors can be configured for normal phase/frequency locking (±360° capture) or nearest-edge phase locking (±180° capture). With nearest-edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically switches to nearest-edge locking when the multicycle phase detector is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the TEST1 register disables nearest-edge locking and forces the DPLL to use phase/frequency locking. The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2* fields of registers T0CR2 and T0CR3 for the T0 DPLL and registers T4CR2 and T4CR3 for the T4 DPLL. The reset default settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot and bandwidth. The multicycle phase detector is enabled by setting MCPDEN = 1 in the PHLIM2 register. The range of the MCPD—from ±1UI up to ±8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase position over many clock cycles, giving high jitter tolerance. Thus the use of the MCPD is an alternative to the use of LOCK8K mode for jitter tolerance. When USEMCPD = 1 in PHLIM2, the MCPD is used in the DPLL loop, giving faster pull-in but more overshoot. In this mode the loop has similar behavior to LOCK8K mode. In both cases large phase differences contribute to the dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is used in the DPLL loop. 19-4596; Rev 4; 5/09 32 of 150 DS3101 7.7.6 Loss of Phase Lock Detection Loss of phase lock is triggered by any of the following in both the T0 and T4 DPLLs:  The fine phase lock detector (measures phase between input and feedback clocks)  The coarse phase lock detector (measures whole cycle slips)  Hard frequency limit detector  Inactivity detector The fine phase lock detector is enabled by setting FLEN = 1 in the PHLIM1 register. The fine phase limit is configured in the FINELIM field of PHLIM1. The coarse phase lock detector is enabled by setting CLEN = 1 in the PHLIM2 register. The coarse phase limit is configured in the COARSELIM field of PHLIM2. This coarse phase lock detector is part of the multicycle phase detector (MCPD) described in Section 7.7.5. the COARSELIM fields sets both the MCPD range and the coarse phase limit, since the two are equivalent. If loss of phase lock should not be declared for multiple-UI input jitter then the fine phase lock detector should be disabled and the coarse phase lock detector should be used instead. The hard frequency limit detector is enabled by setting FLLOL = 1 in the DLIMIT3 register. The hard limit for the T0 DPLL is configured in registers DLIMIT1 and DLIMIT2. The T4 DPLL hard limit is fixed at ±80ppm. When the DPLL frequency reaches the hard limit, loss-of-lock is declared. The DLIMIT3 register also has the SOFTLIM field to specify a soft frequency limit. Exceeding the soft frequency limit does not cause loss-of-lock to be declared. When the T0 DPLL frequency exceeds the soft limit the T0SOFT status bit is set in the OPSTATE register. When the T4 DPLL frequency exceeds the soft limit the T4SOFT status bit is set in OPSTATE. Both the SOFT and HARD alarm limits have hysteresis as required by GR-1244. The inactivity detector is enabled by setting NALOL = 1 in the PHLIM1 register. When this detector is enabled the DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See Section 7.5.3. When the T0 DPLL declares loss of phase lock, the state machine immediately transitions to the loss-of-lock state, which sets the STATE bit in the MSR2 register and requests an interrupt if enabled. When the T4 DPLL declares loss of phase lock, the T4LOCK bit is cleared in the OPSTATE register, which sets the T4LOCK bit in the MSR3 register and requests an interrupt if enabled. 19-4596; Rev 4; 5/09 33 of 150 DS3101 7.7.7 7.7.7.1 Phase Monitor and Phase Build-Out Phase Monitor The T0 DPLL has a phase monitor that measures the phase error between the input clock reference and the DPLL output. The phase monitor is enabled by setting PHMON:PMEN = 1. When the T0 DPLL is set for low bandwidth, a phase transient on the input causes an immediate phase error that is gradually reduced as the DPLL tracks the input. When the measured phase error exceeds the limit set in the PHMON:PMLIM field, the phase monitor declares a phase monitor alarm by setting the MSR3:PHMON bit. The PMLIM field can be configured for a limit ranging from about 1μs to about 3.5μs. 7.7.7.2 Phase Build-Out in Response to Input Phase Transients See Telcordia GR-1244-CORE Section 5.7 for an explanation of phase build-out (PBO) and the requirement for stratum 2 and 3E clocks to perform PBO in response to input phase transients. When the phase monitor is enabled (as described in Section 7.7.7.1) and PHMON:PMPBEN = 1, the T0 DPLL automatically triggers PBO events in response to input transients greater than the limit set in PHMON:PMLIM. The range of limits available in the PMLIM field allows the T0 DPLL to be configured to build out input transients greater than 3.5μs, greater than 1μs, or any threshold in between. To determine when to perform PBO, the phase monitor watches for phase changes greater than 100ns in a 10ms interval on the selected reference. When such a phase change occurs, an internal 0.1 second timer is started. If during this interval the phase change is greater than the PMLIM threshold then a PBO event occurs. During a PBO event the device enters a temporary holdover state in which the phase difference between the selected reference and the output is measured and fed into the DPLL loop to absorb the input transient. After a PBO event, regardless of the input phase transient, the output phase transient is less than or equal to 5ns. Phase build-out can be frozen at the current phase offset by setting MCR10:PBOFRZ = 1. When PBO is frozen the T0 DPLL ignores subsequent phase build-out events and maintains the current phase offset between input and outputs. 7.7.7.3 Phase Build-Out in Response to Reference Switching When MCR10:PBOEN = 0, phase build-out is not performed during reference switching, and the T0 DPLL always locks to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference. When MCR10:PBOEN = 1, phase build-out is performed during reference switching. With PBO enabled, if the selected reference fails and another valid reference is available then the device enters a temporary holdover state in which the phase difference between the new reference and the output is measured and fed into the DPLL loop to absorb the input phase difference. Similarly, during transitions from holdover or free-run to locked mode, the phase difference between the new reference and the output is measured and fed into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the input phase difference, the output phase transient is less than or equal to 5ns. Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ = 1. When PBO is frozen the T0 DPLL ignores subsequent phase build-out events and maintains the current phase offset between inputs and outputs. Disabling PBO while the T0 DPLL is in the locked state causes a phase change on the output clocks while the DPLL switches to tracking the selected reference with 0 degrees of phase error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO in the locked state also causes a PBO event. 19-4596; Rev 4; 5/09 34 of 150 DS3101 7.7.7.4 Manual Phase Build-Out Control Software can have manual control over phase build-out, if required. Initial configuration for manual PBO involves locking to an input clock with frequency ≥ 6.48MHz, setting MCR10:PBOEN = 0 and PHMON:PMPBEN = 0 to disable automatic phase build-out, and setting PHMON:PMEN = 1 and the proper phase limit in PHMON:PMLIM to enable monitoring for a phase transient. During operation, software can monitor for either a phase transient (MSR3:PHMON = 1) or a T0 DPLL state change (MSR2:STATE = 1). When either event occurs, software can perform the following procedure to execute a manual phase build-out (PBO) event: 1) Read the phase offset from the PHASE registers to decide whether or not to initiate a PBO event. 2) If a PBO event is desired then save the phase offset and set MCR10:PBOEN to cause a PBO event. 3) When the PBO event is complete (wait for a timeout and/or PHASE = 0), write the manual phase offset registers (OFFSET) with the phase offset read earlier. (Note: the PHASE register is in degrees, the OFFSET register is in picoseconds) 4) Clear MCR10:PBOEN and wait for the next event that may need a manual PBO. 7.7.7.5 PBO Phase Offset An uncertainty of up to 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The PBOFF register specifies a small fixed offset for each phase build-out event to skew the average error toward zero and eliminate accumulation of phase shifts in one direction. 7.7.8 Input to Output Phase Adjustment When phase build-out is disabled (PBOEN = 0 in MCR10 and PMPBEN = 0 in PHMON), the OFFSET registers can be used to adjust the phase of the T0 DPLL output clocks with respect to the selected reference. Output phase offset can be adjusted over a ±200ns range in 6ps increments. This phase adjustment occurs in the feedback clock so that the output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. To quickly track large changes in phase, either LOCK8K mode (Section 7.4.2.2) or the coarse phase detector (Section 7.7.5) should be used. Simply writing to the OFFSET registers with phase build-out disabled causes a change in the input to output phase which can be considered to be a delay adjustment. 7.7.9 Phase Recalibration When a phase build-out occurs, either automatic or manual, the feedback frequency synthesizer does not get an internal alignment signal to keep it aligned with the output dividers, and therefore the phase difference between input and output may become incorrect. This could occur if there is a power supply glitch or EMI event that affects the sequential logic state machines. Setting the FSCR3:RECAL bit periodically causes a recalibration process to be executed, which corrects any phase error that may have occurred. During the recalibration process the device puts the DPLL into mini holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the OFFSET registers, and then switches the DPLL out of mini holdover. If the OFFSET registers are written during the recalibration process, the process will ramp the phase offset to the new offset value. 7.7.10 Frequency and Phase Measurement Standard input clock frequency monitoring is described in Section 7.5.1. The input clock monitors report measured frequency with 3.8ppm resolution. More accurate measurement of frequency and phase can be accomplished using the DPLLs. The T0 DPLL is always monitoring its selected reference, but if the T4 DPLL is not otherwise used then it can be configured as a high-resolution frequency and phase monitor. Software can then connect the T4 DPLL to various input clocks on a rotating basis to measure frequency and phase. See MCR4:T4FORCE. DPLL frequency measurements can be read from the FREQ field spanning registers FREQ1, FREQ2 and FREQ3. This field indicates the frequency of the selected reference for either the T0 DPLL or the T4 DPLL, depending on the setting of the T4T0 bit in MCR11. This frequency measurement has a resolution of 0.0003068ppm over a ±80ppm range. The value read from the FREQ field is the DPLL’s integral path value, which is an averaged measurement with an averaging time inversely proportional to DPLL bandwidth. DPLL phase measurements can be read from the PHASE field spanning registers PHASE1 and PHASE2. This field indicates the phase difference seen by the phase detector for either the T0 DPLL or the T4 DPLL, depending 19-4596; Rev 4; 5/09 35 of 150 DS3101 on the setting of the T4T0 bit in MCR11. This phase measurement has a resolution of approximately 0.7 degrees and is internally averaged with a -3dB attenuation point of approximately 100Hz. Thus, for low DPLL bandwidths the PHASE field gives input phase wander in the frequency band from the DPLL corner frequency up to 100Hz. This information could be used by software to compute a crude MTIE measurement up to an observation time of approximately 1000 seconds. For the T0 DPLL, the PHASE field always indicates the phase difference between the selected reference and the internal feedback clock. The T4 DPLL, however, can be configured to measure the phase difference between two input clocks. When T0CR1:T4MT0 = 1, the T4 path is disabled and the T4 phase detector is configured to compare the T0 DPLL selected reference with the T4 DPLL selected reference. Any input clock can then be forced to be the T4 DPLL selected reference using the T4FORCE field of MCR4. This feature can be used, for example, to measure the phase difference between the T0 DPLL’s selected reference and its next highest priority reference. Software could compute MTIE and TDEV with respect to the selected reference for any or all of the other input clocks. When comparing the phase of the T0 and T4 selected references by setting T0CR1:T4MT0 = 1, several details must be kept in mind. In this mode, the T4 path receives a copy of the T0 selected reference, either directly or through a divider to 8kHz. If the T4 selected reference is divided down to 8kHz using LOCK8K or DIVN modes (see Section 7.4.2), then the copy of the T0 selected reference is also divided down to 8kHz. If the T4 selected reference is configured for direct-lock mode, then the copy of the T0 selected reference is not divided down and must be the same frequency as the T4 selected reference. See Table 7-6 for more details. (While T0CR1:T4MT0 = 1 the T0 path continues to lock to the T0 selected reference in the manner specified in the corresponding ICR register.) Table 7-6. T0 Adaptation for T4 Phase Measurement Mode LOCKING MODE FOR T4 SELECTED REFERENCE LOCKING MODE FOR T0 SELECTED REFERENCE DIVN or LOCK8K DIVN or LOCK8K DIVN or LOCK8K DIRECT LOCK8K DIVN LOCKING MODE FOR COPY OF T0 SELECTED REF LOCK8K LOCK8K DIVN DIRECT Any DIRECT FREQUENCY OF THE T4 SELECTED REF FOR T4/T0 PHASE MEASUREMENT FREQUENCY OF THE T0 SELECTED REF FOR T4/T0 PHASE MEASUREMENT 8kHz 8kHz 8kHz Same as the T4 selected ref input frequency 8kHz 8kHz 8kHz Same as the T0 selected ref input frequency(1) Note 1: In this case, the T0 select reference must be the same frequency as the T4 selected reference. Note 2: If the T4 selected reference frequency is 8kHz and the T0 selected reference is a different frequency, the two references can be compared by configuring the T4 selected reference for 8 kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided down to 8kHz using either LOCK8K or DIVN mode. 7.7.11 Input Wander and Jitter Tolerance The device is compliant with the jitter and wander tolerance requirements of the standards listed in Table 1-1. Wander is tolerated up to the point where wander causes an apparent long-term frequency offset larger than the limits specified in the ILIMIT and/or SRLIMIT registers. In such a situation the input clock would be declared invalid. Jitter is tolerated up to the point of eye closure. Either LOCK8K mode (see Section 7.4.2.2) or the multicycle phase detector (see Section 7.7.5) should be used for high jitter tolerance. 7.7.12 Jitter and Wander Transfer In the DS3101, the transfer of jitter and wander from the selected reference to the output clocks has a programmable transfer function that is determined by the DPLL bandwidth. (See Section 7.7.3.) In the T0 DPLL, the 3dB corner frequency of the jitter transfer function can be set to any of 18 positions from 0.5mHz to 70Hz. In the T4 DPLL, the 3dB corner frequency of the jitter transfer function can be set to 18Hz, 35Hz, or 70Hz. During locked mode, the transfer of wander from the local oscillator clock (connected to the REFCLK pin) to the output clocks is not significant as long as the DPLL bandwidth is set high enough to allow the DPLL to quickly compensate for oscillator frequency changes. During free-run and holdover modes, local oscillator wander has a much more significant effect. See Section 7.3. 19-4596; Rev 4; 5/09 36 of 150 DS3101 7.7.13 Output Jitter and Wander Several factors contribute to jitter and wander on the output clocks, including:  Jitter and wander amplitude on the selected reference (while in the locked state)  The jitter/wander transfer characteristic of the device (while in the locked state)  The jitter and wander on the local oscillator clock signal (especially wander while in the holdover state) The DPLL in the device has programmable bandwidth (see Section 7.7.3). With respect to jitter and wander, the DPLL behaves as a low-pass filter with a programmable pole. The bandwidth of the DPLL is normally set low enough to strongly attenuate jitter. The wander attenuation depends on the DPLL bandwidth chosen. Over time frequency changes in the local oscillator can cause a phase difference between the selected reference and the output clocks. This is especially true at DPLL bandwidths of 0.1Hz and below because the DPLL’s rate of change may be slower than the oscillator’s rate of change. Oscillators with better stability will minimize this effect. In some applications an OCXO may be required rather than a TCXO. In the most demand applications, the OCXO may need to be shielded to further reduce the rate of temperature change and thus the rate of frequency change. Typical MTIE and TDEV measurements for the DS3101 in locked mode are shown in Figure 7-3 and Figure 7-4, respectively. Figure 7-3. Typical MTIE for T0 DPLL Output 1000 G.813 Option 1 constant temperature mask MTIE (ns) 100 10 Measured MTIE, 19.44 MHz Input and Output, 4 Hz Bandwidth, DS4026 TCXO 1 0.1 0.01 0.1 1 10 100 1000 10000 Obs e rvation Inte rval (s ) 19-4596; Rev 4; 5/09 37 of 150 DS3101 Figure 7-4. Typical TDEV for T0 DPLL Output 10 G.813 Option 1 constant temperature mask TDEV (ns) 1 0.1 Measured TDEV, 19.44 MHz Input and Output, 4 Hz Bandwidth, DS4026 TCXO 0.01 0.001 0.01 0.1 1 10 100 1000 10000 Obs e rvation Inte rnval (s ) 7.8 Output Clock Configuration A total of 11 output clock pins, OC1 to OC11, are available on the device. Output clocks OC1 to OC7 are individually configurable for a variety of frequencies derived from either the T0 DPLL path or the T4 DPLL path. Output clocks OC8 to OC11 are more specialized, serving as a dedicated composite clock transmitter (OC8), a 1544/2.048kHz clock (OC9), an 8kHz frame sync (OC10), and a 2kHz multiframe sync (OC11). Table 7-7 provides more detail on the capabilities of the output clocks. Table 7-7. Output Clock Capabilities OUTPUT CLOCK OC1 OC2 OC3 OC4 OC5 OC6 OC7 OC8 SIGNAL FORMAT CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL LVDS LVDS AMI Frequency selection per Section 7.8.2.3 and Table 7-9 through Table 7-12 OC9 CMOS/TTL 1.544MHz or 2.048MHz OC10 CMOS/TTL 8kHz frame sync with programmable pulse width and polarity OC11 CMOS/TTL 2kHz multiframe sync with programmable pulse width and polarity 19-4596; Rev 4; 5/09 FREQUENCIES SUPPORTED 64kHz composite clock 38 of 150 DS3101 7.8.1 Signal Format Configuration Output clocks OC6 and OC7 are enabled and disabled via the OC6SF and OC7SF configuration bits in the MCR8 register. The LVDS electrical specifications are listed in Table 10-4, and the recommended LVDS termination is shown in Figure 10-1. These outputs can be easily interfaced to LVPECL and CML inputs on neighboring ICs using a few external passive components. Refer to Maxim App Note HFAN-1.0: Introduction to LVDS, PECL, and CML for details. Output clock OC8 is a dedicated composite clock (CC) transmitter. The composite clock signal is a 64kHz AMI clock with an embedded 8kHz clock indicated by deliberate bipolar violations (BPVs) every 8 clock cycles. See Section 7.10.2 for OC8 configuration details. The AMI CC electrical specifications are shown in Table 10-6, and the recommended external components are shown in Figure 10-3. Output clocks OC1 to OC5 and OC9 to OC11 are always CMOS/TTL signal format. 7.8.2 Frequency Configuration The frequency of most of the output clocks is a function of the settings used to configure the components of the T0 and T4 PLL paths. These components are shown in the detailed block diagram of Figure 7-5. The T0 and T4 PLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS, a high-speed master clock (204.8MHz) is divided down to the desired output frequency. The edges of the output clock, however, are not ideally located in time but rather are aligned with the edges of the master clock resulting in jitter with an amplitude equal to 1 period of the master clock (i.e., 4.88ns). 7.8.2.1 T0 DPLL and APLL Details The 77M forward DFS block (see Figure 7-5) uses the 204.8MHz master clock and DFS to synthesize a 77.76MHz clock with 4.88ns inherent peak-to-peak jitter. This clock can be fed directly to the feedback DFS block or it can be passed through the feedback APLL to reduce jitter to less than 1ns. The 77M forward DFS block handles phase build-out and any phase offset configured in the OFFSET registers. Thus, the 77M output DFS block and the 77M forward DFS block are frequency locked but may have a phase offset. The feedback DFS block takes as its input clock either the output from the 77M forward DFS or the jitter-filtered output from the T0 feedback APLL. The feedback DFS block synthesizes the appropriate locking frequency for use in the phase-frequency detector (PFD). The 77M output DFS block also uses the 204.8MHz master clock and DFS to synthesize a 77.76MHz clock with 4.88ns peak-to-peak jitter. This clock goes to both the output APLL and the low frequency (LF) output DFS block. 19-4596; Rev 4; 5/09 39 of 150 DS3101 Figure 7-5. DPLL Block Diagram 0 T4CR1:T4FREQ[3:0] MCR4:LKT4T0 T4 selected reference T4 PFD and Loop Filter 0 1 1 T4 Foward DFS MCR4:T4DFB Locking Frequency 1 T4 Output APLL 0 MCR4:T4DFB 0 T4 LF Output DFS T4 Feedback DFS 1 1 T4 Output Dividers T0CR1:T4APT0 0 0 OC8, OC9 T0CR1:T4MT0 1 T0 selected reference 8 kHz T4 Path OC10, OC11 T0 LF Output DFS T0CR1:T0FREQ[2:0] T0 77M Output DFS T0 selected reference T0 PFD and Loop Filter Locking Frequency T0 77M Foward DFS T0 Feedback DFS T0 Feedback APLL MCR4:OC89 T0 Output APLL T0 Output Dividers OC1 to OC7 OCRm:OFREQn[3:0] FSCR1:2K8KSRC T0CR1:T0FREQ[2:0] 1 0 T0CR1:T0FREQ[2:0]=000 T0 Path The LF output DFS block takes as its input clock either the output from the 77M output DFS or the jitter-filtered output of the output APLL. The LF output DFS block synthesizes three frequencies: Digital1, Digital2, and a third frequency for producing multiple N x DS1/E1 rates via the output APLLs. When the output APLL uses the output from the LF output DFS, the LF output DFS uses the output from the 77M output DFS block to avoid a loop. The LF output DFS also synthesizes frequencies for use by output clocks OC8, OC9, OC10, and OC11. The frequency of the Digital1 clock is configured by the DIG1SS bit in MCR6 and the DIG1F[1:0] field in MCR7. The frequency of the Digital2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the DIG2F[1:0] field in MCR7. Digital1 and Digital2 can be independently configured for any of the frequencies shown in Table 7-8. Because they are generated by DFS and cannot be filtered by an APLL, Digital1 and Digital2 have relatively highamplitude jitter. The minimum jitter is approximately 12ns (one period of the input clock to the LF output DFS) when the T0 path is in analog feedback mode. The maximum jitter is approximately 17ns when T0 is in digital feedback mode. Both the Digital1 and Digital2 rates are available to output clocks OC1 to OC7. The output APLL takes as its input clock either the output of the 77M output DFS or one of the frequencies from the LF output DFS (77.76MHz, 16 x DS1, 24 x DS1, 12 x E1, or 16 x E1). The output frequency of the output APLL is four times the input frequency (e.g., 311.04MHz for 77.76MHz input). The output clock is then divided by 1, 2, 4, 6, 8, 12, 16, and 48. These clock rates are available to the OC1 to OC7 output clocks. 19-4596; Rev 4; 5/09 40 of 150 DS3101 Table 7-8. Digital1 and Digital2 Frequencies DIGxF[1:0] SETTING IN MCR7 00 01 10 11 00 01 10 11 DIGxSS SETTING IN MCR6 0 0 0 0 1 1 1 1 FREQUENCY (MHz) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 Note: When MCR6:DIG2AF = 1, Digital2 generates 6312kHz (must set MCR6:DIG2SS = 0 and MCR7:DIG2F = 00). 7.8.2.2 T4 DPLL and APLL Details The T4 path is simpler than the T0 path and does not support phase build-out or phase offset. The T4 path can be locked to an input clock or to the T0 path (by setting LKT4T0 = 1 in MCR4). Using the 204.8MHz master clock and DFS, the T4 forward DFS block generates a clock with 4.88 ns inherent peak-to-peak jitter at any of the following frequencies: 16 x DS1, 24 x DS1, 12 x E1, 16 x E1, DS3, 2 x E3, 62.5MHz, or 77.76MHz. This clock can be fed directly to the T4 feedback DFS block (T4DFB = 1 in MCR4), or it can be passed through the T4 output APLL to reduce jitter to less than 1ns (T4DFB = 0). The T4 feedback DFS block takes as its input clock either the output from the T4 forward DFS or the jitter-filtered output from the T4 output APLL, depending on the setting of MCR4:T4DFB. The T4 feedback DFS block synthesizes the appropriate locking frequency for use in the T4 phase-frequency detector (PFD). The T4 output APLL filters jitter to less than 1 ns and takes as its input clock either the output of the T4 forward DFS block or one of the frequencies from the T0 LF output DFS (16xDS1, 24xDS1, 12xE1, 16xE1 or 4x6312kHz, as specified by T0CR1:T0FT4[2:0]). The output frequency of the output APLL is four times the input frequency (e.g., 311.04MHz for 77.76MHz input). The output clock is then divided by 2, 4, 8, 16, 48, and 64. These clock rates are available to the OC1 to OC7 output clocks. The T4 LF output DFS block normally takes as its input clock the jitter-filtered output of the T4 output APLL. When the T4 output APLL is connected to the T0 LF output DFS (T0CR1:T4APT0 = 1), the T4 output APLL must be disconnected from the T4 DPLL loop by configuring the loop for digital feedback (MCR4:T4DFB = 1). In this situation the T4 LF output DFS takes its input from the T4 forward DFS block. The T4 LF output DFS block generates 2kHz and 8kHz frequencies for use by output clocks OC1 to OC7 (when FSCR1:2K8KSRC = 1) and synthesizes frequencies for use by output clocks OC8 and OC9 (when MCR4:OC89 = 1). 19-4596; Rev 4; 5/09 41 of 150 DS3101 7.8.2.3 OC1 to OC7 Configuration The following is a step-by-step procedure for configuring the frequencies of output clocks OC1 to OC7: 1) Determine whether the T4 path must be independent of the T0 path or not. If the T4 path must be independent, set T4APT0 = 0 in register T0CR1. If the T4 path can be locked to the T0 path then set T4APT0 = 1. 2) Use Table 7-9 to select a set of output frequencies for each path, T0 and T4. Each path can only generate one set of output frequencies. (In SONET/SDH equipment the T0 path is typically configured for an APLL frequency of 311.04MHz in order to get 19.44MHz and/or 38.88MHz output clocks to distribute to system line cards.) 3) Determine from Table 7-9 the T0 and T4 APLL frequencies required for the frequency sets chosen in step 2. 4) Configure the T0FREQ field in register T0CR1 as shown in Table 7-10 for the T0 APLL frequency determined in step 3. Configure the T4FREQ field in register T4CR1 as shown in Table 7-11 for the T4 APLL frequency determined in step 3. If the T4 APLL is locked to the T0 DPLL then the T0FT4 field in T0CR1 must also be configured as shown in Table 7-11. 5) Using Table 7-9 and Table 7-12, configure the frequencies of output clocks OC1 through OC7 in the OFREQn fields of registers OCR1 to OCR4. 6) If any of OC1 to OC7 are configured for 2kHz or 8kHz frequency, set 2K8KSRC = 0 in FSCR1 to source these frequencies from the T0 path or 2K8KSRC = 1 to source these frequencies from the T4 path. Table 7-13 lists all possible frequencies for output clocks OC1 to OC7 and specifies how to configure the T0 path and/or the T4 path to obtain each frequency. Table 7-13 also indicates the expected jitter amplitude for each frequency. Table 7-9. APLL Frequency to Output Frequencies (T0 and T4) APLL FREQUENCY 311.04 274.944 250.000 178.944 148.224 131.072 100.992 98.816 98.304 APLL/2 APLL/4 APLL/6 APLL/8 APLL/12 APLL/16 APLL/48 APLL/64 155.52 137.472 125.000 89.472 74.112 65.536 50.496 49.408 49.152 77.76 68.376 62.500 44.736 37.056 32.768 25.248 24.704 24.576 51.84 — — — 24.704 21.84533 16.832 16.46933 16.384 38.88 34.368 31.250 22.368 18.528 16.384 12.624 12.352 12.288 25.92 — — — 12.352 10.92267 8.416 8.23467 8.192 19.44 17.184 15.625 11.184 9.264 8.192 6.312 6.176 6.144 6.48 5.728 5.2083 3.728 3.088 2.73067 2.104 2.05867 2.048 4.86 4.296 3.90625 2.796 2.316 2.048 1.578 1.544 1.536 Note: All frequencies in MHz. Common telecom frequencies are in bold type. Table 7-10. T0 APLL Frequency to T0 Path Configuration T0 APLL FREQUENCY (MHz) 311.04 311.04 98.304 131.072 148.224 98.816 100.992 19-4596; Rev 4; 5/09 T0 FREQUENCY MODE 77.76MHz, digital feedback 77.7MHz, analog feedback 12 x E1 (digital feedback) 16 x E1 (digital feedback) 24 x DS1 (digital feedback) 16 x DS1 (digital feedback) 4 x 6312kHz (digital feedback) T0FREQ[2:0] SETTING IN T0CR1 000 001 010 011 100 101 110 OUTPUT JITTER (pk-pk, ns) < 0.5 < 0.5