DS31256+

DEMO KIT AVAILABLE DS31256 256-Channel, High-Throughput HDLC Controller www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS31256 Envoy is a 256-channel HDLC controller that can handle up to 60 T1 or 64 E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The DS31256 is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus. 256 Independent, Bidirectional HDLC Channels Up to 132Mbps Full-Duplex Throughput Supports Up to 60 T1 or 64 E1 Data Streams 16 Physical Ports (16 Tx and 16 Rx) That Can Be Independently Configured for Channelized or Unchannelized Operation Three Fast (52Mbps) Ports; Other Ports Capable of Speeds Up to 10Mbps (Unchannelized) Channelized Ports Can Each Handle One, Two, or Four T1 or E1 Lines Per-Channel DS0 Loopbacks in Both Directions Over-Subscription at the Port Level Transparent Mode Supported On-Board Bit Error-Rate Tester (BERT) with Automatic Error Insertion Capability BERT Function Can Be Assigned to Any HDLC Channel or Any Port Large 16kB FIFO in Both Receive and Transmit Directions Efficient Scatter/Gather DMA Maximizes Memory Efficiency Receive Data Packets are Time-Stamped Transmit Packet Priority Setting V.54 Loopback Code Detector Local Bus Allows for PCI Bridging or Local Access Intel or Motorola Bus Signals Supported Backward Compatibility with DS3134 33MHz 32-Bit PCI (V2.1) Interface 3.3V Low-Power CMOS with 5V Tolerant I/O JTAG Support IEEE 1149.1 256-Pin Plastic BGA (27mm x 27mm) There are 16 HDLC engines (one for each port) that are each capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. The DS31256 Envoy also has three fast HDLC engines that only reside on Ports 0, 1, and 2. They are capable of operating at speeds up to 52Mbps. APPLICATIONS Channelized and Clear-Channel (Unchannelized) T1/E1 and T3/E3 Routers with Multilink PPP Support High-Density Frame-Relay Access xDSL Access Multiplexers (DSLAMs) Triple HSSI High-Density V.35 SONET/SDH EOC/ECC Termination ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS31256 0°C to +70°C 256 PBGA DS31256+ 0°C to +70°C 256 PBGA +Denotes lead-free/RoHS-compliant package. Features continued on page 6. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 183 REV: 012506 DS31256 256-Channel, High-Throughput HDLC Controller TABLE OF CONTENTS 1. 2. 3. MAIN FEATURES............................................................................................................6 DETAILED DESCRIPTION ..............................................................................................7 SIGNAL DESCRIPTION ................................................................................................13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4. OVERVIEW/SIGNAL LIST .............................................................................................................13 SERIAL PORT INTERFACE SIGNAL DESCRIPTION..........................................................................18 LOCAL BUS SIGNAL DESCRIPTION ..............................................................................................19 JTAG SIGNAL DESCRIPTION ......................................................................................................22 PCI BUS SIGNAL DESCRIPTION ..................................................................................................22 PCI EXTENSION SIGNALS...........................................................................................................25 SUPPLY AND TEST SIGNAL DESCRIPTION ....................................................................................25 MEMORY MAP ..............................................................................................................26 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 5. INTRODUCTION ..........................................................................................................................26 GENERAL CONFIGURATION REGISTERS (0XX) .............................................................................26 RECEIVE PORT REGISTERS (1XX)...............................................................................................27 TRANSMIT PORT REGISTERS (2XX).............................................................................................27 CHANNELIZED PORT REGISTERS (3XX) .......................................................................................28 HDLC REGISTERS (4XX)............................................................................................................29 BERT REGISTERS (5XX)............................................................................................................29 RECEIVE DMA REGISTERS (7XX) ...............................................................................................29 TRANSMIT DMA REGISTERS (8XX) .............................................................................................30 FIFO REGISTERS (9XX) .............................................................................................................30 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX).............................................31 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX).............................................31 GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT...........................32 5.1 5.2 5.3 MASTER RESET AND ID REGISTER DESCRIPTION ........................................................................32 MASTER CONFIGURATION REGISTER DESCRIPTION ....................................................................32 STATUS AND INTERRUPT ............................................................................................................34 5.3.1 5.3.2 5.4 6. General Description of Operation ....................................................................................................... 34 Status and Interrupt Register Description ........................................................................................... 37 TEST REGISTER DESCRIPTION ...................................................................................................43 LAYER 1 ........................................................................................................................44 6.1 6.2 6.3 6.4 6.5 6.6 7. GENERAL DESCRIPTION .............................................................................................................44 PORT REGISTER DESCRIPTIONS .................................................................................................48 LAYER 1 CONFIGURATION REGISTER DESCRIPTION ....................................................................51 RECEIVE V.54 DETECTOR ..........................................................................................................56 BERT .......................................................................................................................................60 BERT REGISTER DESCRIPTION .................................................................................................61 HDLC .............................................................................................................................67 7.1 7.2 8. GENERAL DESCRIPTION .............................................................................................................67 HDLC REGISTER DESCRIPTION .................................................................................................69 FIFO ...............................................................................................................................74 8.1 GENERAL DESCRIPTION AND EXAMPLE .......................................................................................74 8.1.1 8.1.2 8.2 9. Receive High Watermark .................................................................................................................... 76 Transmit Low Watermark .................................................................................................................... 76 FIFO REGISTER DESCRIPTION ...................................................................................................76 DMA ...............................................................................................................................83 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 INTRODUCTION ..........................................................................................................................83 RECEIVE SIDE ...........................................................................................................................85 Overview ............................................................................................................................................. 85 Packet Descriptors .............................................................................................................................. 90 Free Queue ......................................................................................................................................... 92 Done Queue........................................................................................................................................ 97 2 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.2.5 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 10. DMA Channel Configuration RAM .................................................................................................... 102 TRANSMIT SIDE .......................................................................................................................105 Overview ........................................................................................................................................... 105 Packet Descriptors ............................................................................................................................ 114 Pending Queue ................................................................................................................................. 116 Done Queue...................................................................................................................................... 120 DMA Configuration RAM................................................................................................................... 125 PCI BUS.......................................................................................................................130 10.1 GENERAL DESCRIPTION OF OPERATION ...................................................................................130 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 10.2 PCI CONFIGURATION REGISTER DESCRIPTION .........................................................................137 10.2.1 10.2.2 10.2.3 10.2.4 11. PCI Read Cycle................................................................................................................................. 131 PCI Write Cycle................................................................................................................................. 132 PCI Bus Arbitration............................................................................................................................ 133 PCI Initiator Abort.............................................................................................................................. 133 PCI Target Retry ............................................................................................................................... 134 PCI Target Disconnect ...................................................................................................................... 134 PCI Target Abort ............................................................................................................................... 135 PCI Fast Back-to-Back...................................................................................................................... 136 Command Bits (PCMD0)................................................................................................................... 138 Status Bits (PCMD0) ......................................................................................................................... 139 Command Bits (PCMD1)................................................................................................................... 143 Status Bits (PCMD1) ......................................................................................................................... 144 LOCAL BUS ................................................................................................................147 11.1 GENERAL DESCRIPTION ...........................................................................................................147 11.1.1 11.1.2 11.2 11.3 12. 12.1 12.2 12.3 12.4 13. 14. 15. 15.1 16. 17. 17.1 17.2 17.3 17.4 PCI Bridge Mode............................................................................................................................... 149 Configuration Mode........................................................................................................................... 151 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION..................................................153 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION .............................155 JTAG............................................................................................................................163 JTAG DESCRIPTION ................................................................................................................163 TAP CONTROLLER STATE MACHINE DESCRIPTION ...................................................................164 INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................................166 TEST REGISTERS .....................................................................................................................167 AC CHARACTERISTICS .............................................................................................168 REVISION HISTORY ...................................................................................................176 PACKAGE INFORMATION .........................................................................................177 256-PIN PBGA (27MM X 27MM) ...............................................................................................177 THERMAL CHARACTERISTICS.................................................................................178 APPLICATIONS...........................................................................................................179 16 PORT T1 OR E1 WITH 256 HDLC CHANNEL SUPPORT.........................................................180 DUAL T3 WITH 256 HDLC CHANNEL SUPPORT ........................................................................181 SINGLE T3 WITH 512 HDLC CHANNEL SUPPORT......................................................................182 SINGLE T3 WITH 672 HDLC CHANNEL SUPPORT......................................................................183 3 of 183 DS31256 256-Channel, High-Throughput HDLC Controller LIST OF FIGURES Figure 2-1. Block Diagram .......................................................................................................................10 Figure 5-1. Status Register Block Diagram for SM and SV54 .................................................................36 Figure 6-1. Layer 1 Block Diagram ..........................................................................................................46 Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ................................................47 Figure 6-3. Layer 1 Register Set .............................................................................................................51 Figure 6-4. Port RAM Indirect Access .....................................................................................................53 Figure 6-5. Receive V.54 Host Algorithm ................................................................................................58 Figure 6-6. Receive V.54 State Machine .................................................................................................59 Figure 6-7. BERT Mux Diagram ..............................................................................................................60 Figure 6-8. BERT Register Set ................................................................................................................61 Figure 8-1. FIFO Example .......................................................................................................................75 Figure 9-1. Receive DMA Operation........................................................................................................88 Figure 9-2. Receive DMA Memory Organization .....................................................................................89 Figure 9-3. Receive Descriptor Example .................................................................................................90 Figure 9-4. Receive Packet Descriptors ..................................................................................................91 Figure 9-5. Receive Free-Queue Descriptor............................................................................................92 Figure 9-6. Receive Free-Queue Structure .............................................................................................94 Figure 9-7. Receive Done-Queue Descriptor ..........................................................................................97 Figure 9-8. Receive Done-Queue Structure ............................................................................................99 Figure 9-9. Receive DMA Configuration RAM .......................................................................................102 Figure 9-10. Transmit DMA Operation...................................................................................................108 Figure 9-11. Transmit DMA Memory Organization ................................................................................109 Figure 9-12. Transmit DMA Packet Handling ........................................................................................110 Figure 9-13. Transmit DMA Priority Packet Handling ............................................................................111 Figure 9-14. Transmit DMA Error Recovery Algorithm ..........................................................................113 Figure 9-15. Transmit Descriptor Example ............................................................................................114 Figure 9-16. Transmit Packet Descriptors .............................................................................................115 Figure 9-17. Transmit Pending-Queue Descriptor.................................................................................116 Figure 9-18. Transmit Pending-Queue Structure...................................................................................118 Figure 9-19. Transmit Done-Queue Descriptor .....................................................................................120 Figure 9-20. Transmit Done-Queue Structure .......................................................................................122 Figure 9-21. Transmit DMA Configuration RAM ....................................................................................125 Figure 10-1. PCI Configuration Memory Map ........................................................................................130 Figure 10-2. PCI Bus Read ...................................................................................................................131 Figure 10-3. PCI Bus Write....................................................................................................................132 Figure 10-4. PCI Bus Arbitration Signaling Protocol..............................................................................133 Figure 10-5. PCI Initiator Abort ..............................................................................................................133 Figure 10-6. PCI Target Retry ...............................................................................................................134 Figure 10-7. PCI Target Disconnect ......................................................................................................134 Figure 10-8. PCI Target Abort ...............................................................................................................135 Figure 10-9. PCI Fast Back-To-Back.....................................................................................................136 Figure 11-1. Bridge Mode ......................................................................................................................148 Figure 11-2. Bridge Mode with Arbitration Enabled ...............................................................................148 Figure 11-3. Configuration Mode ...........................................................................................................149 Figure 11-4. Local Bus Access Flowchart .............................................................................................152 Figure 11-5. 8-Bit Read Cycle ...............................................................................................................155 Figure 11-6. 16-Bit Write Cycle..............................................................................................................156 Figure 11-7. 8-Bit Read Cycle ...............................................................................................................157 Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle ...................................................................158 Figure 11-9. 8-Bit Read Cycle ...............................................................................................................159 Figure 11-10. 8-Bit Write Cycle..............................................................................................................160 Figure 11-11. 16-Bit Read Cycle ...........................................................................................................161 4 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-12. 8-Bit Write Cycle..............................................................................................................162 Figure 12-1. Block Diagram ...................................................................................................................163 Figure 12-2. TAP Controller State Machine...........................................................................................164 Figure 13-1. Layer 1 Port AC Timing Diagram ......................................................................................169 Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram....................................................170 Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams .......................................172 Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued) ....................173 Figure 13-5. PCI Bus Interface AC Timing Diagram..............................................................................174 Figure 13-6. JTAG Test Port Interface AC Timing Diagram ..................................................................175 Figure 16-1. 27mm x 27mm PBGA with 256 Balls, 2oz Planes, +70°C Ambient, Under Natural Convection at 3.0W.........................................................................................................................178 Figure 17-1. Application Drawing Key ...................................................................................................179 Figure 17-2. Single T1/E1 Line Connection...........................................................................................179 Figure 17-3. Quad T1/E1 Connection....................................................................................................180 Figure 17-4. 16-Port T1 Application.......................................................................................................180 Figure 17-5. Dual T3 Application ...........................................................................................................181 Figure 17-6. T3 Application (512 HDLC Channels) ...............................................................................182 Figure 17-7. T3 Application (672 HDLC Channels) ...............................................................................183 LIST OF TABLES Table 1-A. Data Sheet Definitions .............................................................................................................7 Table 2-A. Restrictions ............................................................................................................................11 Table 2-B. Initialization Steps ..................................................................................................................12 Table 2-C. Indirect Registers ...................................................................................................................12 Table 3-A. Signal Description ..................................................................................................................13 Table 3-B. RS Sampled Edge .................................................................................................................18 Table 3-C. TS Sampled Edge..................................................................................................................19 Table 4-A. Memory Map Organization.....................................................................................................26 Table 6-A. Channelized Port Modes........................................................................................................44 Table 6-B. Receive V.54 Search Routine ................................................................................................57 Table 7-A. Receive HDLC Packet Processing Outcomes .......................................................................67 Table 7-B. Receive HDLC Functions.......................................................................................................68 Table 7-C. Transmit HDLC Functions .....................................................................................................68 Table 8-A. FIFO Priority Algorithm Select ...............................................................................................74 Table 9-A. DMA Registers to be Configured by the Host on Power-Up ..................................................84 Table 9-B. Receive DMA Main Operational Areas ..................................................................................86 Table 9-C. Receive Descriptor Address Storage.....................................................................................90 Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation ..............................93 Table 9-E. Receive Free-Queue Internal Address Storage .....................................................................93 Table 9-F. Receive Done-Queue Internal Address Storage ....................................................................98 Table 9-G. Transmit DMA Main Operational Areas ...............................................................................106 Table 9-H. Done-Queue Error-Status Conditions ..................................................................................112 Table 9-I. Transmit Descriptor Address Storage ...................................................................................114 Table 9-J. Transmit Pending-Queue Internal Address Storage.............................................................117 Table 9-K. Transmit Done-Queue Internal Address Storage.................................................................121 Table 11-A. Local Bus Signals ..............................................................................................................147 Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting ...................................................................150 Table 11-C. Local Bus 16-Bit Width Address, LD, LBHE Setting ..........................................................150 Table 12-A. Instruction Codes ...............................................................................................................166 Table 16-A. Thermal Properties, Natural Convection ............................................................................178 Table 16-B. Thermal Properties vs. Airflow ...........................................................................................178 5 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 1. MAIN FEATURES Layer 1 Can simultaneously support up to 60 T1 or 64 E1 data streams, or two T3 data streams 16 independent physical ports capable of speeds up to 10MHz; three ports are also capable of speeds up to 52MHz Each port can be independently configured for either channelized or unchannelized operation Each physical channelized port can handle one, two, or four T1 or E1 data streams Supports N x 64kbps and N x 56kbps On-board V.54 loopback detector On-board BERT generation and detection Per DS0 channel loopback in both directions Unchannelized loopbacks in both directions HDLC 256 independent channels Up to 132Mbps throughput in both the receive and transmit directions Transparent mode Three fast HDLC controllers capable of operating up to 52 MHz Automatic flag detection and generation Shared opening and closing flag Interfame fill Zero stuffing and destuffing CRC16/32 checking and generation Abort detection and generation CRC error and long/short frame error detection Invert clock Invert data FIFO Large 16kB receive and 16kB transmit buffers maximize PCI bus efficiency Small block size of 16 Bytes allows maximum flexibility Programmable low and high watermarks Programmable HDLC channel priority setting DMA Efficient scatter-gather DMA minimizes system memory utilization Programmable small and large buffer sizes up to 8188 Bytes and algorithm select Descriptor bursting to conserve PCI bus bandwidth Identical receive and transmit descriptors minimize host processing in store-andforward Automatic channel disabling and enabling on transmit errors Receive packets are timestamped Transmit packet priority setting PCI Bus 32-bit, 33MHz Version 2.1 Compliant Contains extension signals that allow adoption to custom buses Can burst up to 256 32-bit words to maximize bus efficiency Local Bus Can be bridged from the PCI bus to simplify system design, or a configuration bus Can arbitrate for the bus when in bridge mode Configurable as 8 or 16 bits wide Supports a 1MB address space when in bridge mode Supports Intel and Motorola bus timing JTAG Test Access 3.3V low-power CMOS with 5V tolerant I/Os 256-pin plastic BGA package (27mm x 27mm) Governing Specifications The DS31256 fully meets the following specifications: • ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 • PCI Local Bus Specification V2.1 June 1, 1995 • ITU Q.921 March 1993 • ISO Standard 3309-1979 Data Communications–HDLC Procedures–Frame Structure 6 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 1-A. Data Sheet Definitions The following terms are used throughout this data sheet. Note: The DS31256’s ports are numbered 0 to 255; the HDLC channels are numbered 1 to 256. HDLC Channel 1 is always associated with Port 0, HDLC Channel 2 with Port 1, and so on. TERM BERT Descriptor Dword DMA FIFO HDLC Host n/a V.54 DEFINITION Bit Error-Rate Tester A message passed back and forth between the DMA and the host Double word; a 32-bit data entity Direct Memory Access First In, First Out. A temporary memory storage scheme. High-Level Data-Link Control The main controller that resides on the PCI Bus. Not assigned A pseudorandom pattern that controls loopbacks (see ANSI T1.403) 2. DETAILED DESCRIPTION This data sheet is broken into sections detailing each of the DS31256’s blocks. See Figure 2-1 for a block diagram. The Layer 1 block handles the physical input and output of serial data to and from the DS31256. The DS31256 can handle up to 60 T1 or 64 E1 data streams or two T3 data streams simultaneously. Each of the 16 physical ports can handle up to two or four T1 or E1 data streams. Section 17 details a few common applications for the DS31256. The Layer 1 block prepares the incoming data for the HDLC block and grooms data from the HDLC block for transmission. The block can perform both channelized and unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer 1 block that the host enables HDLC channels and assigns them to a particular port and/or DS0 channel(s). The host assigns HDLC channels through the R[n]CFG[j] and T[n]CFG[j] registers, which are described in Section 6.3. The Layer 1 block interfaces directly to the BERT block. The BERT block can generate and detect both pseudorandom and repeating bit patterns, and is used to test and stress data communication links. The HDLC block consists of two types of HDLC controllers. There are 16 slow HDLC engines (one for each port) that are capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. There are also three fast HDLC engines, which only reside on Ports 0, 1, and 2 and they are capable of operating at speeds up to 52Mbps. Via the RP[n]CR and TP[n]CR registers in the Layer 1 block, the host configures Ports 0, 1, and 2 to use either the slow or the fast HDLC engine. The HDLC engines perform all of the Layer 2 processing, including zero stuffing and destuffing, flag generation and detection, CRC generation and checking, abort generation and checking. In the receive path, the following process occurs. The HDLC engines collect the incoming data into 32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has no bearing on the priority of this data transfer. This situation is of no real concern however since the 7 of 183 DS31256 256-Channel, High-Throughput HDLC Controller DS31256 has been designed to handle up to 132Mbps in both the receive and transmit directions without any potential loss of data due to priority conflicts in the transfer of data from the HDLC engines to the FIFO and vice versa. The FIFO transfers data from the HDLC engines into the FIFO and checks to see if the FIFO has filled to beyond the programmable high watermark. If it has, then the FIFO signals to the DMA that data is ready to be burst read from the FIFO to the PCI Bus. The FIFO block controls the DMA block and it tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need to have data transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm, which allows the selection to be either round robin or priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the application, the selection of this algorithm can be quite important. The DS31256 cannot control when it will be granted PCI Bus access and if bus access is restricted, then the host may wish to prioritize which HDLC channels get top priority access to the PCI Bus when it is granted to the DS31256. When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO (even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC packet is not large enough to fill the FIFO to the high watermark, then the FIFO will not wait for more data to enter the FIFO, it will signal the DMA that an end-of-frame (EOF) was detected and that data is ready to be transferred from the FIFO to the PCI Bus by the DMA. In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC (Layer 2) engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority decoded with Port 0 generally getting the highest priority. Hence, if multiple ports are requesting packet data, the FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports before moving on to the higher numbered ports. Again there is no potential loss of data as long as the transmit throughput maximum of 132Mbps is not exceeded. When the FIFO detects that a HDLC engine needs data, it then transfers the data from the FIFO to the HDLC engines in 32-bit chunks. If the FIFO detects that the FIFO is below the low watermark, it then checks with the DMA to see if there is any data available for that HDLC Channel. The DMA will know if any data is available because the Host on the PCI Bus will have informed it of such via the pending-queue descriptor. When the DMA detects that data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need the DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the DMA will handle next via a host configurable algorithm, which allows the selection to be either round robin or priority, decoded (with HDLC Channel 1 generally getting the highest priority). When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled it to beyond the low watermark (or an EOF is reached), the FIFO will begin transferring 32-bit dwords to the HDLC engine. One of the unique attributes of the DS31256 is the structure of the DMA. The DMA has been optimized to maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. The DMA uses a flexible scatter/gather technique, which allows that packet data to be place anywhere within the 32-bit address space. The user has the option on the receive side of two different buffer sizes 8 of 183 DS31256 256-Channel, High-Throughput HDLC Controller which are called “large” and “small” but that can be set to any size up to 8188 bytes. The user has the option to store the incoming data either, only in the large buffers, only in the small buffers, or fill a small buffer first and then fill large buffers as needed. The varying buffer storage options allow the user to make the best use of the available memory and to be able to balance the tradeoff between latency and bus utilization. The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are handed back and forth from the DMA to the host. Since this descriptor transfer utilizes bus cycles, the DMA has been structured to minimize the number of transfers required. For example on the receive side, the DMA obtains descriptors from the host to know where in the 32-bit address space to place the incoming packet data. These descriptors are known as free-queue descriptors. When the DMA reads these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS31256 DMA does not need to use any more bus cycles to determine where to place the data. Other DMA architectures tend to use pointers, which require them to go back onto the bus to obtain more information and hence use more bus cycles. Another technique that the DMA uses to maximize bus utilization is the ability to burst read and write the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions which reduces the total number of bus cycles needed. The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions that reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus. The Local Bus block has two modes of operation. It can be used as either a bridge from the PCI Bus in which case it is a bus master or it can be used as a configuration bus in which case it is a bus slave. The bridge mode allows the host on the PCI Bus to access the local bus. The DS31256 maps data from the PCI Bus to the local bus. In the configuration mode, the local bus is used only to control and monitor the DS31256 while the HDLC packet data will still be transferred to the host through the PCI Bus. 9 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 2-1. Block Diagram RECEIVE DIRECTION TRANSMIT DIRECTION RC0 RD0 RS0 TC0 TD0 TS0 RC1 RD1 RS1 TC1 TD1 TS1 RC2 RD2 RS2 TC2 TD2 TS2 HDLC Block (Sec. 7) FIFO Block (Sec. 8) DMA Block (Sec. 9) (Sec. 10) Layer One Block PXAS PXDS PXBLAST (Sec. 6) RC15 RD15 RS15 TC15 TD15 TS15 Local Bus Block BERT (Sec. 6.5) Dallas Semiconductor DS31256 JTRST JTDI JTMS JTCLK JTDO PCI Block PCLK PRST PAD[31:0] PCBE[3:0] PPAR PFRAME PIRDY PTRDY PSTOP PIDSEL PDEVSEL PREQ PGNT PPERR PSERR JTAG Test Access (Sec. 12) (Sec. 11) LA[19:0] LD[15:0] LWR (LR/W) LRD (LDS) LIM LINT LRDY LMS LCS LHOLD (LBR) LHLDA (LBG) LBGACK LCLK LBHE Pin Names in ( ) are active when the device is in the MOT mode (i.e., LIM = 1) 10 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Restrictions In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions of the DS31256. Table 2-A lists all of the upper-bound maximum restrictions. Table 2-A. Restrictions ITEM Port Unchannelized Channelized Throughput HDLC RESTRICTION Maximum of 16 channelized and unchannelized physical ports Ports 0 to 2: Maximum data rate of 52Mbps Ports 3 to 15: Maximum data rate of 10Mbps Channelized and with byte interleave interfaces: 60 T1/64 E1 links Maximum receive: 132Mbps Maximum transmit: 132Mbps Maximum of 256 channels: If the fast HDLC engine on Port 0 is being used, then it must be HDLC Channel 1* If the fast HDLC engine on Port 1 is being used, then it must be HDLC Channel 2* If the fast HDLC engine on Port 2 is being used, then it must be HDLC Channel 3* *The 256 HDLC channels within the device are numbered 1 to 256. Internal Device Configuration Registers All internal device configuration registers (with the exception of the PCI configuration registers, which are 32-bit registers) are 16 bits wide and are not byte addressable. When the host on the PCI bus accesses these registers, the particular combination of byte enables (i.e., PCBE signals) is not important, but at least one of the byte enables must be asserted for a transaction to occur. All registers are read/write, unless otherwise noted. Not assigned (n/a) bits should be set to 0 when written to allow for future upgrades. These bits should be treated as having no meaning and could be either 0 or 1 when read. Initialization On a system reset (which can be invoked by either hardware action through the PRST signal or software action through the RST control bit in the master reset and ID register), all of the internal device configuration registers are set to 0 (0000h). The local bus bridge mode control register (LBBMC) is not affected by a software-invoked system reset; it is forced to all zeros only by a hardware reset. The internal registers that are accessed indirectly (these are listed as “indirect registers” in the data sheet and consist of the channelized port registers in the Layer 1 block, the DMA configuration RAMs, the HDLC configuration registers, and the FIFO registers) are not affected by a system reset, so they must be configured on power-up by the host to a proper state. Table 2-B lists the steps required to initialize the DS31256. Note: After device power-up and reset, it takes 0.625ms to get a port up and operating, therefore, the ports must wait a minimum of 0.625ms before packet data can be processed. 11 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 2-B. Initialization Steps INITIALIZATION STEP COMMENTS 1) Initialize the PCI configuration registers 2) Initialize all indirect registers 3) Configure the device for operation 4) Enable the HDLC channels 5) Load the DMA descriptors 6) Enable the DMAs 7) Enable DMA for each HDLC channel 8) Enable data transmission Achieved by asserting the PIDSEL signal. It is recommended that all of the indirect registers be set to 0000h (Table 2-C). Program all necessary registers, which include the Layer 1, HDLC, FIFO, and DMA registers. Done through the RCHEN and TCHEN bits in the R[n]CFG[j] and T[n]CFG[j] registers. Indicate to the DMA where packet data can be written and where pending data (if any) resides. Done through the RDE and TDE control bits in the master configuration (MC) register. Done through the channel-enable bit in the receive and transmit configuration RAM. Set TFDA1 bit in TPnCR registers. Table 2-C. Indirect Registers REGISTER Channelized Port Receive HDLC Channel Definition Transmit HDLC Channel Definition Receive DMA Configuration Transmit DMA Configuration Receive FIFO Staring Block Pointer Receive FIFO Block Pointer Receive FIFO High Watermark Transmit FIFO Staring Block Pointer Transmit FIFO Block Pointer Transmit FIFO Low Watermark NAME CP0RD to CP15RD RHCD THCD RDMAC TDMAC RFSBP RFBP RFHWM TFSBP TFBP TFLWM 12 of 183 NUMBER OF INDIRECT REGISTERS 6144 (16 Ports x 128 DS0 Channels x 3 Registers for each DS0 Channel) 256 (one for each HDLC Channel) 256 (one for each HDLC Channel) 1536 (one for each HDLC Channel) 3072 (one for each HDLC Channel) 256 (one for each HDLC Channel) 1024 (one for each FIFO Block) 256 (one for each HDLC Channel) 256 (one for each HDLC Channel) 1024 (one for each FIFO Block) 256 (one for each HDLC Channel) DS31256 256-Channel, High-Throughput HDLC Controller 3. SIGNAL DESCRIPTION 3.1 Overview/Signal List This section describes the input and output signals on the DS31256. Signal names follow a convention that is shown in the Signal Naming Convention table below. Table 3-A lists all the signals, their signal type, description, and pin location. Signal Naming Convention FIRST LETTER R T L J P SIGNAL CATEGORY Receive Serial Port Transmit Serial Port Local Bus JTAG Test Port PCI Bus SECTION 3.2 3.2 3.3 3.4 3.5 Table 3-A. Signal Description PIN NAME TYPE V19 U18 T17 W20 U19 G20 G19 F20 G18 F19 E20 G17 F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 L20 H20 J20 K19 V20 U20 T18 T19 JTCLK JTDI JTDO JTMS JTRST LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LBGACK LBHE LCLK LCS LD0 LD1 LD2 LD3 I I O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I/O I/O I/O I/O FUNCTION JTAG IEEE 1149.1 Test Serial Clock JTAG IEEE 1149.1 Test Serial Data Input JTAG IEEE 1149.1 Test Serial Data Output JTAG IEEE 1149.1 Test Mode Select JTAG IEEE 1149.1 Test Reset Local Bus Address Bit 0, LSB Local Bus Address Bit 1 Local Bus Address Bit 2 Local Bus Address Bit 3 Local Bus Address Bit 4 Local Bus Address Bit 5 Local Bus Address Bit 6 Local Bus Address Bit 7 Local Bus Address Bit 8 Local Bus Address Bit 9 Local Bus Address Bit 10 Local Bus Address Bit 11 Local Bus Address Bit 12 Local Bus Address Bit 13 Local Bus Address Bit 14 Local Bus Address Bit 15 Local Bus Address Bit 16 Local Bus Address Bit 17 Local Bus Address Bit 18 Local Bus Address Bit 19, MSB Local Bus Grant Acknowledge Local Bus Byte High Enable Local Bus Clock Local Bus Chip Select Local Bus Data Bit 0, LSB Local Bus Data Bit 1 Local Bus Data Bit 2 Local Bus Data Bit 3 13 of 183 DS31256 256-Channel, High-Throughput HDLC Controller PIN NAME TYPE FUNCTION T20 R18 P17 R19 R20 P18 P19 P20 N18 N19 N20 M17 L18 L19 M18 K20 M19 H18 K18 H19 A2, A8, A11, A19, B2, B18, J18, J19, K1–K3, L1–L3, M20, U14, W2, W9, Y1, Y19 V17 U16 Y18 W17 V16 Y17 W16 V15 W15 V14 Y15 W14 Y14 V13 W13 Y13 V9 U9 Y8 W8 V8 Y7 W7 V7 U7 V6 Y5 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LHLDA (LBG) LHOLD (LBR) LIM LINT LMS LRD (LDS) LRDY LWR (LR/W) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I I/O I I/O I I/O Local Bus Data Bit 4 Local Bus Data Bit 5 Local Bus Data Bit 6 Local Bus Data Bit 7 Local Bus Data Bit 8 Local Bus Data Bit 9 Local Bus Data Bit 10 Local Bus Data Bit 11 Local Bus Data Bit 12 Local Bus Data Bit 13 Local Bus Data Bit 14 Local Bus Data Bit 15, MSB Local Bus Hold Acknowledge (Local Bus Grant) Local Bus Hold (Local Bus Request) Local Bus Intel/Motorola Bus Select Local Bus Interrupt Local Bus Mode Select Local Bus Read Enable (Local Bus Data Strobe) Local Bus PCI Bridge Ready Local Bus Write Enable (Local Bus Read/Write Select) N.C. — No Connect. Do not connect any signal to this pin. PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PCI Multiplexed Address and Data Bit 0 PCI Multiplexed Address and Data Bit 1 PCI Multiplexed Address and Data Bit 2 PCI Multiplexed Address and Data Bit 3 PCI Multiplexed Address and Data Bit 4 PCI Multiplexed Address and Data Bit 5 PCI Multiplexed Address and Data Bit 6 PCI Multiplexed Address and Data Bit 7 PCI Multiplexed Address and Data Bit 8 PCI Multiplexed Address and Data Bit 9 PCI Multiplexed Address and Data Bit 10 PCI Multiplexed Address and Data Bit 11 PCI Multiplexed Address and Data Bit 12 PCI Multiplexed Address and Data Bit 13 PCI Multiplexed Address and Data Bit 14 PCI Multiplexed Address and Data Bit 15 PCI Multiplexed Address and Data Bit 16 PCI Multiplexed Address and Data Bit 17 PCI Multiplexed Address and Data Bit 18 PCI Multiplexed Address and Data Bit 19 PCI Multiplexed Address and Data Bit 20 PCI Multiplexed Address and Data Bit 21 PCI Multiplexed Address and Data Bit 22 PCI Multiplexed Address and Data Bit 23 PCI Multiplexed Address and Data Bit 24 PCI Multiplexed Address and Data Bit 25 PCI Multiplexed Address and Data Bit 26 14 of 183 DS31256 256-Channel, High-Throughput HDLC Controller PIN NAME TYPE FUNCTION W5 V5 Y4 Y3 U5 Y16 V12 Y9 W6 Y2 Y11 W10 W4 Y6 W18 V10 W12 V11 V4 W3 Y12 W11 Y10 V18 Y20 W19 B1 D1 F2 H2 M1 P1 P4 V1 B17 B16 C14 D12 A10 B8 B6 C5 D2 E2 G3 J4 M3 R1 T2 U3 D16 C15 PAD27 PAD28 PAD29 PAD30 PAD31 PCBE0 PCBE1 PCBE2 PCBE3 PCLK PDEVSEL PFRAME PGNT PIDSEL PINT PIRDY PPAR PPERR PREQ PRST PSERR PSTOP PTRDY PXAS PXBLAST PXDS RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I O I/O I/O I/O O I O I/O I/O O O O I I I I I I I I I I I I I I I I I I I I I I I I I I PCI Multiplexed Address and Data Bit 27 PCI Multiplexed Address and Data Bit 28 PCI Multiplexed Address and Data Bit 29 PCI Multiplexed Address and Data Bit 30 PCI Multiplexed Address and Data Bit 31 PCI Bus Command/Byte Enable Bit 0 PCI Bus Command/Byte Enable Bit 1 PCI Bus Command/Byte Enable Bit 2 PCI Bus Command/Byte Enable Bit 3 PCI and System Clock. A 25MHz to 33MHz clock is applied here. PCI Device Select PCI Cycle Frame PCI Bus Grant PCI Initialization Device Select PCI Interrupt PCI Initiator Ready PCI Bus Parity PCI Parity Error PCI Bus Request PCI Reset PCI System Error PCI Stop PCI Target Ready PCI Extension Signal: Address Strobe PCI Extension Signal: Burst Last PCI Extension Signal: Data Strobe Receive Serial Clock for Port 0 Receive Serial Clock for Port 1 Receive Serial Clock for Port 2 Receive Serial Clock for Port 3 Receive Serial Clock for Port 4 Receive Serial Clock for Port 5 Receive Serial Clock for Port 6 Receive Serial Clock for Port 7 Receive Serial Clock for Port 8 Receive Serial Clock for Port 9 Receive Serial Clock for Port 10 Receive Serial Clock for Port 11 Receive Serial Clock for Port 12 Receive Serial Clock for Port 13 Receive Serial Clock for Port 14 Receive Serial Clock for Port 15 Receive Serial Data for Port 0 Receive Serial Data for Port 1 Receive Serial Data for Port 2 Receive Serial Data for Port 3 Receive Serial Data for Port 4 Receive Serial Data for Port 5 Receive Serial Data for Port 6 Receive Serial Data for Port 7 Receive Serial Data for Port 8 Receive Serial Data for Port 9 15 of 183 DS31256 256-Channel, High-Throughput HDLC Controller PIN NAME TYPE A14 B12 C10 A7 D7 A3 C2 E3 F1 H1 M2 P2 R3 T4 C17 A16 B14 C12 B10 C8 A5 B4 D3 E1 G2 J3 N1 P3 U1 V2 A18 D14 C13 A12 A9 B7 C6 D5 C1 G4 H3 J1 N3 T1 U2 V3 C16 A15 A13 C11 C9 C7 RD10 RD11 RD12 RD13 RD14 RD15 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 TD10 TD11 TD12 TD13 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O FUNCTION Receive Serial Data for Port 10 Receive Serial Data for Port 11 Receive Serial Data for Port 12 Receive Serial Data for Port 13 Receive Serial Data for Port 14 Receive Serial Data for Port 15 Receive Serial Sync for Port 0 Receive Serial Sync for Port 1 Receive Serial Sync for Port 2 Receive Serial Sync for Port 3 Receive Serial Sync for Port 4 Receive Serial Sync for Port 5 Receive Serial Sync for Port 6 Receive Serial Sync for Port 7 Receive Serial Sync for Port 8 Receive Serial Sync for Port 9 Receive Serial Sync for Port 10 Receive Serial Sync for Port 11 Receive Serial Sync for Port 12 Receive Serial Sync for Port 13 Receive Serial Sync for Port 14 Receive Serial Sync for Port 15 Transmit Serial Clock for Port 0 Transmit Serial Clock for Port 1 Transmit Serial Clock for Port 2 Transmit Serial Clock for Port 3 Transmit Serial Clock for Port 4 Transmit Serial Clock for Port 5 Transmit Serial Clock for Port 6 Transmit Serial Clock for Port 7 Transmit Serial Clock for Port 8 Transmit Serial Clock for Port 9 Transmit Serial Clock for Port 10 Transmit Serial Clock for Port 11 Transmit Serial Clock for Port 12 Transmit Serial Clock for Port 13 Transmit Serial Clock for Port 14 Transmit Serial Clock for Port 15 Transmit Serial Data for Port 0 Transmit Serial Data for Port 1 Transmit Serial Data for Port 2 Transmit Serial Data for Port 3 Transmit Serial Data for Port 4 Transmit Serial Data for Port 5 Transmit Serial Data for Port 6 Transmit Serial Data for Port 7 Transmit Serial Data for Port 8 Transmit Serial Data for Port 9 Transmit Serial Data for Port 10 Transmit Serial Data for Port 11 Transmit Serial Data for Port 12 Transmit Serial Data for Port 13 16 of 183 DS31256 256-Channel, High-Throughput HDLC Controller PIN NAME TYPE FUNCTION A4 B3 C3 E4 F3 G1 J2 N2 R2 T3 W1 A17 B15 B13 B11 B9 A6 B5 C4 D6, D10, D11, D15, F4, F17, K4, K17, L4, L17, R4, R17, U6, U10, U11, U15 A1, D4, D8, D9, D13, D17, H4, H17, J17, M4, N4, N17, U4, U8, U12, U13, U17 TD14 TD15 TEST TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 O O I I I I I I I I I I I I I I I I I Transmit Serial Data for Port 14 Transmit Serial Data for Port 15 Test. Factory tests signal; leave open circuited Transmit Serial Sync for Port 0 Transmit Serial Sync for Port 1 Transmit Serial Sync for Port 2 Transmit Serial Sync for Port 3 Transmit Serial Sync for Port 4 Transmit Serial Sync for Port 5 Transmit Serial Sync for Port 6 Transmit Serial Sync for Port 7 Transmit Serial Sync for Port 8 Transmit Serial Sync for Port 9 Transmit Serial Sync for Port 10 Transmit Serial Sync for Port 11 Transmit Serial Sync for Port 12 Transmit Serial Sync for Port 13 Transmit Serial Sync for Port 14 Transmit Serial Sync for Port 15 VDD — Positive Supply. 3.3V (±10%) VSS — Ground Reference 17 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 3.2 Serial Port Interface Signal Description Signal Name: RC0 to RC15 Signal Description: Receive Serial Clock Signal Type: Input Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of RC. This is programmable on a per port basis. RC0–RC2 can operate at speeds up to 52MHz. RC3–RC15 can operate at speeds up to 10MHz. Unused signals should be wired low. Signal Name: RD0 to RD15 Signal Description: Receive Serial Data Signal Type: Input Can be sampled either on the rising edge of RC (normal clock mode) or the falling edge of RC (inverted clock mode). Unused signals should be wired low. Signal Name: RS0 to RS15 Signal Description: Receive Serial Data Synchronization Pulse Signal Type: Input This is a one-RC clock-wide synchronization pulse that can be applied to the DS31256 to force byte/frame alignment. The applied sync-signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC (Table 3-B). The applied sync pulse can be during the first RC clock period of a 193/256/512/1024-bit frame or it can be applied 1/2, 1, or 2 RC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) RC clocks. It is acceptable to pulse the RS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low. Table 3-B. RS Sampled Edge SIGNAL NORMAL RC CLOCK MODE INVERTED RC CLOCK MODE 0 RC Clock Early Mode 1/2 RC Clock Early Mode 1 RC Clock Early Mode 2 RC Clock Early Mode Falling Edge Rising Edge Falling Edge Falling Edge Rising Edge Falling Edge Rising Edge Rising Edge Signal Name: TC0 to TC15 Signal Description: Transmit Serial Clock Signal Type: Input Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of TC. This is programmable on a per port basis. TC0 and TC1 can operate at speeds up to 52MHz. TC2– TC15 can operate at speeds up to 10MHz. Unused signals should be wired low. Signal Name: TD0 to TD15 Signal Description: Transmit Serial Data Signal Type: Output This can be updated either on the rising edge of TC (normal clock mode) or the falling edge of TC (inverted clock mode). Data can be forced high. 18 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Signal Name: TS0 to TS15 Signal Description: Transmit Serial Data Synchronization Pulse Signal Type: Input This is a one-TC clock-wide synchronization pulse that can be applied to the DS31256 to force byte/frame alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The TS signal can be sampled either on the falling edge or on rising edge of TC (Table 3-C). The applied sync pulse can be during the first TC clock period of a 193/256/512/1024-bit frame or it can be applied 1/2, 1, or 2 TC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) TC clocks. It is acceptable to pulse the TS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by counting TC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low. Table 3-C. TS Sampled Edge SIGNAL 0 TC Clock Early Mode 1/2 TC Clock Early Mode 1 TC Clock Early Mode 2 TC Clock Early Mode NORMAL TC CLOCK MODE INVERTED TC CLOCK MODE Falling Edge Rising Edge Falling Edge Falling Edge Rising Edge Falling Edge Rising Edge Rising Edge 3.3 Local Bus Signal Description Signal Name: LMS Signal Description: Local Bus Mode Select Signal Type: Input This signal should be connected low when the device operates with no local bus access or if the local bus is used as a bridge from the PCI bus. This signal should be connected high if the local bus is to be used by an external host to configure the device. 0 = local bus is in the PCI bridge mode (master) 1 = local bus is in the configuration mode (slave) Signal Name: LIM Signal Description: Local Bus Intel/Motorola Bus Select Signal Type: Input The signal determines whether the local bus operates in the Intel mode (LIM = 0) or the Motorola mode (LIM = 1). The signal names in parentheses are operational when the device is in the Motorola mode. 0 = local bus is in the Intel mode 1 = local bus is in the Motorola mode Signal Name: LD0 to LD15 Signal Description: Local Bus Nonmultiplexed Data Bus Signal Type: Input/Output (tri-state capable) In PCI bridge mode (LMS = 0), data from/to the PCI bus can be transferred to/from these signals. When writing data to the local bus, these signals are outputs and updated on the rising edge of LCLK. When reading data from the local bus, these signals are inputs, which are sampled on the rising edge of LCLK. Depending on the assertion of the PCI byte enables (PCBE0 to PCBE3) and the local bus-width (LBW) control bit in the local bus bridge mode control register (LBBMC), this data bus uses all 16 bits (LD[15:0]) or just the lower 8 bits (LD[7:0]) or the upper 8 bits (LD[15:8]). If the upper LD bits (LD[15:8]) are used, then the local bus high-enable signal (LBHE) is asserted during the bus transaction. If the local bus is not currently involved in a bus transaction, all 16 signals are tri-stated. When reading data from the local bus, these signals are outputs that are updated on the rising edge of LCLK. When writing data to the local bus, these signals become inputs, which are sampled on the rising edge of LCLK. In configuration mode (LMS = 1), the external host configures the device and obtains real-time status 19 of 183 DS31256 256-Channel, High-Throughput HDLC Controller information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is not available). Signal Name: LA0 to LA19 Signal Description: Local Bus Nonmultiplexed Address Bus Signal Type: Input/Output (tri-state capable) In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to indicate which address to be written to or read from. These signals are tri-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. In configuration mode (LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active. The upper four (LA[19:16]) are ignored and should be connected low. Signal Name: LWR (LR/W) Signal Description: Local Bus Write Enable (Local Bus Read/Write Select) Signal Type: Input/Output (tri-state capable) In the PCI bridge mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be written to the local bus. In Motorola mode (LIM = 1), this signal determines whether a read or write is to occur. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In Intel mode (LIM = 0), it determines when data is to be written to the device. In Motorola mode (LIM = 1), this signal determines whether a read or write is to occur. Signal Name: LRD (LDS) Signal Description: Local Bus Read Enable (Local Bus Data Strobe) Signal Type: Input/Output (tri-state capable) In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising edge is used to write data into the slave device. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In Intel mode (LIM = 0), it determines when data is to be read from the device. In Motorola mode (LIM = 1), the rising edge writes data into the device. Signal Name: LINT Signal Description: Local Bus Interrupt Signal Type: Input/Output (open drain) In the PCI bridge mode (LMS = 0), this active-low signal is an input that is sampled on the rising edge of LCLK. If asserted and unmasked, this signal causes an interrupt at the PCI bus through the PINTA signal. If not used in PCI bridge mode, this signal should be connected high. In configuration mode (LMS = 1), this signal is an opendrain output that is forced low if one or more unmasked interrupt sources within the device is active. The signal remains low until either the interrupt is serviced or masked. Signal Name: LRDY Signal Description: Local Bus PCI Bridge Ready (PCI Bridge Mode Only) Signal Type: Input This active-low signal is sampled on the rising edge of LCLK to determine when a bus transaction is complete. This signal is only examined when a bus transaction is taking place. This signal is ignored when the local bus is in configuration mode (LMS = 1) and should be connected high. 20 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Signal Name: LHLDA (LBG) Signal Description: Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only) Signal Type: Input This input signal is sampled on the rising edge of LCLK to determine when the device has been granted access to the bus. In Intel mode (LIM = 0), this is an active-high signal; in Motorola mode (LIM = 1) this is an active-low signal. This signal is ignored and should be connected high when the local bus is in configuration mode (LMS = 1). Also, in PCI bridge mode (LMS = 0), this signal should be wired deasserted when the local bus arbitration is disabled through the LBBMC register. Signal Name: LHOLD (LBR) Signal Description: Local Bus Hold (Local Bus Request) (PCI Bridge Mode Only) Signal Type: Output This signal is asserted when the DS31256 is attempting to control the local bus. In Intel mode (LIM = 0), this signal is an active-high signal; in Motorola mode (LIM = 1) this signal is an active-low signal. It is deasserted concurrently with LBGACK. This signal is tri-stated when the local bus is in configuration mode (LMS = 1) and also in PCI bridge mode (LMS = 0) when the local bus arbitration is disabled through the LBBMC register. Signal Name: LBGACK Signal Description: Local Bus Grant Acknowledge (PCI Bridge Mode Only) Signal Type: Output (tri-state capable) This active-low signal is asserted when the local bus hold-acknowledge/bus grant signal (LHLDA/LBG) has been detected and continues its assertion for a programmable (32 to 1,048,576) number of LCLKs, based on the local bus arbitration timer setting in the LBBMC register. This signal is tri-stated when the local bus is in configuration mode (LMS = 1). Signal Name: LBHE Signal Description: Local Bus Byte-High Enable (PCI Bridge Mode Only) Signal Type: Output (tri-state capable) This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if only the lower 8 bits (LD[7:0)] are active. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal remains in tri-state when the local bus is not involved in a bus transaction and is in configuration mode (LMS = 1). Signal Name: LCLK Signal Description: Local Bus Clock (PCI Bridge Mode Only) Signal Type: Output (tri-state capable) This signal outputs a buffered version of the clock applied at the PCLK input. All local bus signals are generated and sampled from this clock. This output is tri-stated when the local bus is in configuration mode (LMS = 1). It can be disabled in the PCI bridge mode through the LBBMC register. Signal Name: LCS Signal Description: Local Bus Chip Select (Configuration Mode Only) Signal Type: Input This active-low signal must be asserted for the device to accept a read or write command from an external host. This signal is ignored in the PCI bridge mode (LMS = 0) and should be connected high. 21 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 3.4 JTAG Signal Description Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If unused, this signal should be pulled high. Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial-Data Input Signal Type: Input (with internal 10kΩ pullup) Test instructions and data are clocked into this signal on the rising edge of JTCLK. If unused, this signal should be pulled high. This signal has an internal pullup. Signal Name: JTDO Signal Description: JTAG IEEE 1149.1 Test Serial-Data Output Signal Type: Output Test instructions are clocked out of this signal on the falling edge of JTCLK. If unused, this signal should be left open circuited. Signal Name: JTRST Signal Description: JTAG IEEE 1149.1 Test Reset Signal Type: Input (with internal 10kΩ pullup) This signal is used to asynchronously reset the test access port controller. At power-up, JTRST must be set low and then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation. If boundary scan is not used, this signal should be held low. This signal has an internal pullup. Signal Name: JTMS Signal Description: JTAG IEEE 1149.1 Test Mode Select Signal Type: Input (with internal 10kΩ pullup) This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. If unused, this signal should be pulled high. This signal has an internal pullup. 3.5 PCI Bus Signal Description Signal Name: PCLK Signal Description: PCI and System Clock Signal Type: Input (Schmitt triggered) This clock input provides timing for the PCI bus and the device’s internal logic. A 25MHz to 33MHz clock with a nominal 50% duty cycle should be applied here. Signal Name: PRST Signal Description: PCI Reset Signal Type: Input This active-low input is used to force an asynchronous reset to both the PCI bus and the device’s internal logic. When forced low, this input forces all the internal logic of the device into its default state, forces the PCI outputs into tri-state, and forces the TD[15:0] output port-data signals high. Signal Name: PAD0 to PAD31 Signal Description: PCI Address and Data Multiplexed Bus Signal Type: Input/Output (tri-state capable) Both address and data information are multiplexed onto these signals. Each bus transaction consists of an address phase followed by one or more data phases. Data can be either read or written in bursts. The address is transferred during the first clock cycle of a bus transaction. When the Little Endian format is selected, PAD[31:24] is the MSB of the DWORD; when Big Endian is selected, PAD[7:0] contains the MSB. When the device is an initiator, 22 of 183 DS31256 256-Channel, High-Throughput HDLC Controller these signals are always outputs during the address phase. They remain outputs for the data phase(s) in a write transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs during the address phase. They remain inputs for the data phase(s) in a read transaction and become outputs for a write transaction. When the device is not involved in a bus transaction, these signals remain tri-stated. These signals are always updated and sampled on the rising edge of PCLK. Signal Name: PCBE0/PCBE1/PCBE2/PCBE3 Signal Description: PCI Bus Command and Byte Enable Signal Type: Input/Output (tri-state capable) Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals define the bus command. During the data phase, these signals are used as byte enables. During data phases, PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is high, the associated byte is invalid; when low, the associated byte is valid. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, these signals are tri-stated. Signal Name: PPAR Signal Description: PCI Bus Parity Signal Type: Input/Output (tri-state capable) This signal provides information on even parity across both the PAD address/data bus and the PCBE bus command/byte enable bus. When the device is an initiator, this signal is an output for writes and an input for reads. It is updated on the rising edge of PCLK. When the device is a target, this signal is an input for writes and an output for reads. It is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PPAR is tri-stated. Signal Name: PFRAME Signal Description: PCI Cycle Frame Signal Type: Input/Output (tri-state capable) This active-low signal is created by the bus initiator and is used to indicate the beginning and duration of a bus transaction. PFRAME is asserted by the initiator during the first clock cycle of a bus transaction and remains asserted until the last data phase of a bus transaction. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PFRAME is tri-stated. Signal Name: PIRDY Signal Description: PCI Initiator Ready Signal Type: Input/Output (tri-state capable) The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue sending/accepting data. This signal handshakes with the PTRDY signal during a bus transaction to control the rate at which data transfers across the bus. During a bus transaction, PIRDY is deasserted when the initiator cannot temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PIRDY is tri-stated. Signal Name: PTRDY Signal Description: PCI Target Ready Signal Type: Input/Output (tri-state capable) The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue sending/accepting data. This signal handshakes with the PIRDY signal during a bus transaction to control the rate at which data transfers across the bus. During a bus transaction, PTRDY is deasserted when the target cannot temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PTRDY is tri-stated. 23 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Signal Name: PSTOP Signal Description: PCI Stop Signal Type: Input/Output (tri-state capable) The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PSTOP is tri-stated. Signal Name: PIDSEL Signal Description: PCI Initialization Device Select Signal Type: Input This input signal is used as a chip select during configuration read and write transactions. This signal is disabled when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device allows access to the PCI configuration registers, and the PDEVSEL signal is asserted during the PCLK cycle. PIDSEL is sampled on the rising edge of PCLK. Signal Name: PDEVSEL Signal Description: PCI Device Select Signal Type: Input/Output (tri-state capable) The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PDEVSEL is tri-stated. Signal Name: PREQ Signal Description: PCI Bus Request Signal Type: Output (tri-state capable) The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is updated on the rising edge of PCLK. Signal Name: PGNT Signal Description: PCI Bus Grant Signal Type: Input The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus has been granted. The device samples PGNT on the rising edge of PCLK and, if detected, initiates a bus transaction when it has sensed that the PFRAME signal has been deasserted. Signal Name: PPERR Signal Description: PCI Parity Error Signal Type: Input/Output (tri-state capable) This active-low signal reports parity errors. PPERR can be enabled and disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK. Signal Name: PSERR Signal Description: PCI System Error Signal Type: Output (open drain) This active-low signal reports any parity errors that occur during the address phase. PSERR can be enabled and disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK. 24 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Signal Name: PINTA Signal Description: PCI Interrupt Signal Type: Output (open drain) This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This signal is updated on the rising edge of PCLK. 3.6 PCI Extension Signals These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the DS31256 is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a non-PCI environment like an Intel i960-type bus. Signal Name: PXAS Signal Description: PCI Extension Address Strobe Signal Type: Output This active-low signal is asserted low on the same clock edge as PFRAME and is deasserted after one clock period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK. Signal Name: PXDS Signal Description: PCI Extension Data Strobe Signal Type: Output This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK. Signal Name: PXBLAST Signal Description: PCI Extension Burst Last Signal Type: Output This active-low signal is asserted on the same clock edge as PFRAME is deasserted and is deasserted on the same clock edge as PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK. 3.7 Supply and Test Signal Description Signal Name: TEST Signal Description: Factory Test Input Signal Type: Input (with internal 10kΩ pullup) This input should be left open-circuited by the user. Signal Name: VDD Signal Description: Positive Supply Signal Type: n/a 3.3V (±10%). All VDD signals should be connected together. Signal Name: VSS Signal Description: Ground Reference Signal Type: n/a All VSS signals should be connected to the local ground plane. 25 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 4. MEMORY MAP 4.1 Introduction All addresses within the memory map are on dword boundaries, even though all internal device configuration registers are only one word (16 bits) wide. The memory map consumes an address range of 4kB (12 bits). When the PCI bus is the host (i.e., the local bus is in bridge mode), the actual 32-bit PCI bus addresses of the internal device configuration registers are obtained by adding the DC base address value in the PCI device-configuration memory-base address register (Section 10.2) to the offset listed in Sections 4.1 to 4.10. When an external host is configuring the device through the local bus (i.e., the local bus is in the configuration mode), the offset is 0h and the host on the local bus uses the 16-bit addresses listed in Sections 4.2 to 4.10. Table 4-A. Memory Map Organization REGISTER General Configuration Registers Receive Port Registers Transmit Port Registers Channelized Port Registers HDLC Registers BERT Registers Receive DMA Registers Transmit DMA Registers FIFO Registers PCI Configuration Registers for Function 0 PCI Configuration Registers for Function 1 PCI HOST [OFFSET FROM DC BASE] (0x000) (0x1xx) (0x2xx) (0x3xx) (0x4xx) (0x5xx) (0x7xx) (0x8xx) (0x9xx) (PIDSEL) (PIDSEL) LOCAL BUS HOST (16-BIT ADDRESS) (00xx) (01xx) (02xx) (03xx) (04xx) (05xx) (07xx) (08xx) (09xx) (0Axx) (0Bxx) SECTION 4.2 4.3 4.4 4.6 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.2 General Configuration Registers (0xx) OFFSET/ ADDRESS 0000 0010 0020 0024 0028 002C 0030 0034 0040 0050 NAME MRID MC SM ISM SDMA ISDMA SV54 ISV54 LBBMC TEST REGISTER Master Reset and ID Register Master Configuration Master Status Register Interrupt Mask Register for SM Status Register for DMA Interrupt Mask Register for SDMA Status Register for V.54 Loopback Detector Interrupt Mask Register for SV.54 Local Bus Bridge Mode Control Register Test Register 26 of 183 SECTION 5.1 5.2 5.3.2 5.3.2 5.3.2 5.3.2 5.3.2 5.3.2 11.2 5.4 DS31256 256-Channel, High-Throughput HDLC Controller 4.3 Receive Port Registers (1xx) OFFSET/ ADDRESS 0100 0104 0108 010C 0110 0114 0118 011C 0120 0124 0128 012C 0130 0134 0138 013C NAME RP0CR RP1CR RP2CR RP3CR RP4CR RP5CR RP6CR RP7CR RP8CR RP9CR RP10CR RP11CR RP12CR RP13CR RP14CR RP15CR REGISTER Receive Port 0 Control Register Receive Port 1 Control Register Receive Port 2 Control Register Receive Port 3 Control Register Receive Port 4 Control Register Receive Port 5 Control Register Receive Port 6 Control Register Receive Port 7 Control Register Receive Port 8 Control Register Receive Port 9 Control Register Receive Port 10 Control Register Receive Port 11 Control Register Receive Port 12 Control Register Receive Port 13 Control Register Receive Port 14 Control Register Receive Port 15 Control Register SECTION 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 4.4 Transmit Port Registers (2xx) OFFSET/ ADDRESS 0200 0204 0208 020C 0210 0214 0218 021C 0220 0224 0228 022C 0230 0234 0238 023C NAME TP0CR TP1CR TP2CR TP3CR TP4CR TP5CR TP6CR TP7CR TP8CR TP9CR TP10CR TP11CR TP12CR TP13CR TP14CR TP15CR REGISTER Transmit Port 0 Control Register Transmit Port 1 Control Register Transmit Port 2 Control Register Transmit Port 3 Control Register Transmit Port 4 Control Register Transmit Port 5 Control Register Transmit Port 6 Control Register Transmit Port 7 Control Register Transmit Port 8 Control Register Transmit Port 9 Control Register Transmit Port 10 Control Register Transmit Port 11 Control Register Transmit Port 12 Control Register Transmit Port 13 Control Register Transmit Port 14 Control Register Transmit Port 15 Control Register 27 of 183 SECTION 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 6.2 DS31256 256-Channel, High-Throughput HDLC Controller 4.5 Channelized Port Registers (3xx) OFFSET/ ADDRESS 0300 0304 0308 030C 0310 0314 0318 031C 0320 0324 0328 032C 0330 0334 0338 033C 0340 0344 0348 034C 0350 0354 0358 035C 0360 0364 0368 036C 0370 0374 0378 037C NAME CP0RDIS CP0RD CP1RDIS CP1RD CP2RDIS CP2RD CP3RDIS CP3RD CP4RDIS CP4RD CP5RDIS CP5RD CP6RDIS CP6RD CP7RDIS CP7RD CP8RDIS CP8RD CP9RDIS CP9RD CP10RDIS CP10RD CP11RDIS CP11RD CP12RDIS CP12RD CP13RDIS CP13RD CP14RDIS CP14RD CP15RDIS CP15RD REGISTER Channelized Port 0 Register Data Indirect Select Channelized Port 0 Register Data Channelized Port 1 Register Data Indirect Select Channelized Port 1 Register Data Channelized Port 2 Register Data Indirect Select Channelized Port 2 Register Data Channelized Port 3 Register Data Indirect Select Channelized Port 3 Register Data Channelized Port 4 Register Data Indirect Select Channelized Port 4 Register Data Channelized Port 5 Register Data Indirect Select Channelized Port 5 Register Data Channelized Port 6 Register Data Indirect Select Channelized Port 6 Register Data Channelized Port 7 Register Data Indirect Select Channelized Port 7 Register Data Channelized Port 8 Register Data Indirect Select Channelized Port 8 Register Data Channelized Port 9 Register Data Indirect Select Channelized Port 9 Register Data. Channelized Port 10 Register Data Indirect Select. Channelized Port 10 Register Data. Channelized Port 11 Register Data Indirect Select. Channelized Port 11 Register Data Channelized Port 12 Register Data Indirect Select Channelized Port 12 Register Data Channelized Port 13 Register Data Indirect Select Channelized Port 13 Register Data Channelized Port 14 Register Data Indirect Select Channelized Port 14 Register Data Channelized Port 15 Register Data Indirect Select Channelized Port 15 Register Data 28 of 183 SECTION 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 6.3 DS31256 256-Channel, High-Throughput HDLC Controller 4.6 HDLC Registers (4xx) OFFSET/ ADDRESS 0400 0404 0410 0480 0484 NAME RHCDIS RHCD RHPL THCDIS THCD REGISTER Receive HDLC Channel Definition Indirect Select Receive HDLC Channel Definition Receive HDLC maximum Packet Length. One per device. Transmit HDLC Channel Definition Indirect Select Transmit HDLC Channel Definition SECTION 7.2 7.2 7.2 7.2 7.2 4.7 BERT Registers (5xx) OFFSET/ ADDRESS 0500 0504 0508 050C 0510 0514 0518 051C NAME BERTC0 BERTC1 BERTRP0 BERTRP1 BERTBC0 BERTBC1 BERTEC0 BERTEC1 REGISTER BERT Control 0 BERT Control 1 BERT Repetitive Pattern Set 0 (lower word) BERT Repetitive Pattern Set 1 (upper word) BERT Bit Counter 0 (lower word) BERT Bit Counter 1 (upper word) BERT Error Counter 0 (lower word) BERT Error Counter 1 (upper word) SECTION 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 4.8 Receive DMA Registers (7xx) OFFSET/ ADDRESS 0700 0704 0708 070C 0710 0714 0718 071C 0730 0734 0738 073C 0740 0744 0750 0754 0770 0774 0780 0790 0794 NAME RFQBA0 RFQBA1 RFQEA RFQSBSA RFQLBWP RFQSBWP RFQLBRP RFQSBRP RDQBA0 RDQBA1 RDQEA RDQRP RDQWP RDQFFT RDBA0 RDBA1 RDMACIS RDMAC RDMAQ RLBS RSBS REGISTER Receive Free-Queue Base Address 0 (lower word) Receive Free-Queue Base Address 1 (upper word) Receive Free-Queue End Address Receive Free-Queue Small Buffer Start Address Receive Free-Queue Large Buffer Host Write Pointer Receive Free-Queue Small Buffer Host Write Pointer Receive Free-Queue Large Buffer DMA Read Pointer Receive Free-Queue Small Buffer DMA Read Pointer Receive Done-Queue Base Address 0 (lower word) Receive Done-Queue Base Address 1 (upper word) Receive Done-Queue End Address Receive Done-Queue Host Read Pointer Receive Done-Queue DMA Write Pointer Receive Done-Queue FIFO Flush Timer Receive Descriptor Base Address 0 (lower word) Receive Descriptor Base Address 1 (upper word) Receive DMA Configuration Indirect Select Receive DMA Configuration Receive DMA Queues Control Receive Large Buffer Size Receive Small Buffer Size 29 of 183 SECTION 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.4 9.2.4 9.2.4 9.2.4 9.2.4 9.2.4 9.2.2 9.2.2 9.3.5 9.3.5 9.2.3/9.2.4 9.2.1 9.2.1 DS31256 256-Channel, High-Throughput HDLC Controller 4.9 Transmit DMA Registers (8xx) OFFSET/ ADDRESS 0800 0804 0808 080C 0810 0830 0834 0838 083C 0840 0844 0850 0854 0870 0874 0880 NAME TPQBA0 TPQBA1 TPQEA TPQWP TPQRP TDQBA0 TDQBA1 TDQEA TDQRP TDQWP TDQFFT TDBA0 TDBA1 TDMACIS TDMAC TDMAQ REGISTER Transmit Pending-Queue Base Address 0 (lower word) Transmit Pending-Queue Base Address 1 (upper word) Transmit Pending-Queue End Address Transmit Pending-Queue Host Write Pointer Transmit Pending-Queue DMA Read Pointer Transmit Done-Queue Base Address 0 (lower word) Transmit Done-Queue Base Address 1 (upper word) Transmit Done-Queue End Address Transmit Done-Queue Host Read Pointer Transmit Done-Queue DMA Write Pointer Transmit Done-Queue FIFO Flush Timer Transmit Descriptor Base Address 0 (lower word) Transmit Descriptor Base Address 1 (upper word) Transmit DMA Configuration Indirect Select Transmit DMA Configuration Transmit DMA Queues Control SECTION 9.3.3 9.3.3 9.3.3 9.3.3 9.3.3 9.3.4 9.3.4 9.3.4 9.3.4 9.3.4 9.3.4 9.3.2 9.3.2 9.3.5 9.3.5 9.3.3/9.3.4 4.10 FIFO Registers (9xx) OFFSET/ ADDRESS 0900 0904 0910 0914 0920 0924 0980 0984 0990 0994 09A0 09A4 NAME RFSBPIS RFSBP RFBPIS RFBP RFHWMIS RFHWM TFSBPIS TFSBP TFBPIS TFBP TFLWMIS TFLWM REGISTER Receive FIFO Starting Block Pointer Indirect Select Receive FIFO Starting Block Pointer Receive FIFO Block Pointer Indirect Select Receive FIFO Block Pointer Receive FIFO High-Watermark Indirect Select Receive FIFO High Watermark Transmit FIFO Starting Block Pointer Indirect Select Transmit FIFO Starting Block Pointer Transmit FIFO Block Pointer Indirect Select Transmit FIFO Block Pointer Transmit FIFO Low-Watermark Indirect Select Transmit FIFO Low Watermark 30 of 183 SECTION 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 DS31256 256-Channel, High-Throughput HDLC Controller 4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ ADDRESS 0x000/0A00 0x004/0A04 0x008/0A08 0x00C/0A0C 0x010/0A10 0x03C/0A3C NAME PVID0 PCMD0 PRCC0 PLTH0 PDCM PINTL0 REGISTER PCI Vendor ID/Device ID 0 PCI Command Status 0 PCI Revision ID/Class Code 0 PCI Cache Line Size/Latency Timer/Header Type 0 PCI Device Configuration Memory Base Address PCI Interrupt Line and Pin/Min Grant/Max Latency 0 SECTION 10.2 10.2 10.2 10.2 10.2 10.2 4.12 PCI Configuration Registers for Function 1 (PIDSEL/Bxx) OFFSET/ ADDRESS 0x100/0B00 0x104/0B04 0x108/0B08 0x10C/0B0C 0x110/0B10 0x13C/0B3C NAME PVID1 PCMD1 PRCC1 PLTH1 PLBM PINTL1 REGISTER PCI Vendor ID/Device ID 1 PCI Command Status 1 PCI Revision ID/Class Code 1 PCI Cache Line Size/Latency Timer/Header Type 1 PCI Device Local Base Memory Base Address PCI Interrupt Line and Pin/Min Grant/Max Latency 1 31 of 183 SECTION 10.2 10.2 10.2 10.2 10.2 10.2 DS31256 256-Channel, High-Throughput HDLC Controller 5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to 1, all the internal registers (except the PCI configuration registers) are placed into their default state, which is 0000h. The host must set the RST bit back to 0 before the device can be programmed for normal operation. The RST bit does not force the PCI outputs to tri-state as does the hardware reset, which is invoked by the PRST pin. A reset invoked by the PRST pin forces the RST bit to 0 as well as the rest of the internal configuration registers. See Section 2 for more details about device initialization. The upper byte of the MRID register is read-only and it can be read by the host to determine the chip revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits. Register Name: Register Description: Register Address: MRID Master Reset and ID Register 0000h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 n/a 0 3 n/a 0 2 n/a 0 1 n/a 0 0 RST 0 Bit # Name Default 15 ID7 0 14 ID6 0 13 ID5 0 12 ID4 0 11 ID3 0 10 ID2 0 9 ID1 0 8 ID0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Master Software Reset (RST) 0 = normal operation 1 = force all internal registers (except LBBMC) to their default value of 0000h Bits 8 to 15/Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the meaning of the ID bits. 5.2 Master Configuration Register Description The master configuration (MC) register is used by the host to enable the receive and transmit DMAs as well as to control their PCI bus bursting attributes and select which port the BERT is dedicated to. Register Name: Register Description: Register Address: MC Master Configuration Register 0010h Bit # Name Default 7 BPS0 0 6 PBO 0 5 TDT1 0 4 TDT0 0 3 TDE 0 2 RDT1 0 1 DT0 0 0 RDE 0 Bit # Name Default 15 TFPC1 0 14 TFPC0 0 13 RFPC1 0 12 RFPC0 0 11 BPS4 0 10 BPS3 0 9 BPS2 0 8 BPS1 0 Note: Bits that are underlined are read-only; all other bits are read-write. 32 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive DMA does not pass any data from the receive FIFO to the PCI bus, even if one or more HDLC channels is enabled. On device initialization, the host should fully configure the receive DMA before enabling it through this bit. 0 = receive DMA is disabled 1 = receive DMA is enabled Bit 1/Receive DMA Throttle Select Bit 0 (RDT0); Bit 2/Receive DMA Throttle Select Bit 1 (RDT1). These two bits select the maximum burst length that the receive DMA is allowed on the PCI bus. The DMA can be restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency and bus efficiency. 00 = burst length maximum is 32 dwords 01 = burst length maximum is 64 dwords 10 = burst length maximum is 128 dwords 11 = burst length maximum is 256 dwords Bit 3/Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to 0, the transmit DMA does not pass any data from the PCI bus to the transmit FIFO, even if one or more HDLC channels is enabled. On device initialization, the host should fully configure the transmit DMA before enabling it through this bit. 0 = transmit DMA is disabled 1 = transmit DMA is enabled Bit 4/Transmit DMA Throttle Select Bit 0 (TDT0); Bit 5/Transmit DMA Throttle Select Bit 1 (TDT1). These two bits select the maximum burst length the transmit DMA is allowed on the PCI bus. The DMA can be restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency and bus efficiency. 00 = burst length maximum is 32 dwords 01 = burst length maximum is 64 dwords 10 = burst length maximum is 128 dwords 11 = burst length maximum is 256 dwords Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address, while Big Endian places the least significant byte at the highest address. This bit setting only affects HDLC data on the PCI bus. All other PCI bus transactions to the internal device configuration registers, PCI configuration registers, and local bus are always in Little Endian format. 0 = HDLC packet data on the PCI bus is in Little Endian format 1 = HDLC packet data on the PCI bus is in Big Endian format 33 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bits 7 to 11/BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These bits select which port has the dedicated resources of the BERT. 00000 = Port 0 00001 = Port 1 00010 = Port 2 00011 = Port 3 00100 = Port 4 00101 = Port 5 00110 = Port 6 00111 = Port 7 01000 = Port 8 01001 = Port 9 01010 = Port 10 01011 = Port 11 01100 = Port 12 01101 = Port 13 01110 = Port 14 01111 = Port 15 10000 = Port 0 (high speed) 10001 = Port 1 (high speed) 10010 = Port 2 (high speed) 10011 = n/a 10100 = n/a 10101 = n/a 10110 = n/a 10111 = n/a 11000 = n/a 11001 = n/a 11010 = n/a 11011 = n/a 11100 = n/a 11101 = n/a 11110 = n/a 11111 = n/a Bit 12/Receive FIFO Priority Control Bit 0 (RFPC0); Bit 13/Receive FIFO Priority Control Bit 1 (RFPC1). These bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest priority to the DMA to transfer data from the FIFO to the PCI bus. In the priority decoded scheme, the lower the HDLC channel numbers, generally the higher the priority. In schemes ’10 and ’11, the upper priority decode channels have priority over the lower priority decode channels. 00 = all HDLC channels are serviced round robin 01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin 10 = HDLC channels 16 to 1 are priority decoded; HDLC channels 17-up are round robin 11 = HDLC channels 64 to 1 are priority decoded; HDLC channels 65-up are round robin Bit 14/Transmit FIFO Priority Control Bit 0 (TFPC0); Bit 15/Transmit FIFO Priority Control Bit 1 (TFPC1). These two bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest priority to the DMA to transfer data from the PCI bus to the FIFO. In the schemes ’01 and ‘11m upper priority decode channels have priority over the lower priority decode channels. 00 = all HDLC channels are serviced round robin 01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin 10 = HDLC channels 16 to 1 are priority decoded; other HDLC channels 17-up re round robin 11 = HDLC channels 64 to 1 are priority decoded; other HDLC channels 65-up are round robin 5.3 Status and Interrupt 5.3.1 General Description of Operation There are three status registers in the device: status master (SM), status for the receive V.54 loopback detector (SV54), and status for DMA (SDMA). These registers report events in real-time by setting a bit within the register to 1. All bits that have been set within the register are cleared when the register is read, and the bit is not set again until the event has occurred again. Each bit can generate an interrupt at the PCI bus through the PINTA output signal pin, and, if the local bus is in the configuration mode, then an interrupt also be created at the LINT output signal pin. Each status register has an associated interrupt mask register, which can allow/deny interrupts from being generated on a bit-by-bit basis. All status registers remain active even if the associated interrupt is disabled. SM Register The status master (SM) register reports events that occur at the port interface, at the BERT receiver, at the PCI bus, and at the local bus. See Figure 5-1 for details. The port interface reports change-of-frame alignment (COFA) events. If the software detects that one of these bits is set, the software must begin polling the RP[n]CR or TP[n]CR registers of each active port (a maximum of 16 reads) to determine which port or ports has incurred a COFA. Also, the host can allow/deny the COFA indications to be passed to the SRCOFA and STCOFA status bits through the 34 of 183 DS31256 256-Channel, High-Throughput HDLC Controller interrupt enable for the receive COFA (IERC) and interrupt enable for the transmit COFA (IETC) control bits in the RP[n]CR and TP[n]CR registers, respectively. The BERT receiver reports three events: a change in the receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. Each of these events can be masked within the BERT function through the BERT control register (BERTC0). If the software detects that the BERT has reported an event, the software must read the BERT status register (BERTEC0) to determine which event(s) has occurred. The SM register also reports events as they occur in the PCI bus and the local bus. There are no control bits to stop these events from being reported in the SM register. When the local bus is operated in the PCI bridge mode, SM reports any interrupts detected through the local bus LINT input signal pin and if any timing errors occur because the external timing signal LRDY. When the local bus is operated in the configuration mode, the LBINT and LBE bits are meaningless and should be ignored. SV54 Register The status for receive V.54 detector (SV54) register reports if the V.54 loopback detector has either timed out in its search for the V.54 loop-up pattern or if the detector has found and verified the loopup/down pattern. There is a separate status bit (SLBP) for each port. When set, the host must read the VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the V.54 detector. When the V.54 detector experiences a timeout in its search for the loop-up code (VTO = 1), then the SLBP status bit is continuously set until the V.54 detector is reset by the host, toggling the VRST bit in RP[n]CR register. There are no control bits to stop these events from being reported in the SV54 register. See Figure 5-1 for details on the status bits and Section 6 for details on the operation of the V.54 loopback detector. SDMA Register The status DMA (SDMA) register reports events pertaining to the receive and transmit DMA blocks as well as the receive HDLC controller and FIFO. The SDMA reports when the DMA reads from either the receive free queue or transmit pending queue or writes to the receive or transmit done queues. Also reported are error conditions that might occur in the access of one of these queues. The SDMA reports if any of the HDLC channels experiences an FIFO overflow/underflow condition and if the receive HDLC controller encounters a CRC error, abort signal, or octet length problem on any of the HDLC channels. The host can determine which specific HDLC channel incurred an FIFO overflow/underflow, CRC error, octet length error, or abort by reading the status bits as reported in done queues, which are created by the DMA. There are no control bits to stop these events from being reported in the SDMA register. 35 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 5-1. Status Register Block Diagram for SM and SV54 BERT BERTEC0 Bit 1 (BECO) OR BERTEC0 Bit 2 (BBCO) BERTC0 Bit 13 (IEOF) Change in BERTEC0 Bit 0 (SYNC) BERTC0 Bit 15 (IESYNC) BERTEC0 Bit 3 (BED) BERTC0 Bit 14 (IEBED) Transmit Port I/F # 0 Receive Port I/F # 0 TCOFA TP0CR Bit #14 RCOFA RP0CR Bit #14 #1 #2 #3 #1 #2 #3 OR #13 #14 #15 #13 #14 #15 int_bd OR SM: Status Master Register LBINT LBE n/a n/a OR ST PPERR PSERR SBERT COFA SR COFA SV54: Status for V54 Detector SLBP15 SLBP14 SLBP13 SLBP5 SLBP4 SLBP3 SLBP2 SLBP1 SLBP0 Change in V.54 Detector (SLBP) Change in V.54 Detector (SLBP) Change in V.54 Detector (SLBP) Change in V.54 Detector (SLBP) Port #15 Port #14 Port #1 Port #0 36 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 5.3.2 Status and Interrupt Register Description Register Name: Register Description: Register Address: SM Status Master Register 0020h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 PPERR 0 3 PSERR 0 2 SBERT 0 1 STCOFA 0 0 SRCOFA 0 Bit # Name Default 15 LBINT 0 14 LBE 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Status Bit for Change-of-Frame Alignment (SRCOFA). This status bit is set to 1 if one or more of the receive ports has experienced a COFA event. The host must read the RCOFA bit in the receive port control registers (RP[n]CR) of each active port to determine which port or ports has seen the COFA. The SRCOFA bit is cleared when read and is not set again until the one or more receive ports has experienced another COFA. If enabled through the SRCOFA bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA). This status bit is set to 1 if one or more of the transmit ports has experienced a COFA event. The host must read the TCOFA bit in the transmit port control registers (TP[n]CR) of each active port to determine which port or ports has seen the COFA. The STCOFA bit is cleared when read and is not set again until one or more transmit ports has experienced another COFA. If enabled through the STCOFA bit in the ISM, the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 2/Status Bit for Change of State in BERT (SBERT). This status bit is set to 1 if there is a major change of state in the BERT receiver. A major change of state is defined as either a change in the receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the error counter. The host must read the status bits of the BERT in the BERT status register (BERTEC0) to determine the change of state. The SBERT bit is cleared when read and is not set again until the BERT has experienced another change of state. If enabled through the SBERT bit in the ISM, the setting of this bit causees a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 3/Status Bit for PCI System Error (PSERR). This status bit is a software version of the PCI bus hardware pin PSERR. It is set to 1 if the PCI bus detects an address parity error or other PCI bus error. The PSERR bit is cleared when read and is not set again until another PCI bus error has occurred. If enabled through the PSERR bit in the ISM, the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. This status bit is also reported in the control/status register in the PCI configuration registers (Section 10). Bit 4/Status Bit for PCI System Error (PPERR). This status bit is a software version of the PCI bus hardware pin PPERR. It is set to 1 if the PCI bus detects parity errors on the PAD and PCBE buses as experienced or reported by a target. The PPERR bit is cleared when read and is not set again until another parity error has been detected. If enabled through the PPERR bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. This status bit is also reported in the control/status register in the PCI configuration registers (Section 10). 37 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI bridge mode. It is set to 1 when the local bus LRDY signal is not detected within nine LCLK periods. This indicates to the host that an aborted local bus access has occurred. If enabled through the LBE bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. The LBE bit is meaningless when the local bus is operated in the configuration mode and should be ignored. Bit 15/Status Bit for Local Bus Interrupt (LBINT). This status bit is set to 1 if the local bus LINT signal has been detected as asserted. This status bit is only valid when the local bus is operated in PCI bridge mode. The LBINT bit is cleared when read and is not set again until the LINT signal pin once again has been detected as asserted. If enabled through the LBINT bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin. The LBINT bit is meaningless when the local bus is operated in the configuration mode and should be ignored. Register Name: Register Description: Register Address: ISM Interrupt Mask Register for SM 0024h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 PPERR 0 3 PSERR 0 2 SBERT 0 1 STCOFA 0 0 SRCOFA 0 Bit # Name Default 15 LBINT 0 14 LBE 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Status Bit for Receive Change-of-Frame Alignment (SRCOFA) 0 = interrupt masked 1 = interrupt unmasked Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA) 0 = interrupt masked 1 = interrupt unmasked Bit 2/Status Bit for Change of State in BERT (SBERT) 0 = interrupt masked 1 = interrupt unmasked Bit 3/Status Bit for PCI System Error (PSERR) 0 = interrupt masked 1 = interrupt unmasked Bit 4/Status Bit for PCI System Error (PPERR) 0 = interrupt masked 1 = interrupt unmasked Bit 14/Status Bit for Local Bus Error (LBE) 0 = interrupt masked 1 = interrupt unmasked 38 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 15/Status Bit for Local Bus Interrupt (LBINT) 0 = interrupt masked 1 = interrupt unmasked Register Name: Register Description: Register Address: SV54 Status Register for the Receive V.54 Detector 0030h Bit # Name Default 7 SLBP7 0 6 SLBP6 0 5 SLBP5 0 4 SLBP4 0 3 SLBP3 0 2 SLBP2 0 1 SLBP1 0 0 SLBP0 0 Bit # Name Default 15 SLBP15 0 14 SLBP14 0 13 SLBP13 0 12 SLBP12 0 11 SLBP11 0 10 SLBP10 0 9 SLBP9 0 8 SLBP8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Status Bits for Change of State in Receive V.54 Loopback Detector (SLBP0 to SLBP15). These status bits are set to 1 when the V.54 loopback detector within the port has either timed out in its search for the loop-up pattern or it has detected and validated the loop-up or loop-down pattern. There is one status bit per port. The host must read the VTO and VLB status bits in RP[n]CR register of the corresponding port to determine the exact status of the V.54 detector. If the V.54 detector has timed out in its search for the loop-up code (VTO = 1), then SLBP is continuously set until the host resets the V.54 detector by toggling the VRST bit in RP[n]CR. If enabled through the SLBP[n] bit in the interrupt mask for SV54 (ISV54), the setting of these bits causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. See Section 6 for specific details about the operation of the V.54 loopback detector. Register Name: Register Description: Register Address: ISV54 Interrupt Mask Register for SV54 0034h Bit # Name Default 7 SLBP7 0 6 SLBP6 0 5 SLBP5 0 4 SLBP4 0 3 SLBP3 0 2 SLBP2 0 1 SLBP1 0 0 SLBP0 0 Bit # Name Default 15 SLBP15 0 14 SLBP14 0 13 SLBP13 0 12 SLBP12 0 11 SLBP11 0 10 SLBP10 0 9 SLBP9 0 8 SLBP8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Status Bit for Change of State in Receive V.54 Loopback Detector (SLBP0 to SLBP15) 0 = interrupt masked 1 = interrupt unmasked 39 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: SDMA Status Register for DMA 0028h Bit # Name Default 7 RLBRE 0 6 RLBR 0 5 ROVFL 0 4 RLENC 0 3 RABRT 0 2 RCRCE 0 1 n/a 0 0 n/a 0 Bit # Name Default 15 TDQWE 0 14 TDQW 0 13 TPQR 0 12 TUDFL 0 11 RDQWE 0 10 RDQW 0 9 RSBRE 0 8 RSBR 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE). This status bit is set to 1 if any of the receive HDLC channels experiences a CRC checksum error. The RCRCE bit is cleared when read and is not set again until another CRC checksum error has occurred. If enabled through the RCRCE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive HDLC channels detects an abort. The RABRT bit is cleared when read and is not set again until another abort has been detected. If enabled through the RABRT bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 4/Status Bit for Receive HDLC Length Check (RLENC). This status bit is set to 1 if any of the HDLC channels: • exceeds the octet length count (if so enabled to check for octet length) • receives an HDLC packet that does not meet the minimum length criteria of either 4 or 6 bytes • experiences a nonintegral number of octets between opening and closing flags The RLENC bit is cleared when read and is not set again until another length violation has occurred. If enabled through the RLENC bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 5/Status Bit for Receive FIFO Overflow (ROVFL). This status bit is set to 1 if any of the HDLC channels experiences an overflow in the receive FIFO. The ROVFL bit is cleared when read and is not set again until another overflow has occurred. If enabled through the ROVFL bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit is set to 1 each time the receive DMA completes a single read or a burst read of the large buffer free queue. The RLBR bit is cleared when read and is not be set again until another read of the large buffer free queue has occurred. If enabled through the RLBR bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit is set to 1 each time the receive DMA tries to read the large buffer free queue and it is empty. The RLBRE bit is cleared when read and is not set again until another read of the large buffer free queue detects that it is empty. If enabled through the RLBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. 40 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive DMA completes a single read or a burst read of the small buffer free queue. The RSBR bit is cleared when read and is not set again until another read of the small buffer free queue has occurred. If enabled through the RSBR bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE). This status bit is set to 1 each time the receive DMA tries to read the small buffer free queue and it is empty. The RSBRE bit is cleared when read and is not set again until another read of the small buffer free queue detects that it is empty. If enabled through the RSBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW). This status bit is set to 1 when the receive DMA writes to the done queue. Based of the setting of the receive done-queue threshold setting (RDQT0 to RDQT2) bits in the receive DMA queues-control (RDMAQ) register, this bit is set either after each write or after a programmable number of writes from 2 to 128 (Section 9.2.4). The RDQW bit is cleared when read and is not set again until another write to the done queue has occurred. If enabled through the RDQW bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE). This status bit is set to 1 each time the receive DMA tries to write to the done queue and it is full. The RDQWE bit is cleared when read and is not set again until another write to the done queue detects that it is full. If enabled through the RDQWE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL). This status bit is set to 1 if any of the HDLC channels experiences an underflow in the transmit FIFO. The TUDFL bit is cleared when read and is not set again until another underflow has occurred. If enabled through the TUDFL bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR). This status bit is set to 1 each time the transmit DMA reads the pending queue. The TPQR bit is cleared when read and is not set again until another read of the pending queue has occurred. If enabled through the TPQR bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW). This status bit is set to 1 when the transmit DMA writes to the done queue. Based on the setting of the transmit done-queue threshold setting (TDQT0 to TDQT2) bits in the transmit DMA queues-control (TDMAQ) register, this bit is set either after each write or after a programmable number of writes from 2 to 128 (Section 9.2.4). The TDQW bit is cleared when read and is not set again until another write to the done queue has occurred. If enabled through the TDQW bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE). This status bit is set to 1 each time the transmit DMA tries to write to the done queue and it is full. The TDQWE bit is cleared when read and is not set again until another write to the done queue detects that it is full. If enabled through the TDQWE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. 41 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: ISDMA Interrupt Mask Register for SDMA 002Ch Bit # Name Default 7 RLBRE 0 6 RLBR 0 5 ROVFL 0 4 RLENC 0 3 RABRT 0 2 RCRCE 0 1 n/a 0 0 n/a 0 Bit # Name Default 15 TDQWE 0 14 TDQW 0 13 TPQR 0 12 TUDFL 0 11 RDQWE 0 10 RDQW 0 9 RSBRE 0 8 RSBR 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE) 0 = interrupt masked 1 = interrupt unmasked Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT) 0 = interrupt masked 1 = interrupt unmasked Bit 4/Status Bit for Receive HDLC Length Check (RLENC) 0 = interrupt masked 1 = interrupt unmasked Bit 5/Status Bit for Receive FIFO Overflow (ROVFL) 0 = interrupt masked 1 = interrupt unmasked Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR) 0 = interrupt masked 1 = interrupt unmasked Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE) 0 = interrupt masked 1 = interrupt unmasked Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR) 0 = interrupt masked 1 = interrupt unmasked Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE) 0 = interrupt masked 1 = interrupt unmasked Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW) 0 = interrupt masked 1 = interrupt unmasked Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE) 0 = interrupt masked 1 = interrupt unmasked Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL) 0 = interrupt masked 1 = interrupt unmasked 42 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR) 0 = interrupt masked 1 = interrupt unmasked Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW) 0 = interrupt masked 1 = interrupt unmasked Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE) 0 = interrupt masked 1 = interrupt unmasked 5.4 Test Register Description Register Name: Register Description: Register Address: TEST Test Register 0050h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 n/a 0 3 n/a 0 2 n/a 0 1 n/a 0 0 FT 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Factory Test (FT). This bit is used by the factory to place the DS31256 into the test mode. For normal device operation, this bit should be set to 0 whenever this register is written to. Setting this bit places the RAMs into a low-power standby mode. Bit 1 to 15/Device Internal Test Bits. Bits 1 to 15 are for internal (Dallas Semiconductor) test use only, not user test-mode controls. Values of these bits should always be 0. If any of these bits are set to 1 the device does not function properly. 43 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 6. LAYER 1 6.1 General Description Figure 6-1 shows the Layer 1 block. Each of the DS31256’s 16 Layer 1 ports can be configured to support either a channelized application or an unchannelized application. Users can mix the applications on the ports as needed. Some or all of the ports can be channelized, while the others can be configured as unchannelized. A channelized application is defined as one that requires an 8kHz synchronization pulse to subdivide the serial data stream into a set of 8-bit DS0 channels (also called time slots), which are time division multiplexed (TDM) one after another. Ports running a channelized application require an 8kHz pulse at the RS and TS signals. An unchannelized application is defined as a synchronous clock and data interface. No synchronization pulse is required and the RS and TS signals are forced low in this application. Section 17 contains examples of some various configurations. In channelized applications, the Layer 1 ports can be configured to operate in one of four modes, as shown in Table 6-A. Each port is capable of handling one, two, or four T1/E1 data streams. When more than one T1/E1 data stream is applied to the port, the individual T1/E1 data streams must be TDM into a single data stream at either a 4.096MHz or 8.192MHz data rate. Since the DS31256 can map any HDLC channel to any DS0 channel, it can support any form (byte interleaved, frame interleaved, etc.) of TDM that the application may require. On a DS0-by-DS0 basis, the DS31256 can be configured to process all 8 bits (64kbps), the seven most significant bits (56kbps), or no data. Table 6-A. Channelized Port Modes MODE T1 (1.544MHz) E1 (2.048MHz) 4.096MHz 8.192MHz FUNCTION N x 64kbps or N x 56kbps; where N = 1 to 24 (one T1 data stream) N x 64kbps or N x 56kbps; where N = 1 to 32 (one T1 or E1 data stream) N x 64kbps or N x 56kbps; where N = 1 to 64 (two T1 or E1 data streams) N x 64kbps or N x 56kbps; where N = 1 to 128 (four T1 or E1 data streams) Each port in the Layer 1 block is connected to a slow HDLC engine. The slow HDLC engine can handle channelized applications at speeds up to 8.192Mbps and unchannelized applications at speeds of up to 10Mbps. Ports 0 and 1 have the added capability of fast HDLC engines that can only handle unchannelized applications but at speeds of up to 52MHz. Each port has an associated receive port control register (RP[n]CR, where n = 0 to 15) and a transmit port control register (TP[n]CR where n = 0 to 15). These control registers are defined in detail in Section 6.2. They control all the circuitry in the Layer 1 block with the exception of the Layer 1 state machine, which is shown in the center of the block diagram (Figure 6-1). Each port contains a Layer 1 state machine that connects directly to the slow HDLC engine. It prepares the raw incoming data for the slow HDLC engine and grooms the outgoing data. The Layer 1 state machine performs a number of tasks that include the following: Assigning the HDLC channel number to the incoming and outgoing data Channelized local and network loopbacks Channelized selection of 64kbps, 56kbps, or no data Channelized transmits DS0 channel fill of all ones Routing data to and from the BERT function Routing data to the V.54 loop pattern detector 44 of 183 DS31256 256-Channel, High-Throughput HDLC Controller The DS31256 has a set of three registers per DS0 channel for each port that determine how each DS0 channel is configured. These three registers are defined in Section 6.3. If the fast (52Mbps) HDLC engine is enabled on port 0, then HDLC channel 1 is assigned to it. Likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 1 if it is enabled, and HDLC channel 2 is assigned to the fast HDLC engine on port 2 if it is enabled. The DS31256 contains an on-board full-featured BERT capable of generating and detecting both pseudorandom and repeating serial bit patterns. The BERT function is a shared resource among the 16 ports on the DS31256 and can only be assigned to one port at a time. It can be used in both channelized and unchannelized applications and at speeds up to 52MHz. In channelized applications, data can be routed to and from any combination of DS0 channels that are being used on the port. The details on the BERT function are covered in Section 6.5. The Layer 1 block also contains a V.54 detector. Each of the 16 ports contains a V.54 loop pattern detector on the receive side. The device can search for the V.54 loop-up and loop-down patterns in both channelized and unchannelized applications at speeds up to 10MHz. In channelized applications, the device can be configured to search for the patterns in any combination of DS0 channels. Section 6.4 describes all of the details on the V.54 detector. 45 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 6-1. Layer 1 Block Diagram 1 of 16 RC RS RD Local LoopBack (LLB) V.54 Detector Invert Clock / Data / Sync LLB TC TS TD Force All Ones Ports 0, 1, 2 Only OverSample with PCLK Receive UNLB Invert Clock / Data / Sync BERT/ Fast HDLC Mux OverSample with PCLK Layer 1 State Machine PORT RAM (see Sec. 5.3) UnChannelized Network Loopback (UNLB) Channelized Local LoopBack (CLLB) Channelized Network LoopBack (CNLB) SLOW HDLC From (One per Port) Transmit Ports 0 & 1 Only l1_bd 46 of 183 FIFO Block FAST HDLC BERT Mux (Figure 6-7) To / DS31256 256-Channel, High-Throughput HDLC Controller Figure 6-2. Port Timing (Channelized and Unchannelized Applications) RC[n] / TC[n] Normal Mode RC[n] / TC[n] Inverted Mode Bit 191 or 254 or 510 or 1022 RD[n] TD[n] Bit 192 or 255 or 511 or 1023 Last Bit of the Frame Bit 0 Bit 1 First Bit of the Frame RS[n] / TS[n] 0 Clock Early & Not Inverted RS[n] / TS[n] 1/2 Clock Early & Inverted RS[n] / TS[n] 1 Clock Early & Not Inverted RS[n] / TS[n] 2 Clocks Early & Not Inverted tdm_tim 47 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 6.2 Port Register Descriptions Receive-Side Control Bits (one each for all 16 ports) Register Name: Register Description: Register Address: RP[n]CR, where n = 0 to 15 for each port Receive Port [n] Control Register See the Register Map in Section 4. Bit # Name Default 7 RSS1 0 6 RSS0 0 5 RSD1 0 4 RSD0 0 3 VRST 0 2 RISE 0 1 RIDE 0 0 RICE 0 Bit # Name Default 15 RCOFA 0 14 IERC 0 13 VLB 0 12 VTO 0 11 n/a 0 10 LLB 0 9 RUEN 0 8 RP[i]HS 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Invert Clock Enable (RICE) 0 = do not invert clock (normal mode) 1 = invert clock (inverted clock mode) Bit 1/Invert Data Enable (RIDE) 0 = do not invert data (normal mode) 1 = invert data (inverted data mode) Bit 2/Invert Sync Enable (RISE) 0 = do not invert sync pulse (normal mode) 1 = invert sync pulse (inverted sync pulse mode) Bit 3/V.54 Detector Reset (VRST). Toggling this bit from 0 to 1 and then back to 0 causes the internal V.54 detector to be reset and begin searching for the V.54 loop-up pattern. See Section 6.4 for more details. Bit 4/Sync Delay Bit 0 (RSD0); Bit 5/Sync Delay Bit 1 (RSD1). These two bits define the format of the sync signal that is applied to the RS[n] input. These bits are ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1). 00 = sync pulse is 0 clocks early 01 = sync pulse is 1/2 clock early 10 = sync pulse is 1 clock early 11 = sync pulse is 2 clocks early Bit 6/Sync Select Bit 0 (RSS0); Bit 7/Sync Select Bit 1 (RSS1). These two bits select the mode in which each port is to be operated. Each port can be configured to accept 24, 32, 64, or 128 DS0 channels at an 8kHz rate. These bits are ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1). 00 = T1 Mode (24 DS0 channels and 193 RC clocks between RS sync signals) 01 = E1 Mode (32 DS0 channels and 256 RC clocks between RS sync signals) 10 = 4.096MHz Mode (64 DS0 channels and 512 RC clocks between RS sync signals) 11 = 8.192MHz Mode (128 DS0 channels and 1024 RC clocks between RS sync signals) 48 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 8/Port 0 High-Speed Mode (RP0 (1, 2) HS). If enabled, the port 0 (1 or 2) Layer 1 state machine logic is defeated, and RC0 (1, 2) and RD0 (1, 2) are routed to some dedicated high-speed HDLC processing logic. Only present in RP0CR, RP1CR, and RP2CR. Bit 8 is not assigned in ports 3 through 15. 0 = disabled 1 = enabled Bit 9/Unchannelized Enable (RUEN). When enabled, this bit forces the port to operate in an unchannelized fashion. When disabled, the port operates in a channelized mode. 0 = channelized mode 1 = unchannelized mode Bit 10/Local Loopback Enable (LLB). This loopback routes transmit data back to the receive port. It can be used in both channelized and unchannelized port operating modes, even on ports 0, 1, and 2 operating at speeds up to 52MHz (Figure 6-1). In channelized applications, a per-channel loopback can be realized by using the channelized local loopback (CLLB) function. See Section 6.3 for details on CLLB. 0 = loopback disabled 1 = loopback enabled Bit 12/V.54 Time Out (VTO). This read-only bit reports the real-time status of the V.54 detector. It is set to 1 when the V.54 detector has finished searching for the V.54 loop-up pattern and has not detected it. This indicates to the host that the V.54 detector can now be used to search for the V.54 loop-up pattern on other HDLC channels, and the host can initiate this by configuring the RV54 bits in the RP[n]CR register and then toggling the VRST control bit. See Section 6.4 for more details about how the V.54 detector operates. Bit 13/V.54 Loopback (VLB). This read-only bit reports the real-time status of the V.54 detector. It is set to 1 when the V.54 detector has verified that a V.54 loop-up pattern has been seen. When set, it remains set until either the V.54 loop-down pattern is seen or the V.54 detector is reset by the host (i.e., by toggling VRST). See Section 6.4 for more details on how the V.54 detector operates. Bit 14/Interrupt Enable for RCOFA (IERC) 0 = interrupt masked 1 = interrupt enabled Bit 15/COFA Status Bit (RCOFA). This latched read-only status bit sets if a COFA is detected. The COFA is detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the 193/256/512/1024-bit frame. This bit resets when read and does not set again until another COFA has occurred. Transmit-Side Control Bits (one each for all 16 ports) Register Name: Register Description: Register Address: TP[n]CR, where n = 0 to 15 for each port Transmit Port [n] Control Register See the Register Map in Section 4. Bit # Name Default 7 TSS1 0 6 TSS0 0 5 TSD1 0 4 TSD0 0 3 TFDA1 0 2 TISE 0 1 TIDE 0 0 TICE 0 Bit # Name Default 15 TCOFA 0 14 IETC 0 13 n/a 0 12 n/a 0 11 TUBS 0 10 UNLB 0 9 TUEN 0 8 TP[i]HS 0 Note: Bits that are underlined are read-only; all other bits are read-write. 49 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 0/Invert Clock Enable (TICE) 0 = do not invert clock (normal mode) 1 = invert clock (inverted mode) Bit 1/Invert Data Enable (TIDE) 0 = do not invert data (normal mode) 1 = invert data (inverted mode) Bit 2/Invert Sync Enable (TISE) 0 = do not invert sync (normal mode) 1 = invert sync pulse (inverted mode) Bit 3/Force Data All Ones (TFDA1) 0 = force all data at TD to be 1 1 = allow data to be transmitted normally Bit 4/Sync Delay Bit 0 (TSD0); Bit 5/Sync Delay Bit 1 (TSD1). These bits define the format of the sync signal that is applied to the TS[n] input. These bits are ignored if the port has been configured to operate in an unchannelized fashion (TUEN = 1). 00 = sync pulse is 0 clocks early 01 = sync pulse is 1/2 clock early 10 = sync pulse is 1 clock early 11 = sync pulse is 2 clocks early Bit 6/Sync Select Bit 0 (TSS0); Bit 7/Sync Select Bit 1 (TSS1). These bits select the mode in which each port operates. Each port can be configured to accept 24, 32, 64, or 128 DS0 channels at an 8kHz rate. These bits are ignored if the port has been configured to operate in an unchannelized fashion (TUEN = 1). 00 = T1 Mode (24 DS0 channels and 193 RC clocks between TS sync signals) 01 = E1 Mode (32 DS0 channels and 256 RC clocks between TS sync signals) 10 = 4.096MHz Mode (64 DS0 channels and 512 RC clocks between TS sync signals) 11 = 8.192MHz Mode (128 DS0 channels and 1024 RC clocks between TS sync signals) Bit 8/Port 0 High-Speed Mode (TP0 (1, 2) HS). If enabled, the port 0 (1 or 2) Layer 1 state machine logic is defeated and TC0 (1, 2) and TD0 (1, 2) are routed to some dedicated high-speed HDLC processing logic. Only present in TP0CR, TP1CR, and TP2CR. Bit 8 is not assigned in ports 3 through 15. 0 = disabled 1 = enabled Bit 9/Unchannelized Enable (TUEN). When enabled, this bit forces the port to operate in an unchannelized fashion. When disabled, the port operates in a channelized mode. This bit overrides the transmit channel-enable (TCHEN) bit in the transmit Layer 1 configuration (T[n]CFG[j]) registers, which are described in Section 6.3. 0 = channelized mode 1 = unchannelized mode Bit 10/Unchannelized Network Loopback Enable (UNLB). See Figure 6-1 for details. This loopback cannot be used for ports 0 and 1 when they are operating at speeds greater than 10MHz. 0 = loopback disabled 1 = loopback enabled Bit 11/Unchannelized BERT Select (TUBS). This bit is ignored if TUEN = 0. This bit overrides the transmit BERT (TBERT) bit in the transmit layer 1 configuration (T[n]CFG[j]) registers, which are described in Section 6.3. 0 = source transmit data from the HDLC controller 1 = source transmit data from the BERT block 50 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 14/Interrupt Enable for TCOFA (IETC) 0 = interrupt masked 1 = interrupt enabled Bit 15/COFA Status Bit (TCOFA). This latched read-only status bit is set if a COFA is detected. A COFA is detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the 193/256/512/1024-bit frame. This bit is reset when read and is not set again until another COFA has occurred. 6.3 Layer 1 Configuration Register Description There are three configuration registers for each DS0 channel on each port (Figure 6-3). As shown in Figure 6-1, each of the 16 ports contains a PORT RAM, which controls the Layer 1 state machine. These 384 registers (three registers x 128 DS0 channels per port) comprise the PORT RAM for each port, controlling and providing access to the Layer 1 state machine. The registers are accessed indirectly through the channelized port register data (CP[n]RD) register. The host must first write to the channelized port register data-indirect select (CP[n]RDIS) register to choose which DS0 channel and channelized PORT RAM it wishes to configure or read. On power-up, the host must write to all the used R[n]CFG[j] and T[n]CFG[j] locations to make sure they are set into a known state. Figure 6-3. Layer 1 Register Set C[n]DAT[j]: Channelized DS0 Data RDATA(8): Receive DS0 Data MSB TDATA(8): Transmit DS0 Data LSB R[n]CFG[j]: Receive Configuration RCH#(8): Receive HDLC Channel Number MSB RCHEN RBERT n/a RV54 n/a CLLB LSB T[n]CFG[j]: Transmit Configuration TCH#(8): Transmit HDLC Channel Number MSB TCHEN TBERT n/a n/a CNLB n/a 51 of 183 n/a R56 LSB TFAO T56 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: CP[n]RDIS, where n = 0 to 15 for each port Channelized Port [n] Register Data Indirect Select See the Register Map in Section 4. Bit # Name Default 7 n/a 0 6 CHID6 0 5 CHID5 0 4 CHID4 0 3 CHID3 0 2 CHID2 0 1 CHID1 0 0 CHID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 CPRS1 0 8 CPRS0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 6/DS0 Channel ID (CHID0 to CHID6). The number of DS0 channels used depends on whether the port has been configured for an unchannelized application or for a channelized application. If set for a channelized application, the number of DS0 channels depends on whether the port has been configured in the T1, E1, 4.096MHz, or 8.192MHz mode. 0000000 (00h) = DS0 channel number 0 1111111 (7Fh) = DS0 channel number 127 DS0 CHANNELS AVAILABLE 0 PORT MODE Unchannelized (RUEN/TUEN = 1) Channelized T1 (RUEN/TUEN = 0 and RSS0/TSS0 = 0 and RSS1/TSS1 = 0) 0 to 23 Channelized E1 (RUEN/TUEN = 0 and RSS0/TSS0 = 1 and RSS1/TSS1 = 0) 0 to 31 Channelized 4.096MHz (RUEN/TUEN = 0 and RSS0/TSS0 = 0 and RSS1/TSS1 = 1) 0 to 63 Channelized 8.192MHz (RUEN/TUEN = 0 and RSS0/TSS0 = 1 and RSS1/TSS1 = 1) 0 to 127 Bit 8/Channelized PORT RAM Select Bit 0 (CPRS0); Bit 9/Channelized PORT RAM Select Bit 1 (CPRS1) 00 = channelized DS0 data (C[n]DAT[j]) 01 = receive configuration (R[n]CFG[j]) 10 = transmit configuration (T[n]CFG[j]) 11 = illegal selection Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal channelized PORT RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining data from the DS0 channel location indicated by the CHID bits and the data from the PORT RAM indicated by the CPRS0 and CPRS1 bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the CP[n]RD register, the IAB bit is set to 0. When the host wishes to write data to the internal channelized PORT RAM, the host should write this bit to 0. This causes the device to take the data that is currently present in the CP[n]RD register and write it to the PORT RAM indicated by the CPRS0 and CPRS1 bits and the DS0 channel indicated by the CHID bits. When the device has completed the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. 52 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: CP[n]RD, where n = 0 to 15 for each port Channelized Port [n] Register Data See the Register Map in Section 4. Bit # Name Default 7 CHD7 0 6 CHD6 0 5 CHD5 0 4 CHD4 0 3 CHD3 0 2 CHD2 0 1 CHD1 0 0 CHD0 0 Bit # Name Default 15 CHD15 0 14 CHD14 0 13 CHD13 0 12 CHD12 0 11 CHD11 0 10 CHD10 0 9 CHD9 0 8 CHD8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/DS0 Channel Data (CHD0 to CHD15). This is the 16-bit data that is to either be written into or read from the PORT RAM, specified by the CP[n]RDIS register. Figure 6-4. Port RAM Indirect Access CP[n]RDIS CP[n]RD Port RAM (one each for all 16 ports; n = 0 to 15) C[n]DAT0 R[n]CFG0 T[n]CFG0 C[n]DAT1 R[n]CFG1 T[n]CFG1 C[n]DAT2 R[n]CFG2 T[n]CFG2 C[n]DAT3 R[n]CFG3 T[n]CFG3 C[n]DAT4 R[n]CFG4 T[n]CFG4 ... ... ... C[n]DAT126 R[n]CFG126 T[n]CFG126 C[n]DAT127 R[n]CFG127 T[n]CFG127 Register Name: Register Description: Register Address: C[n]DAT[j], where n = 0 to 15 for each port and j = 0 to 127 for each DS0 Channelized Layer 1 DS0 Data Register Indirect Access through CP[n]RD Bit # Name Default 7 6 5 4 3 RDATA(8): Receive DS0 Data 2 1 0 Bit # Name Default 15 14 13 12 11 10 TDATA(8): Transmit DS0 Data 9 8 Note: Bits that are underlined are read-only; all other bits are read-write. Note: In normal device operation, the host must never write to the C[n]DAT[j] registers. Bits 0 to 7/Receive DS0 Data (RDATA). This register holds the most current DS0 byte received. It is used by the transmit-side Layer 1 state machine when channelized network loopback (CNLB) is enabled. 53 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bits 8 to 15/Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted. It is used by the receive-side Layer 1 state machine when channelized local loopback (CLLB) is enabled. Register Name: Register Description: Register Address: R[n]CFG[j] where n = 0 to 15 for each port and j = 0 to 127 for each DS0 Receive Layer 1 Configuration Register Indirect Access through CP[n]RD Bit # Name Default 7 6 Bit # Name Default 15 RCHEN 14 RBERT 5 4 3 2 RCH#(8): Receive HDLC Channel Number 13 n/a 12 RV54 11 n/a 10 CLLB 1 0 9 n/a 8 R56 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/Receive Channel Number (RCH#). The CPU loads the number of the HDLC channels associated with this particular DS0 channel. If the port is running in an unchannelized mode (RUEN = 1), the HDLC channel number only needs to be loaded into R[n]CFG0. If the fast (52Mbps) HDLC engine is enabled on port 0, HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 2, if it is enabled. Therefore, these HDLC channel numbers should not be used if the fast HDLC engines are enabled. 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0) 00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2) 00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256 Bit 8/Receive 56kbps (R56). If the port is running a channelized application, this bit determines whether the LSB of each DS0 should be processed or not. If this bit is set, the LSB of each DS0 channel is not routed to the HDLC controller (or the BERT, if it has been enabled through the RBERT bit). This bit does not affect the operation of the V.54 detector. It always searches on all 8 bits in the DS0. 0 = 64kbps (use all 8 bits in the DS0) 1 = 56kbps (use only the first 7 bits received in the DS0) Bit 10/Channelized Local Loopback Enable (CLLB). Enabling this loopback forces the transmit data to replace the receive data. This bit must be set for each and every DS0 channel that is to be looped back. In order for the loopback to become active, the DS0 channel must be enabled (RCHEN = 1) and the DS0 channel must be set into the 64kbps mode (R56 = 0). 0 = loopback disabled 1 = loopback enabled Bit 12/Receive V.54 Enable (RV54E). If this bit is cleared, this DS0 channel is not examined to check if the V.54 loop pattern is present. If set, the DS0 is examined for the V.54 loop pattern. When searching for the V.54 pattern within a DS0 channel, all 8 bits of the DS0 channel are examined, regardless of how the DS0 channel is configured (i.e., 64k or 56k). 0 = do not examine this DS0 channel for the V.54 loop pattern 1 = examine this DS0 channel for the V.54 loop pattern Bit 14/Route Data Into BERT (RBERT). Setting this bit routes the DS0 data into the BERT function. If the DS0 channel has been configured for 56kbps operation (R56 = 1), the LSB of each DS0 channel is not routed to the BERT block. In order for the data to make it to the BERT block, the host must also configure the BERT for the proper port through the master control register (Section 5). 0 = do not route data to BERT 1 = route data to BERT 54 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 15/Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still be set up to route data to the V.54 detector and/or the BERT block. In addition, although a DS0 channel is active, the loopback function (CLLB = 1) overrides this activation and routes transmit data back to the HDLC controller instead of the data coming in through the RD pin. In an unchannelized mode (RUEN = 1), only the RCHEN bit in R[n]CFG0 needs to be configured. 0 = deactivated DS0 channel 1 = active DS0 channel Register Name: Register Description: Register Address: T[n]CFG[j], where n = 0 to 15 for each port and j = 0 to 127 for each DS0 Transmit Layer 1 Configuration Register Indirect Access through CP[n]RD Bit # Name Default 7 6 Bit # Name Default 15 TCHEN 14 TBERT 5 4 3 2 TCH#(8): Transmit HDLC Channel Number 13 n/a 12 n/a 11 CNLB 10 n/a 1 0 9 TFAO 8 T56 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/Transmit Channel Number (TCH#). The CPU loads the number of the HDLC channels associated with this particular DS0 channel. If the port is running in an unchannelized mode (TUEN = 1), the HDLC channel number only needs to be loaded into T[n]CFG0. If the fast (52Mbps) HDLC engine is enabled on port 0, HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 2, if it is enabled. Therefore, these HDLC channel numbers should not be used if the fast HDLC engines are enabled. 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0) 00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2) 00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256 Bit 8/Transmit 56kbps (T56). If the port is running a channelized application, this bit determines whether or not the LSB of each DS0 should be processed. If this bit is set, the LSB of each DS0 channel is not routed from the HDLC controller (or the BERT, if it has been enabled through the RBERT bit), and the LSB bit position is forced to 1. 0 = 64kbps (use all 8 bits in the DS0) 1 = 56kbps (use only the first 7 bits transmitted in the DS0; force the LSB to 1) Bit 9/Transmit Force All Ones (TFAO). If this bit is set, then eight 1s are placed into the DS0 channel for transmission instead of the data that is being sourced from the HDLC controller. If this bit is cleared, the data from the HDLC controller is transmitted. This bit is useful in instances when CLLB is being activated to keep the looped back data from being sent out onto the network. This bit overrides TCHEN. 0 = transmit data from the HDLC controller 1 = force transmit data to all 1s Bit 11/Channelized Network Loopback Enable (CNLB). Enabling this loopback forces the receive data to replace the transmit data. This bit must be set for each and every DS0 channel that is to be looped back. This bit overrides TBERT, TFAO, and TCHEN. 0 = loopback disabled 1 = loopback enabled 55 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 14/Route Data from BERT (TBERT). Setting this bit routes DS0 data to the TD pin from the BERT block instead of from the HDLC controller. If the DS0 channel has been configured for 56kbps operation (T56 = 1), the LSB of each DS0 channel is not routed from the BERT block but instead is forced to 1. In order for the data to make it from the BERT block, the host must also configure the BERT for the proper port through the master control register (Section 5). This bit overrides TFAO and TCHEN. 0 = do not route data from BERT 1 = route data from BERT (override the data from the HDLC controller) Bit 15/Transmit DS0 Channel Enable (TCHEN). This bit must be set for each active DS0 channel in a channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still be set up to route data from the BERT block. In addition, although a DS0 channel is active, the loopback function (CNLB = 1) overrides this activation and routes receive data to the TD pin instead of from the HDLC. In an unchannelized mode (TUEN = 1), only the TCHEN bit in T[n]CFG0 needs to be configured. 0 = deactivated DS0 channel 1 = active DS0 channel 6.4 Receive V.54 Detector Each port within the device contains a V.54 loop pattern detector. V.54 is a pseudorandom pattern that is sent for at least 2 seconds, followed immediately by an all-ones pattern for at least 2 seconds if the channel is to be placed into loopback. The exact pattern and sequence is defined in Annex B of ANSI T1.403-1995. When a port is configured for unchannelized operation (RUEN = 1), all data entering the port through RD is routed to the V.54 detector. If the host wishes not to use the V.54 detector, the SLBP status bits in the status V.54 (SV54) register should be ignored, and their corresponding interrupt mask bits in ISV54 should be set to 0 to keep from disturbing the host. Details about the status and interrupt bits can be found in Section 5. When the port is configured for channelized operation (RUEN = 0), it is the host’s responsibility to determine which DS0 channels should be searched for the V.54 pattern. In channelized applications, it may be that there are multiple HDLC channels the host wishes to look in for the V.54 pattern. If this is true, then the host performs the routine shown in Table 6-B. A flow chart of the same routine is shown in Figure 6-5. 56 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 6-B. Receive V.54 Search Routine STEP DIRECTION 1 Set up the channel search 2 Toggle VRST 3 Wait for SLBP 4 Read VTO and VLB FUNCTION By configuring the RV54 bit in the R[n]CFG[j] register, the host determines in which DS0 channels the V.54 search is to take place. If this search sequence does not detect the V.54 pattern, the host can pick some new DS0 channels and try again. Once the DS0 channels have been set, the host toggles the VRST bit in the RP[n]CR register and begins monitoring the SLBP status bit. The SLBP status bit reports any change of state in the V.54 search process. It can also generate a hardware interrupt (Section 5). When SLBP is set, the host knows that something significant has occurred and that it should read the VLB and VTO real-time status bits in the RP[n]CR register. If VTO = 1, the V.54 pattern did not appear in this set of channels and the host can reconfigure the search in other DS0 channels and move back to Step #1. If VLB = 1, the V.54 loop-up pattern has been detected and the channel should be placed into loopback. A loopback can be invoked by the host by configuring the CNLB bit in the T[n]CFG[j] register for each DS0 channel that needs to be placed into loopback. Move back to Step #3. If VLB = 0, if the DS0 channels are already in loopback, the host monitors VLB to know when the loop-down pattern has been detected and when to take the channels out of loopback. The DS0 channels are taken out of loopback by again configuring the CNLB bits. Move on to Step #1. 57 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 6-5. Receive V.54 Host Algorithm ALGORITHM Set Up the DS0 Channel Search Toggle VRST Wait for SLBP = 1 Yes VTO = 1? NOTES DS0 channels can be configured to search for the V.54 loop pattern via the Receive Layer 1 Configuration Register (Section 6.3) VRST is a control bit that is in the Receive Port Control Register (Section 6.2) SLBP is a status bit that is reported in the SV54 register (Section 5.3) VTO is a status bit that is in the Receive Port Control Register (Section 6.2) No Place DS0 Channels into Loopback Wait for SLBP = 1 Take DS0 Channels out of Loopback DS0 channels can be placed into loopback via the Receive Layer 1 Configuration Register (Section 6.3) SLBP is a status bit that is reported in the SV54 register (Section 5.3) DS0 channels can be taken out of loopback via the Receive Layer 1 Configuration Register (Section 6.3) v54host 58 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 6-6. Receive V.54 State Machine VRST = 1 VLB = 0 VTO = 0 SLBP = 0 CLK V.54 State Machine Data VRST (in RP[n]CR) Time Out (VTO) Loopback (VLB); both in RP[n]CR Change of State in Status (SLBP); in SV54 SYSCLK Search for Loop Up Pattern for 32 VCLKs Sysclk is used only to time a 4 second timer. It is run into a 2E27 counter which provides a 4.03 second time out with a 33MHz clock and a 5.37 second time out with a 25MHz clock Sync = 0 Sync = 1 Reset 4 second timer; wait for Loss of Sync or All 1s (64 in a Row) or for the 4 second timer to expire All Ones Sync = 0 or 4 Second Timer Has Expired SLBP = 1 Search for Loop Down Pattern VLB = 1 Sync = 0 Sync = 1 Sync = 0 wait for Loss of Sync or All 1s (64 in a Row) All Ones VTO = 1 VLB = 0 SLBP = 1 59 of 183 v54sm DS31256 256-Channel, High-Throughput HDLC Controller 6.5 BERT The BERT block is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words that flip every 1 to 256 words The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters. See Section 5 for details on status bits and interrupts from the BERT block. To activate the BERT block, the host must configure the BERT mux (Figure 6-7). In channelized applications, the host must also configure the Layer 1 state machine to send/obtain data to/from the BERT block through the Layer 1 configuration registers (Section 6.3). Figure 6-7. BERT Mux Diagram Port 0 (slow) Port 1 (slow) Port 2 (slow) Port 3 (slow) Port 4 (slow) SBERT STATUS BIT IN SM BERT Mux BERT BLOCK Port 5 (slow) Port 13 (slow) INTERNAL CONTROL AND CONFIGURATION BUS Port 14 (slow) Port 15 (slow) Port 0 (fast) Port 1 (fast) Port 2 (fast) BERT SELECT (5) IN THE MASTER CONFIGURATION REGISTER 60 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 6.6 BERT Register Description Figure 6-8. BERT Register Set BERTC0: BERT Control 0 n/a TINV RINV MSB IESYNC IEBED IEOF BERTC1: BERT Control 1 EIB2 EIB1 EIB0 MSB PS2 PS1 PS0 LC LSB RESYNC n/a RPL3 RPL2 RPL1 RPL0 SBE n/a n/a n/a LSB TC Alternating Word Count BERTRP0: BERT Repetitive Pattern Set 0 (lower word) BERT Repetitive Pattern Set (lower byte) MSB BERT Repetitive Pattern Set LSB BERTRP1: BERT Repetitive Pattern Set 1 (upper word) BERT Repetitive Pattern Set MSB BERT Repetitive Pattern Set (upper byte) LSB BERTBC0: BERT Bit Counter 0 (lower word) BERT 32-Bit Bit Counter (lower byte) MSB BERT 32-Bit Bit Counter LSB BERTBC1: BERT Bit Counter 0 (upper word) BERT 32-Bit Bit Counter MSB BERT 32-Bit Bit Counter (upper byte) LSB BERTEC0: BERT Error Counter 0/Status n/a RA1 RA0 RLOS BED BBCO MSB BERT 24-Bit Error Counter (lower byte) BERTEC1: BERT Error Counter 1 (upper word) BERT 24-Bit Error Counter MSB BERT 24-Bit Error Counter (upper byte) 61 of 183 BECO LSB SYNC LSB DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: BERTC0 BERT Control Register 0 0500h Bit # Name Default 7 n/a 0 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit # Name Default 15 IESYNC 0 14 IEBED 0 13 IEOF 0 12 n/a 0 11 RPL3 0 10 RPL2 0 9 RPL1 0 8 RPL0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. It must be cleared and set again for a subsequent resynchronization. Note: Bits 2, 3, and 4 must be set, minimum of 64 system clock cycles, before toggling the resync bit (bit 0). Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for subsequent loads. Bit 2/Pattern Select Bit 0 (PS0); Bit 3/Pattern Select Bit 1 (PS1); Bit 4/Pattern Select Bit 2 (PS2) 000 = pseudorandom pattern 2E7 - 1 001 = pseudorandom pattern 2E11 - 1 010 = pseudorandom pattern 2E15 - 1 011 = pseudorandom pattern QRSS (2E20 - 1 with a 1 forced, if the next 14 positions are 0) 100 = repetitive pattern 101 = alternating word pattern 110 = illegal state 111 = illegal state Bit 5/Receive Invert Data Enable (RINV) 0 = do not invert the incoming data stream 1 = invert the incoming data stream Bit 6/Transmit Invert Data Enable (TINV) 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream Bit 8/Repetitive Pattern Length Bit 0 (RPL0); Bit 9/Repetitive Pattern Length Bit 1 (RPL1); Bit 10/Repetitive Pattern Length Bit 2 (RPL2); Bit 11/Repetitive Pattern Length Bit 3 (RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or 24 (0111) or 30 (1101). 62 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Repetitive Pattern Length Map Length 17 Bits 21 Bits 25 Bits 29 Bits Code 0000 0100 1000 1100 Length 18 Bits 22 Bits 26 Bits 30 Bits Code 0001 0101 1001 1101 Length 19 Bits 23 Bits 27 Bits 31 Bits Code 0010 0110 1010 1101 Length 20 Bits 24 Bits 28 Bits 32 Bits Code 0011 0111 1011 1111 Bit 13/Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either the bit counter or the error counter overflows. 0 = interrupt masked 1 = interrupt enabled Bit 14/Interrupt Enable for Bit Error Detected (IEBED). Allows the receive BERT to cause an interrupt if a bit error is detected. 0 = interrupt masked 1 = interrupt enabled Bit 15/Interrupt Enable for Change-of-Synchronization Status (IESYNC). Allows the receive BERT to cause an interrupt if there is a change of state in the synchronization status (i.e., the receive BERT either goes into or out of synchronization). 0 = interrupt masked 1 = interrupt enabled Register Name: Register Description: Register Address: BERTC1 BERT Control Register 1 0504h Bit # Name Default 7 EIB2 0 6 EIB1 0 5 EIB0 0 Bit # Name Default 15 14 13 0 0 0 4 SBE 0 3 n/a 0 12 11 Alternating Word Count 0 0 2 n/a 0 1 n/a 0 0 TC 0 10 9 8 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with repetitive or pseudorandom pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for subsequent loads. Bit 4/Single Bit-Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set again for a subsequent bit error to be inserted. Bit 5/Error Insert Bit 0 (EIB0); Bit 6/Error Insert Bit 1 (EIB1); Bit 7/Error Insert Bit 2 (EIB2). Automatically inserts bit errors at the prescribed rate into the generated data pattern. Useful for verifying error detection operation. 63 of 183 DS31256 256-Channel, High-Throughput HDLC Controller EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 Error Rate Inserted No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7 Bits 8 to 15/Alternating Word Count Rate. When the BERT is programmed in the alternating word mode, the words repeat for the count loaded into this register, then flip to the other word and again repeat for the number of times loaded into this register. The valid count range is from 05h to FFh. Register Name: Register Description: Register Address: BERTBRP0 BERT Repetitive Pattern Set 0 0508h Register Name: Register Description: Register Address: BERTBRP1 BERT Repetitive Pattern Set 1 050Ch BERTRP0: BERT Repetitive Pattern Set 0 (lower word) Bit # 7 6 5 4 3 2 Name BERT Repetitive Pattern Set (lower byte) Default 0 0 0 0 0 0 Bit # Name Default 15 14 13 0 0 0 12 11 BERT Repetitive Pattern Set 0 0 BERTRP1: BERT Repetitive Pattern Set 1 (upper word) Bit # 23 22 21 20 19 Name BERT Repetitive Pattern Set Default 0 0 0 0 0 Bit # Name Default 31 30 0 0 1 0 0 0 10 9 8 0 0 0 18 17 16 0 0 0 25 24 0 0 29 28 27 26 BERT Repetitive Pattern Set (upper byte) 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 31/BERT Repetitive Pattern Set (BERTRP0 and BERTRP1). These registers must be properly loaded for the BERT to properly generate and synchronize to either a repetitive pattern, a pseudorandom pattern, or an alternating word pattern. For a repetitive pattern that is less than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the repeating 5-bit pattern …01101… (where the right-most bit is sent first and received first), then PBRP0 should be loaded with xB5AD and PBRP1 should be loaded with x5AD6. For a pseudorandom pattern, both registers should be loaded with all ones (i.e., xFFFF). For an alternating word pattern, one word should be placed into PBRP0 and the other word should be placed into PBRP1. For example, if the DDS stress pattern “7E” is to be described, the user would place x0000 in PBRP0 and x7E7E in PBRP1 and the alternating word counter would be set to 50 (decimal) to allow 100 Bytes of 00h followed by 100 Bytes of 7Eh to be sent and received. 64 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: BERTBC0 BERT 32-Bit Bit Counter (lower word) 0510h Register Name: Register Description: Register Address: BERTBC1 BERT 32-Bit Bit Counter (upper word) 0514h BERTBC0: BERT Bit Counter 0 (lower word) Bit # 7 6 5 4 3 2 Name BERT 32-Bit Bit Counter (lower byte) Default 0 0 0 0 0 0 Bit # Name Default 15 14 13 0 0 0 12 11 BERT 32-Bit Bit Counter 0 0 1 0 0 0 10 9 8 0 0 0 18 17 16 BERTBC1: BERT Bit Counter 0 (upper word) Bit # Name Default 23 22 21 20 19 BERT 32-Bit Bit Counter 0 0 0 0 0 0 0 0 Bit # Name Default 31 30 25 24 0 0 29 28 27 26 BERT 32-Bit Bit Counter (upper byte) 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 31/BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter increments for each data bit (i.e., clock) received. This counter is not disabled when the receive BERT loses synchronization. This counter is loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from low (0) to high (1). When full, this counter saturates and sets the BBCO status bit. Register Name: Register Description: Register Address: BERTEC0 BERT 24-Bit Error Counter (lower) and Status Information 0518h Bit # Name Default 7 n/a 0 6 RA1 0 Bit # Name Default 15 14 0 0 5 RA0 0 4 RLOS 0 3 BED 0 2 BBCO 0 13 12 11 10 BERT 24-Bit Error Counter (lower byte) 0 0 0 0 1 BECO 0 0 SYNC 0 9 8 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Real-Time Synchronization Status (SYNC). Real-time status of the synchronizer (this bit is not latched). Is set when the incoming pattern matches for 32 consecutive bit positions. Is cleared when six or more bits out of 64 are received in error. 65 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 2/BERT Bit Counter Overflow (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 3/Bit Error Detected (BED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Cleared when read. Bit 4/Receive Loss of Synchronization (RLOS). A latched bit that is set whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit remains set until read. Bit 5/Receive All Zeros (RA0). A latched bit that is set when 31 consecutive 0s are received. Allowed to be cleared once a 1 is received. Bit 6/Receive All Ones (RA1). A latched bit that is set when 31 consecutive 1s are received. Allowed to be cleared once 0 is received. Bits 8 to 15/BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the BERTEC1 register description for details. Register Name: Register Description: Register Address: BERTEC1 BERT 24-Bit Error Counter (upper) 051Ch Bit # Name Default 7 6 5 4 3 BERT 24-Bit Error Counter 0 0 2 1 0 0 0 0 0 0 0 Bit # Name Default 15 14 0 0 13 12 11 10 BERT 24-Bit Error Counter (upper byte) 0 0 0 0 9 8 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. default value for all bits is 0. Bits 0 to 15/BERT 24-Bit Error Counter (BEC). Upper two words of the 24-bit error counter. This 24-bit counter increments for each data bit received in error. This counter is not disabled when the receive BERT loses synchronization. This counter is loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from low (0) to high (1). When full, this counter saturates and sets the BECO status bit. 66 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 7. HDLC 7.1 General Description The DS31256 contains two different types of HDLC controllers. Each port has a slow HDLC engine (type #1) associated with it that can operate in either a channelized mode up to 8.192Mbps or an unchannelized mode at rates up to 10Mbps. Ports 0 and 1 also have an additional fast HDLC engine (type #2) that can operate in only an unchannelized fashion up to 52Mbps. Through the Layer 1 registers (Section 6.2), the host determines which type of HDLC controller is used on a port and if the HDLC controller is to be operated in either a channelized or unchannelized mode. If the HDLC controller is to be operated in the channelized mode, then the Layer 1 registers (Section 6.3) also determine which HDLC channels are associated with which DS0 channels. If the fast HDLC engine is enabled on port 0, HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 1 if it is enabled. The HDLC controllers can handle all required normal real-time tasks. Table 7-B lists all the functions supported by the receive HDLC and Table 7-C lists all the functions supported by the transmit HDLC. Each of the 256 HDLC channels within the DS31256 are configured by the host through the receive HDLC channel definition (RHCD) and transmit channel definition (THCD) registers. There is a separate RHCD and THCD register for each HDLC channel. The host can access the RHCD and THCD registers indirectly through the RHCDIS indirect select and THCDIS indirect select registers. See Section 7.2 for details. On the receive side, one of the outcomes shown in Table 7-A occurs when the HDLC block is processing a packet. For each packet, one of these outcomes is reported in the receive done-queue descriptor (Section 9.2.4). On the transmit side, when the HDLC block is processing a packet, an error in the PCI block (parity or target abort) or transmit FIFO underflow causes the HDLC block to send an abort sequence (eight 1s in a row) followed continuously by the selected interfill (either 7Eh or FFh) until the HDLC channel is reset by the transmit DMA block (Section 9.3.1). This same sequence of events will occur even if the transmit HDLC channel is being operated in the transparent mode. In the transparent mode, when the FIFO empties the device sends either 7Eh or FFh. If any of the 256 receive HDLC channels detects an abort sequence, an FCS checksum error, or if the packet length was incorrect, then the appropriate status bit in SDMA is set. If enabled, the setting of any of these statuses can cause a hardware interrupt to occur. See Section 5.3.2 for details about the operation of these status bits. Table 7-A. Receive HDLC Packet Processing Outcomes OUTCOME EOF/Normal Packet EOF/Bad FCS Abort Detected EOF/Too Few Bytes Too Many Bytes EOF/Bad # of Bits FIFO Overflow CRITERIA Integral number of packets > min and < max is received and CRC is okay Integral number of packets > min and < max is received and CRC is bad Seven or more 1s in a row detected Fewer than 4 or 6 Bytes received Greater than the packet maximum is received (if detection enabled) Not an integral number of bytes received Tried to write a byte into an already full FIFO 67 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 7-B. Receive HDLC Functions FUNCTION DESCRIPTION Zero Destuff This operation is disabled if the channel is set to transparent mode. Flag Detection and Byte Alignment Okay to have two packets separated by only one flag or by two flags sharing a 0. This operation is disabled if the channel is set to transparent mode. The minimum check is for 4 Bytes with CRC-16 and 6 Bytes with CRC-32 (packets with less than the minimum lengths are not passed to the PCI bus). The maximum check is programmable up to 65,536 Bytes through the RHPL register. The maximum check can be disabled through the ROLD control bit in the RHCD register. The minimum and maximum counts include the FCS. An error is also reported if a noninteger number of octets occur between flags. Can be either set to CRC-16 or CRC-32 or none. The CRC can be passed through to the PCI bus or not. The CRC check is disabled if the channel is set to transparent mode. Octet Length Check CRC Check Abort Detection Checks for seven or more 1s in a row. Invert Data All data (including the flags and FCS) is inverted before HDLC processing. Also available in the transparent mode. Bit Flip Transparent Mode The first bit received becomes either the LSB (normal mode) or the MSB (telecom mode) of the byte stored in the FIFO. Also available in the transparent mode. If enabled, flag detection, zero destuffing, abort detection, length checking, and FCS checking are disabled. Data is passed to the PCI bus on octet (i.e., byte) boundaries in channelized operation. Table 7-C. Transmit HDLC Functions Zero Stuffing Only used between opening and closing flags. Is disabled between a closing flag and an opening flag and for sending aborts and/or interfill data. Disabled if the channel is set to the transparent mode. Interfill Selection Can be either 7Eh or FFh. Flag Generation CRC Generation Invert Data Bit Flip Transparent Mode Invert FCS A programmable number of flags (1 to 16) can be set between packets. Disabled if the channel is set to the transparent mode. Can be either CRC-16 or CRC-32 or none. Disabled if the channel is set to transparent mode. All data (including the flags and FCS) is inverted after processing. Also available in the transparent mode. The LSB (normal mode) of the byte from the FIFO becomes the first bit sent or the MSB (telecom mode) becomes the first bit sent. Also available in the transparent mode. If enabled, flag generation, zero stuffing, and FCS generation is disabled. Passes bytes from the PCI Bus to Layer 1 on octet (byte) boundaries. When enabled, it inverts all of the bits in the FCS (useful for HDLC testing). 68 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 7.2 HDLC Register Description Register Name: Register Description: Register Address: RHCDIS Receive HDLC Channel Definition Indirect Select 0400h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0) 00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2) 00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive HDLC definition RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RHCD register, the IAB bit is set to 0. When the host wishes to write data to the internal receive HDLC definition RAM, the host should write this bit to 0. This causes the device to take the data that is currently present in the RHCD register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit sets to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation completes. Register Name: Register Description: Register Address: RHCD Receive HDLC Channel Definition 0404h Bit # Name Default 7 RABTD 0 6 RCS 0 5 RBF 0 4 RID 0 3 RCRC1 0 2 RCRC0 0 1 ROLD 0 0 RTRANS 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 RZDD 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Receive Transparent Enable (RTRANS). When this bit is set low, the HDLC controller performs flag delineation, zero destuffing, abort detection, octet length checking (if enabled through ROLD), and FCS checking (if enabled through RCRC0/1). When this bit is set high, the HDLC controller does not perform flag delineation, 69 of 183 DS31256 256-Channel, High-Throughput HDLC Controller zero destuffing, and abort detection, octet length checking, or FCS checking. When in transparent mode, the device must not be configured to write done-queue descriptors only at the end of a packet, if it is desired that donequeue descriptors be written; there is not an end of packet on the receive side in transparent mode by definition. Please note that an end of packet does not occur on the receive side while in transparent mode. 0 = transparent mode disabled 1 = transparent mode enabled Bit 1/Receive Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC engine does not check to see if the octet length of the received packets exceeds the count loaded into the receive HDLC packet length (RHPL) register. When this bit is set high, the HDLC engine checks to see if the octet length of the received packets exceeds the count loaded into the RHPL register. When an incoming packet exceeds the maximum length, the packet is aborted and the remainder is discarded. This bit is ignored if the HDLC channel is set to transparent mode (RTRANS = 1). 0 = octet length detection disabled 1 = octet length detection enabled Bits 2, 3/Receive CRC Selection (RCRC0/RCRC1). These two bits are ignored if the HDLC channel is set into transparent mode (RTRANS = 1). RCRC1 0 0 1 1 RCRC0 0 1 0 1 ACTION No CRC verification performed 16-bit CRC (CCITT/ITU Q.921) 32-bit CRC Illegal state Bit 4/Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not inverted before processing. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and FCS) before processing the data. The data is not reinverted before passing to the FIFO. 0 = do not invert data 1 = invert all data (including flags and FCS) Bit 5/Receive Bit Flip (RBF). When this bit is set low, the HDLC engine places the first HDLC bit received in the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high, the HDLC controller places the first HDLC bit received in the highest bit position of the PCI bus bytes (i.e., PAD[7], PAD[15], PAD[23], PAD[31]). 0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI bus 1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI bus Bit 6/Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through to the PCI bus. When this bit is set low, the HDLC engine includes the 2-Byte FCS (16-bit) or 4-Byte FCS (32-bit) in the data that it transfers to the PCI bus. This bit is ignored if the HDLC channel is set into transparent mode (RTRANS = 1). 0 = send FCS to the PCI bus 1 = do not send the FCS to the PCI bus Bit 7/Receive Abort Disable (RABTD). When this bit is set low, the HDLC engine examines the incoming data stream for the abort sequence, which is seven or more consecutive 1s. When this bit is set high, the incoming data stream is not examined for the abort sequence, and, if an incoming abort sequence is received, no action is taken. This bit is ignored when the HDLC controller is configured in the transparent mode (RTRANS = 1). Bit 8/Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC engine zero destuffs the incoming data stream. When this bit is set high, the HDLC engine does not zero destuff the incoming data stream. This bit is ignored when the HDLC engine is configured in the transparent mode (RTRANS = 1). 70 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: RHPL Receive HDLC Maximum Packet Length 0410h Bit # Name Default 7 RHPL7 0 6 RHPL6 0 5 RHPL5 0 4 RHPL4 0 3 RHPL3 0 2 RHPL2 0 1 RHPL1 0 0 RHPL0 0 Bit # Name Default 15 RHPL15 0 14 RHPL14 0 13 RHPL13 0 12 RHPL12 0 11 RHPL11 0 10 RHPL10 0 9 RHPL9 0 8 RHPL8 0 Note: Bits that are underlined are read-only; all other bits are read-write. This is a globe control; only one per device, not one for each individual HDLC channel. Bits 0 to 15/Receive HDLC Packet Length (RHPL0 to RHPL15). If the receive length-detection enable bit is set to 1, the HDLC engine checks the number of received octets in a packet to see if they exceed the count in this register. If the length is exceeded, the packet is aborted and the remainder is discarded. The definition of “octet length” is everything between the opening and closing flags, which includes the address field, control field, information field, and FCS. Register Name: Register Description: Register Address: THCDIS Transmit HDLC Channel Definition Indirect Select 0480h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0) 00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2) 00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit HDLC definition RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the THCD register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit HDLC definition RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the THCD register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation is complete. 71 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: THCD Transmit HDLC Channel Definition 0484h Bit # Name Default 7 TABTE 6 TCFCS 5 TBF 4 TID 3 TCRC1 2 TCRC0 1 TIFS 0 TTRANS Bit # Name Default 15 n/a 14 n/a 13 n/a 12 TZSD 11 TFG3 10 TFG2 9 TFG1 8 TFG0 Note: Bits that are underlined are read only, all other bits are read-write. Bit 0/Transmit Transparent Enable (TTRANS). When this bit is set low, the HDLC engine generates flags and the FCS (if enabled through TCRC0/1) and performs zero stuffing. When this bit is set high, the HDLC engine does not generate flags or the FCS and does not perform zero stuffing. 0 = transparent mode disabled 1 = transparent mode enabled Bit 1/Transmit Interfill Select (TIFS) 0 = the interfill byte is 7Eh (01111110) 1 = the interfill byte is FFh (11111111) Bits 2, 3/Transmit CRC Selection (TCRC0/TCRC1). These bits are ignored if the HDLC channel is set to transparent mode (TTRANS = 1). TCRC1 0 0 1 1 TCRC0 0 1 0 1 ACTION No CRC is generated 16-bit CRC (CCITT/ITU Q.921) 32-bit CRC Illegal state Bit 4/Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are not inverted after being generated. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and FCS) after the packet has been generated. 0 = do not invert data 1 = invert all data (including flags and FCS) Bit 5/Transmit Bit Flip (TBF). When this bit is set low, the HDLC engine obtains the first HDLC bit to be transmitted from the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high, the HDLC engine obtains the first HDLC bit to be transmitted from the highest bit position of the PCI bus bytes (i.e., PAD[7], PAD[15], PAD[23], PAD[31]). 0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the PCI bus 1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the PCI bus Bit 6/Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC engine allows the frame checksum sequence (FCS) to be transmitted as generated. When this bit is set high, the HDLC engine inverts all the bits of the FCS before transmission occurs. This is useful in debugging and testing HDLC channels at the system level. 0 = generate FCS normally 1 = invert all FCS bits Bit 7/Transmit Abort Enable (TABTE). When this bit is set low, the HDLC engine performs normally, only sending an abort sequence (eight 1s in a row) when an error occurs in the PCI block or the FIFO underflows. When this bit is set high, the HDLC engine continuously transmits an all-ones pattern (i.e., an abort sequence). This bit is still active when the HDLC engine is configured in the transparent mode (TTRANS = 1). 72 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bits 8 to 11/Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These four bits determine how many flags and interfill bytes are sent between consecutive packets. TFG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TFG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TFG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TFG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ACTION Share closing and opening flag Closing flag/no interfill bytes/opening flag Closing flag/1 interfill byte/opening flag Closing flag/2 interfill bytes/opening flag Closing flag/3 interfill bytes/opening flag Closing flag/4 interfill bytes/opening flag Closing flag/5 interfill bytes/opening flag Closing flag/6 interfill bytes/opening flag Closing flag/7 interfill bytes/opening flag Closing flag/8 interfill bytes/opening flag Closing flag/9 interfill bytes/opening flag Closing flag/10 interfill bytes/opening flag Closing flag/11 interfill bytes/opening flag Closing flag/12 interfill bytes/opening flag Closing flag/13 interfill bytes/opening flag Closing flag/14 interfill bytes/opening flag Bit 12/Transmit Zero Stuffing Disable (TZSD). When this bit is set low, the HDLC engine performs zero stuffing on the outgoing data stream. When this bit is set high, the outgoing data stream is not zero stuffed. This bit is ignored when the HDLC engine is configured in the transparent mode (TTRANS = 1). 73 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 8. FIFO 8.1 General Description and Example The DS31256 contains one 16kB FIFO for the receive path and another 16kB FIFO for the transmit path. Both of these FIFOs are organized into blocks. Since a block is defined as 4 dwords (16 Bytes), each FIFO is made up of 1024 blocks. Figure 8-1 shows an FIFO example. The FIFO contains a state machine that is constantly polling the 16 ports to determine if any data is ready for transfer to/from the FIFO from/to the HDLC engines. The 16 ports are priority decoded with port 0 getting the highest priority and port 15 getting the lowest priority. Therefore, all the enabled HDLC channels on the lower numbered ports are serviced before the higher numbered ports. As long as the maximum throughput rate of 132Mbps is not exceeded, the DS31256 ensures there is enough bandwidth in this transfer to prevent any data loss between the HDLC engines and the FIFO. The FIFO also controls which HDLC channel the DMA should service to read data out of the FIFO on the receive side and to write data into the FIFO on the transmit side. Which channel gets the highest priority from the FIFO is configurable through some control bits in the master configuration register (Section 5.2). There are two control bits for the receive side (RFPC0 and RFPC1) and two control bits for the transmit side (TFPC0 and TFPC1) that determine the priority algorithm as shown in Table 8-A. Table 8-A. FIFO Priority Algorithm Select OPTION 1 2 3 4 HDLC CHANNELS THAT ARE PRIORITY DECODED None 1 to 3 16 to 1 64 to 1 HDLC CHANNELS THAT ARE SERVICED ROUND ROBIN 1 to 256 4 to 256 17 to 256 65 to 256 To maintain maximum flexibility for channel reconfiguration, each block within the FIFO can be assigned to any of the 256 HDLC channels. Also, blocks are link-listed together to form a chain whereby each block points to the next block in the chain. The minimum size of the link-listed chain is 4 blocks (64 Bytes) and the maximum is the full size of the FIFO, which is 1024 blocks. To assign a set of blocks to a particular HDLC channel, the host must configure the starting block pointer and the block pointer RAM. The starting block pointer assigns a particular HDLC channel to a set of link-listed blocks by pointing to one of the blocks within the chain (it does not matter which block in the chain is pointed to). The block pointer RAM must be configured for each block that is being used within the FIFO. The block pointer RAM indicates the next block in the link-listed chain. Figure 8-1 shows an example of how to configure the starting block pointer and the block pointer RAM. In this example, only three HDLC channels are being used (channels 2, 6, and 16). The device knows that channel 2 has been assigned to the eight link-listed blocks of 112, 118, 119, 120, 121, 122, 125, and 126 because a block pointer of 125 has been programmed into the channel 2 position of the starting block pointer. The block pointer RAM tells the device how to link the eight blocks together to form a circular chain. The host must set the watermarks for the receive and transmit paths. The receive path has a high watermark and the transmit path has a low watermark. 74 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 8-1. FIFO Example HDLC Channel Number Starting Block Pointer 1024 Block FIFO (1 Block = 4 dwords) not used Block Pointer RAM not used CH 1 not used CH 2 Block Pointer 125 CH 3 not used CH 4 not used CH 5 not used CH 6 Block Pointer 113 CH 7 not used CH 8 not used CH 9 not used CH 10 not used Block 112 Channel 2 Block 112 Block 118 CH 11 not used Block 113 Channel 6 Block 113 Block 114 CH 12 not used Block 114 Channel 6 Block 114 Block 113 CH 13 not used Block 115 not used Block 115 not used CH 14 not used Block 116 not used Block 116 not used CH 15 not used Block 117 not used Block 117 not used CH 16 Block Pointer 5 Block 118 Channel 2 Block 118 Block 119 CH 17 not used Block 119 Channel 2 Block 119 Block 120 CH 18 not used Block 120 Channel 2 Block 120 Block 121 CH 19 not used Block 121 Channel 2 Block 121 Block 122 CH 20 not used Block 122 Channel 2 Block 122 Block 125 CH 21 not used Block 123 not used Block 123 not used Block 124 not used Block 124 not used Block 125 Channel 2 Block 125 Block 126 not used Block 126 Channel 2 Block 126 Block 112 not used Block 127 not used Block 127 not used Block 1022 not used Block 1022 not used Block 1023 not used Block 1023 not used CH 255 CH 256 fifobd.drw Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 not used Channel 16 Channel 16 Channel 16 Channel 16 not used 75 of 183 Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 not used Block 4 Block 5 Block 3 Block 2 not used DS31256 256-Channel, High-Throughput HDLC Controller 8.1.1 Receive High Watermark The high watermark tells the device how many blocks the HDLC engines should write into the receive FIFO before the DMA sends data to the PCI bus, or rather, how full the FIFO should get before it should be emptied by the DMA. When the DMA begins reading the data from the FIFO, it reads all available data and tries to completely empty the FIFO even if one or more EOFs (end of frames) are detected. For example, if four blocks were link-listed together and the host programmed the high watermark to three blocks, then the DMA would read the data out of the FIFO and transfer it to the PCI bus after the HDLC controller had written three complete blocks in succession into the FIFO and still had one block left to fill. The DMA would not read the data out of the FIFO again until another three complete blocks had been written into the FIFO in succession by the HDLC engine or until an EOF was detected. In this example of four blocks being link-listed together, the high watermark could also be set to 1 or 2, but no other values would be allowed. If an incoming packet does not fill the FIFO enough to reach the high watermark before an EOF is detected, the DMA still requests that the data be sent to the PCI bus; it does not wait for additional data to be written into the FIFO by the HDLC engines. 8.1.2 Transmit Low Watermark The low watermark tells the device how many blocks should be left in the FIFO before the DMA should begin getting more data from the PCI bus, or rather, how empty the FIFO should get before it should be filled again by the DMA. When the DMA begins reading the data from the PCI bus, it reads all available data and tries to completely fill the FIFO even if one or more EOFs (HDLC packets) are detected. For example, if five blocks were link-listed together and the host programmed the low watermark to two blocks, then the DMA would read the data from the PCI bus and transfer it to the FIFO after the HDLC engine has read three complete blocks in succession from the FIFO and, therefore, still had two blocks left before the FIFO was empty. The DMA would not read the data from the PCI bus again until another three complete blocks had been read from the FIFO in succession by the HDLC engines. In this example of five blocks being link-listed together, the low watermark could also be set to any value from 1 to 3 (inclusive) but no other values would be allowed. In other words, the tranmist low watermark can be set to a value of 1 to N - 2, where N = number of blocks linked together. When a new packet is written into a completely empty FIFO by the DMA, the HDLC engines wait until the FIFO fills beyond the low watermark or until an EOF is seen before reading the data out of the FIFO. 8.2 FIFO Register Description Register Name: Register Description: Register Address: RFSBPIS Receive FIFO Starting Block Pointer Indirect Select 0900h Bit # Name Default 6 HCID6 0 Bit # Name Default 7 HCID7 0 15 IAB 0 14 IARW 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 76 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently presetn in the RFSBP register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation completes. Register Name: Register Description: Register Address: RFSBP Receive FIFO Starting Block Pointer 0904h Bit # Name Default 7 RSBP7 6 RSBP6 5 RSBP5 4 RSBP4 3 RSBP3 2 RSBP2 1 RSBP1 0 RSBP0 Bit # Name Default 15 n/a 14 n/a 13 n/a 12 n/a 11 n/a 10 n/a 9 RSBP9 8 RSBP8 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Starting Block Pointer (RSBP0 to RSBP9). These bits determine which of the 1024 blocks within the receive FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits are read, they report the current block pointer being used to write data into the receive FIFO from the HDLC Layer 2 engines. 0000000000 (000h) = use block 0 as the starting block 0111111111 (1FFh) = use block 511 as the starting block 1111111111 (3FFh) = use block 1023 as the starting block Register Name: Register Description: Register Address: RFBPIS Receive FIFO Block Pointer Indirect Select 0910h Bit # Name Default 7 BLKID7 0 6 BLKID6 0 5 BLKID5 0 4 BLKID4 0 3 BLKID3 0 2 BLKID2 0 1 BLKID1 0 0 BLKID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 BLKID9 0 8 BLKID8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Block ID (BLKID0 to BLKID9) 0000000000 (000h) = block number 0 0111111111 (1FFh) = block number 511 1111111111 (3FFh) = block number 1023 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive block pointer RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal receive 77 of 183 DS31256 256-Channel, High-Throughput HDLC Controller block pointer RAM, the host should write this bit to 0. This causes the device to take the data that is currently present in the RFBP register and write it to the channel location indicated by the BLKID bits. When the device completes the write, the IAB is set to 0. Note: The RFSBP is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation completes. Register Name: Register Description: Register Address: RFBP Receive FIFO Block Pointer 0914h Bit # Name Default 7 RBP7 6 RBP6 5 RBP5 4 RBP4 3 RBP3 2 RBP2 1 RBP1 0 RBP0 Bit # Name Default 15 n/a 14 n/a 13 n/a 12 n/a 11 n/a 10 n/a 9 RBP9 8 RBP8 Note: Bits that are underlined are read only, all other bits are read-write. Bits 0 to 9/Block Pointer (RBP0 to RBP9). These bits indicate which of the 10242 blocks is the next block in the link-list chain. A block is not allowed to point to itself. 0000000000 (000h) = block 0 is the next linked block 0111111111 (1FFh) = block 511 is the next linked block 1111111111 (3FFh) = block 1023 is the next linked block Register Name: Register Description: Register Address: RFHWMIS Receive FIFO High-Watermark Indirect Select 0920h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive highwatermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFHWM register, the IAB bit is set to 0. When the host wishes to write data to the internal receive high-watermark RAM, this bit should be written to 0 by the host. This causes the device to take 78 of 183 DS31256 256-Channel, High-Throughput HDLC Controller the data that is currently present in the RFHWM register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: Register Description: Register Address: RFHWM Receive FIFO High Watermark 0924h Bit # Name Default 7 RHWM7 6 RHWM6 5 RHWM5 4 RHWM4 3 RHWM3 2 RHWM2 1 RHWM1 0 RHWM0 Bit # Name Default 15 n/a 14 n/a 13 n/a 12 n/a 11 n/a 10 n/a 9 RHWM9 8 RHWM8 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/High Watermark (RHWM0 to RHWM9). These bits indicate the setting of the receive highwatermark. The high-watermark setting is the number of successive blocks that the HDLC controller writes to the FIFO before the DMA sends the data to the PCI bus. The high-watermark setting must be between (inclusive) one block and one less than the number of blocks in the link-list chain for the particular channel involved. For example, if four blocks are linked together, the high watermark can be set to either 1, 2, or 3. In other words, the high watermark can be set to a value of 1 to N - 1, where N = number of block linked together. Any other numbers are illegal. 0000000000 (000h) = invalid setting 0000000001 (001h) = high watermark is 1 block 0000000010 (002h) = high watermark is 2 blocks 0111111111 (1FFh) = high watermark is 511 blocks 1111111111 (3FFh) = high watermark is 1023 blocks Register Name: Register Description: Register Address: TFSBPIS Transmit FIFO Starting Block Pointer Indirect Select 0980h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. 79 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to the internal transmit starting block pointer RAM, this bit should be written to 1 by the host. This causes the device to take the data that is in the TFSBP register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0. Note: The TFSBP register is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: Register Description: Register Address: TFSBP Transmit FIFO Starting Block Pointer 0984h Bit # Name Default 7 TSBP7 6 TSBP6 5 TSBP5 4 TSBP4 3 TSBP3 2 TSBP2 1 TSBP1 0 TSBP0 Bit # Name Default 15 n/a 14 n/a 13 n/a 12 n/a 11 n/a 10 n/a 9 TSBP9 8 TSBP8 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Starting Block Pointer (TSBP0 to TSBP9). These bits determine which of the 1024 blocks within the transmit FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits are read, they report the current block pointer being used to read data from the transmit FIFO by the HDLC Layer 2 engines. 0000000000 (000h) = use block 0 as the starting block 0111111111 (1FFh) = use block 511 as the starting block 1111111111 (3FFh) = use block 1023 as the starting block Register Name: Register Description: Register Address: TFBPIS Transmit FIFO Block Pointer Indirect Select 0990h Bit # Name Default 7 BLKID7 0 6 BLKID6 0 5 BLKID5 0 4 BLKID4 0 3 BLKID3 0 2 BLKID2 0 1 BLKID1 0 0 BLKID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 BLKID9 0 8 BLKID8 0 Note: Bits that are underlined are read-only; all other bits are read-write. 80 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bits 0 to 9/Block ID (BLKID0 to BLKID9) 00000000000 (000h) = block number 0 01111111111 (1FFh) = block number 511 1111111111 (3FFh) = block number 1023 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit block pointer RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the TFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit block pointer RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the TFBP register and write it to the channel location indicated by the BLKID bits. When the device has completed the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: Register Description: Register Address: TFBP Transmit FIFO Block Pointer 0994h Bit # Name Default 7 TBP7 6 TBP6 5 TBP5 4 TBP4 3 TBP3 2 TBP2 1 TBP1 0 TBP0 Bit # Name Default 15 n/a 14 n/a 13 n/a 12 n/a 11 n/a 10 n/a 9 TBP9 8 TBP8 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Block Pointer (TBP0 to TBP9). These bits indicate which of the 1024 blocks is the next block in the link list chain. A block is not allowed to point to itself. 0000000000 (000h) = block 0 is the next linked block 0111111111 (1FFh) = block 511 is the next linked block 1111111111 (3FFh) = block 1023 is the next linked block Register Name: Register Description: Register Address: TFLWMIS Transmit FIFO Low-Watermark Indirect Select 09A0h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only, all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 81 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit lowwatermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the TFLWM register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit low-watermark RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the TFLWM register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: Register Description: Register Address: TFLWM Transmit FIFO Low Watermark 09A4h Bit # Name Default 7 TLWM7 6 TLWM6 5 TLWM5 4 TLWM4 3 TLWM3 2 TLWM2 1 TLWM1 0 TLWM0 Bit # Name Default 15 n/a 14 n/a 13 n/a 12 n/a 11 n/a 10 n/a 9 TLWM9 8 TLWM8 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Low Watermark (TLWM0 to TLWM9). These bits indicate the setting of the transmit low watermark. The low watermark setting is the number of blocks left in the transmit FIFO before the DMA gets more data from the PCI bus. The low-watermark setting must be between (inclusive) one block and one less than the number of blocks in the link-list chain for the particular channel involved. For example, if five blocks are linked together, the low watermark can be set to 1, 2, or 3. In other words, the low watermark can be set at a value of 1 to N - 2, where N = number of block linked together. Any other numbers are illegal. 0000000000 (000h) = invalid setting 0000000001 (001h) = low watermark is 1 block 0000000010 (002h) = low watermark is 2 blocks 0111111111 (1FFh) = low watermark is 511 blocks 1111111111 (3FFh) = low watermark is 1023 blocks 82 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9. DMA 9.1 Introduction The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block and vice versa. Throughout this section, the terms host and descriptor are used. Host is defined as the CPU or intelligent controller that sits on the PCI bus and instructs the device about how to handle the incoming and outgoing packet data. Descriptor is defined as a preformatted message that is passed from the host to the DMA block or vice versa to indicate where packet data should be placed or obtained from. On power-up, the DMA is disabled because the RDE and TDE control bits in the master configuration register (Section 5) are set to 0. The host must configure the DMA by writing to all of the registers listed in Table 9-A (which includes all 256 channel locations in the receive and transmit configuration RAMs), then enable the DMA by setting to the RDE and TDE control bits to 1. The structure of the DMA is such that the receive- and transmit-side descriptor-address spaces can be shared, even among multiple chips on the same bus. Through the master control register, the host determines how long the DMA is allowed to burst onto the PCI bus. The default value is 32 dwords (128 Bytes) but, through the DT0 and DT1 control bits, the host can enable the receive or transmit DMAs to burst either 64 dwords (256 Bytes), 128 dwords (512 Bytes), or 256 dwords (1024 Bytes). The receive and transmit packet descriptors have almost identical structures (Sections 9.2.2 and 9.3.2), which provide a minimal amount of host intervention in store-and-forward applications. In other words, the receive descriptors created by the receive DMA can be used directly by the transmit DMA. The receive and transmit portions of the DMA are completely independent and are discussed separately. The DS31256 has no restrictions on the transmit side, but has the following restrictions on the location and size of receive buffers in host memory: • • All receive buffers must start on a DWORD aligned address. All receive buffers must have a size in bytes that is a multiple of 4. 83 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 9-A. DMA Registers to be Configured by the Host on Power-Up ADDRESS NAME 0700 0704 0708 070C 0710 0714 0718 071C 0730 0734 0738 073C 0740 0744 0750 0754 0770 0774 0780 0790 0794 0800 0804 0808 080C 0810 0830 0834 0838 083C 0840 0844 0850 0854 0870 0874 0880 RFQBA0 RFQBA1 RFQEA RFQSBSA RFQLBWP RFQSBWP RFQLBRP RFQSBRP RDQBA0 RDQBA1 RDQEA RDQRP RDQWP RDQFFT RDBA0 RDBA1 RDMACIS RDMAC RDMAQ RLBS RSBS TPQBA0 TPQBA1 TPQEA TPQWP TPQRP TDQBA0 TDQBA1 TDQEA TDQRP TDQWP TDQFFT TDBA0 TDBA1 TDMACIS TDMAC TDMAQ REGISTER Receive Free-Queue Base Address 0 (lower word) Receive Free-Queue Base Address 1 (upper word) Receive Free-Queue End Address Receive Free-Queue Small Buffer Start Address Receive Free-Queue Large Buffer Host Write Pointer Receive Free-Queue Small Buffer Host Write Pointer Receive Free-Queue Large Buffer DMA Read Pointer Receive Free-Queue Small Buffer DMA Read Pointer Receive Done-Queue Base Address 0 (lower word) Receive Done-Queue Base Address 1 (upper word) Receive Done-Queue End Address Receive Done-Queue Host Read Pointer Receive Done-Queue DMA Write Pointer Receive Done-Queue FIFO Flush Timer Receive Descriptor Base Address 0 (lower word) Receive Descriptor Base Address 1 (upper word) Receive DMA Configuration Indirect Select Receive DMA Configuration (all 256 channels) Receive DMA Queues Control Receive Large Buffer Size Receive Small Buffer Size Transmit Pending-Queue Base Address 0 (lower word) Transmit Pending-Queue Base Address 1 (upper word) Transmit Pending-Queue End Address Transmit Pending-Queue Host Write Pointer Transmit Pending-Queue DMA Read Pointer Transmit Done-Queue Base Address 0 (lower word) Transmit Done-Queue Base Address 1 (upper word) Transmit Done-Queue End Address Transmit Done-Queue Host Read Pointer Transmit Done-Queue DMA Write Pointer Transmit Done-Queue FIFO Flush Timer Transmit Descriptor Base Address 0 (lower word) Transmit Descriptor Base Address 1 (upper word) Transmit DMA Configuration Indirect Select Transmit DMA Configuration (all 256 channels) Transmit Queues FIFO Control 84 of 183 SECTION 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.3 9.2.4 9.2.4 9.2.4 9.2.4 9.2.4 9.2.4 9.2.2 9.2.2 9.2.5 9.2.5 9.2.3, 9.2.4 9.2.1 9.2.1 9.3.3 9.3.3 9.3.3 9.3.3 9.3.3 9.3.4 9.3.4 9.3.4 9.3.4 9.3.4 9.3.4 9.3.2 9.3.2 9.3.5 9.3.5 9.3.3, 9.3.4 DS31256 256-Channel, High-Throughput HDLC Controller 9.2 Receive Side 9.2.1 Overview The receive DMA uses a scatter-gather technique to write packet data into main memory. The host keeps track of and decides where the DMA should place the incoming packet data. There are a set of descriptors that get handed back and forth between the DMA and the host. Through these descriptors, the host can inform the DMA where to place the packet data and the DMA can tell the host when the data is ready to be processed. The operation of the receive DMA has three main areas, as shown in Figure 9-1, Figure 9-2, and Table 9-B. The host writes to the free-queue descriptors informing the DMA where it can place the incoming packet data. Associated with each free data buffer location is a free packet descriptor where the DMA can write information to inform the host about the attributes of the packet data (i.e., status information, number of bytes, etc.) that it outputs. To accommodate the various needs of packet data, the host can quantize the free data buffer space into two different buffer sizes. The host sets the size of the buffers through the receive large buffer size (RLBS) and the receive small buffer size (RSBS) registers. Register Name: Register Description: Register Address: RLBS Receive Large Buffer Size Select 0790h Bit # Name Default 7 LBS7 0 6 LBS6 0 5 LBS5 0 4 LBS4 0 3 LBS3 0 2 LBS2 0 1 LBS1 0 0 LBS0 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 LBS12 0 11 LBS11 0 10 LBS10 0 9 LBS9 0 8 LBS8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 12/Large Buffer Select Bit (LBS0 to LBS12) 0000000000000 (0000h) = buffer size is 0 Bytes 1111111111100 (1FFCh) = buffer size is 8188 Bytes Register Name: Register Description: Register Address: RSBS Receive Small Buffer Size Select 0794h Bit # Name Default 7 SBS7 0 6 SBS6 0 5 SBS5 0 4 SBS4 0 3 SBS3 0 2 SBS2 0 1 SBS1 0 0 SBS0 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 SBS12 0 11 SBS11 0 10 SBS10 0 9 SBS9 0 8 SBS8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 12/Small Buffer Select Bit (SBS0 to SBS12) 0000000000000 (0000h) = buffer size is 0 Bytes 1111111111100 (1FFCh) = buffer size is 8188 Bytes 85 of 183 DS31256 256-Channel, High-Throughput HDLC Controller On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers for the incoming packet data on that particular HDLC channel. The host has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer, then, if the incoming packet requires more buffer space, use one or more large buffers for the remainder of the packet. The host selects the option through the size field in the receive configuration RAM (Section 9.2.5). Large buffers are best used for data-intensive, time-insensitive packets like graphics files, whereas small buffers are best used for time-sensitive information like real-time voice. Table 9-B. Receive DMA Main Operational Areas DESCRIPTORS Packet Free Queue Done Queue FUNCTION A dedicated area of memory that describes the location and attributes of the packet data. A dedicated area of memory that the host writes to inform the DMA where to store incoming packet data. A dedicated area of memory that the DMA writes to inform the host that the packet data is ready for processing. SECTION 9.2.2 9.2.3 9.2.4 The done-queue descriptors contain information that the DMA wishes to pass to the host. Through the done-queue descriptors, the DMA informs the host about the incoming packet data and where to find the packet descriptors that it has written into main memory. Each completed descriptor contains the starting address of the data buffer where the packet data is stored. If enabled, the DMA can burst read the free-queue descriptors and burst write the done-queue descriptors. This helps minimize PCI bus accesses, freeing the PCI bus up to do more time critical functions. See Sections 9.2.3 and 9.2.4 for more details about this feature. Receive DMA Actions A typical scenario for the receive DMA is as follows: 1) The receive DMA gets a request from the receive FIFO that it has packet data that needs to be sent to the PCI bus. 2) The receive DMA determines whether the incoming packet data should be stored in a large buffer or a small buffer. 3) The receive DMA then reads a free-queue descriptor (either by reading a single descriptor or a burst of descriptors), indicating where, in main memory, there exists some free data buffer space and where the associated free packet descriptor resides. 4) The receive DMA starts storing packet data in the previously free buffer data space by writing it out through the PCI bus. 5) When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it can calculate this), it then reads another free-queue descriptor to find another free data buffer and packet descriptor location. 6) The receive DMA then writes the previous packet descriptor and creates a linked list by placing the current descriptor in the next descriptor pointer field; it then starts filling the new buffer location. Figure 9-1 provides an example of packet descriptors being link listed together (see channel 2). 7) This continues until the entire packet data is stored. 8) The receive DMA either waits until a packet has been completely received or until a programmable number (from 1 to 7) of data buffers have been filled before writing the done-queue descriptor, which indicates to the host that packet data is ready for processing. 86 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Host Actions The host typically handles the receive DMA as follows: 1) The host is always trying to make free data buffer space available and therefore tries to fill the freequeue descriptor. 2) The host either polls, or is interrupted, when some incoming packet data is ready for processing. 3) The host then reads the done-queue descriptor circular queue to find out which channel has data available, what the status is, and where the receive packet descriptor is located. 4) The host then reads the receive packet descriptor and begins processing the data. 5) The host then reads the next descriptor pointer in the link-listed chain and continues this process until either a number (from 1 to 7) of descriptors have been processed or an end of packet has been reached. 6) The host then checks the done-queue descriptor circular queue to see if any more data buffers are ready for processing. 87 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-1. Receive DMA Operation Free Queue Descriptors (circular queue) 00h Free Data Buffer Address unused 08h 10h Free Desc. Ptr. Free Data Buffer Address unused Free Desc. Ptr. Free Data Buffer Address unused Free Desc. Ptr. Open Descriptor Space Available for Use by the DMA Open Descriptor Space Available for Use by the DMA Free Data Buffer (up to 8188 bytes) Free Data Buffer (up to 8188 bytes) Free Packet Descriptors & Data Buffers Used Packet Descriptors & Data Buffers Done Queue Descriptors (circular queue) 00h EOF Status CH #5 Desc. Ptr. 04h EOF Status CH #2 Desc. Ptr. 08h EOF Status 0Ch EOF Status CH #9 Desc. Ptr. CH # Desc. Ptr. Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #2 Unused Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #5 Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #2 Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #2 dmarbd Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #9 88 of 183 First Filled Data Buffer for Channel 2 Single Filled Data Buffer for Channel 5 Second Filled Data Buffer for Channel 2 Last Filled Data Buffer for Channel 2 Single Filled Data Buffer for Channel 9 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-2. Receive DMA Memory Organization Main Off-Board Memory (32-Bit Address Space) Internal Registers Free Data Buffer Space Used Data Buffer Space Free-Queue Base Address (32) Free-Queue Large Buffer Host Write Pointer (16) Free-Queue Large Buffer DMA Read Pointer (16) Receive Free-Queue Descriptors: Contains 32-Bit Addresses for Free Data Buffers and their Associated Free Packet Descriptors Free-Queue Small Buffer Start Address (16) Free-Queue Small Buffer Host Write Pointer (16) Free-Queue Small Buffer DMA Read Pointer (16) Up to 64k Dual dwords Free-Queue Descriptors Allowed Free-Queue End Address (16) Done-Queue Base Address (32) Done-Queue DMA Write Pointer (16) Receive Done-Queue Descriptors: Contains Index Pointers to Used Packet Descriptors Done-Queue Host Read Pointer (16) Up to 64k dwords Done-Queue Descriptors Allowed Done-Queue End Address (16) Descriptor Base Address (32) Receive Packet Descriptors: Contains 32-Bit Addresses to Free Buffer as well as Status/Control Information and Links to Other Packet Descriptors Up to 64k Quad dwords Descriptors Allowed 89 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.2.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the receive packet descriptors resides in main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed anywhere in the 32-bit address space through the receive descriptor base address (Table 9-C). A data buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a contiguous section of main memory. The host can set two different data buffer sizes through the receive large buffer size (RLBS) and the receive small buffer size (RSBS) registers (Section 9.2.1). If an incoming packet requires more space than the data buffer allows, packet descriptors are link-listed together by the DMA to provide a chain of data buffers. Figure 9-3 shows an example of how three descriptors were linked together for an incoming packet on HDLC channel 2. Figure 9-2 shows a similar example. Channel 9 only required a single data buffer and therefore only one packet descriptor was used. Packet descriptors can be either free (available for use by the DMA) or used (currently contain data that needs to be processed by the host). The free-queue descriptors point to the free-packet descriptors. The done-queue descriptors point to the used-packet descriptors. Table 9-C. Receive Descriptor Address Storage REGISTER Receive Descriptor Base Address 0 (lower word) Receive Descriptor Base Address 1 (upper word) NAME RDBA0 RDBA1 ADDRESS 0750h 0754h Figure 9-3. Receive Descriptor Example Base + 00h Free-Queue Descriptor Address Done-Queue Descriptor Pointer Base + 10h Channel 2 First Buffer Descriptor Base + 20h Channel 9 Single Buffer Descriptor Base + 30h Free Descriptor Base + 40h Free Descriptor Base + 50h Channel 2 Second Buffer Descriptor Base + 60h Free Descriptor Base + 70h Base + 80h Maximum of 65,536 Descriptors Free Descriptor Channel 2 Last Buffer Descriptor Free Descriptor Base + FFFD0h Free Descriptor Base + FFFF0h Free Descriptor 90 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-4. Receive Packet Descriptors dword 0 Data Buffer Address (32) dword 1 BUFS (3) dword 2 Byte Count (13) Next Descriptor Pointer (16) Timestamp (24) HDLC Channel (8) dword 3 unused (32) Note: The organization of the receive descriptor is not affected by the enabling of Big Endian. dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of the data buffer that is associated with this receive descriptor. dword 1; Bits 0 to 15/Next Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of the next descriptor in the chain. Only valid if buffer status = 001 or 010. Note: This is an index, not absolute address. dword 1; Bits 16 to 28/Byte Count. Number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes). dword 1; Bits 29 to 31/Buffer Status. Must be one of the three states listed below. 001 = first buffer of a multiple buffer packet 010 = middle buffer of a multiple buffer packet 100 = last buffer of a multiple or single buffer packet (equivalent to EOF) dword 2; Bits 0 to 7/HDLC Channel Number. HDLC channel number, which can be from 1 to 256. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 dword 2; Bits 8 to 31/Timestamp. When each descriptor is written into memory by the DMA, this 24-bit timestamp is provided to keep track of packet arrival times. The timestamp is based on the PCLK frequency divided by 16. For a 33MHz PCLK, the timestamp increments every 485ns and rolls over every 8.13 seconds. For a 25MHz clock, the timestamp increments every 640ns and rolls over every 10.7 seconds. The host can calculate the difference in packets’ arrival times by knowing the PCLK frequency and then taking the difference in timestamp readings between consecutive packet descriptors. dword 3; Bits 0 to 31/Unused. Not written to by the DMA. Can be used by the host. Application Note: dword 3 is used by the transmit DMA and, in store and forward applications, the receive and transmit packet descriptors have been designed to eliminate the need for the host to groom the descriptors before transmission. In these type of applications, the host should not use dword 3 of the receive packet descriptor. 91 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.2.3 Free Queue The host writes the 32-bit addresses of the available (free) data buffers and their associated packet descriptors to the receive free queue. The descriptor space is indicated through a 16-bit pointer, which the DMA uses along with the receive packet descriptor base address to find the exact 32-bit address of the associated receive packet descriptor. Figure 9-5. Receive Free-Queue Descriptor dword 0 Free Data Buffer Address (32) dword 1 Unused (16) Free Packet Descriptor Pointer (16) Note: The organization of the free queue is not affected by the enabling of Big Endian. dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of a free data buffer. dword 1; Bits 0 to 15/Free Packet Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of the free descriptor space associated with the free data buffer in dword 0. Note: This is an index, not an absolute address. dword 1; Bits 16 to 31/Unused. Not used by the DMA. Can be set to any value by the host and is ignored by the receive DMA. The receive DMA reads from the receive free-queue descriptor circular queue which data buffers and their associated descriptors are available for use by the DMA. The receive free-queue descriptor is actually a set of two circular queues (Figure 9-6). There is one circular queue that indicates where free large buffers and their associated free descriptors exist. There is another circular queue that indicates where free small buffers and their associated free descriptors exist. Large and Small Buffer Size Handling Through the receive configuration-RAM buffer-size field, the DMA knows for a particular HDLC channel whether the incoming packets should be stored in the large or the small free data buffers. The host informs the DMA of the size of both the large and small buffers through the receive large and small buffer size (RLBS/RSBS) registers. For example, when the DMA knows that data is ready to be written onto the PCI bus, it checks to see if the data is to be sent to a large buffer or a small buffer, and then it goes to the appropriate free-queue descriptor and pulls the next available free buffer address and free descriptor pointer. If the host wishes to have only one buffer size, then the receive free queue smallbuffer start address is set equal to the receive free-queue end address. In the receive configuration RAM, none of the active HDLC channels are configured for the small buffer size. There are a set of internal addresses within the device to keep track of the addresses of the dual circular queues in the receive free queue. These are accessed by the host and the DMA. On initialization, the host configures all the registers shown in Table 9-E. After initialization, the DMA only writes to (changes) the read pointers and the host only writes to the write pointers. 92 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty State read pointer > empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor < write pointer Full Case The receive free queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty. Receive Free-Queue Full State read pointer > valid descriptor valid descriptor empty descriptor valid descriptor valid descriptor valid descriptor valid descriptor < write pointer Table 9-D describes how to calculate the absolute 32-bit address of the read and write pointers for the receive free queue. Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation BUFFER Large Small ALGORITHM Absolute Address = Free Queue Base + Write Pointer x 8 Absolute Address = Free Queue Base + Read Pointer x 8 Absolute Address = Free Queue Base + Small Buffer Start x 8 + Write Pointer x 8 Absolute Address = Free Queue Base + Small Buffer Start x 8 + Read Pointer x 8 Table 9-E. Receive Free-Queue Internal Address Storage REGISTER Receive Free-Queue Base Address 0 (lower word) Receive Free-Queue Base Address 1 (upper word) Receive Free-Queue Large Buffer Host Write Pointer Receive Free-Queue Large Buffer DMA Read Pointer Receive Free-Queue Small Buffer Start Address Receive Free-Queue Small Buffer Host Write Pointer Receive Free-Queue Small Buffer DMA Read Pointer Receive Free-Queue End Address NAME RFQBA0 RFQBA1 RFQLBWP RFQLBRP RFQSBSA RFQSBWP RFQSBRP RFQEA ADDRESS 0700h 0704h 0710h 0718h 070Ch 0714h 071Ch 0708h Note: Both RFQSBSA and RFQEA are not absolute addresses, i.e., the absolute end address is “Base + RFQEA x 8.” 93 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-6. Receive Free-Queue Structure Free-Queue Large Buffer Host Write Pointer Free-Queue Large Buffer DMA Read Pointer Base + 00h Host Readied Free-Queue Descriptor Base + 08h DMA Acquired Free-Queue Descriptor Base + 10h DMA Acquired Free-Queue Descriptor Base + 18h DMA Acquired Free-Queue Descriptor Base + 20h Host Readied Free-Queue Descriptor Large Buffer Circular Queue Host Readied Free-Queue Descriptor Free-Queue Small Buffer Start Address Host Readied Free-Queue Descriptor Host Readied Free Queue Descriptor Free-Queue Small Buffer Host Write Pointer DMA Acquired Free-Queue Descriptor DMA Acquired Free-Queue Descriptor Small Buffer Circular Queue DMA Acquired Free-Queue Descriptor Free-Queue Small Buffer DMA Read Pointer Maximum of 65,536 Free-Queue Descriptors Base + End Address Host Readied Free-Queue Descriptor Host Readied Free-Queue Descriptor Once the receive DMA is activated (by setting the RDE control bit in the master configuration register, see Section 5), it can begin reading data out of the free queue. It knows where to read data out of the free queue by reading the read pointer and adding it to the base address to obtain the actual 32-bit address. Once the DMA has read the free queue, it increments the read pointer by two dwords. A check must be made to ensure the incremented address does not equal or exceed either the receive free-queue smallbuffer start address (in the case of the large buffer circular queue) or the receive free-queue end address (in the case of the small buffer circular queue). If the incremented address does equal or exceed either of these addresses, the incremented read pointer is set equal to 0000h. 94 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Status/Interrupts On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for receive DMA small buffer read (RSBR) in the status register for DMA (SDMA). The DMA also checks the receive free-queue large-buffer host write pointer and the receive free-queue small-buffer host write pointer to ensure that an underflow does not occur. If it does occur, the DMA sets either the status bit for receive DMA large buffer read error (RLBRE) or the status bit for receive DMA small buffer read error (RSBRE) in the status register for DMA (SDMA), and it does not read the free queue nor does it increment the read pointer. In such a scenario, the receive FIFO can overflow if the host does not provide free-queue descriptors. Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 5 for more details. Free-Queue Burst Reading The DMA can read the free queue in bursts, which allows for a more efficient use of the PCI bus. The DMA can grab messages from the free queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions. An internal FIFO stores up to 16 free-queue descriptors (32 dwords, as each descriptor occupies two dwords). The free queue can either opeate in dual or singular circular queue mode. It can be divided into large buffer and small buffer. The LBSA (large buffer starting address) and the LBEA (large buffer ending address) form the large buffer queue, and the SBSA (small buffer starting address) and the RFQEA (receive free-queue end address) form the small buffer queue. When the SBSA is not equal to and greater than the RFQEA, the free queue is set up in a dual circular mode. If the SBSA is equal to the FRQEA, the free queue is operating in a single queue mode. When the free queue is operated as a dual circular queue supporting both large and small buffers, then the FIFO is cut into two 8-message FIFOs. If the free queue is operated as a single circular queu supporting only the large buffers, then the FIFO is set up as a single 16-descriptor FIFO. The host must configure the free-queue FIFO for proper operation through the receive DMA queues control (RDMAQ) register (see the following). When enabled through the receive free-queue FIFO-enable (RFQFE) bit, the free-queue FIFO does not read the free queue until it reaches the low watermark. When the FIFO reaches the low watermark (which is two descriptors in the dual mode or four descriptors in the single mode), it attempts to fill the FIFO with additional descriptors by burst reading the free queue. Before it reads the free queue, it checks (by examining the receive free-queue host write pointer) to ensure the free queue contains enough descriptors to fill the free-queue FIFO. If the free queue does not have enough descriptors to fill the FIFO, it only reads enough to keep from underflowing the free queue. If the FIFO detects that there are no free-queue descriptors available for it to read, then it sets either the status bit for the receive DMA large buffer read error (RLBRE) or the status bit for the receive DMA small buffer read error (RSBRE) in the status register for DMA (SDMA); it does not read the free queue nor does it increment the read pointer. In such a scenario, the receive FIFO can overflow if the host does not provide free-queue descriptors. If the free-queue FIFO can read descriptors from the free queue, it burst reads them, increments the read pointer, and sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for the receive DMA small buffer read (RSBR) in the status register for DMA (SDMA). See Section 5 for more details on status bits. 95 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: RDMAQ Receive DMA Queues Control 0780h Bit # Name Default 7 n/a 0 6 n/a 0 5 RDQF 0 4 RDQFE 0 3 RFQSF 0 2 RFQLF 0 1 n/a 0 0 RFQFE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 RDQT2 0 9 RDQT1 0 8 RDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Receive Free-Queue FIFO Enable (RFQFE). To enable the DMA to burst read descriptors from the free queue, this bit must be set to 1. If this bit is set to 0, descriptors are read one at a time. 0 = free-queue burst read disabled 1 = free-queue burst read enabled Bit 2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). When this bit is set to 1, the internal large buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). When this bit is set to 1, the internal small buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed Bit 4/Receive Done-Queue FIFO Enable (RDQFE). See Section 9.2.4 for details. Bit 5/Receive Done-Queue FIFO Flush (RDQF). See Section 9.2.4 for details. Bits 8 to 10/Receive Done-Queue Status Bit Threshold Setting (RDQT0 to RDQT2). See Section 9.2.4 for details. 96 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.2.4 Done Queue The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the associated packet descriptor with all the necessary information. The descriptor location is indicated through a 16-bit pointer that the host uses with the receive descriptor base address to find the exact 32-bit address of the associated receive descriptor. Figure 9-7. Receive Done-Queue Descriptor dword 0 V EOF Status(3) BUFCNT(3) HDLC Channel (8) Descriptor Pointer (16) Note 1: The organization of the done queue is not affected by the enabling of Big Endian. Note 2: Descriptor pointer is an index, not an absolute address. dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of a receive packet descriptor that has been readied by the DMA and is available for the host to begin processing. Note: This is an index, not an absolute address. dword 0; Bits 16 to 23/HDLC Channel Number. This is an HDLC channel number, which can be from 1 to 256. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 dword 0; Bits 24 to 26/Buffer Count (BUFCNT). If an HDLC channel has been configured to only write to the done queue after a packet has been completely received (i.e., the threshold field in the receive DMA configuration RAM is set to 000), then BUFCNT is always set to 000. If the HDLC channel has been configured through the threshold field to write to the done queue after a programmable number of buffers (from 1 to 7) has been filled, then BUFCNT corresponds to the number of buffers that have been written to host memory. The BUFCNT is less than the threshold field value when the incoming packet does not require the number of buffers specified in the threshold field. 000 = indicates that a complete packet has been received (only used when threshold = 000) 001 = 1 buffer has been filled 010 = 2 buffers have been filled 111 = 7 buffers have been filled dword 0; Bits 27 to 29/Packet Status. These three bits report the final status of an incoming packet. They are only valid when the EOF bit is set to 1 (EOF = 1). 000 = no error, valid packet received 001 = receive FIFO overflow (remainder of the packet discarded) 010 = CRC checksum error 011 = HDLC frame abort sequence detected (remainder of the packet discarded) 100 = nonaligned byte count error (not an integral number of bytes) 101 = long frame abort (max packet length exceeded; remainder of the packet discarded) 110 = PCI abort (remainder of the packet discarded) 111 = reserved state (never occurs in normal device operation) dword 0; Bit 30/End of Frame (EOF). This bit is set to 1 when this receive descriptor is the last one in the current descriptor chain. This indicates that a packet has been fully received or an error has been detected, which has caused a premature termination. dword 0; Bit 31/Valid Done-Queue Descriptor (V). This bit is set to 0 by the receive DMA. Instead of reading the receive done-queue read pointer to locate completed done-queue descriptors, the host can use this bit, since the DMA sets the bit to 0 when it is written into the queue. If the latter scheme is used, the host must set this bit to 1 when the done queue descriptor is read. 97 of 183 DS31256 256-Channel, High-Throughput HDLC Controller The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing. The receive done queue is circular. A set of internal addresses within the device that are accessed by the host and the DMA keep track of the queue’s addresses. On initialization, the host configures all the registers, as shown in Table 9-F. After initialization, the DMA only writes to (changes) the write pointer and the host only writes to the read pointer. Empty Case The receive done queue is considered empty when the read and write pointers are identical. Receive Done-Queue Empty State read pointer > empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor < write pointer Full Case The receive done queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty. Receive Done-Queue Full State read pointer > valid descriptor valid descriptor empty descriptor valid descriptor valid descriptor valid descriptor valid descriptor < write pointer Table 9-F. Receive Done-Queue Internal Address Storage REGISTER Receive Done-Queue Base Address 0 (lower word) Receive Done-Queue Base Address 1 (upper word) Receive Done-Queue DMA Write Pointer Receive Done-Queue Host Read Pointer Receive Done-Queue End Address Receive Done-Queue FIFO Flush Timer NAME ADDRESS RDQBA0 RDQBA1 RDQWP RDQRP RDQEA RDQFFT 0730h 0734h 0740h 073Ch 0738h 0744h Note: Receive done-queue end address is not an absolute address. The absolute end address is “Base + RDQEA x 4.” 98 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-8. Receive Done-Queue Structure Done-Queue DMA Write Pointer Done-Queue Host Read Pointer Base + 00h DMA Readied Done-Queue Descriptor Base + 04h DMA Readied Done-Queue Descriptor Base + 08h Host Processed Done-Queue Descriptor Base + 0Ch Host Processed Done-Queue Descriptor Base + 10h Host Processed Done-Queue Descriptor Base + 14h DMA Readied Done-Queue Descriptor Base + End Address DMA Readied Done-Queue Descriptor Maximum of 65,536 Done-Queue Descriptors Once the receive DMA is activated (through the RDE control bit in the master configuration register, see Section 5), it can begin writing data to the done queue. It knows where to write data into the done queue by reading the write pointer and adding it to the base address to obtain the actual 32-bit address. Once the DMA has written to the done queue, it increments the write pointer by one dword. A check must be made to ensure the incremented address does not exceed the receive done-queue end address. If the incremented address exceeds this address, the incremented write pointer is set equal to 0000h (i.e., the base address). Status Bits/Interrupts On writes to the done queue by the DMA, the DMA sets the status bit for the receive DMA done-queue write (RDQW) in the SDMA. The host can configure the DMA to either set this status bit on each write to the done queue or only after multiple (from 2 to 128) writes. The host controls this by setting the RDQT0 to RDQT2 bits in the receive DMA queues control (RDMAQ) register. See the description of the RDMAQ register at the end of Section 9.2.4 for more details. The DMA also checks the receive done-queue host read pointer to ensure an overflow does not occur. If this does occur, the DMA then sets the status bit for the receive DMA done-queue write error (RDQWE) in the status register for DMA (SDMA), and it does not write to the done queue nor does it increment the write pointer. In such a scenario, packets can be lost and unrecoverable. Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 5 for more details. Buffer Write Threshold Setting In the DMA configuration RAM (Section 9.2.5), there is a host-controlled field called “threshold” (bits RDT0 to RDT2) that informs the DMA when it should write to the done queue. The host has the option to have the DMA place information in the done queue after a programmable number (from 1 to 7) data 99 of 183 DS31256 256-Channel, High-Throughput HDLC Controller buffers have been filled or wait until the completed packet data has been written. The DMA always writes to the done queue when it has finished receiving a packet, even if the threshold has not been met. Done-Queue Burst Writing The DMA can write to the done queue in bursts, which allows for a more efficient use of the PCI bus. The DMA can hand off descriptors to the done queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions. An internal FIFO stores up to eight done-queue descriptors (8 dwords as each descriptor occupies one dword). The host must configure the FIFO for proper operation through the receive DMA queues-control (RDMAQ) register (see the following). When enabled through the receive done-queue FIFO-enable (RDQFE) bit, the done-queue FIFO does not write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the high watermark (which is six descriptors), it attempts to empty the done-queue FIFO by burst writing to the done queue. Before it writes to the done queue, it checks (by examining the receive done-queue host read pointer) to ensure the done queue has enough room to empty the done-queue FIFO. If the done queue does not have enough room, then it only burst writes enough descriptors to keep from overflowing the done queue. If the FIFO detects that there is no room for any descriptors to be written, it sets the status bit for the receive DMA done-queue write error (RDQWE) in the status register for DMA (SDMA). It does not write to the done queue nor does it increment the write pointer. In such a scenario, packets can be lost and unrecoverable. If the done-queue FIFO can write descriptors to the done queue, it burst writes them, increments the write pointer, and sets the status bit for the receive DMA done-queue write (RDQW) in the status register for DMA (SDMA). See Section 5 for more details on status bits. Done-Queue FIFO Flush Timer To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the DMA uses the receive done-queue FIFO flush timer (RDQFFT) to determine the maximum wait time between writes. The RDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256. It is only monitored by the DMA when the receive done-queue FIFO is enabled (RDQFE = 1). For a 33MHz PCLK, the timer is decremented every 7.76µs. For a 25MHz clock, it is decremented every 10.24µs. Each time the DMA writes to the done queue it resets the timer to the count placed into it by the host. On initialization, the host sets a value into the RDQFFT that indicates the maximum time the DMA should wait in between writes to the done queue. For example, with a PCLK of 33MHz, the range of wait times is from 7.8µs (RDQFFT = 0001h) to 508ms (RDQFFT = FFFFh). With a PCLK of 25MHz, the wait times range from 10.2µs (RDQFFT = 0001h) to 671ms (RDQFFT = FFFFh). 100 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: RDQFFT Receive Done-Queue FIFO Flush Timer 0744h Bit # Name Default 7 TC7 0 6 TC6 0 5 TC5 0 4 TC4 0 3 TC3 0 2 TC2 0 1 TC1 0 0 TC0 0 Bit # Name Default 15 TC15 0 14 TC14 0 13 TC13 0 12 TC12 0 11 TC11 0 10 TC10 0 9 TC9 0 8 TC8 0 Note: Bits that are underlined are read-only, all other bits are read-write. Bits 0 to 15/Receive Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be activated (RDQFE = 1), then the host must first configure the timer to a proper state and then set the RDQFE bit to one. 0000h = illegal setting 0001h = timer count resets to 1 FFFFh = timer count resets to 65,536 Register Name: Register Description: Register Address: RDMAQ Receive DMA Queues Control 0780h Bit # Name Default 7 n/a 0 6 n/a 0 5 RDQF 0 4 RDQFE 0 3 RFQSF 0 2 RFQLF 0 1 n/a 0 0 RFQFE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 RDQT2 0 9 RDQT1 0 8 RDQT0 0 Note: Bits that are underlined are read-only, all other bits are read-write. Bit 0/Receive Free-Queue FIFO Enable (RFQFE). See Section 9.2.3 for details. Bit 2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). See Section 9.2.3 for details. Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). See Section 9.2.3 for details. Bit 4/Receive Done-Queue FIFO Enable (RDQFE). To enable the DMA to burst write descriptors to the done queue, this bit must be set to 1. If this bit is set to 0, messages are written one at a time. 0 = done-queue burst-write disabled 1 = done-queue burst-write enabled Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is flushed by sending all data into the done queue. This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed 101 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA (SDMA) register. 000 = set the RDQW status bit after each descriptor write to the done queue 001 = set the RDQW status bit after 2 or more descriptors are written to the done queue 010 = set the RDQW status bit after 4 or more descriptors are written to the done queue 011 = set the RDQW status bit after 8 or more descriptors are written to the done queue 100 = set the RDQW status bit after 16 or more descriptors are written to the done queue 101 = set the RDQW status bit after 32 or more descriptors are written to the done queue 110 = set the RDQW status bit after 64 or more descriptors are written to the done queue 111 = set the RDQW status bit after 128 or more descriptors are written to the done queue 9.2.5 DMA Channel Configuration RAM There is a set of 768 dwords (3 dwords per channel times 256 channels) on-board the device that the host uses to configure the DMA. It uses the DMA to store values locally when it is processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the host never writes to these fields. The host is only allowed to write (configure) to the lower word of dword 2 for each HDLC channel. The host-configurable fields are denoted with a thick box as shown below. Figure 9-9. Receive DMA Configuration RAM msb 31 HDLC Channel 1 HDLC Channel 2 Start Descriptor Pointer (16) 004h Threshold Count (3) 00Ch Start Descriptor Pointer (16) Threshold Count (3) BF4h HDLC Channel 256 Byte Count (13) Current Descriptor Pointer (16) Size CH FBF unused (5) Threshold(3) Unused (4) (2) EN Current Packet Data Buffer Address (32) 010h 014h lsb 0 Current Packet Data Buffer Address (32) 000h 008h Receive DMA Configuration RAM BF8h Threshold BFCh Count (3) Byte Count (13) Current Descriptor Pointer (16) Size CH FBF unused (5) Threshold(3 Unused (4) (2) EN Current Packet Data Buffer Address (32) Start Descriptor Pointer (16) Byte Count (13) Current Descriptor Pointer (16) Size CH FBF unused (5) Threshold(3 Unused (4) (2) EN Fields shown within the thick box are written by the Host; all other fields are for usage by the DMA and can only be read by the Host 102 of 183 DS31256 256-Channel, High-Throughput HDLC Controller - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being used. This address is used by the DMA to track where data should be written to as it comes in from the receive FIFO. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 0 to 15/Current Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of the current receive descriptor being used by the DMA to describe the specifics of the data stored in the associated data buffer. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 16 to 31/Starting Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of the first receive descriptor in a link-list chain of descriptors. This pointer is written into the done queue by the DMA after a specified number of data buffers (see the threshold value below) have been filled. - HOST MUST CONFIGURE dword 2; Bit 0/Channel Enable (CHEN). This bit is controlled by the host to enable and disable an HDLC channel. 0 = HDLC channel disabled 1 = HDLC channel enabled - HOST MUST CONFIGURE dword 2; Bits 1, 2/Buffer Size Select. These bits are controlled by the host to select the manner in which the receive DMA stores incoming packet data. 00 = use large size data buffers only 01 = use small size data buffers only 10 = fill a small buffer first, followed then by large buffers as needed 11 = illegal state and should not be selected - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 3 to 6/DMA Reserved. These could be any value when read. They should be set to 0 when the host writes to it. - HOST MUST CONFIGURE dword 2; Bits 7 to 9/Threshold. These bits are controlled by the host to determine when the DMA should write into the done queue that data is available for processing. They cannot be set to 000 when in transparent mode (RTRANS = 1). 000 = DMA should write to the done queue only after packet reception is complete 001 = DMA should write to the done queue after 1 data buffer has been filled 010 = DMA should write to the done queue after 2 data buffers have been filled 011 = DMA should write to the done queue after 3 data buffers have been filled 100 = DMA should write to the done queue after 4 data buffers have been filled 101 = DMA should write to the done queue after 5 data buffers have been filled 110 = DMA should write to the done queue after 6 data buffers have been filled 111 = DMA should write to the done queue after 7 data buffers have been filled - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 10 to 14/DMA Reserved. These could be any value when read. They should be set to 0 when the host writes to it. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bit 15/First Buffer Fill (FBF). This bit is set to 1 by the receive DMA when it is in the process of filling the first buffer of a packet. The DMA uses this bit to determine when to switch to large buffers when the buffer size-select field is set to 10. 103 of 183 DS31256 256-Channel, High-Throughput HDLC Controller - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 16 to 28/Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes). - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 29 to 31/Threshold Count. These bits keep track of the number of data buffers that have been filled so that the receive DMA knows when, based on the host-controlled threshold, to write to the done queue. 000 = threshold count is 0 data buffers 001 = threshold count is 1 data buffer 010 = threshold count is 2 data buffers 011 = threshold count is 3 data buffers 100 = threshold count is 4 data buffers 101 = threshold count is 5 data buffers 110 = threshold count is 6 data buffers 111 = threshold count is 7 data buffers Register Name: Register Description: Register Address: RDMACIS Receive DMA Channel Configuration Indirect Select 0770h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 RDCW2 0 9 RDCW1 0 8 RDCW0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 Bits 8 to 10/Receive DMA Configuration RAM Word Select Bits 0 to 2 (RDCW0 to RDCW2) 000 = lower word of dword 0 001 = upper word of dword 0 010 = lower word of dword 1 011 = upper word of dword 1 100 = lower word of dword 2 (only word that the host can write to) 101 = upper word of dword 2 110 = illegal state 111 = illegal state Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive DMA configuration RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RDMAC register, the IAB bit is set to 0. When the host wishes to write data to the internal receive DMA configuration RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the RDMAC register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB bit is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is 104 of 183 DS31256 256-Channel, High-Throughput HDLC Controller ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: Register Description: Register Address: RDMAC Receive DMA Channel Configuration 0774h Bit # Name Default 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Bit # Name Default 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D9 8 D8 Note: Bits that are underlined are read-only, all other bits are read-write. Bits 0 to 15/Receive DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the receive DMA configuration RAM. 9.3 Transmit Side 9.3.1 Overview The transmit DMA uses a scatter-gather technique to read packet data from main memory. The host keeps track of and decides from where (and when) the DMA should grab the outgoing packet data. A set of descriptors that get handed back and forth between the host and the DMA can tell the DMA where to obtain the packet data, and the DMA can tell the host when the data has been transmitted. The transmit DMA operation has three main areas, as shown in Figure 9-10, Figure 9-11, and Table 9-G. The host writes to the pending queue, informing the DMA which channels have packet data ready to be transmitted. Associated with each pending-queue descriptor is a data buffer that contains the actual data payload of the HDLC packet. The data buffers can be between 1 and 8188 Bytes in length (inclusive). If an outgoing packet requires more memory than a data buffer contains, the host can link the data buffers to handle packets of any size. The done-queue descriptors contain information that the DMA wishes to pass to the host. The DMA writes to the done queue when it has completed transmitting either a complete packet or data buffer (see below for the discussion on the DMA update to the done queue). Through the done-queue descriptors, the DMA informs the host about the status of the outgoing packet data. If an error occurs in the transmission, the done queue can be used by the host to recover the packet data that did not get transmitted and the host can then re-queue the packets for transmission. If enabled, the DMA can burst read the pending-queue descriptors and burst write the done-queue descriptors. This helps minimize PCI bus accesses, freeing the PCI bus up to do more time-critical functions. See Sections 9.3.3 and 9.3.4 for more details on this feature. 105 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 9-G. Transmit DMA Main Operational Areas DESCRIPTORS Packet Pending Queue Done Queue FUNCTION A dedicated area of memory that describes the location and attributes of the packet data. A dedicated area of memory that the host writes to inform the DMA that packet data is queued and ready for transmission. A dedicated area of memory that the DMA writes to inform the host that the packet data has been transmitted. SECTION 9.3.2 9.3.3 9.3.4 Host Linking of Data Buffers As previously mentioned, the data buffers are limited to a length of 8188 Bytes. If an outgoing packet requires more memory space than the available data buffer contains, the host can link multiple data buffers together to handle a packet length of any size. The host does this through the end-of-frame (EOF) bit in the packet descriptor. Each data buffer has a one-to-one association with a packet descriptor. If the host wants to link multiple data buffers together, the EOF bit is set to 0 in all but the last data buffer. Figure 9-10 shows an example for HDLC channel 5 where the host has linked three data buffers together. The transmit DMA knows where to find the next data buffer when the EOF bit is set to 0 through the next descriptor pointer field. Host Linking of Packets (Packet Chaining) The host also has the option to link multiple packets together in a chain. Through the chain valid (CV) bit in the packet descriptor, the host can inform the transmit DMA that the next descriptor pointer field contains the descriptor of another HDLC packet that is ready for transmission. The transmit DMA ignores the CV bit until it sees EOF = 1, which indicates the end of a packet. If CV = 1 when EOF = 1, this indicates to the transmit DMA that it should use the next descriptor pointer field to find the next packet in the chain. Figure 9-12 shows an example of packet chaining. Each column represents a separate packet chain. In column 1, three data buffers have been linked together by the host for packet #1, and the host has created a packet chain by setting CV = 1 in the last descriptor of packet #1. DMA Linking of Packets (Horizontal Link Listing) The transmit DMA also has the ability to link packets together. Internally, the transmit DMA can store up to two packet chains, but if the host places more packet chains into the pending queue, the transmit DMA must begin linking these chains together externally. The transmit DMA does this by writing to packet descriptors (Figure 9-12). If columns 1 and 2 were the only two packet chains queued for transmission, then the transmit DMA would not need to link packet chains together, but as soon as column 3 was queued for transmission, the transmit DMA had to store the third chain externally because it had no more room internally. The transmit DMA links the packet chain in the third column to the one in the second column by writing the first descriptor of the third chain in the next pending descriptor pointer field of the first descriptor of the second column (it also sets the PV bit to 1). As shown in the figure, this chaining was carried one step farther to link the fourth column to the third. 106 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Priority Packets The host has the option to change the order in which packets are transmitted by the DMA. If the host sets the priority packet (PRI) bit in the pending-queue descriptor to 1, the transmit DMA knows that this packet is a priority packet and should be transmitted ahead of all standard packets. The rules for packet transmission are as follows: 1) Priority packets are transmitted as soon as the current standard packet (not packet chain) finishes transmission. 2) All priority packets are transmitted before any more standard packets are transmitted. 3) Priority packets are ordered on a first come, first served basis. Figure 9-13 shows an example of a set of priority packets interrupting a set of standard packets. In the example, the first priority packet chain (shown in column 2) was read by the transmit DMA from the pending queue while it was transmitting standard packet #1. It waited until standard packet #1 was complete and then began sending the priority packets. While column 2 was being sent, the priority packet chains of columns 3 and 4 arrived in the pending queue, so the transmit DMA linked column four to column three and then waited until all of the priority packets were transmitted before returning to the standard packet chain in column 1. Note that the packet chain in column 1 was interrupted to transmit the priority packets. In other words, the transmit DMA did not wait for the complete packet to finish transmitting, only the current packet. 107 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-10. Transmit DMA Operation EOF = 1 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #5 unused PV Next Pend. Desc. Done-Queue Descriptors (circular queue) 00h Status CH#5 Free Desc. Ptr. 04h Status CH#1 Free Desc. Ptr. 08h Status CH# Free Desc. Ptr. 0Ch Status CH# Free Desc. Ptr. 10h Status CH# Free Desc. Ptr. 14h Status CH# Free Desc. Ptr. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc. EOF = 1 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc. Transmitted Data Buffer for Channel 5 1st Transmitted Data Buffer for Channel 1 2nd Transmitted Data Buffer for Channel 1 Last Transmitted Data Buffer for Channel 1 Open Descriptor Space Available for Use by the Host Open Descriptor Space Available for Use by the Host Pending-Queue Descriptors (circular queue) 00h PRI CH#5 Free Desc. Ptr. 04h PRI CH#1 Free Desc. Ptr. 08h PRI CH# Free Desc. Ptr. 0Ch PRI CH# Free Desc. Ptr. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #5 unused PV Next Pend. Desc. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #5 unused PV Next Pend. Desc. EOF = 1 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #5 unused PV Next Pend. Desc. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc. 108 of 183 1st Queued Data Buffer for Channel 5 2nd Queued Data Buffer for Channel 5 Last Queued Data Buffer for Channel 5 Queued Data Buffer for Channel 1 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-11. Transmit DMA Memory Organization Main Offboard Memory (32-Bit Address Space) Internal Registers Free Data Buffer Space Used Data Buffer Space Pending-Queue Base Address (32) Pending-Queue Host Write Pointer (16) Pending-Queue DMA Read Pointer (16) Transmit Pending-Queue Descriptors: Contains Index Pointers to Packet Descriptors of Queued Data Buffers that are Ready to be Transmitted Up to 64k dwords Free-Queue Descriptors Allowed Pending-Queue End Address (16) Done-Queue Base Address (32) Transmit Done-Queue Descriptors: Contains Index Pointers to Packet Descriptors of Data Buffers that have been Transmitted Done-Queue DMA Write Pointer (16) Done-Queue Host Read Pointer (16) Up to 64k dwords Done-Queue Descriptors Allowed Done-Queue End Address (16) Descriptor Base Address (32) Transmit Packet Descriptors: Contains 32-Bit Addresses to Data Buffers as well as Status/Control Information and Links to Other Packet Descriptors Up to 64k quad dwords Descriptors Allowed 109 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-12. Transmit DMA Packet Handling Transmit DMA Configuration RAM Last Pending Descriptor Pointer Next Pending Descriptor Pointer Next Descriptor Pointer Start Descriptor Pointer Next Pending Descriptor Pointer stored within the Packet Descriptor 1st Descriptor (EOF=0/CV=0) Buffer 1 Packet 1 2nd Descriptor (EOF=0/CV=0) Buffer 2 Packet 1 Last Descriptor (EOF=1/CV=1) Buffer 3 Packet 1 Last Descriptor (EOF=1/CV=0) Buffer 1 Packet 2 Packet Chain Column 1 1st Descriptor (EOF=0/CV=0) PV=1 Buffer 1 Next Pending Descriptor Pointer stored within the Packet Descriptor Last Descriptor (EOF=1/CV=0) PV=1 Buffer 1 Packet 3 Packet 5 2nd Descriptor (EOF=0/CV=0) 1st Descriptor (EOF=0/CV=0) Buffer 1 Packet 6 2nd Descriptor (EOF=0/CV=0) Buffer 2 Packet 3 Buffer 2 Packet 6 Last Descriptor (EOF=1/CV=1) Last Descriptor (EOF=1/CV=0) Buffer 3 Packet 3 Buffer 3 Packet 6 Last Descriptor (EOF=1/CV=0) Buffer 1 Packet 4 Packet Chain Column 2 110 of 183 Packet Chain Column 3 Packet Chain Column 4 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-13. Transmit DMA Priority Packet Handling Transmit DMA Configuration RAM Standard Queue Pointers Last Pending Descriptor Pointer Priority Queue Pointers Next Pending Descriptor Pointer Last Pending Descriptor Pointer Next Descriptor Pointer Next Pending Descriptor Pointer Start Descriptor Pointer Next Descriptor Pointer See Note 1 1st Descriptor (EOF=0/CV=0) Buffer 1 Packet 1 2nd Descriptor (EOF=0/CV=0) Buffer 2 Packet 1 Next Pending Descriptor Pointer stored within the Packet Descriptor Last Descriptor (EOF=1/CV=1) Buffer 3 Packet 1 1st Descriptor (EOF=0/CV=0) Service Priority Packets Buffer 1 Pri. Packet 1 Last Descriptor (EOF=1/CV=0) PV = 1 Buffer 1 Pri. Packet 3 Last Descriptor (EOF=1/CV=1) Normal Path if No Priority Packets Had Occurred 1st Descriptor (EOF=0/CV=0) Buffer 1 Pri. Packet 4 2nd Descriptor (EOF=0/CV=0) Buffer 2 Pri. Packet 1 Buffer 2 Pri. Packet 4 Last Descriptor (EOF=1/CV=0) Last Descriptor (EOF=1/CV=0) Buffer 1 Pri. Packet 2 Buffer 3 Pri. Packet 4 All Priority Packets Have Been Serviced Last Descriptor (EOF=1/CV=0) Buffer 1 Packet 2 Standard Packet Chain Column 1 Priority Packet Chain Column 2 Priority Packet Chain Column 3 Priority Packet Chain Column 4 Note 1: The start descriptor pointer field in the transmit DMA configuration RAM is used by both the normal and priority pending queues. 111 of 183 DS31256 256-Channel, High-Throughput HDLC Controller DMA Updates to the Done Queue The host has two options for when the transmit DMA should write descriptors that have completed transmission to the done queue. On a channel-by-channel basis, through the done-queue select (DQS) bit in the transmit DMA configuration RAM, the host can condition the DMA to: 1) Write to the done queue only when the complete HDLC packet has been transmitted (DQS = 0). 2) Write to the done queue when each data buffer has been transmitted (DQS = 1). The status field in the done-queue descriptor is configured based on the setting of the DQS bit. If DQS = 0, it is set to 000 when a packet has successfully completed transmission to the status field. If DQS = 1, it is set to 001 when the first data buffer has successfully completed transmission to the status field. The status field is set to 010 when each middle buffer (i.e., the second through the next to last) has successfully completed transmission. The status field is set to 011 when the last data buffer of a packet has successfully completed transmission. Error Conditions While processing packets for transmission, the DMA can encounter a number of error conditions, which include the following: • • • • • PCI error (an abort error) transmit FIFO underflow channel is disabled (CHEN = 0) in the transmit DMA configuration RAM channel number discrepancy between the pending queue and the packet descriptor Byte count of 0 Bytes in the packet descriptor If any of these errors occur, the transmit DMA automatically disables the affected channel by setting the channel enable (CHEN) bit in the transmit DMA configuration RAM to 0. Then it writes the current descriptor into the done queue with the appropriate error status, as shown in Table 9-H. Table 9-H. Done-Queue Error-Status Conditions PACKET STATUS 100 101 110 111 ERROR DESCRIPTION Software provisioning error; this channel was not enabled Descriptor error; either byte count = 0 or channel code inconsistent with pending queue PCI error; either parity or abort Transmit FIFO error; it has underflowed Since the transmit DMA has disabled the channel, any remaining queued descriptors are not transmitted and are written to the done queue with a packet status of 100 (i.e., reporting that the channel was not enabled). At this point the host has two options. Option 1: It can wait until all of the remaining queued descriptors are written to the done queue with an errored status, manually re-enable the channel by setting the CHEN bit to 1, and then re-queue all of the affected packets. Option 2: As soon as it detects an errored status, it can force the channel active again by setting the channel reset (CHRST) bit to 1 for the next descriptor that it writes to the pending queue for the affected channel. As soon as the transmit DMA detects that the CHRST is set to 1, it re-enables the channel by forcing the CHEN bit to 1. The DMA does not re-enable the channel until it has finished writing all of the previously queued descriptors to the done queue. Then the host can collect the errored descriptors as they arrive in the done queue and re-queue them for transmission by writing descriptors to the pending queue, so the transmit DMA knows where to find the packets that did not get transmitted (Note: The host must set the next-pending 112 of 183 DS31256 256-Channel, High-Throughput HDLC Controller descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second option allows the software a cleaner error-recovery technique. See Figure 9-14 for more details. Figure 9-14. Transmit DMA Error Recovery Algorithm Read Done Queue Data Buffers and Packet Descriptor Space Available for Reuse No Status = 1xx? Yes Set CHRST = 1 for the Next Descriptor Written to the Pending Queue Set the PV and the Next Pending Descriptor Pointer Fields to 0 in the Errored Packet Descriptor Place the Errored Packet Descriptor Back into the Pending Queue for Retransmission Host Actions The host typically handles the transmit DMA as follows: 1) The host places readied packets into the pending queue. 2) The host either polls (or is interrupted) that some outgoing packets have completed transmission and that it should read the done queue. 3) If done queue reports that an error was incurred and that a packet was not transmitted, the host must requeue the packet for transmission. Transmit DMA Actions A typical scenario for the transmit DMA is as follows: 1) The transmit DMA constantly reads the pending queue looking for packets that are queued for transmission. 2) The transmit DMA updates the done queue as packets or data buffers to complete transmission. 3) If an error occurs, the transmit DMA disables the channel and waits for the host to request that the channel be enabled. 113 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.3.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed anywhere in the 32-bit address space through the transmit descriptor base address (Table 9-I). A data buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a contiguous section of main memory. The host informs the DMA of data buffers’ actual sizes through the byte count field that resides in the packet descriptor. If an outgoing packet requires more space than the data buffer allows, then packet descriptors are linklisted together by the host to provide a chain of data buffers. Figure 9-15 shows an example of how three descriptors were linked together for an incoming packet on HDLC channel 7. Channel 3 only required a single data buffer and thus only one packet descriptor was used. Figure 9-10 shows a similar example for channels 5 and 1. Packet descriptors can be either pending (i.e., queued up by the host and ready for transmission by the DMA) or completed (i.e., have been transmitted by the DMA and are available for processing by the host). Pending-packet descriptors are pointed to by the pending-queue descriptors and completed packet descriptors are pointed to by the done-queue descriptors. Table 9-I. Transmit Descriptor Address Storage REGISTER Transmit Descriptor Base Address 0 (lower word) Transmit Descriptor Base Address 1 (upper word) NAME TDBA0 TDBA1 ADDRESS 0850h 0854h Figure 9-15. Transmit Descriptor Example Done-Queue Descriptor Pointer Pending-Queue Descriptor Address Base + 00h CH 5 Single Sent Buffer Descriptor Base + 10h CH 7 1st Queued Buffer Descriptor Base + 20h CH 3 Single Queued Buffer Desc. Base + 30h CH 7 Sent 1st Buffer Descriptor Base + 40h Free Descriptor Base + 50h CH 7 2nd Queued Buffer Descriptor Base + 60h Free Descriptor Base + 70h CH 7 Last Queued Buffer Descriptor Base + 80h Maximum of 65,536 Descriptors CH 7 Last Sent Buffer Descriptor Base + FFFD0h Free Descriptor Base + FFFF0h Free Descriptor 114 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-16. Transmit Packet Descriptors dword 0 Data Buffer Address (32) dword 1 EOF dword 2 CV unused Byte Count (13) Next Descriptor Pointer (16) unused (24) HDLC Channel (8) dword 3 unused (15) PV Next Pending Descriptor Pointer (16) Note 1: The organization of the transmit descriptor is not affected by the enabling of Big Endian. Note 2: The format of the transmit descriptor is almost identical to the receive descriptor; this lessens the burden of the host in preparing descriptors in store-and-forward applications. Note 3: Next descriptor pointer is an index, not an absolute address. dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of the data buffer that is associated with this transmit descriptor. dword 1; Bits 0 to 15/Next Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the next descriptor in the chain. Only valid if EOF = 0 (next descriptor in the same packet chain) or if EOF = 1 and CV = 1 (first descriptor in the next packet). dword 1; Bits 16 to 28/Byte Count. Number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes). dword 1; Bit 29/Unused. This bit is ignored by the transmit DMA and can be set to any value. dword 1; Bit 30/Chain Valid (CV). If CV is set to 1 when EOF = 1, then this indicates that the next descriptor pointer field is valid and corresponds to the first descriptor of the next packet that is queued up for transmission. The CV bit is ignored when EOF = 0. dword 1; Bit 31/End of Frame (EOF). When set to 1, this bit indicates that the descriptor is the last buffer in the current packet. When set to 0, this bit indicates that next descriptor pointer field is valid and points to the next descriptor in the packet chain. dword 2; Bits 0 to 7/HDLC Channel Number. HDLC channel number, which can be from 1 to 256. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 dword 2; Bits 8 to 31/Unused. These bits are ignored by the transmit DMA and can be set to any value. dword 3; Bits 0 to 15/Next Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address to another descriptor chain that is queued up for transmission. The transmit DMA can store up to two queued packet chains internally, but additional packet chains must be stored as a link list by the transmit DMA using this field. This field is only valid if PV = 1, and it should be set to 0000h by the host when the host is preparing the descriptor. dword 3; Bit 16/Pending Descriptor Valid (PV). If set, this bit indicates that the next pending descriptor pointer field is valid and corresponds to the first descriptor of the next packet chain that is queued up for transmission. This field is written to by the transmit DMA to link descriptors together and should always be set to 0 by the host. dword 3; Bits 17 to 31/Unused. These bits are ignored by the transmit DMA and can be set to any value. 115 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.3.3 Pending Queue The host writes to the transmit pending queue the location of the readied descriptor, channel number, and control information. The descriptor space is indicated through a 16-bit pointer, which the DMA uses with the transmit packet-descriptor base address to find the exact 32-bit address of the associated transmit packet descriptor. Figure 9-17. Transmit Pending-Queue Descriptor dword 0 Unused (3) Status(3) CHRST PRI HDLC Channel (8) Descriptor Pointer (16) Note 1: The organization of the pending queue is not affected by the enabling of Big Endian. Note 2: Decriptor pointer is an index, not an absolute address. dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address to the first descriptor in a packet chain (can be a single descriptor) that is queued up for transmission. dword 0; Bits 16 to 23/HDLC Channel Number. HDLC channel number, which can be from 1 to 256. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 dword 0; Bit 24/Priority Packet (PRI). If this bit is set to 1, this indicates to the transmit DMA that the packet or packet chain pointed to by the descriptor pointer field should be transmitted immediately after the current packet transmission (whether it be standard or priority) is complete. dword 0; Bit 25/Channel Reset (CHRST). Under normal operating conditions, this bit should always be set to 0. When an error condition occurs and the transmit DMA places the channel into an out-of-service state by setting the channel enable (CHEN) bit in the transmit DMA configuration register to 0, the host can force the channel active again by setting the CHRST bit to 1. Only the first descriptor loaded into the pending queue after an error condition should have CHRST set to 1; all subsequent descriptors (until another error condition occurs) should have CHRST set to 0. The transmit DMA examines this bit and forces the channel active (CHEN = 1) if CHRST is set to 1. If CHRST is set to 0, then the transmit DMA does not modify the state of the CHEN bit. See Section 9.2.2 for more details about how error conditions are handled. dword 0; Bits 26 to 28/Packet Status. Not used by the DMA. Can be set to any value by the host and is ignored by the transmit DMA. This field is used by the transmit DMA when it writes to the done queue to inform the host of the status of the outgoing packet data. dword 0; Bits 29 to 31/Unused. Not used by the DMA. Can be set to any value by the host and is ignored by the transmit DMA. 116 of 183 DS31256 256-Channel, High-Throughput HDLC Controller The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers and their associated descriptors are ready for transmission. A set of internal addresses within the device that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit pending queue. On initialization, the host configures all of the registers shown in Table 9-J. After initialization, the DMA only writes to (changes) the read pointers and the host only writes to the write pointers. Empty Case The transmit pending queue is considered empty when the read and write pointers are identical. Transmit Pending-Queue Empty State read pointer > empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor < write pointer Full Case The transmit pending queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty. Transmit Pending-Queue Full State read pointer > valid descriptor valid descriptor empty descriptor valid descriptor valid descriptor valid descriptor valid descriptor < write pointer Table 9-J. Transmit Pending-Queue Internal Address Storage REGISTER NAME ADDRESS Transmit Pending-Queue Base Address 0 (lower word) Transmit Pending-Queue Base Address 1 (upper word) Transmit Pending-Queue Host Write Pointer Transmit Pending-Queue DMA Read Pointer Transmit Pending-Queue End Address TPQBA0 TPQBA1 TPQWP TPQRP TPQEA 0800h 0804h 080Ch 0810h 0808h Note: Transmit free-queue end address is not an absolute address. The absolute end address is “Base + TPQEA.” 117 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-18. Transmit Pending-Queue Structure Base + 00h Base + 04h Pending-Queue Host Write Pointer Base + 08h Maximum of 65,536 Pending-Queue Descriptors Host Readied Pending-Queue Descriptor DMA Acquired Pending-Queue Descriptor Base + 10h DMA Acquired Pending-Queue Descriptor DMA Acquired Pending-Queue Descriptor Base + 14h Host Readied Pending-Queue Descriptor Base + 0Ch Pending-Queue DMA Read Pointer Host Readied Pending-Queue Descriptor Base + End Address Host Readied Pending-Queue Descriptor Once the transmit DMA is activated (by setting the TDE control bit in the master configuration register; see Section 5), it can begin reading data out of the pending queue. It knows where to read the data by reading the read pointer and adding it to the base address to obtain the actual 32-bit address. Once the DMA has read the pending queue, it increments the read pointer by one dword. A check must be made to ensure the incremented address does not exceed the transmit pending-queue end address. If the incremented address does exceed this address, the incremented read pointer is set equal to 0000h. Status/Interrupts On each read of the pending queue by the DMA, the DMA sets the status bit for transmit DMA pendingqueue read (TPQR) in the status register for DMA (SDMA). The status bits can also (if enabled) cause an hardware interrupt to occur. See Section 5 for more details. Pending-Queue Burst Reading The DMA can read the pending queue in bursts, which allows for a more efficient use of the PCI bus. The DMA can grab descriptors from the pending queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions. An internal FIFO can store up to 16 pending-queue descriptors (16 dwords, since each descriptor occupies one dword). The host must configure the pending-queue FIFO for proper operation through the transmit DMA queues-control (TDMAQ) register (see the following). When enabled through the transmit pending-queue FIFO-enable (TPQFE) bit, the pending-queue FIFO does not read the pending queue until it is empty. When the pending queue is empty, it attempts to fill the FIFO with additional descriptors by burst reading the pending queue. Before it reads the pending queue, it checks (by examining the transmit pending-queue host write pointer) to ensure the pending queue contains enough descriptors to fill the pending-queue FIFO. If the pending queue does not have enough descriptors to fill the FIFO, it only reads enough to empty the pending queue. If the FIFO detects that there are no pending-queue descriptors available for it to read, it waits and tries again later. If the pending-queue FIFO can read descriptors from the pending queue, it burst reads them, increments the 118 of 183 DS31256 256-Channel, High-Throughput HDLC Controller read pointer, and sets the status bit for transmit DMA pending-queue read (TPQR) in the status register for DMA (SDMA). See Section 5 for more details about status bits. Register Name: Register Description: Register Address: TDMAQ Transmit DMA Queues Control 0880h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 n/a 0 3 TDQF 0 2 TDQFE 0 1 TPQF 0 0 TPQFE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 TDQT2 0 9 TDQT1 0 8 TDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). This bit must be set to 1 to enable the DMA to burst read descriptors from the pending queue. If this bit is set to 0, descriptors are read one at a time. 0 = pending-queue burst read disabled 1 = pending-queue burst read enabled Bit 1/Transmit Pending-Queue FIFO Flush (TPQF). When this bit is set to 1, the internal pending-queue FIFO is flushed (currently loaded pending-queue descriptors are lost). This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed Bit 2/Transmit Done-Queue FIFO Enable (TDQFE). See Section 9.3.4 for details. Bit 3/Transmit Done-Queue FIFO Flush (TDQF). See Section 9.3.4 for details. Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). See Section 9.3.4 for more details. 119 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.3.4 Done Queue The DMA writes to the transmit done queue when it has finished either transmitting a complete packet chain or a complete data buffer. This option is selected by the host when it configures the DQS field in the transmit DMA configuration RAM (Section 9.3.5). The descriptor location is indicated in the done queue through a 16-bit pointer that the host uses along with the transmit descriptor base address to find the exact 32-bit address of the associated transmit descriptor. Figure 9-19. Transmit Done-Queue Descriptor dword 0 unused Status (3) CHRST PRI HDLC Channel (8) Descriptor Pointer (16) Note: The organization of the done queue is not affected by the enabling of Big Endian. dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address to either the first descriptor in a HDLC packet (can be a single descriptor) that has been transmitted (DQS = 0) or the descriptor that corresponds to a single data buffer that has been transmitted (DQS = 1). dword 0; Bits 16 to 23/HDLC Channel Number. HDLC channel number, which can be from 1 to 256. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 dword 0; Bit 24/Priority Packet (PRI). This field is meaningless in the done queue and could be set to any value. See Section 9.3.3 for details. dword 0; Bit 25/Channel Reset (CHRST). This field is meaningless in the done queue and could be set to any value. See Section 9.3.3 for details. dword 0; Bits 26 to 28/Packet Status. These three bits report the final status of an outgoing packet. All the error states cause a HDLC abort sequence (eight 1s in a row, followed by continuous interfill bytes of either FFh or 7Eh) to be sent, and the channel is placed out of service by the transmit DMA, setting the channel enable (CHEN) bit in the transmit DMA configuration RAM to 0. The status state of 000 is only used when the channel has been configured by the host to write to the done queue only after a complete HDLC packet (can be a single data buffer) has been transmitted (i.e., DQS = 0). The status states of 001, 010, and 011 are only used when the channel has been configured by the host to write to the done queue after each data buffer has been transmitted (i.e., DQS = 1). 000 = packet transmission complete and the descriptor pointer field corresponds to the first descriptor in a HDLC packet (can be a single descriptor) that has been transmitted (DQS = 0) 001 = first buffer transmission complete of a multi (or single) buffer packet (DQS = 1) 010 = middle buffer transmission complete of a multibuffer packet (DQS = 1) 011 = last buffer transmission complete of a multibuffer packet (DQS = 1) 100 = software provisioning error; this channel was not enabled 101 = descriptor error; either byte count = 0 or channel code inconsistent with pending queue 110 = PCI error 111 = transmit FIFO error; it has underflowed dword 0; Bits 29 to 31/Unused. Not used by the DMA. Could be any value when read. 120 of 183 DS31256 256-Channel, High-Throughput HDLC Controller The host reads from the transmit done queue to find which data buffers and their associated descriptors have completed transmission. The transmit done queue is circular queue. A set of internal addresses within the device that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit done queue. On initialization, the host configures all of the registers, as shown in Table 9-K. After initialization, the DMA only writes to (changes) the write pointer and the host only writes to the read pointer. Empty Case The transmit done queue is considered empty when the read and write pointers are identical. Transmit Done-Queue Empty State read pointer > empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor < write pointer Full Case The transmit done queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty. Transmit Done-Queue Full State read pointer > valid descriptor valid descriptor empty descriptor valid descriptor valid descriptor valid descriptor valid descriptor < write pointer Table 9-K. Transmit Done-Queue Internal Address Storage REGISTER Transmit Done-Queue Base Address 0 (lower word) Transmit Done-Queue Base Address 1 (upper word) Transmit Done-Queue DMA Write Pointer Transmit Done-Queue Host Read Pointer Transmit Done-Queue End Address Transmit Done-Queue FIFO Flush Timer NAME TDQBA0 TDQBA1 TDQWP TDQRP TDQEA TDQFFT ADDRESS 0830h 0834h 0840h 083Ch 0838h 0844h Note: Transmit done-queue end address is not an absolute address. The absolute end address is “Base + TDQEA x 4.” 121 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 9-20. Transmit Done-Queue Structure Done Queue DMA Write Pointer Done Queue Host Read Pointer Maximum of 65536 Done Queue Descriptors Base + 00h DMA Readied Done Queue Descriptor Base + 04h DMA Readied Done Queue Descriptor Base + 08h Host Processed Done Queue Descriptor Base + 0Ch Host Processed Done Queue Descriptor Base + 10h Host Processed Done Queue Descriptor Base + 14h DMA Readied Done Queue Descriptor Base + End Address DMA Readied Done Queue Descriptor dmatdq Once the transmit DMA is activated (through the TDE control bit in the master configuration register; see Section 5 for more details), it can begin writing data to the done queue. It knows where to write data into the done queue by reading the write pointer and adding it to the base address to obtain the actual 32bit address. Once the DMA writes to the done queue, it increments the write pointer by one dword. A check must be made to ensure the incremented address does not exceed the transmit done-queue end address. If the incremented address does exceed this address, the incremented write pointer is set equal to 0000h (i.e., the base address). Status Bits/Interrupts On writes to the done queue by the DMA, the DMA sets the status bit for the transmit DMA done-queue write (TDQW) in the status register for DMA (SDMA). The host can configure the DMA to either set this status bit on each write to the done queue or only after multiple (from 2 to 128) writes. The host controls this by setting the TDQT0 to TDQT2 bits in the transmit DMA queues-control (TDMAQ) register. See the description of the TDMAQ register at the end of this section for more details. The DMA also checks the transmit done-queue host read pointer to ensure that an overflow does not occur. If this does occur, the DMA sets the status bit for transmit DMA done-queue write error (TDQWE) in the status register for DMA (SDMA), and it does not write to the done queue nor does it increment the write pointer. In such a scenario, information on transmitted packets is lost and unrecoverable. Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 5 for more details. Done-Queue Burst Writing The DMA can write to the done queue in bursts. This allows for a more efficient use of the PCI bus. The DMA can hand off descriptors to the done queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions. An internal FIFO can store up to eight done-queue descriptors (8 dwords, since each descriptor occupies one dword). The host must configure the FIFO for proper operation through the transmit DMA queues control (TDMAQ) register (see the following). 122 of 183 DS31256 256-Channel, High-Throughput HDLC Controller When enabled through the transmit done-queue FIFO-enable (TDQFE) bit, the done-queue FIFO does not write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the high watermark (which is six descriptors), it attempts to empty the done-queue FIFO by burst writing to the done queue. Before it writes to the done queue, it checks (by examining the transmit done-queue host read pointer) to ensure the done queue has enough room to empty. If the done queue does not have enough room, then it only burst writes enough descriptors to keep from overflowing. If the FIFO detects that there is no room for any descriptors to be written, then it sets the status bit for transmit DMA donequeue write error (TDQWE) in the SDMA and it does not write to the done queue nor does it increment the write pointer. In such a scenario, information on transmitted packets is lost and unrecoverable. If the done-queue FIFO can write descriptors to the done queue, then it burst writes them, increments the write pointer, and sets the status bit for transmit DMA done-queue write (TDQW) in the SDMA. See Section 5 for more details about status bits. Done-Queue FIFO Flush Timer To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the transmit donequeue FIFO flush timer (TDQFFT) is used by the DMA to determine the maximum wait time in between writes. The TDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256. It is only monitored by the DMA when the transmit done-queue FIFO is enabled (TDQFE = 1). For a 33MHz PCLK, the timer is decremented every 7.76µs. For a 25MHz clock, it decrements every 10.24µs. Each time the DMA writes to the done queue it resets the timer to the count placed into it by the host. On initialization, the host sets a value into the TDQFFT that indicates the maximum time the DMA should wait in between writes to the done queue. For example, with a PCLK of 33MHz, the range of wait times is from 7.8µs (RDQFFT = 0001h) to 508ms (RDQFFT = FFFFh). With a PCLK of 25MHz, the wait times range from 10.2µs (RDQFFT = 0001h) to 671ms (RDQFFT = FFFFh). Register Name: Register Description: Register Address: TDQFFT Transmit Done-Queue FIFO Flush Timer 0844h Bit # Name Default 7 TC7 0 6 TC6 0 5 TC5 0 4 TC4 0 3 TC3 0 2 TC2 0 1 TC1 0 0 TC0 0 Bit # Name Default 15 TC15 0 14 TC14 0 13 TC13 0 12 TC12 0 11 TC11 0 10 TC10 0 9 TC9 0 8 TC8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Transmit Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be activated (TDQFE = 1), the host must first configure the timer to a proper state and then set the TDQFE bit to 1. 0000h = illegal setting 0001h = timer count resets to 1 FFFFh = timer count resets to 65,536 123 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: TDMAQ Transmit DMA Queues Control 0880h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 n/a 0 3 TDQF 0 2 TDQFE 0 1 TPQF 0 0 TPQFE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 TDQT2 0 9 TDQT1 0 8 TDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). See Section 9.3.3 for details. Bit 1/Transmit Pending-Queue FIFO Flush (TPQLF). See Section 9.3.3 for details. Bit 3/Transmit Done-Queue FIFO Enable (TDQFE). This bit must be set to 1 to enable the DMA to burst write descriptors to the done queue. If this bit is set to 0, descriptors are written one at a time. 0 = done-queue burst write disabled 1 = done-queue burst write enabled Bit 4/Transmit Done-Queue FIFO Flush (TDQF). When this bit is set to 1, the internal done-queue FIFO is flushed by sending all data into the done queue. This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). These bits determine when the DMA sets the transmit DMA done-queue write (TDQW) status bit in the status register for DMA (SDMA) register. 000 = set the TDQW status bit after each descriptor write to the done queue 001 = set the TDQW status bit after 2 or more descriptors are written to the done queue 010 = set the TDQW status bit after 4 or more descriptors are written to the done queue 011 = set the TDQW status bit after 8 or more descriptors are written to the done queue 100 = set the TDQW status bit after 16 or more descriptors are written to the done queue 101 = set the TDQW status bit after 32 or more descriptors are written to the done queue 110 = set the TDQW status bit after 64 or more descriptors are written to the done queue 111 = set the TDQW status bit after 128 or more descriptors are written to the done queue 124 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 9.3.5 DMA Configuration RAM The device contains an on-board set of 1536 dwords (6 dwords per channel times 256 channels) that are used by the host to configure the DMA and used by the DMA to store values locally when it is processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the host never writes to these fields. The host is only allowed to write (configure) to the lower word of dword 1 for each HDLC channel. In Figure 9-21, the host-configurable fields are denoted with a thick box. Figure 9-21. Transmit DMA Configuration RAM msb 31 000h 004h Current Packet Data Buffer Address (32) unused (9) HDLC 008h Channel 1 00Ch PRI PPP ST(2) unCH used DQS EN Next Pending Descriptor Pointer (16) Next Priority Descriptor Pointer (16) unused (16) Next Priority Pending Descriptor Pointer (16) Last Priority Pending Descriptor Pointer (16) Current Packet Data Buffer Address (32) unused (9) PRI PPP ST(2) PEND ST(2) EOF CV Start Descriptor Pointer (16) 17F4h Byte Count (13) unCH used DQS EN Next Descriptor Pointer (16) Last Pending Descriptor Pointer (16) 17F8h 17FCh Byte Count (13) Next Descriptor Pointer (16) Last Pending Descriptor Pointer (16) 17D8h HDLC 17DCh Channel 256 17F0h PEND ST(2) EOF CV Start Descriptor Pointer (16) 010h 014h lsb 0 Transmit DMA Configuration RAM Next Pending Descriptor Pointer (16) Next Priority Descriptor Pointer (16) unused (16) Next Priority Pending Descriptor Pointer (16) Last Priority Pending Descriptor Pointer (16) Fields shown within the thick box are written by the Host; all other fields are for usage by the DMA and can only be read by the Host dmatcram 125 of 183 DS31256 256-Channel, High-Throughput HDLC Controller - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit address of the data buffer that is being used. This address is used by the DMA to keep track of where data should be read from as it is passed to the transmit FIFO. - HOST MUST CONFIGURE dword 1; Bit 0/Channel Enable (CHEN). This bit is controlled by both the host and the transmit DMA to enable and disable a HDLC channel. The DMA automatically disables a channel when an error condition occurs (see Section 9.2.1 for a discussion on error conditions). The DMA automatically enables a channel when it detects that the channel reset (CHRST) bit in the pending-queue descriptor is set to 1. 0 = HDLC channel disabled 1 = HDLC channel enabled - HOST MUST CONFIGURE dword 1; Bit 1/Done-Queue Select (DQS). This bit determines whether the transmit DMA writes to the done queue only after a complete HDLC packet (which may be only a single buffer) has been transmitted (in which case the descriptor pointer in the done queue corresponds to the first descriptor of the packet) or whether it should write to the done queue after each data buffer has been transmitted (in which case the descriptor pointer in the done queue corresponds to a single data buffer). The setting of this bit also affects the reporting of the status field in the transmit done queue. When DQS = 0, the only nonerrored status possible is a setting of 000. When DQS = 1, then the nonerrored settings of 001, 010, and 011 are possible. 0 = write to the done queue only after a complete HDLC packet has been transmitted 1 = write to the done queue after each data buffer is transmitted - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bit 2/Unused. This field is not used by the DMA and could be any value when read. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 3 to 15/Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes). - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bit 16/Chain Valid (CV). This is an internal copy of the CV field that resides in the current packet descriptor that the DMA is operating on. See Section 9.2.2 for more details on the CV bit. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bit 17/End of Frame (EOF). This is an internal copy of the EOF field that resides in the current Packet Descriptor that the DMA is operating on. See Section 9.2.2 for more details about the EOF bit. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 18 to 19/Pending State (PENDST). This field is used by the transmit DMA to keep track of queued descriptors as they arrive from the pending queue and for the DMA to know when it should create a horizontal linked list of transmit descriptors and where it can find the next valid descriptor. This field handles standard packets and the PRIST field handles priority packets. State Next Descriptor Pointer Field Next Pending Descriptor Pointer Field 00 01 10 11 Not Valid Valid Not Valid Valid Not Valid Not Valid Valid Valid 126 of 183 DS31256 256-Channel, High-Throughput HDLC Controller - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transmit DMA to keep track of queued priority descriptors as they arrive from the pending queue, and for the DMA to know when it should create a horizontal linked list of transmit priority descriptors and where it can find the next valid priority descriptor. This field handles priority packets and the PENDST field handles standard packets. State Next Priority Descriptor Pointer Field Next Priority Pending Descriptor Pointer Field 00 01 10 11 Not Valid Valid Not Valid Valid Not Valid Not Valid Valid Valid -FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bit 22/Processing Priority Packet (PPP). This bit is set to 1 when the DMA is currently processing a priority packet. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 23 to 31/Unused. This field is not used by the DMA and could be any value when read. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 0 to 15/Next Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the next transmit packet descriptor for the packet that is currently being transmitted. Only valid if EOF = 0 or if EOF = 1 and CV = 1. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 16 to 31/Start Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit packet descriptor for the packet that is currently being transmitted. If DQS = 0, then this pointer is written back to the done queue when the packet has completed transmission. This field is used by the DMA for processing standard as well as priority packets. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 3; Bits 0 to 15/Next Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit packet descriptor for the packet that is queued up next for transmission. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 3; Bits 16 to 31/Last Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit packet descriptor for the packet that is queued up last for transmission. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 4; Bits 0 to 15/Next Priority Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the next transmit priority packet descriptor for the priority packet that is currently being transmitted. Only valid if EOF = 0 or if EOF = 1 and CV = 1. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 4; Bits 16 to 31/Unused. This field is not used by the DMA and could be any value when read. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 5; Bits 0 to 15/Last Priority Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit priority packet descriptor for the priority packet that is queued up last for transmission. 127 of 183 DS31256 256-Channel, High-Throughput HDLC Controller - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit priority packet descriptor for the packet priority that is queued up next for transmission. Register Name: Register Description: Register Address: TDMACIS Transmit DMA Configuration Indirect Select 0870h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 TDCW3 0 10 TDCW2 0 9 TDCW1 0 8 TDCW0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 Bits 8 to 11/Transmit DMA Configuration RAM Word Select Bits 0 to 3 (TDCW0 to TDCW3) 0000 = lower word of dword 0 0001 = upper word of dword 0 0010 = lower word of dword 1 (only word that the host can write to) 0011 = upper word of dword 1 0100 = lower word of dword 2 0101 = upper word of dword 2 0110 = lower word of dword 3 0111 = upper word of dword 3 1000 = lower word of dword 4 1001 = upper word of dword 4 1010 = lower word of dword 5 1011 = upper word of dword 5 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit DMA configuration RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the TDMAC register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit DMA configuration RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the TDMAC register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB bit is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. 128 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: TDMAC Transmit DMA Configuration 0874h Bit # Name Default 7 D7 0 6 D6 0 5 D5 0 4 D4 0 3 D3 0 2 D2 0 1 D1 0 0 D0 0 Bit # Name Default 15 D15 0 14 D14 0 13 D13 0 12 D12 0 11 D11 0 10 D10 0 9 D9 0 8 D8 0 Note: Bits that are underlined are read only, all other bits are read-write. Bits 0 to 15/Transmit DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the transmit DMA configuration RAM. 129 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 10. PCI BUS 10.1 General Description of Operation The PCI block interfaces the DMA block to an external high-speed bus. The PCI block complies with Revision 2.1 (June 1, 1995) of the PCI Local Bus Specification. HDLC packet data always passes to and from the DS31256 through the PCI bus. The user has the option to configure and monitor the internal device registers either through the PCI bus (local bus bridge mode) or through the local bus (local bus configuration mode). When the local bus bridge mode is used, the host on the PCI bus can also bridge to the local bus and sets/monitors the PCI configuration registers. When the local bus configuration mode is used, the CPU on the local bus sets/monitors the PCI configuration registers. The PCI configuration registers (Figure 10-1) are described in detail in Section 10.2. The following notes apply to the PCI configuration registers: 1) All unused locations (the shaded areas of Figure 10-1) return zeros when read. 2) Read-only locations can be written with either 1 or 0 with no effect. 3) All bits are read/write, unless otherwise noted. Figure 10-1. PCI Configuration Memory Map 0x000 Device ID Vendor ID 0x004 Status Command Class Code 0x008 Header Type 0x00C 0x010 0x03C Revision ID Latency Timer Base Address for Device Configuration Max. Latency Min. Grant Cache Line Size 0x000 Interrupt Pin Interrupt Line 0x100 Device ID Vendor ID 0x104 Status Command 0x108 0x10C 0x110 Class Code Revision ID Header Type 0x00000 Base Address for Local Bus 0x13C Interrupt Pin 130 of 183 Interrupt Line DS31256 256-Channel, High-Throughput HDLC Controller 10.1.1 PCI Read Cycle A read cycle on the PCI bus is shown in Figure 10-2. During clock cycle #1, the initiator asserts the PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a read) onto the PCBE signal lines. The target reads the address and bus command and, if the address matches its own, it then asserts the PDEVSEL signal and begins the bus transaction. During clock cycle #2, the initiator stops driving the address onto the PAD signal lines and switches the PCBE signal lines to indicate byte enables. It also asserts the PIRDY signal and begins monitoring the PDEVSEL and PTRDY signals. During clock cycle #4, the target asserts PTRDY, indicating to the initiator that valid data is available to be read on the PAD signal lines by the initiator. During clock cycle #5, the target is not ready to provide data #2 because PTRDY is deasserted. During clock cycle #6, the target again asserts PTRDY, informing the initiator to read data #2. During clock cycle #7, the initiator deasserts PIRDY, indicating to the target that it is not ready to accept data. During clock cycle #8, the initiator asserts PIRDY and acquires data #3. Also during clock cycle #8, the initiator deasserts PFRAME, indicating to the target that the bus transaction is complete and no more data needs to be read. During clock cycle #9, the target deasserts PTRDY and PDEVSEL and the initiator deasserts PIRDY. The PXAS, PXDS, and PXBLAST signals are not part of a standard PCI bus. These PCI extension signals are unique to the device and are useful in adapting the PCI bus to a proprietary bus scheme. They are only asserted when the device is a bus master. Figure 10-2. PCI Bus Read PCLK 1 2 3 4 5 6 7 8 PFRAME PAD PCBE Address CMD data #1 Byte Enable #1 data #2 BE #2 PIRDY PTRDY PDEVSEL PXAS PXDS PXBLAST 131 of 183 data #3 BE #3 9 10 DS31256 256-Channel, High-Throughput HDLC Controller 10.1.2 PCI Write Cycle A write cycle on the PCI bus is shown in Figure 10-3. During clock cycle #1, the initiator asserts the PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a write) onto the PCBE signal lines. The target reads the address and bus command and, if the address matches its own, it then asserts the PDEVSEL signal and begins the bus transaction. During clock cycle #2, the initiator stops driving the address onto the PAD signal lines and begins driving data #1. It also switches the PCBE signal lines to indicate the byte enable for data #1. The initiator asserts the PIRDY signal and begins monitoring the PDEVSEL and PTRDY signals. During clock cycle #3, the initiator detects that PDEVSEL and PTRDY are asserted, which indicates that the target has accepted data #1 and the initiator begins driving the data and byte enable for data #2. During clock cycle #4, since PDEVSEL and PTRDY are asserted, data #2 is written by the initiator to the target. During clock cycle #5, both PIRDY and PTRDY are deasserted, indicating that neither the initiator nor the target are ready for data #3 to be passed. During clock cycle #6, the initiator is ready so it asserts PIRDY and deasserts PFRAME, which indicates that data #3 is the last one passed. During clock cycle #8, the target asserts PTRDY, which indicates to the initiator that data #3 is ready to be accepted by the target. During clock cycle #9, the initiator deasserts PIRDY and stops driving the PAD and PCBE signal lines. The target deasserts PDEVSEL and PTRDY. The PXAS, PXDS, and PXBLAST signals are not part of a standard PCI bus. These PCI extension signals are unique to the device. They are useful in adapting the PCI bus to a proprietary bus scheme. They are only asserted when the device is a bus master. Figure 10-3. PCI Bus Write PCLK 1 2 3 4 5 6 7 8 PFRAME PAD PCBE Address data #1 CMD BE #1 data #2 BE #2 PIRDY PTRDY PDEVSEL PXAS PXDS PXBLAST 132 of 183 data #3 BE #3 9 10 DS31256 256-Channel, High-Throughput HDLC Controller 10.1.3 PCI Bus Arbitration The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been granted, the initiator waits until both PIRDY and PFRAME are deasserted (i.e., an idle cycle) before acquiring the bus and beginning the transaction. As shown in Figure 10-3, the bus was still being used when it was granted and the device had to wait until clock cycle #6 before it acquired the bus and began the transaction. The arbiter can deassert PGNT at any time and the initiator must relinquish the bus after the current transfer is complete, which can be limited by the latency timer. Figure 10-4. PCI Bus Arbitration Signaling Protocol PCLK 1 2 3 4 5 6 7 8 10 9 PREQ PGNT PFRAME Wait for PGNT Asserted and then PFRAME and PIRDY Deasserted 10.1.4 Bus is Acquired Bus is Relinquished PCI Initiator Abort If a target fails to respond to an initiator by asserting PDEVSEL and PTRDY within 5 clock cycles, then the initiator aborts the transaction by deasserting PFRAME and then, one clock later, by deasserting PIDRY (Figure 10-5). If such a scenario occurs, it is reported through the master abort status bit in the PCI command/status configuration register (Section 10.2). Figure 10-5. PCI Initiator Abort PCLK 1 2 3 4 5 PFRAME PIRDY PTRDY PDEVSEL 133 of 183 6 7 8 9 10 DS31256 256-Channel, High-Throughput HDLC Controller 10.1.5 PCI Target Retry Targets can terminate the requested bus transaction before any data is transferred because the target is busy and temporarily unable to process the transaction. Such a termination is called a target retry and no data is transferred. A target retry is signaled to the initiator by the assertion of PSTOP and not asserting PTRDY on the initial data phase (Figure 10-6). When the DS31256 is a target, it only issues a target retry when the host is accessing the local bus. This occurs when the local bus is operating in the arbitration mode. It is busy at the instant the host requests access to the local bus. See Section 11.1 for more details about the operation of the local bus. Figure 10-6. PCI Target Retry PCLK 1 2 3 4 5 6 7 8 9 10 PFRAME PIRDY PTRDY PSTOP PDEVSEL 10.1.6 PCI Target Disconnect A target can prematurely terminate a transaction by asserting PSTOP (Figure 10-7). Depending on the current state of the ready signals when PSTOP is asserted, data may or may not be transferred. The target always deasserts PSTOP when it detects that the initiator has deasserted PFRAME. When the DS31256 is a target, it disconnects with data after the first data phase is complete, if the master attempts a burst transaction. This is because the device does not support burst transactions when it is a target. When it is an initiator and experiences a disconnect from the target, it attempts another bus transaction (if it still has the bus granted) after waiting either one (disconnect without data) or two clock cycles (disconnect with data). Figure 10-7. PCI Target Disconnect PCLK 1 2 3 4 5 PFRAME PSTOP PDEVSEL 134 of 183 6 7 8 9 10 DS31256 256-Channel, High-Throughput HDLC Controller 10.1.7 PCI Target Abort Targets can also abort the current transaction, which means they do not wish for the initiator to attempt the request again. No data is transferred in a target abort scenario. A target abort is signaled to the initiator by the simultaneous assertion of PSTOP and deassertion of PDEVSEL (Figure 10-8). When the DS31256 is a target, it only issues a target abort when the host is accessing the local bus. This occurs when the host attempts a bus transaction with a combination of byte enables (PCBE) that are not supported by the local bus. If such a scenario occurs, it reports through the target-abort-initiated status bit in the PCI command/status configuration register (Section 10.2). See Section 11.1 for details about local bus operation. When the DS31256 is a bus master, if it detects a target abort, it reports through the target abort detected by master status bit in the PCI command/status configuration register (Section 10.2). Figure 10-8. PCI Target Abort PCLK 1 2 3 4 5 PFRAME PTRDY PSTOP PDEVSEL 135 of 183 6 7 8 9 10 DS31256 256-Channel, High-Throughput HDLC Controller 10.1.8 PCI Fast Back-to-Back Fast back-to-back transactions are two consecutive bus transactions without the usually required idle cycle (PFRAME and PIRDY deasserted) between them. This can only occur when there is a guarantee that there is not any contention on the signal lines. The PCI specification allows two types of fast backto-back transactions—those that access the same agent (Type 1) and those that do not (Type 2). Figure 10-9 shows an example of a fast back-to-back transaction where no idle cycle exists. As a bus master, the DS31256 cannot perform a Type 2 access. As a target, it can accept both types of fast backto-back transactions. Figure 10-9. PCI Fast Back-To-Back PCLK 1 2 3 4 5 6 7 PFRAME PAD PCBE Address data #1 data #2 Address data #1 CMD BE #1 BE #2 CMD BE #1 PIRDY PTRDY PDEVSEL 136 of 183 data #2 BE #2 8 9 10 DS31256 256-Channel, High-Throughput HDLC Controller 10.2 PCI Configuration Register Description Register Name: Register Description: Register Address: PVID0 PCI Vendor ID/Device ID Register 0 0x000 LSB Vendor ID (Read Only/Set to EAh) Vendor ID (Read Only/Set to 13h) Device ID (Read Only/Set to 34h) MSB Device ID (Read Only/Set to 31h) Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was assigned by Dallas Semiconductor and is fixed at 3134h. Register Name: Register Description: Register Address: STEPC PCMD0 PCI Command/Status Register 0 0x004 PARC VGA MWEN SCC MASC Reserved (Read Only/Set to All Zeros) FBBCT MSB PPE UDF 66MHz PSE MABT MSC FBBEN LSB IOC PSEC Reserved (Read Only/Set to All Zeros) TABTM TABT DTS1 DTS0 PARR Note: Read-only bits in the PCMD0 register are underlined; all other bits are read-write. The lower word (bits 0 to 15) of the PCMD0 register is the command portion and is used for PCI bus control. When all bits in the lower word are set to 0, the device is logically disconnected from the bus for all accesses, except for accesses to the configuration registers. The upper word (bits 16 to 31) is the status portion and is used for status information. Reads to the status portion behave normally but writes are unique in that bits can be reset (i.e., forced to 0) but not set (i.e., forced to 1). A bit in the status portion resets when 1 is written to that bit position. Bit positions that have 0 written to them do not reset. 137 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 10.2.1 Command Bits (PCMD0) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses by the PCI bus to the memory space (the internal device configuration registers). When this bit is set to 0, the device ignores accesses attempted to the internal configuration registers. When set to 1, the device allows accesses to the internal configuration registers. This bit should be set to 0 when the local bus is operated in the configuration mode. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = ignore accesses to the internal device configuration registers 1 = allow accesses to the internal device configuration registers Bit 2/Master Control (MASC). This read/write bit controls whether or not the device can act as a master on the PCI bus. When this bit is set to 0, the device cannot act as a master. When it is set to 1, the device can act as a bus master. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = deny the device from operating as a bus master 1 = allow the device to operate as a bus master Bit 3/Special Cycle Control (SCC). This read-only bit is forced to 0 by the device to indicate that it cannot decode special cycle operations. Bit 4/Memory Write and Invalidate Command Enable (MWEN). This read-only bit is forced to 0 by the device to indicate that it cannot generate the memory write and invalidate command. Bit 5/VGA Control (VGA). This read-only bit is forced to 0 by the device to indicate that it is not a VGAcompatible device. Bit 6/Parity Error Response Control (PARC). This read/write bit controls whether or not the device should ignore parity errors. When this bit is set to 0, the device ignores any parity errors that it detects and continues to operate normally. When this bit is set to 1, the device must act on parity errors. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = ignore parity errors 1 = act on parity errors Bit 7/Address Stepping Control (STEPC). This read-only bit is forced to 0 by the device to indicate that it is not capable of address/data stepping. Bit 8/PCI System Error Control (PSEC). This read/write bit controls whether or not the device should enable the PSERR output pin. When this bit is set to 0, the device disables the PSERR pin. When this bit is set to 1, the device enables the PSERR pin. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = disable the PSERR pin 1 = enable the PSERR pin Bit 9/Fast Back-to-Back Master Enable (FBBEN). This read-only bit is forced to 0 by the device to indicate that it is not capable of generating fast back-to-back transactions to different agents. Bits 10 to 15/Reserved. These read-only bits are forced to 0 by the device. 138 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 10.2.2 Status Bits (PCMD0) The upper word in the PCMD0 register is the status portion, which reports events as they occur. As previously mentioned, reads of the status portion occur normally but writes are unique in that bits can only be reset (i.e., forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no effect. This allows individual bits to be reset. Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device. Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable of running at 66MHz. Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it does not support user-definable features. Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent. Bit 24/PCI Parity Error Reported (PARR). This read/write bit is set to 1 when the device is a bus master and detects or asserts the PPERR signal when the PARC command bit is enabled. This bit can be reset (set to 0) by the host by writing 1 to this bit. 0 = no parity errors have been detected 1 = parity errors detected Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the device to indicate that it is capable of the medium timing requirements for the PDEVSEL signal. Bit 27/Target Abort Initiated (TABT). This read-only bit is forced to 0 by the device since it does not terminate a bus transaction with a target abort when the device is a target. Bit 28/Target Abort Detected by Master (TABTM). This read/write bit is set to 1 when the device is a bus master and it detects that a bus transaction has been aborted by the target with a target abort. This bit can be reset (set to 0) by the host by writing 1 to this bit. Bit 29/Master Abort (MABT). This read/write bit is set to 1 when the device is a bus master and the bus transaction is terminated with a master abort (except for special cycle). This bit can be reset (set to 0) by the host by writing 1 to this bit. Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the PSERR signal. This bit can be reset (set to 0) by the host by writing 1 to this bit. Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error (even if parity is disabled through the PARC command bit). This bit can be reset (set to 0) by the host by writing 1 to this bit. 139 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: PRCC0 PCI Revision ID/Class Code Register 0 0x008h LSB Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) Class Code (Read Only/Set to 80h) MSB Class Code (Read Only/Set to 02h) Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, which is selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface. These read-only bits identify the subclass interface value for the device and are fixed at 00h. See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Bits 16 to 23/Class Code Subclass. These read-only bits identify the subclass value for the device and are fixed at 80h, which indicate “Other Network Controller.” See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Bits 24 to 31/Class Code Base Class. These read-only bits identify the base class value for the device and are fixed at 02h, which indicate “Network Controllers.” See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Register Name: Register Description: Register Address: PLTH0 PCI Latency Timer/Header Type Register 0 0x00Ch LSB Cache Line Size Latency Timer Header Type (Read Only/Set to 80h) MSB BIST (Read Only/Set to 00h) Bits 0 to 7/Cache Line Size. These read/write bits indicate the cache line size in terms of dwords. If the burst size of a data read transaction exceeds this value, the PCI block uses the memory read multiple command. Valid settings are 04h (4 dwords), 08h, 10h, 20h, and 40h (64 dwords). Other settings are interpreted as 00h. These bits are forced to 0 when a hardware reset is initiated through the PRST pin. Bits 8 to 15/Latency Timer. These read/write bits indicate the value of the latency timer (in terms of the number of PCI clocks) for use when the device is a bus master. These bits are forced to 0 when a hardware reset is initiated through the PRST pin. Bits 16 to 23/Header Type. These read-only bits are forced to 80h, which indicate a multifunction device. Bits 24 to 31/Built-In Self-Test (BIST). These read only bits are forced to 0. 140 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: PDCM PCI Device Configuration Memory Base Address Register 0x010h Base Address (Read Only/Set to 0h) PF Base Address TYPE1 TYPE0 LSB MSI Base Address (Read Only/Set to 0h) Base Address MSB Base Address Note: Read-only bits in the PDCM register are underlined; all other bits are read-write. Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the internal device configuration registers are mapped to memory space. Bits 1, 2/Type 0, Type 1. These read-only bits are forced to 00b to indicate that the internal device configuration registers can be mapped anywhere in the 32-bit address space. Bit 3/Prefetchable (PF). This read-only bit is forced to 0 to indicate that prefetching is not supported by the device for the internal device configuration registers. Bits 4 to 11/Base Address. These read-only bits are forced to 0 to indicate that the internal device configuration registers require 4kB of memory space. Bits 12 to 31/Base Address. These read/write bits define the location of the 4kB memory space that is mapped to the internal configuration registers. These bits correspond to the most significant bits of the PCI address space. Register Name: Register Description: Register Address: PINTL0 PCI Interrupt Line and Pin/Minimum Grant/Maximum Latency Register 0 0x03Ch LSB Interrupt Line Interrupt Pin (Read Only/Set to 01h) Maximum Grant (Read Only/Set to 05h) MSB Maximum Latency (Read Only/Set to 0 Fh) Bits 0 to 7/Interrupt Line. These read/write bits indicate and store interrupt line routing information. The device does not use this information, it is only posted here for the host to use. Bits 8 to 15/Interrupt Pin. These read-only bits are forced to 01h to indicate that PINTA is used as an interrupt. Bits 16 to 23/Minimum Grant. These read-only bits are used to indicate to the host how long of a burst period the device needs, assuming a clock rate of 33MHz. The values placed in these bits specify a period of time in 0.25µs increments. These bits are forced to 05h. Bits 24 to 31/Maximum Latency. These read-only bits are used to indicate to the host how often the device needs to gain access to the PCI bus. The values placed in these bits specify a period of time in 0.25µs increments. These bits are forced to 0Fh. 141 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: PVID1 PCI Vendor ID/Device ID Register 1 0x100h LSB Vendor ID (Read Only/Set to EAh) Vendor ID (Read Only/Set to 13h) Device ID (Read Only/Set to 34h) MSB Device ID (Read Only/Set to 31h) Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was assigned by Dallas Semiconductor and is fixed at 3134h. Register Name: Register Description: Register Address: STEPC PCMD1 PCI Command/Status Register 1 0x104h PARC VGA MWEN SCC MASC Reserved (Read Only/Set to All Zeros) FBBCT MSB PPE UDF 66MHz PSE MABT MSC LSB IOC FBBEN PSEC Reserved (Read Only/Set to All Zeros) TABTM TABT DTS1 DTS0 PARR Note: Read-only bits in the PCMD1 register are underlined; all other bits are read-write. The lower word (bits 0 to 15) of the PCMD1 register is the command portion and is used for the PCI bus control. When all bits in the lower word are set to 0, the device is logically disconnected from the bus for all accesses, except for accesses to the configuration registers. The upper word (bits 16 to 31) is the status portion and is used for status information. Reads to the status portion behave normally but writes are unique in that bits can be reset (i.e., forced to 0) but not set (i.e., forced to 1). A bit in the status portion is reset when a 1 is written to that bit position. Bit positions that have 0 written to them do not reset. 142 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 10.2.3 Command Bits (PCMD1) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses by the PCI bus to the memory space, which is the local bus. When this bit is set to 0, the device ignores accesses attempted to the local bus. When set to 1, the device allows accesses to the local bus. This bit should be set to 0 when the local bus operates in configuration mode. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = ignore accesses to the local bus 1 = allow accesses to the bus Bit 2/Master Control (MASC). This read-only bit is forced to 0 by the device since it cannot act as a bus master. Bit 3/Special Cycle Control (SCC). This read-only bit is forced to 0 by the device to indicate that it cannot decode special cycle operations. Bit 4/Memory Write and Invalidate Command Enable (MWEN). This read-only bit is forced to 0 by the device to indicate that it cannot generate the memory write and invalidate command. Bit 5/VGA Control (VGA). This read-only bit is forced to 0 by the device to indicate that it is not a VGAcompatible device. Bit 6/Parity Error Response Control (PARC). This read/write bit controls whether or not the device should ignore parity errors. When this bit is set to 0, the device ignores any parity errors that it detects and continues to operate normally. When this bit is set to 1, the device must act on parity errors. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = ignore parity errors 1 = act on parity errors Bit 7/Address Stepping Control (STEPC). This read-only bit is forced to 0 by the device to indicate that it is not capable of address/data stepping. Bit 8/PCI System Error Control (PSEC). This read/write bit controls whether or not the device should enable the PSERR output pin. When this bit is set to 0, the device disables the PSERR pin. When this bit is set to 1, the device enables the PSERR pin. This bit is forced to 0 when a hardware reset is initiated through the PRST pin. 0 = disable the PSERR pin 1 = enable the PSERR pin Bit 9/Fast Back-to-Back Master Enable (FBBEN). This read-only bit is forced to 0 by the device to indicate that it is not capable of generating fast back-to-back transactions to different agents. Bits 10 to 15/Reserved. These read-only bits are forced to 0 by the device. 143 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 10.2.4 Status Bits (PCMD1) The upper word in the PCMD1 register is the status portion, which reports events as they occur. As mentioned earlier, reads of the status portion occur normally, but writes are unique in that bits can only be reset (i.e., forced to 0). This occurs when a 1 is written to a bit position. Writes with a 0 to a bit position have no effect. This allows individual bits to be reset. Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device. Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable of running at 66MHz. Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it does not support user-definable features. Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent. Bit 24/PCI Parity Error Reported (PARR). This read-only bit is forced to 0 by the device since the device cannot act as a bus master. Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the device to indicate that they are capable of the medium timing requirements for the PDEVSEL signal. Bit 27/Target Abort Initiated (TABT). This read/write bit is set to 1 when the device terminates a bus transaction with a target abort. This occurs only when the local bus is operating in the bus arbitration mode and the local bus does not have bus control when the host requests access. This bit can be reset (set to 0) by the host by writing a 1 to this bit. Bit 28/Target Abort Detected by Master (TABTM). This read-only bit is forced to 0 by the device since the device cannot act as a bus master. Bit 29/Master Abort (MABT). This read-only bit is forced to 0 by the device since the device cannot act as a bus master. Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the PSERR signal (even if it is disabled through the PSEC command bit). This bit can be reset (set to 0) by the host by writing 1 to this bit. Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error. The host can reset this bit (set to 0) by writing a 1 to this bit. 144 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: PRCC1 PCI Revision ID/Class Code Register 1 0x108h LSB Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) Class Code (Read Only/Set to 80h) MSB Class Code (Read Only/Set to 06h) Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface. These read-only bits identify the subclass interface value for the device and are fixed at 00h. See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Bits 16 to 23/Class Code Subclass. These read-only bits identify the subclass value for the device and are fixed at 80h, indicating “Other Bridge Device.” See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Bits 24 to 31/Class Code Base Class. These read-only bits identify the base class value for the device and are fixed at 06h, which indicate “Bridge Devices.” See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Register Name: PLTH1 Register Description: Register Address: PCI Latency Timer/Header Type Register 1 0x10Ch LSB Cache Line Size (Read Only/Set to 00h) Latency Timer (Read Only/Set to 00h) Header Type (Read Only/Set to 80h) MSB BIST (Read Only/Set to 00h) Bits 0 to 7/Cache Line Size. These read-only bits are forced to 0. Bits 8 to 15/Latency Timer. These read-only bits are forced to 0 by the device since the device cannot act as a bus master. Bits 16 to 23/Header Type. These read-only bits are forced to 80h, which indicate a multifunction device. Bits 24 to 31/Built-In Self-Test (BIST). These read-only bits are forced to 0. 145 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Register Name: Register Description: Register Address: PLBM PCI Local Bus Memory Base Address Register 0x110h LSB Base Address (Read Only/Set to 0h) PF TYPE1 Base Address TYPE0 MSI Base Address (Read Only/Set to 0h) Base Address MSB Base Address Note: Read-only bits in the PLBM register are underlined; all other bits are read-write. Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the local bus is mapped to memory space. Bits 1 and 2/Type 0 and Type 1. These read-only bits are forced to 00b to indicate that the local bus can be mapped anywhere in the 32 bit address space. Bit 3/Prefetchable (PF). This read-only bit is forced to 0 to indicate that prefetching is not supported by the device for the local bus. Bits 4 to 19/Base Address. These read-only bits are forced to 0 to indicate that the local bus requires 1MB of memory space. Bits 20 to 31/Base Address. These read/write bits define the location of the 1MB memory space that is mapped to the local bus. These bits correspond to the most significant bits of the PCI address space. Register Name: Register Description: Register Address: PINTL1 PCI Interrupt Line and Pin/Minimum Grant/Maximum Latency Register 1 0x13Ch LSB Interrupt Line Interrupt Pin (Read Only/Set to 01h) Maximum Grant (Read Only/Set to 00h) MSB Maximum Latency (Read Only/Set to 00h) Bits 0 to 7/Interrupt Line. These read/write bits indicate and store interrupt line routing information. The device does not use this information, it is only posted here for the host to use. Bits 8 to 15/Interrupt Pin. These read-only bits are forced to 01h to indicate that PINTA is used as an interrupt. Bits 16 to 23/Minimum Grant. These read-only bits are forced to 0. Bits 24 to 31/Maximum Latency. These read-only bits are forced to 0. 146 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 11. LOCAL BUS 11.1 General Description The local bus can operate in two modes, either as a PCI bridge (master mode) or as a configuration bus (slave mode). This selection is made in hardware by connecting the LMS pin high or low. Figure 11-1 shows an example of the local bus operating in the PCI bridge mode. In this example, the host can access the control ports on the T1/E1 devices through the local bus. Figure 11-2 also shows an example of the PCI bridge mode, but the local bus arbitration is enabled, which allows a local CPU to control when the host can have access to the local bus. To access the local bus, the host must first request the bus and then wait until it is granted. Figure 11-3 features an example of the configuration mode. In this mode, the CPU on the local bus configures and monitors the DS31256. In this mode, the host on the PCI/custom bus cannot access the DS31256 and the PCI/custom bus is only used to transfer HDLC packet data to and from the host. Table 11-A lists all the local bus pins and their applications in both operating modes. The local bus operates only in a nonmultiplexed fashion; it is not capable of operating as a multiplexed bus. For both operating modes, the local bus can be set up for either Intel or Motorola type buses. This selection is made in hardware by connecting the LIM pin high or low. Table 11-A. Local Bus Signals SIGNAL FUNCTION PCI BRIDGE MODE (LMS = 0) CONFIGURATION MODE (LMS = 1) LD[0:15] Data Bus Input on Read/Output on Write Input on Write/Output on Read LA[0:19] Address Bus Output Input LWR (LR/W) Bus Write (Read/Write Select) Output Input LRD (LDS) Bus Read (Data Strobe) Output Input LBHE Byte High Enable Output Tri-stated LIM Intel/Motorola Select Input Input LINT Interrupt Input Output LMS Mode Select Input Input LCLK Bus Clock Output Tri-stated LRDY Bus Ready Input Ignored LCS Chip Select Ignored Input LHOLD (LBR) Hold Request (Bus Request) Output Tri-stated LHLDA (LBG) Hold Acknowledge (Bus Grant) Input Ignored LBGACK Bus Acknowledge Output Tri-stated Note: Signals shown in parentheses are active when Motorola mode (LIM = 1) is selected. 147 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-1. Bridge Mode T1 / E1 Framer or Transceiver PCI / Custom Bus T1 / E1 Framer or Transceiver DS31256 Host Processor and Main Memory T1 / E1 Framer or Transceiver T1 / E1 Framer or Transceiver Local Bus Figure 11-2. Bridge Mode with Arbitration Enabled T1 / E1 Framer or Transceiver PCI / Custom Bus DS31256 T1 / E1 Framer or Transceiver T1 / E1 Framer or Transceiver 1 2 T1 / E1 Framer or Transceiver 3 1. Request Bus Access 2. Bus Access Granted 3. Transaction Occurs Local Bus Local CPU that Handles the Real-Time Tasks Required by the T1 / E1 Interfaces 148 of 183 Local RAM & ROM Host Processor and Main Memory DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-3. Configuration Mode T1 / E1 Framer or Transceiver DS31256 T1 / E1 Framer or Transceiver No Access Allowed T1 / E1 Framer or Transceiver PCI / Custom Bus Host Processor and Main Memory Only Used to Transfer HDLC Data T1 / E1 Framer or Transceiver Local Bus CPU Configures and Monitors Ds31256 11.1.1 Local RAM & ROM PCI Bridge Mode In PCI bridge mode, data from the PCI bus can be transferred to the local bus. The local bus acts as a “master” and creates all the necessary signals to control the bus. The user must configure the local bus bridge mode control register (LBBMC), which is described in Section 11.2. With 20 address lines, the local bus can address 1MB address space. The host on the PCI bus determines where to map this 1MB address space within the 32-bit address space of the PCI bus by configuring the base address in the PCI configuration registers (Section 10). Bridge Mode 8-Bit and 16-Bit Access During a bus access by the host, the local bus can determine how to map the four possible byte positions from/to the PCI bus to/from the local bus data bus (LD) pins by examining the PCBE signals and the local bus width (LBW) control bit that resides in the local bus bridge mode control (LBBMC) register. If the local bus is used as an 8-bit bus (LBW = 1), then the host must only assert one of the PCBE signals. The PCI data is mapped to/from the LD[7:0] signal lines; the LD[15:0] signal lines remain inactive. The local bus block drives the A0 and A1 address lines according to the assertion of the PCBE signals by the host. See Table 11-B for details. If the host asserts more than one of the PCBE signals when the local bus is configured as an 8-bit bus, then the local bus rejects the access and the PCI block returns a target abort to the host. See Section 10 for details about a target abort. 149 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting PCBE [3:0] 1110 1101 1011 0111 A1 0 0 1 1 A0 0 1 0 1 LBHE 1 1 1 1 Note 1: All other possible states for PCBE cause the device to return a target abort to the host. Note 2: The 8-bit data picked from the PCI bus is routed/sampled to/from the LD[7:0] signal lines. Note 3: If no PCBE signals are asserted during an access, a target abort is not returned and no transaction occurs on the local bus. If the local bus is used as 16-bit bus, the LBW control bit must be set to 0. In 16-bit accesses, the host can either perform 16-bit access or an 8-bit access by asserting the appropriate PCBE signals (Table 11-C). For 16-bit access, the host enables the combination of either PCBE0/PCBE1 or PCBE2/PCBE3 and the local bus block maps the word from/to the PCI bus to/from the LD[15:0] signals. For 8-bit access in the 16-bit bus mode, the host must assert just one of the PCBE0 to PCBE3 signals. If the host asserts a combination of PCBE signals not supported by the local bus, the local bus rejects the access and the PCI block returns a target abort to the host. See Section 10 for details on a target abort. Section 11.3 contains a number of timing examples for the local bus. Table 11-C. Local Bus 16-Bit Width Address, LD, LBHE Setting PCBE [3:0] 1110 1101 1100 1011 0111 0011 8/16 8 8 16 8 8 16 A1 0 0 0 1 1 1 A0 0 1 0 0 1 0 LD[15:8] Active Active Active Active LD[7:0] Active Active Active Active LBHE 1 0 0 1 0 0 Note 1: All other possible states for PCBE cause the device to return a target abort to the host. Note 2: The 16-bit data picked from the PCI bus is routed/sampled to/from the LD[7:0] and LD[15:8] signal lines as shown. Note 3: If no PCBE signals are asserted during an access, a target abort is not returned and no transaction occurs on the local bus. Bridge Mode Bus Arbitration In bridge mode, the local bus can arbitrate for bus access. In order for this feature to operate, the host must access the PCI bridge mode control register (LBBMC) and enable it through the LARBE control bit (the default is bus arbitration disabled). If bus arbitration is enabled, then, before a bus transaction can occur, the local bus first requests bus access by asserting the LHOLD (LBR) signal and then waits for the bus to be granted from the local bus arbiter by sensing that the LHLDA (LBG) has been asserted. If the host on the PCI bus attempts a local bus access when the local bus is not granted by the local bus master (LBGACK is deasserted), the local bus block immediately informs the host by issuing a PCI target retry that the local bus is busy and cannot be accessed at that time (in other words, come back later). See Section 10 for details about the PCI target retry. When this happens, the local bus block does not attempt the bus access and keeps the LA, LD, LBHE, LWR (LR/W), and LRD (LDS) signals tri-stated. If the host attempts a local bus access when the bus is busy, the local bus block requests bus access, and, after it has been granted, it seizes the bus for the time programmed into the local bus arbitration timer (LAT0 to LAT3 in the LBBMC register), which can be from 32 to 1,048,576 clocks. As long as the local bus has been granted and the arbitration timer has at least 16 clocks left, the host is allowed to access the local bus. See Figure 11-4 and the timing examples in Section 11.3 for more details. 150 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bridge Mode Bus Transaction Timing When the local bus is operated in PCI bridge mode, the bus transaction time can be determined either from an external ready signal (LRDY) or from the PCI bridge mode control register (LBBMC), which allows a bus transaction time of 1 to 11 LCLK cycles. If the total access time to the local bus exceeds 16 PCLK cycles, the PCI access times out and a PCI target retry is sent to the host. This only occurs when LRDY has not been detected within 9 clocks. If this happens, the local bus error (LBE) status bit in the status master (SM) register is set. Additional details about the LBE status bit can be found in Section 5. More details about transaction timing can be found in Figure 10-4 and the timing examples in Section 11.3. Bridge Mode Interrupt In the PCI bridge mode, the local bus can detect an external interrupt through the LINT signal. If the local bus detects that the LINTA signal has been asserted, it then sets the LBINT status bit in the status master (SM) register. Setting this status bit can cause a hardware interrupt to occur at the PCI bus through the PINTA signal. This interrupt can be masked through the ISM register. See Section 5 for more details. 11.1.2 Configuration Mode In configuration mode, the local bus is used only to configure the device and obtain status information from the device. It is also used to configure the PCI configuration registers and therefore the PCI bus signal PIDSEL is disabled when the local bus is in the configuration mode. The DS31256 PCI configuration registers can't be accessed via the PCI bus when the DS31256 is in Configuration mode (LMS=1). In this mode no device registers are accessible via the PCI bus. Data cannot be passed from the local bus to the PCI bus in this mode. The PCI bus is only used as a high-speed I/O bus for the HDLC packet data. In this mode, bus arbitration, bus format, and the usersettable bus transaction time features are disabled. All bus accesses are based on 16-bit addresses and 16bit data in this mode. The upper four addresses (LA[19:16]) are ignored and 8-bit data accesses are not allowed. See Section 13 for the AC timing requirements. 151 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-4. Local Bus Access Flowchart PCI Host Initiates a Local Bus Access No Is Arbitration Enabled for the Local Bus? Yes Is the Local Bus Granted? Request the Bus No Yes Are there 16 Clocks Remaining? No Yes Yes Is the External Local Bus Ready (LRDY) Being Used? No Start 9 Clock Timer LRDY Active? Yes Local Bus Access Progresses No Timer Expired? No Yes Local Bus Access Progresses Set the LBE Status Bit Normal Access Occurs 152 of 183 PCI Target Retry Issued DS31256 256-Channel, High-Throughput HDLC Controller 11.2 Local Bus Bridge Mode Control Register Description Register Name: Register Description: Register Address: LBBMC Local Bus Bridge Mode Control 0040h Note: This register can only be accessed through the PCI bus and therefore only in the PCI bridge mode. In configuration mode, this register cannot be accessed. It is set to all zeros upon a hardware reset issued through the PRST pin. It is not affected by a software reset issued through the RST control bit in the master reset and ID (MRID) register. Bit # Name Default 7 n/a 0 6 LBW 0 5 LRDY3 0 4 LRDY2 0 3 LRDY1 0 2 LRDY0 0 1 LARBE 0 0 LCLKE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 LAT3 0 10 LAT2 0 9 LAT1 0 8 LAT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Local Bus Clock Enable (LCLKE) 0 = tri-state the LCLK output signal pin 1 = allow LCLK to appear at the pin Bit 1/Local Bus Arbitration Enable (LARBE). When enabled, the LHOLD (LBR), LBGACK, and LHLDA (LBG) signal pins are active and the proper arbitration handshake sequence must occur for a proper bus transaction. When disabled, the LHOLD (LBR), LBGACK, and LHLDA (LBG) signal pins are deactivated and bus arbitration on the local bus is not invoked. Also, the arbitration timer is enabled (see the description of the LAT0 to LAT3 bits) when LARBE is set to 1. 0 = local bus arbitration is disabled 1 = local bus arbitration is enabled Bit 2/Local Bus Ready Control Bit 0 (LRDY0). LSB Bit 3/Local Bus Ready Control Bit 1 (LRDY1) Bit 4/Local Bus Ready Control Bit 2 (LRDY2) Bit 5/Local Bus Ready Control Bit 3 (LRDY3). MSB. These control bits determine the duration of the local bus transaction in the PCI bridge mode. The bus transaction can either be controlled through the external LRDY input signal or through a predetermined period of 1 to 11 LCLK periods. 0000 = use the LRDY signal input pin to control the bus transaction 0001 = bus transaction is defined as 1 LCLK period 0010 = bus transaction is defined as 2 LCLK periods 0011 = bus transaction is defined as 3 LCLK periods 0100 = bus transaction is defined as 4 LCLK periods 0101 = bus transaction is defined as 5 LCLK periods 0110 = bus transaction is defined as 6 LCLK periods 0111 = bus transaction is defined as 7 LCLK periods 1000 = bus transaction is defined as 8 LCLK periods 1001 = bus transaction is defined as 9 LCLK periods 1010 = bus transaction is defined as 10 LCLK periods 1011 = bus transaction is defined as 11 LCLK periods 1100 = illegal state 1101 = illegal state 1110 = illegal state 1111 = illegal state 153 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Bit 6/Local Bus Width (LBW) 0 = 16 bits 1 = 8 bits Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These four bits determine the total time the local bus seizes the bus when it has been granted in the arbitration mode (LARBE = 1). This period is measured from LHLDA (LBG) being detected to LBGACK inactive. CONDITION 0000 = when granted, hold the bus for 32 LCLKs 0001 = when granted, hold the bus for 64 LCLKs 0010 = when granted, hold the bus for 128 LCLKs 0011 = when granted, hold the bus for 256 LCLKs 0100 = when granted, hold the bus for 512 LCLKs 1101 = when granted, hold the bus for 262,144 LCLKs 1110 = when granted, hold the bus for 524,288 LCLKs 1111 = when granted, hold the bus for 1,048,576 LCLKs 154 of 183 33MHz PCLK 0.97µs 1.9µs 3.9µs 7.8µs 15.5µs 7.9ms 15.9ms 31.8ms 25MHz PCLK 1.3µs 2.6µs 5.1µs 10.2µs 20.5µs 10.5ms 21.0ms 41.9ms DS31256 256-Channel, High-Throughput HDLC Controller 11.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been granted (LBGACK asserted), the timing shown at the bottom of the page applies. LCLK LHOLD LHLDA 32 to 1,048,576 LCLKs LBGACK Note: LA, LD, LBHE, LWR, and LRD are tri-stated. 1 LCLK Tri-state 2 3 Address Valid LA[19:0] LD[7:0] LD[15:8] Tri-State LBHE Tri-State LWR Tri-State LRD 155 of 183 4 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-6. 16-Bit Write Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page occurs, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been granted (LBGACK asserted), the timing shown at the bottom of the page applies. LCLK LHOLD LHLDA 32 to 1,048,576 LCLKs LBGACK Note: LA, LD, LBHE, LWR, and LRD are tri-stated. 1 LCLK Tri-State 2 3 Address Valid LA[19:0] Tri-State Data Valid LD[7:0] Tri-State Data Valid LD[15:8] Tri-State LBHE Tri-State LRD Tri-State LWR 156 of 183 4 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-7. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 Address Valid LD[7:0] LD[15:8] LBHE LWR LRD LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set. 157 of 183 10 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 10 Address Valid LD[7:0] LD[15:8] Data Valid LBHE LRD LWR LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set. 158 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page occurs, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been granted (LBGACK asserted), the timing shown at the bottom of the page applies. LCLK LBR LBG 32 to 1,048,576 LCLKs LBGACK Note: LA, LD, LBHE, LDS, and LR/W are tri-stated. 1 LCLK Tri-State LA[19:0] 2 3 Address Valid Data Valid LD[7:0] LD[15:8] Tri-State LBHE LR/W Tri-State Tri-State LDS 159 of 183 4 5 6 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-10. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page occurs, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been granted (LBGACK asserted), the timing shown at the bottom of the page applies. LCLK LBR LBG 32 to 1,048,576 LCLKs LBGACK Note: LA, LD, LBHE, LDS, and LR/W are tri-stated. 1 LCLK Tri-State LA[19:0] Tri-State LD[7:0] 2 3 Address Valid Data Valid Tri-State LD[15:8] Tri-State LBHE LR/W Tri-State Tri-State LDS 160 of 183 4 5 6 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-11. 16-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 10 Address Valid LD[7:0] LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set 161 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] LD[7:0] 1 2 3 4 5 6 7 8 9 10 Address Valid Data Valid Tri-State LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set. 162 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 12. JTAG 12.1 JTAG Description The DS31256 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. Figure 12-1 is a block diagram. The DS31256 contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The TAP has the necessary interface pins JTCLK, JTRST, JTDI, JTDO, and JTMS. Details about these pins can be found in Section 3.4. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b1994 for details about the Boundary Scan Architecture and the TAP. Figure 12-1. Block Diagram BOUNDARY SCAN REGISTER MUX IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER SELECT TEST ACCESS PORT CONTROLLER 10k JTDI 10k JTMS TRI-STATE 10k JTCLK JTRST 163 of 183 JTDO DS31256 256-Channel, High-Throughput HDLC Controller 12.2 TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See Figure 12-2 for details about each of the states. The TAP controller is a finite state machine, which responds to the logic level at JTMS on the rising edge of JTCLK. Figure 12-2. TAP Controller State Machine Test-Logic-Reset 1 0 Run-Test/Idle 1 Select DR-Scan 1 0 0 1 1 Select IR-Scan 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 0 1 1 1 Exit1-DR 0 0 Pause-DR Pause-IR 0 1 0 0 0 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 1 Exit1-IR 0 164 of 183 Update-IR 1 0 DS31256 256-Channel, High-Throughput HDLC Controller Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS31256 power-up. The instruction register contains the IDCODE instruction. All system logic on the DS31256 operates normally. Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test registers remain idle. Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-IR-Scan state. Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or it goes to the Exit1-DR state if JTMS is high. Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the UpdateDR state, which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR state. Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain their previous states. The controller remains in this state while JTMS is low. A rising edge on JTCLK with JTMS high puts the controller in the Exit2-DR state. Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the UpdateDR state and terminates the scanning process. A rising edge on JTCLK with JTMS low enters the ShiftDR state. Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output because of changes in the shift register. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. Select-IR-Scan. All test registers retain their previous states. The instruction register remains unchanged during this state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller enters the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state. Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel register as 165 of 183 DS31256 256-Channel, High-Throughput HDLC Controller well as all test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state while moving data one stage through the instruction shift register. Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge on JTCLK. Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The controller loops back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state. Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. 12.3 Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output, and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Table 12-A shows instructions supported by the DS31256 and their respective operational binary codes. Table 12-A. Instruction Codes INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001 SAMPLE/PRELOAD. SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the DS31256 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the CaptureDR state. SAMPLE/PRELOAD also allows the DS31256 to shift data into the boundary scan register through JTDI using the Shift-DR state. EXTEST. EXTEST allows testing of all interconnections to the DS31256. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs of all digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR samples all digital inputs into the boundary scan register. 166 of 183 DS31256 256-Channel, High-Throughput HDLC Controller BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s normal operation. IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code loads into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The device ID code always has 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. The device ID code for the DS31256 is 00006143h. 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An optional identification register has been included in the DS31256 design that is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Bypass Register This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions that provides a short path between JTDI and JTDO. Boundary Scan Register This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells. Visit www.maxim-ic.com/telecom for a downloadable BDSL file that contains all bit identity and definition information. Identification Register The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. 167 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 13. AC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS…....…………………………………………………….-0.3V to +3.63V Operating Temperature/Ambient Temperature Under Bias………………………………………………….0°C to +70°C Junction Temperature Under Bias……………………………………………………………………………………≤ 125°C Storage Temperature Range………………………………………………………………………………..-55°C to +125°C Soldering Temperature…………………………………………………………See IPC/JEDEC J-STD-020 Specification ESD Tolerance (Note 1)……………………………………………………Class 2 (2000V→4000V HBM: 1.5kΩ, 100pF) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 1 VIH (Notes 2, 3) 1.8 5.5 V Logic 0 VIL (Note 2) -0.3 +0.8 V Supply VDD 3.0 3.6 V TYP MAX UNITS 500 7 0.6 770 mA pF V µA µA µA mA mA pF pF DC CHARACTERISTICS (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER Supply Current at VDD = 3.6V Lead Capacitance Schmitt Hysteresis Input Leakage Input Leakage (with pullups) Output Leakage Output Current (2.4V) Output Current (0.4V) Output Capacitance Output Capacitance SYMBOL IDD CIO VTH IIL IILP ILO IOH IOL COUT COUTB CONDITIONS MIN (Note 4) (Note 5) (Note 5) (Note 6) (Note 1) (Note 1) -10 -500 -10 -4.0 +4.0 +10 +500 +10 25 50 Note 1: COUTB refers to bus-related outputs (PCI and local bus); COUT refers to all other outputs. Note 2: Assumes a reasonably noise-free environment. Note 3: The PCI 2.1 Specification states that VIH should be VDD/2 in a 3.3V signaling environment, and 2.0V in a 5V signaling environment. Note 4: Measured 550mA with RC0 to RC15 and TC0 to TC15 = 2.048MHz, PCLK = 33MHz, constant traffic on all ports. Note 5: 0V < VIN < VDD Note 6: Outputs in tri-state. Note 7: The typical values listed above are not production tested. Note 8: Dallas Semiconductor Communications devices are tested in accordance with ESDA STM 5.1-1998. 168 of 183 DS31256 256-Channel, High-Throughput HDLC Controller AC CHARACTERISTICS: LAYER 1 PORTS (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL RC/TC Clock Period t1 RC/TC Clock Low Time t2 RC/TC Clock High Time t3 RD Setup Time to the Falling Edge or Rising Edge of RC RS/TS Setup Time from the Falling Edge or Rising Edge of RC/TC RD Hold Time from the Falling Edge or Rising Edge of RC RS/TS Hold Time from the Falling Edge or Rising Edge of RC/TC Delay from the Rising Edge or Falling Edge of TC to Data Valid on TD t4 CONDITIONS (Note 9) (Note 10) (Note 9) (Note 10) (Note 9) (Note 10) (Note 9) (Note 10) MIN 100 19 40 8 40 8 5 2 TYP MAX UNITS ns ns ns ns t4 (Note 9) 5 t1 - 10 t5 (Note 9) (Note 10) 5 5 t5 (Note 9) 5 t1 - 10 ns t6 (Note 9) (Note 10) 5 3 25 15 ns ns Note 9: Ports 0 to 15 in applications running up to 10MHz. Note 10: Port 0, 1, or 2 running in applications up to 52MHz. Note 11: Aggregate, maximum bandwidth and port speed for the DS31256 are directly proportional to PCLK frequency. Throughput measurements are made at PCLK = 33MHz. Figure 13-1. Layer 1 Port AC Timing Diagram t1 t2 t3 RC[n] / TC[n] Normal Mode RC[n] / TC[n] Inverted Mode t4 t5 RD[n] / RS[n] / TS[n] t6 TD[n] l1 ac Note: TC and RC are independent of each other. In the above timing diagram, all the signals beginning with “T” reference the transmit clock TC; all signals beginning with “R” reference the receive clock RC. 169 of 183 ns DS31256 256-Channel, High-Throughput HDLC Controller AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 0) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL Delay Time from the Rising Edge of PCLK to Output Valid from Tri-state Delay Time from the Rising Edge of PCLK to Tri-State from Output Valid Delay Time from the Rising Edge of PCLK to Output Valid from an Already Active Drive State LD[15:0] Setup Time to the Rising Edge of PCLK LD[15:0] Hold Time from the Rising Edge of PCLK Input Setup Time to the Rising Edge of PCLK Input Hold Time from the Rising Edge of PCLK Delay Time from the Rising Edge of PCLK to the Rising Edge of LCLK Delay Time from the Falling Edge of PCLK to the Falling Edge of LCLK CONDITIONS MIN TYP MAX UNITS t1 7 17 ns t2 7 15 ns t3 6 14 ns t4 1 ns t5 5 ns t6 1 ns t7 5 ns t8 4 7 ns t9 5 8 ns Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram PCLK t1 LA[19:0], LD[15:0], LBHE, LWR (LR/W), LRD (DS) Data Valid Tri-state t2 LA[19:0], LWR (LR/W), LRD (LDS), LBHE Tri-state Data Valid t3 LA[19:0], LWR (LR/W), LRD (DS), LHOLD (LBR), LBGACK Data Valid t4 t5 t6 t7 LD[15:0] LINT, LRDY LHLDA (LBG) t8 LCLK t9 170 of 183 DS31256 256-Channel, High-Throughput HDLC Controller AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 1) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time for LA[15:0] Valid to LCS Active t1 0 ns Setup Time for LCS Active to Either LRD, LWR, or LDS Active t2 0 ns Delay Time from Either LRD or LDS Active to LD[15:0] Valid t3 Hold Time from Either LRD, LWR, or LDS Inactive to LCS Inactive t4 0 Hold Time from Either LRD or LDS Inactive to LD[15:0] Tri-State t5 5 Wait Time from Either LWR or LDS Active to Latch LD[15:0] t6 LD[15:0] Setup Time to Either LWR or LDS Inactive (Note 12) (Note 13) 75 ns ns 20 ns 75 ns t7 10 ns LD[15:0] Hold Time from Either LWR or LDS Inactive t8 2 ns LA[15:0] Hold from Either LWR, LRD, or LDS Inactive t9 5 ns LRD, LWD, or LDS Inactive Time t10 65 ns (Note 14) Note 12: Given value for 33MHz PCLK. Calculated as 1.5 x (PCLK Period) + 30ns Note 13: Given value for 33MHz PCLK. Calculated as 2 x (PCLK Period) + 15ns Note 14: Given value for 33MHz PCLK. Calculated as 2 x (PCLK Period) + 5ns 171 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams Intel Read Cycle t9 LA[15:0] t9 Address Valid Data Valid LD[15:0] t5 LWR t1 LCS t2 t3 t4 t10 LRD Intel Write Cycle LA[15:0] Address Valid LD[15:0] t7 LRD t8 t1 LCS t2 t6 t4 t10 LWR 172 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued) Motorola Read Cycle t9 LA[15:0] Address Valid Data Valid LD[15:0] t5 LR/W t1 LCS t2 t3 t4 t10 LDS Motorola Write Cycle t9 LA[15:0] Address Valid LD[15:0] t7 LR/W LCS t8 t1 t2 t6 t4 t10 LDS 173 of 183 DS31256 256-Channel, High-Throughput HDLC Controller AC CHARACTERISTICS: PCI BUS INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS (Note 15) MIN TYP UNITS 40 ns PCLK Period t1 PCLK Low Time t2 12 ns PCLK High Time All PCI Inputs and I/O Setup Time to the Rising Edge of PCLK All PCI Inputs and I/O Hold Time from the Rising Edge of PCLK Delay from the Rising Edge of PCLK to Data Valid on All PCI Outputs and I/O Delay from the Rising Edge of PCLK to Tri-State on All PCI Outputs and I/O Delay from the Rising Edge of PCLK to Active from Tri-State on All PCI Outputs and I/O t3 12 ns t4 7 ns t5 0 ns t6 30 MAX (Note 16) 2 t7 t8 2 11 ns 28 ns ns Note 15: Aggregate, maximum bandwidth and port speed for the DS31256 are directly proportional to PCLK frequency. Ensure that PCLK is 33MHz for maximum throughput. Note 16: The PCI extension signals PABLAST, PXAS, and PXDS have a 15ns max. These signals are not part of the PCI Specification. Figure 13-5. PCI Bus Interface AC Timing Diagram t1 t2 t3 PCLK t4 t5 PCI Input & I/O t6 PCI Output Data Valid & I/O t7 Tri-State PCI Output & I/O to Tri-State t8 PCI Output & I/O from Tri-State Tri-State 174 of 183 DS31256 256-Channel, High-Throughput HDLC Controller AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN JTCLK Clock Period JTCLK Clock Low Time JTCLK Clock High Time JTMS/JTDI Setup Time to the Rising Edge of JTCLK JTMS/JTDI Hold Time from the Rising Edge of JTCLK Delay Time from the Falling Edge of JTCLK to Data Valid on JTDO t1 t2 t3 1000 400 400 ns ns ns t4 50 ns t5 50 ns t6 2 Figure 13-6. JTAG Test Port Interface AC Timing Diagram t1 t2 t3 JTCLK t4 t5 JTMS/JTDI t6 JTDO 175 of 183 TYP MAX 50 UNITS ns DS31256 256-Channel, High-Throughput HDLC Controller 14. REVISION HISTORY REVISION 112102 073103 101104 DESCRIPTION New product release. Corrected various typographical errors, including: Lifted some usage restrictions Changed maximum number of T1 links from 64 to 60 Added U12 as a Ground in Table 3-A. Removed PCI t5 and VIH exceptions to PCI 2.1 compliance. Changed 8191 to 8188 in Figure 9-1 to be dword consistent. Changed Logic 1 minimum from 2.2V to 1.8V in Section 13. Added typical supply current and increase the maximum in Section 13. Added typical supply current and increase the maximum in Section 13. Removed t5 compliance issue and added Note 16 in Section 13, PCI. Added Chapter 15, Thermal Properties. Updated recommended components in Section 17:Applications. Page 109: Removed “Chateau” from Figure 9-11. Page 137, Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was assigned by Dallas Semiconductor and is fixed at 31256h. The device ID is 3134, not 31256. Page 142, Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was assigned by Dallas Semiconductor and is fixed at 31256h. The device ID is 3134, not 31256. Page 151: Section 11.1.2 Configuration Mode. Added info about how data cannot be passed from the local bus to the PCI bus in this mode—The DS31256 PCI configuration registers cannot be accessed via the PCI bus when the DS31256 is in Configuration mode (LMS=1). In this mode no device registers are accessible via the PCI bus. 031405 Page 83: Added the last paragraph that states the DS31256 has no restrictions on the transmit side, but lists the restrictions on the location and size of the receive buffers in host memory. Page 90: Removed “Chateau” from Figure 9-2. 012506 Added lead-free package information to Ordering Information table (page 1). Section 3.3: Local Bus Signal Description: • Removed sentence “These signals are sampled on the rising edge of LCLK to determine the internal device configuration register that the external host wishes to access.” from LA0 to LA19 description. • Removed sentence “In configuration mode (LMS = 1), this signal is sampled on the rising edge of LCLK.” from LWR(LR/W) description. • Removed sentence “In configuration mode (LMS = 1), this signal is sampled on the rising edge of LCLK.” from LRD(LDS) description. 176 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 15. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.1 256-pin PBGA (27mm x 27mm) (56-G6004-001) 177 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 16. THERMAL CHARACTERISTICS Table 16-A. Thermal Properties, Natural Convection PARAMETER Ambient Temperature Junction Temperature Theta-JA (θJA), Still Air Psi-JB (ΨJB), Still Air Psi-JT (ΨJT), Still Air CONDITIONS MIN TYP 0 0 (Note 1) MAX UNITS +70°C +125°C °C °C °C/W °C/W °C/W 15.4 7.03 0.07 (Note 2) Note 1: The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power. Note 2: Theta-JA (θJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power. Table 16-B. Thermal Properties vs. Airflow FORCED AIR (m/s) 0 1 2.5 THETA-JA (θJA) 15.4°C/W 13.0°C/W 11.9°C/W Psi-JB (ΨJB) 7.03°C/W 6.77°C/W 6.53°C/W Psi-JT (ΨJT) 0.07°C/W 0.40°C/W 0.57°C/W Figure 16-1. 27mm x 27mm PBGA with 256 Balls, 2oz Planes, +70°C Ambient, Under Natural Convection at 3.0W 178 of 183 DS31256 256-Channel, High-Throughput HDLC Controller 17. APPLICATIONS This section describes some possible applications for the DS31256. There are numerous potential configurations but only a few are shown. Users are encouraged to contact the factory for support of their particular application. Email telecom.support@dalsemi.com or visit our website at www.maxim-ic.com/telecom for more information. The T1 and E1 channelized application examples in this section are one of two types. The first type is where a single T1 or E1 data stream is routed to and from the DS31256. This is represented as a thin arrow in the application examples (Figure 17-1). Figure 17-2 shows the electrical connections. The second type is where four T1 or E1 data streams have been TDM into a single 8.192MHz data stream, which is routed to and from the DS31256. This type is represented as a thick arrow in Figure 17-1. Figure 17-3 shows the electrical connections. Figure 17-1. Application Drawing Key 1x 4x SINGLE T1 OR E1 LINE AT 1.544MHz OR 2.048MHz QUAD (4) T1 OR 31 LINES BYTE INTERLEAVED AT 8.192MHz Figure 17-2. Single T1/E1 Line Connection RC RD RS DS31256 TC TD TS RCLK RSER RSYNC TCLK TSER TSYNC DALLAS FRAMER OR TRANSCEIVER (ELASTIC STORES DISABLED) Note: A looped timed application is shown. The transmit clock may be decoupled from the receive in timing master applications. 179 of 183 DS31256 256-Channel, High-Throughput HDLC Controller Figure 17-3. Quad T1/E1 Connection 17.1 16 Port T1 or E1 with 256 HDLC Channel Support Figure 17-4 shows an application where 16 T1 or E1 links are framed and interfaced to a single DS31256. The T1 lines can be either clear-channel or channelized. The DS21Q55 quad T1/E1/J1 single-chip transceiver performs the line interface function and frames to the T1/E1/J1 line. Figure 17-4. 16-Port T1 Application DS31256 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 DS21455 Quad T1/E1 Transceiver Four DS21455 Quad T1/E1 Transceiver Four T1 or E1Lines Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Quad T1/E1 Transceiver T1 or E1Lines DS21455 DS21455 Quad T1/E1 Transceiver 180 of 183 Four T1 or E1Lines Four T1 or E1Lines DS31256 256-Channel, High-Throughput HDLC Controller 17.2 Dual T3 with 256 HDLC Channel Support Figure 17-5 shows an application where two T3 lines are interfaced to a single DS31256. The T3 lines are demultiplexed by DS3112 M13 devices and passed to the DS21FF42 4 x 4 16-channel T1 framer and DS21FT42 4 x 3 12-channel T1 framer devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256 by aggregating four T1 lines into a single 8.192MHz data stream, which then flows into and out of the DS31256. The T1 lines can be either clear channel or channelized. Figure 17-5. Dual T3 Application DS31256 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 DS21FF42 4x4 16-Channel T1 Framer DS21FT42 4x3 12-Channel T1 Framer DS21FF42 4x4 16-Channel T1 Framer DS21FT42 4x3 12-Channel T1 Framer 181 of 183 1 2 16 17 18 DS3152 Dual T3/E3 LIU 28 1 2 16 17 18 28 T3 Line #1 DS3112 M13 Interface DS3112 M13 Interface T3 Line #2 DS31256 256-Channel, High-Throughput HDLC Controller 17.3 Single T3 with 512 HDLC Channel Support Figure 17-6 shows an application where a T3 line is interfaced to two DS31256s. The T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.192MHz data stream is not required since the DS31256 has enough physical ports to support the application, but aggregation could be done to cut down on the number of electrical connections between the DS31256 and the T1 framers. The T1 lines can be either clear channel or channelized. Figure 17-6. T3 Application (512 HDLC Channels) DS31256 #1 DS31256 #2 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 DS21FF42 4x4 16-Channel T1 Framer 1 2 16 17 18 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 28 DS21FT42 4x3 12-Channel T1 Framer 182 of 183 DS3112 M13 Interface DS31256 256-Channel, High-Throughput HDLC Controller 17.4 Single T3 with 672 HDLC Channel Support Figure 17-7 shows an application where a fully channelized T3 line is interfaced to three DS31256s. The T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.192MHz data stream is not required since the DS31256 has enough physical ports to support the applicationm, but aggregation could be done to cut down on the number of electrical connections between the DS31256 and the T1 framers. The T1 lines can be either clear channel or channelized. Figure 17-7. T3 Application (672 HDLC Channels) DS31256 #1 (Supports 10 T1 Lines) DS31256 #2 (Supports 10 T1 Lines) DS31256 #3 (Supports 8 T1 Lines) Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 DS21FF42 Four x Four 16-Channel T1 Framer 1 2 16 DS3112 M13 Interface 17 18 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 28 DS21FT42 Four x Three 12-Channel T1 Framer Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 183 of 183 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. 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