PRELIMINARY
PRELIMINARY
DS3150
3.3V T3 / E3 / STS-1 Line Interface
www.dalsemi.com
FEATURES
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Integrated transmit and receive for T3, E3 and
STS-1 line interfaces
Performs clock/data recovery and wave
shaping
Requires no special external components
other than 1:2 transformers
Interfaces to 75Ω coaxial cable at lengths up
to 380 meters (T3), 440 meters (E3), or
360 meters (STS-1)
Adaptive receive equalizer handles from 0 dB
to 15 dB of cable loss
Interfaces directly to a DSX monitor signal
(20 dB flat loss)
On-chip jitter attenuator can be placed either
in the receive path or the transmit path
Built-in B3ZS and HDB3 coder/decoder
Bipolar and NRZ interfaces
Analog and digital loopbacks
Onboard 215 – 1 and 223 – 1 Pseudo Random
Bit Sequence (PRBS) generator and detector
Transmit line driver monitor checks for a
faulty transmitter or a shorted output
Complete T3 AIS generator (ANSI T1.107)
Unframed all ones generator (E3 AIS)
Digital clock inversion capability
Tri-state line driver for low-power mode
Loss of signal detector (ANSI T1.231-1999
and ITU G.775)
Pin compatible to the TDK 78P7200 and
78P2241 footprint
Low power 3.3V operation (5V tolerant I/O)
Industrial temperature range: -40°C to +85°C
Small packaging: 28-lead PLCC, 48-lead
TQFP and 49-lead CSBGA (7 x 7 mm)
FUNCTIONAL DIAGRAM
DS3150 LIU
Line In
T3, E3,
STS-1
RX+
RX–
RCLK
RPOS
RNEG
Receive
Clock and
Data
Line Out
T3, E3,
STS-1
TX+
TX–
TCLK
TPOS
TNEG
Transmit
Clock and
Data
ORDERING INFORMATION
DS3150QN
DS3150Q
DS3150TN
DS3150T
DS3150GN
DS3150G
1 of 22
28-lead PLCC (-40°C to +85°C)
28-lead PLCC (0°C to 70°C)
48-lead TQFP (-40°C to +85°C)
48-lead TQFP (0°C to 70°C)
49-lead CSBGA (-40°C to +85°C)
49-lead CSBGA (0°C to 70°C)
110200
DS3150
TABLE OF CONTENTS
Section 1:
Section 2:
Section 3:
Section 4:
Section 5:
Section 6:
Functional Description ……………………………………………………………
Signal Description…………………………………………………………………
AC Characteristics …………………………...………………...…………………
Pin Assignments …………………………………………………………………
Mechanical Dimensions ………………...……………...…………………………
Applications……………..………………………………………………………...
2
11
15
17
19
22
SECTION 1: FUNCTIONAL DESCRIPTION
The DS3150 performs all of the functions necessary for interfacing at the physical layer to T3, E3, and
STS-1 lines. The device has independent receive and transmit paths. See Figure 1A. The receiver
performs clock and data recovery from a B8ZS- or HDB3-code AMI signal and monitors for loss of the
incoming signal. The recovered data optionally can be B8ZS/HDB3 decoded and output in NRZ format.
The transmitter accepts either NRZ or bipolar data and drives standard pulse-shape waveforms onto
75 ohm coaxial cable. The receiver and transmitter sections will be discussed separately below. Table 1A
lists the telecommunications standards that the DS3150 was designed to meet.
DS3150 Block Diagram Figure 1A
RMON
MCLK
LOS*
Output Decode
Digital Loss Of
Signal Detector
(Analog
Loss Of
Signal
Detect)
squelch
Analog
Loopback
DM*
Driver
Monitor
TX+
Line
Driver
WaveShaping
TX-
mux
Clock
Invert
Power
Connections
TTS*
LBKS*
LBO
VDD
VSS
RCLK
Remote
Loopback
ZCSE*
ICE
TESS
TNEG
TPOS/TNRZ
B3ZS/
HDB3
Encoder
Loopback Control
liu_bd
RPOS/RNRZ
RNEG
Clock
Invert
mux
RX-
Clock &
Data
Recovery
mux
20dB
Flat
Gain
Jitter Attenuator
(can be placed in either the receive path or the transmit path)
RX+
PRBS
Detector
B3ZS/HDB3
Decoder
Filter /
Equalizer
PRBS
AIS /
1010.../
PRBS
Generation
Test Functions
EFE
2 of 22
TDS0
TDS1
TCLK
DS3150
Applicable Standards Table 1A
T1.102-1993
T1.107-1995
T1.231-1997
T1.231-1993
T1.404-1994
GR-499-CORE
GR-253-CORE
G.703, 1991
G.751, 1993
G.823, 1993
G.775, 1994
O.151, 1992
TBR 24, 1997
ETS 300 687, 1996
ETS 300 686, 1996
(ANSI) “Digital Hierarchy – Electrical Interfaces”
(ANSI) “Digital Hierarchy - Formats Specification”
(ANSI) Draft “Digital Hierarchy - Layer 1 In-Service Digital Transmission
Performance Monitoring”
(ANSI) “Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance
Monitoring”
(ANSI) “Network-to-Customer Installation - DS3 Metallic Interface Specification”
(Bellcore) Issue 1, December1995 “Transport Systems Generic Requirements
(TSGR): Common Requirements”
(Bellcore) Issue 2, December 1995 “SONET Transport Systems: Common
Generic Criteria”
(ITU) “Physical/Electrical Characteristics of Hierarchical Digital Interfaces
(ITU) “Digital Multiplex Equipment Operating at the Third Order Bit Rate of
34,368 kbit/s and the Fourth Order bit Rate of 139,264 kbit/s and Using Postive
Justification”
(ITU) “The Control of Jitter and Wander Within Digital Networks Which are
Based on the 2048 kbit/s Hierarchy”
(ITU) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection
and Clearance Criteria”
(ITU)“Error Performance Measuring Equipment Operating at the Primary Rate and
Above”
(ETSI) “Business TeleCommunications; 34Mbit/s digital unstructured and
structured lease lines; attachment requirements for terminal equipment interface
(ETSI) “Business TeleCommunications; 34Mbit/s digital leased lines (D34U and
D34S); Connection characteristics
(ETSI) “Business TeleCommunications; 34Mbit/s and 140Mbits/s digital leased
lines (D34U, D34S, D140U and D140S); Network interface presentation
RECEIVER
The DS3150 interfaces to the receive T3/E3/STS-1 coax line via a 1:2 step up transformer. See
Figure 1B. The receiver automatically adapts to coax cable loses from 0 to 15 dB which translates into
0 to 380 meters (T3) or 440 meters (E3) or 360 meters (STS-1) of coax cable (AT&T 734A or
equivalent). The receiver has the ability to interface to monitor jacks as well. Via the RMON input (see
Table 2A), the device can be configured to insert a 20 dB flat boost into the incoming signal. Monitor
jacks typically have series resistors that result in a resistive loss of 20 dB. The receiver has excellent
jitter tolerance characteristics. See Figure 1C.
The receiver contains both analog and digital loss-of-signal detectors. The analog loss of signal detector
resides in the equalizer. If the incoming signal drops below –24 dB of the nominal signal level, the
analog loss-of-signal detector will activate and it will step on the recovered data and force all zeros out of
the data recovery circuitry. The analog loss-of-signal detector will not clear until the signal level is above
-18 dB of the nominal signal level. The digital Loss of Signal (LOS) detector is activated when it detects
192±1 consecutive zeros. LOS is cleared when there are no Excessive Zero occurrences over a span of
192±1 clock periods. An Excessive Zero occurrence is defined as 3 or more consecutive zeros in the T3
and STS-1 modes and 4 or more zeros in the E3 mode. The status of the digital LOS is reflected at the
LOS* output (see Table 2A). There is no status output available for the analog loss-of-signal detector.
While the device is in a loss-of-signal state, the RCLK output will be referenced to the MCLK input (or
the TCLK input if MCLK is high/floating or to the internal oscillator if MCLK is tied low). The analog
3 of 22
DS3150
loss-of-signal detector has a longer time constant than the digital LOS. Hence when the incoming signal
is lost, the digital LOS will activate first followed by the analog loss-of-signal detector. When a signal is
restored, the digital LOS will not be allowed to qualify a signal for no Excessive Zero violations until the
analog loss-of-signal detector has seen the signal rise above –18 dB. Governing specifications for the
loss-of-signal detectors are ANSI T1.231 and ITU G.775.
The recovered data from the receiver can be output in either bipolar format or a Non Return to Zero
(NRZ) format. To select the bipolar format, the ZCSE* input is tied high. In this format, the
B3ZS/HDB3 decoder is disabled and the received data is buffered and then output on the RPOS and
RNEG outputs. To select the NRZ format, the ZCSE* input is tied low. In this format, the B3ZS/HBD3
decoder is enabled and the recovered data is B3ZS/HDB3 decoded and then logically OR’ed together and
output at the RPOS output while the RNEG output is forced low.
DS3150 EXTERNAL CONNECTION Figure 1B
Transmit
DS3150
0.1uF
VDD
TX+
0.1uF
1uF
0.01uF
0.1uF
1uF
0.01uF
0.1uF
1uF
3.3V
Power
Plane
VDD
330Ω
(1%)
0.05uF
0.01uF
TX-
VDD
RX+
VSS
1:2ct
Receive
Ground
Plane
VSS
330Ω
(1%)
0.05uF
VSS
RX1:2ct
DS3150 RECEIVER JITTER TOLERANCE Figure 1C
10
T3 [GR-499 (1995)]
Category II
10
5
Jitter
Tolerance
(UIpp)
T3 [GR-499 (1995)]
Category I
E3 [G.823(1993)]
DS3150
Jitter
Tolerance
1.5
1.0
0.3
0.15
0.1
0.1
669
10
100
2.3K
1K
Frequency (Hz)
4 of 22
22.3K
10K
60K
300K 800K
100K
1M
DS3150
TRANSMITTER
Via the ZCSE* input, the device is configured to accept either bipolar data or NRZ data to be input to the
transmitter. When the ZCSE* input is tied high, bipolar data must be applied at the TPOS and TNEG
inputs. In this mode, the device will not perform B3ZS/HDB3-encoding on the outgoing data stream.
When the ZCSE* input is tied low, an NRZ data stream must be applied at the TPOS input (TNEG is
ignored). In this mode, the device will perform B3ZS/HDB3-encoding on the outgoing data stream.
The clock applied at the TCLK input is used to transmit data onto the T3/E3/STS-1 line. Hence TCLK
must be of transmission quality (i.e. accurate to ±20 ppm). The duty cycle of TCLK is not a key
parameter as long as the clock high and low times listed in Section 3 are met.
The DS3150 also has the ability to generate a number of different patterns, including an unframed all
ones pattern (which is also the E3 AIS signal), a 101010… pattern, or a T3 Alarm Indication Signal
(AIS). See Figure 1E for a description of the T3 AIS. The TDS0 and TDS1 inputs are used to select
these onboard patterns. See Tables 2A and 2B.
The DS3150 interfaces to the transmit T3/E3/STS-1 coax cable via a 1:2 step up transformer. See Figure
1B. It will drive the 75 ohm cable and create the proper waveforms required for interfacing to
T3/E3/STS-1 lines. In T3 and STS-1 modes, the LBO (Line Build-Out) pin controls waveform shape.
For cable lengths less than 225 feet, LBO should be pulled high. For 225 feet or more of cable, LBO
should be pulled low. Tables 1C through 1G and Figure 1D detail the waveform template specifications
and testing parameters.
The transmitter can be disabled and the TX+ and TX– outputs tri-stated via the TTS* input. See
Table 2A for details.
The transmit driver monitor constantly checks the analog signal output at TX+ and TX–. If the output
fails, then the DM* output will be pulled low. See Figures 1F and 1G. When the transmitter is disabled
(TTS* = 0) or enhanced features are disabled (EFE=0), the driver monitor is also disabled.
T3 TRANSMIT WAVEFORM TEMPLATE Table 1C
Time Axis Range
Normalized Amplitude Equations
Upper Curve
-0.85 ≤ T ≤ -0.68
-0.68 ≤ T ≤ 0.36
0.36 ≤ T ≤ 1.4
0.03
0.5 {1 + sin[(π/2)(1 + T/0.34)]} + 0.03
0.08 + 0.407e-1.84(T - 0.36)
Lower Curve
-0.03
-0.85 ≤ T ≤ -0.36
-0.36 ≤ T ≤ 0.36
0.5 {1 + sin[(π/2)(1 + T/0.18)]} - 0.03
-0.03
0.36 ≤ T ≤ 1.4
Governing Specifications: ANSI T1.102-1993 and Bellcore GR-499.
5 of 22
DS3150
T3 TRANSMIT WAVEFORM TEST PARAMETERS AND LIMITS Table 1D
Parameter
Rate
Line code
Transmission medium
Test measurement point
Test termination
Pulse amplitude
Pulse shape
Unframed All Ones Power level
@ 22.368 MHz
Unframed All Ones Power level
@ 44.736 MHz
Pulse imbalance of isolated pulses
Specification
44.736 Mbit/s (± 20 ppm)
B3ZS
coax cable (AT&T 734A or equivalent)
At the end of 0 to 450 feet of coax cable
75Ω (± 1%) resistive
Between 0.36V and 0.85V
An isolated pulse (preceded by two zeros and followed by
one or more zeros) falls within the curved listed in Table
1C
Between –1.8 dBm and +5.7 dBm
At least 20 dB less than the power measured at 22.368
MHz
Ratio of positive and negative pulses must be between
0.90 and 1.10
STS-1 TRANSMIT WAVEFORM TEMPLATE Table 1E
Time Axis Range
Normalized Amplitude Equations
Upper Curve
-0.85 ≤ T ≤ -0.68
-0.68 ≤ T ≤ 0.26
0.26 ≤ T ≤ 1.4
0.03
0.5 {1 + sin[(π/2)(1 + T/0.34)]} + 0.03
0.1 + 0.61e-2.4(T - 0.26)
Lower Curve
-0.03
-0.85 ≤ T ≤ -0.36
-0.36 ≤ T ≤ 0.36
0.5 {1 + sin[(π/2)(1 + T/0.18)]} - 0.03
-0.03
0.36 ≤ T ≤ 1.4
Governing Specifications: Bellcore GR-253 and Bellcore GR-499.
STS-1 TRANSMIT WAVEFORM TEST PARAMETERS AND LIMITS Table 1F
Parameter
Rate
Line code
Transmission medium
Test measurement point
Test termination
Pulse shape
Unframed All Ones Power level
@ 25.92 MHz
Unframed All Ones Power level
@51.84 MHz
Specification
51.840 Mbit/s (± 20 ppm)
B3ZS
coax cable (AT&T 734A or equivalent)
At the end of 0 to 450 feet of coax cable
75Ω (± 1%) resistive
An isolated pulse (preceded by two zeros and followed by
one or more zeros) falls within the curved listed in Table
1E
Between –1.8 dBm and +5.7 dBm
At least 20 dB less than the power measured at 25.92
MHz
6 of 22
DS3150
E3 TRANSMIT WAVEFORM TEMPLATE Figure 1D
1.2
1.1
17ns
1.0
0.9
0.8
8.65ns
0.7
G.703
E3
Template
Output
0.6
Level (V)
0.5
0.4
12.1ns
0.3
0.2
0.1
24.5ns
0
-0.1
29.1ns
-0.2
Time (ns)
E3 TRANSMIT WAVEFORM TEST PARAMETERS AND LIMITS Table 1G
Parameter
Rate
Line code
Transmission medium
Test measurement point
Test termination
Pulse amplitude
Pulse shape
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
Specification
34.368 Mbit/s (± 20 ppm)
HDB3
coax cable (AT&T 734A or equivalent)
At the transmitter
75Ω (± 1%) resistive
1.0V (nominal)
An isolated pulse (preceded by two zeros and
followed by one or more zeros) falls within the
template shown in Figure 1D
0.95 to 1.05
0.95 to 1.05
7 of 22
DS3150
T3 AIS STRUCTURE Figure 1E
M1 Subframe
84
X1 Info F1
(1) Bits (1)
84
Info
Bits
M2 Subframe
84
X2 Info F1
(1) Bits (1)
C1
(0)
84
Info
Bits
84
Info
Bits
M3 Subframe
84
P1 Info F1
(0) Bits (1)
84
Info
Bits
M4 Subframe
84
P2 Info F1
(0) Bits (1)
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
C1
(0)
84
Info
Bits
C1
(0)
84
Info
Bits
84
Info
Bits
M5 Subframe
84
M1 Info F1
(0) Bits (1)
84
Info
Bits
M6 Subframe
84
M2 Info F1
(1) Bits (1)
M7 Subframe
84
M3 Info F1
(0) Bits (1)
F4
(1)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
NOTES:
X1 is transmitted first.
The 84 Info Bits are the sequence 101010… where the one (“1”) starts after each X, P, F, C, or M bit.
8 of 22
DS3150
DIAGNOSTICS
The DS3150 contains an onboard Pseudo Random Binary Sequence (PRBS) generator and detector. This
function is useful in testing the device at the physical layer. It will generate and detect either a 215 – 1
(T3 or STS-1) or 223 – 1 PRBS according to the ITU O.151 specification. The PRBS pattern generated
and detected by the DS3150 is an unframed pattern. In other words, no T3, E3, or STS-1 framing
patterns are inserted in the transmit data stream nor expected in the received data stream. The PRBS
generator is enabled via the TDS0 and TDS1 inputs. See Tables 2A and 2B for details. The PRBS
detector is always enabled and will report it’s status via the PRBS output if signal EFE = 1. When the
PRBS detector is out of synchronization, the PRBS output will be forced high. When the PRBS detector
synchronizes to the incoming pseudorandom pattern, the PRBS output will go low and then pulse high for
each bit detected in error. See Figures 1F and 1G. On the receive side, the recovered data is
B3ZS/HDB3 decoded before it is routed to the PRBS decoder.
The DS3150 also has two internal loopbacks that can be used for testing. See Figure 1A. The Analog
Loopback loops the outgoing transmit waveform back to the receiver. When this loopback is enabled,
data will be transmitted as it normally would be and the incoming data at RX+ and RX– is ignored. The
Remote Loopback loops data from the receive side to the transmit side. When this loopback is enabled,
data will continue to pass through the receive side as it normally would and data at the TPOS and TNEG
inputs is ignored. These two loopbacks are invoked via the LBKS* input. See Table 2A.
PRBS OUTPUT WITH NORMAL RCLK OPERATION Figure 1F
ICE = 0 or 1
RCLK
PRBS
PRBS Detector
is Not in Sync
PRBS Detector is In Sync; the PRBS
Signal Will Pulse High for Each Bit Error Detected
PRBS OUTPUT WITH INVERTED RCLK OPERATION Figure 1G
ICE = Float
RCLK
PRBS
PRBS Detector
is Not in Sync
PRBS Detector is In Sync; the PRBS
Signal Will Pulse High for Each Bit Error Detected
9 of 22
DS3150
JITTER ATTENUATOR
The DS3150 contains an onboard jitter attenuator that can be placed in either the receive path or the
transmit path or disabled. This selection is made via the RMON and TTS* input signals. See Table 1H
below for details. Figure 1H shows the minimum jitter attenuation for the device when the jitter
attenuator is enabled. Figure 1H also shows the receive jitter transfer when the jitter attenuator is
disabled. Depending on whether the device is in the T3/STS-1 or E3 mode, the jitter attenuation will be
adjusted. Note that for best results, a highly accurate clock source should be present at MCLK (or at
TCLK if MCLK is tied high or left floating).
RMON & TTS* SIGNAL DECODE Table 1H
RMON
0
0
0
1
1
1
Float
Float
Float
TTS*
0
1
Float
0
1
Float
0
1
Float
Receive 20 dB
Flat Gain
disabled
disabled
disabled
enabled
enabled
enabled
disabled
disabled
disabled
Transmit Line
Driver
tri-stated
enabled
enabled
tri-stated
enabled
enabled
tri-stated
enabled
enabled
Jitter Attenuator
disabled
disabled
enabled in TX path
disabled
disabled
enabled in TX path
enabled in RX path
enabled in RX path
enabled in RX path
DS3150 JITTER ATTENUATION / JITTER TRANSFER Figure 1H
17Hz
800
60K
0
T3 [GR-499 (1995)]
E3 [TBR24 (1997)]
-10
Jitter
Attenuation
(dB)
DS3150
T3 / STS-1
Minimum
Jitter
Attenuation
DS3150
E3
Minimum
Jitter
Attenuation
-20
DS3150
Typical
Receiver
Jitter
Transfer with
Jitter
Attenuation
Disabled
-30
15K
10
100
1K
Frequency (Hz)
10 of 22
10K
100K
1M
DS3150
SECTION 2: SIGNAL DESCRIPTIONS
Table 2A below lists all of the signals on the DS3150 and their function. The signals are listed in
alphabetical order. Section 4 shows the signal pin assignments for each package option.
SIGNAL DESCRIPTIONS Table 2A
Signal
Name
DM*
I/O
O
EFE
I3
ICE
I3
LBKS*
I3
LBO
I
LOS*
O
MCLK
I
Description
Driver Monitor (active low, open drain). This signal reports the status of the transmit
driver monitor. When the transmit driver monitor detects a faulty transmitter, this
pin is pulled low. This pin should have an external pull-up to VDD. This signal is not
bonded out in the PLCC package.
Enhanced Feature Enable. This signal enables the enhanced DS3150 features (PRBS
generation/detection; transmit driver monitor; and transmission of all ones, T3 AIS or
the 1010… pattern).
0 = Enhanced Features Disabled: TDS0 and TDS1 ignored, PRBS/DM tri-stated
1 = Enhanced Features Enabled: TDS0, TDS1 and PRBS/DM active
Float = Test Mode Enabled: TDS0, TDS1, LBO, LOS* redefined as test pins
Invert Clock Enable. This signal determines on which RCLK edge RPOS and RNEG
are updated and on which TCLK edge TPOS and TNEG are sampled.
0 = Normal RCLK / Normal TCLK: update RPOS/RNRZ and RNEG on falling edge
of RCLK and sample TPOS/TNRZ and TNEG on rising edge of TCLK
1 = Normal RCLK / Inverted TCLK: update RPOS/RNRZ and RNEG on falling edge
of RCLK and sample TPOS/TNRZ and TNEG on falling edge of TCLK
Float = Inverted RCLK / Inverted TCLK: update RPOS/RNRZ & RNEG on rising
edge of RCLK and sample TPOS/TNRZ and TNEG on falling edge of TCLK
Loopback Select. This input determines if either the Analog Loopback or the
Remote Loopback is enabled. See the Block Diagram in Section 1 for details.
0 = Analog Loopback Enabled
1 = No Loopback Enabled
Float = Remote Loopback Enabled
Line Build-Out. This input indicates cable length for waveform shaping in DS3 and
STS-1 modes. LBO is ignored for E3 mode.
0 = Cable length less than 225 feet.
1 = Cable length greater than or equal to 225 feet.
Loss Of Signal (active low). This signal will be asserted upon detection of 192±1
consecutive zeros. Signals lower than 21dB below nominal are squelched. LOS* is
deasserted when there are no Excessive Zero occurrences over a span of 192±1 clock
periods. An Excessive Zero occurrence is defined as 3 or more consecutive zeros in
the T3 and STS-1 modes or 4 or more zeros in the E3 mode. Governing
Specifications are ANSI T1.231 and ITU G.775.
Master Clock. The clock input at this signal is used by the clock and data recovery
machine. A T3 (44.736 MHz ± 20 ppm), E3 (34.368 MHz ± 20 ppm), or STS-1
(51.840 MHz ± 20 ppm) clock should be applied at this signal. Tying this pin high or
leaving it floating forces the device to use the clock applied at the TCLK input for the
receive side clock and data recovery. Tying this pin low enables an internal
oscillator. The frequency of this oscillator is determined by a resistor placed between
OFSEL and VSS. MCLK has an internal 15 kΩ pull-up resistor to VDD.
11 of 22
DS3150
SIGNAL DESCRIPTIONS Table 2A (cont.)
PRBS
O3
RCLK
O
RMON
I3
RNEG
O
RPOS/
RNRZ
O
RX+
RX–
TCLK
I
TDS0
I
I
PRBS Detector. This signal reports the status of the PRBS Detector. The PRBS
detector will constantly search for either a 215 – 1 (T3 or STS-1) or 223 – 1 (E3)
psuedo random bit sequence. This signal will remain high when the PRBS detector is
out of synchronization. When the PRBS detector syncs to the PRBS, this signal will
go low and will create a high pulse (synchronous with RCLK) for each bit error
detected. See Figures 1F and 1G for more details. If EFE = 0, then this signal is tristated. This signal is not bonded out in the PLCC package.
Receive Clock. The recovered clock is output at this pin. When the DS3150
experiences a Loss Of Signal (LOS* = 0), the clock applied at MCLK (or TCLK if
MCLK is high/floating or the internal oscillator if MCLK is tied low) appears at this
signal. The recovered data is updated at the RPOS and RNEG outputs on either the
falling edge of RCLK (ICE = 0 or 1) or the rising edge of RCLK (ICE = FLOAT).
Receive Monitor Mode. This input determines whether or not a 20 dB flat gain will
be applied to the incoming signal before it is fed to the receive equalizer. This mode
is invoked when the device is being used to monitor signals that have been resistively
attenuated by a monitor jack. In this mode, the maximum input signal allowed at
RX+ and RX– is reduced by 20 dB. This input also controls the jitter attenuator. See
Table 2C.
0 = disable the 20 dB gain, disable RX jitter attenuation
1 = enable the 20 dB gain, disable RX jitter attenuation
Float = disable the 20 dB gain, enable RX jitter attenuation
Receive Negative Data. When the B3ZS/HBD3 encoder/decoder is disabled (ZCSE*
= 1), this signal indicates reception of a negative AMI pulse. When the B3ZS/HDB3
encoder/decoder is enabled (ZCSE* = 0), this signal will be forced low and the NRZ
data stream will be output at RPOS. This signal will be updated either on the rising
edge of RCLK (ICE = Float) or the falling edge of RCLK (ICE = 0 or 1) with the
recovered data stream.
Receive Positive or NRZ Data. When the B3ZS/HBD3 encoder/decoder is disabled
(ZCSE* = 1), this signal indicates reception of a positive AMI pulse. When the
B3ZS/HDB3 encoder/decoder is enabled (ZCSE* = 0), this signal will contain the
recovered NRZ data stream. This signal will be updated either on the rising edge of
RCLK (ICE = Float) or the falling edge of RCLK (ICE = 0 or 1) with the recovered
data stream.
Receive Analog Inputs. These differential AMI inputs are coupled to the T3, STS-1,
or E3 75Ω coax line via a 1:2 step-up transformer. See Figure 1B for details.
Transmit Clock. A T3 (44.736 MHz ± 20 ppm), E3 (34.368 MHz ± 20 ppm) or
STS-1 (51.840 ± 20 ppm) clock should be applied at this signal. Data to be
transmitted will be clocked into the device at TPOS/TNRZ and TNEG either on a
rising edge of TCLK (ICE = 0) or falling edge of TCLK (ICE = 1 or FLOAT). The
duty cycle on TCLK is not restricted as long it meets the high and low times listed in
Section 3.
Transmit Data Select Bit 0. If EFE = 1, this signal and signals TDS1 and TESS
select the source of the transmit data (see Table 2B). If EFE = 0, this signal is
ignored.
12 of 22
DS3150
SIGNAL DESCRIPTIONS Table 2A (cont.)
TDS1/
OFSEL
I
TESS
I3
TNEG
I
TPOS/
TNRZ
I
TTS*
I3
TX+
TX–
O3
VDD
VSS
ZCSE*
I
Transmit Data Select Bit 1 / Oscillator Frequency Select. If EFE = 1, this pin (TDS1)
and signals TDS0 and TESS select the source of the transmit data (see Table 2B). If
MCLK is tied low, TDS1 is internally pulled low and a resistor connected between
this pin (OFSEL) and ground determines the frequency of an internal oscillator. The
following resistor values should be used for specific applications.
E3:
6.81 kΩ
T3:
5.23 kΩ
STS1: 4.53 kΩ
If EFE = 0, this signal is ignored.
T3 / E3 / STS-1 Select. This input determines the mode of operation for the device.
0 = E3
1 = T3
Float = STS-1
Transmit Negative Data. For bipolar data, the B3ZS/HDB3 encoder/decoder should
be disabled (ZCSE* = 1) and TNEG should be driven high to generate a negative
AMI pulse on the coax. For NRZ data, the B3ZS/HDB3 encoder/decoder should be
enabled (ZCSE* = 0), the NRZ data stream should be applied to TNRZ, and TNEG is
ignored and can be tied either high or low. TNEG is sampled either on the falling
edge of TCLK (ICE = 1 or Float) or the rising edge of TCLK (ICE = 0).
Transmit Positive Data. For bipolar data, the B3ZS/HDB3 encoder/decoder should
be disabled (ZCSE* = 1) and TPOS should be driven high to generate a positive AMI
pulse on the coax. For NRZ data, the B3ZS/HDB3 encoder/decoder should be
enabled (ZCSE* = 0), the NRZ data stream should be applied to TNRZ, and TNEG is
ignored and can be tied either high or low. TPOS/TNRZ is sampled either on the
falling edge of TCLK (ICE = 1 or Float) or the rising edge of TCLK (ICE = 0).
Transmit Tri-State. This input determines whether the TX+ and TX– analog output
signals are forced into tri-state or are active. This input also controls the jitter
attenuator. See Table 2C.
0 = tri-state the transmit output driver, disable TX jitter attenuation
1 = enable the transmit driver, disable TX jitter attenuation
Float = enable the transmit driver, enable TX jitter attenuation
Transmit Analog Outputs. These differential AMI outputs drive the T3, STS-1, or E3
signal into the 75Ω coax line. They are coupled to the coax line via a 2:1 step-down
transformer. See Section 1 for details. These outputs can be tri-stated via the TTS*
input signal.
Positive Supply. 3.3V ± 5%. All VDD signals should be tied together.
Ground Reference. All VSS signals should be tied together.
Zero Code Suppression Enable.
0 = B3ZS/HDB3 encoder/decoder enabled (NRZ interface enabled)
1 = B3ZS/HDB3 encoder/decoder disabled (NRZ interface disabled)
NOTES:
•
•
•
I3 indicates an input capable of detecting 3 states, high, low and float. All I3 input have a 10 kΩ
pull-up to 1.5V.
O3 indicates an output that is tri-state capable.
Symbols appended with an asterisks (*) are active low signals.
13 of 22
DS3150
TRANSMIT DATA MODE SELECT PIN DESCRIPTIONS Table 2B
TDS1
0
0
1
1
1
1
TDS0
0
1
0
0
1
1
TESS
X
X
0 or float
1
0
1 or float
Transmit Mode Selected
Transmit data normally as input at TPOS and TNEG
Transmit Unframed All Ones
Transmit an Unframed 101010… pattern
Transmit T3 AIS as per ANSI T1.107 (see Figure 1E)
Transmit a 223 – 1 PRBS pattern as per ITU O.151
Transmit a 215 – 1 PRBS pattern as per ITU O.151
NOTES:
TDS0 and TDS1 are ignored when EFE is tied low and the device will transmit TPOS / TNEG data
RMON & TTS* SIGNAL DECODE Table 2C
RMON
0
0
0
1
1
1
Float
Float
Float
TTS*
0
1
Float
0
1
Float
0
1
Float
Receive 20 dB
Flat Gain
disabled
disabled
disabled
enabled
enabled
enabled
disabled
disabled
disabled
Transmit Line
Driver
tri-stated
enabled
enabled
tri-stated
enabled
enabled
tri-stated
enabled
enabled
14 of 22
Jitter Attenuator
disabled
disabled
enabled in TX path
disabled
disabled
enabled in TX path
enabled in RX path
enabled in RX path
enabled in RX path
DS3150
SECTION 3: AC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Lead with Respect to VSS (except VDD)
Supply Voltage (VDD) with Respect to VSS
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to 5.5V
-0.3V to 3.63V
-40°C to +85°C
-55°C to +125°C
See J-STD-020A specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
NOTE:
The typical values listed below are not production tested.
RECOMMEND DC OPERATING CONDITIONS
PARAMETER
Logic 1
Logic 0
Supply (VDD)
SYMBOL
VIH
VIL
VDD
MIN
2.4
-0.3
3.135
TYP
MAX
5.5
0.8
3.465
UNITS
V
V
V
NOTES
(-40°C to +85°C; VDD = 3.3V±
±5%)
DC CHARACTERISTICS
PARAMETER
Supply Current (VDD = 3.465V)
Power Down Current
(VDD = 3.465V)
Lead Capacitance
Input Leakage
Input Leakage (w/ pull-ups or float)
Output Current (2.4V)
Output Current (0.4V)
(-40°C to +85°C)
SYMBOL
IDD
IPD
CIO
IIL
IILP
IOH
IOL
MIN
TYP
TBD
TBD
MAX
7
-10
-500
-4.0
+4.0
+10
+500
UNITS
mA
mA
pF
uA
uA
mA
mA
NOTES
1
2
3
3
NOTES:
1. TCLK = MCLK = 44.736 MHz & TX+ and TX– driving all ones into a 75Ω load / other inputs at VDD
or grounded / other outputs left open circuited
2. MCLK = 44.736 MHz & TTS* = 0 / other inputs at VDD or grounded / other outputs left open
circuited
3. 0V < VIN < VDD
4. Outputs in Tri-State
15 of 22
DS3150
AC CHARACTERISTICS – DIGITAL
PARAMETER
RCLK / TCLK Clock Period
RCLK Clock High / Low Time
TCLK Clock High / Low Time
TPOS / TNEG to TCLK Setup Time
TPOS / TNEG Hold Time
RCLK to RPOS / RNEG Valid,
Signal Change on PRBS
(-40°C to +85°C; VDD = 3.3V±5%)
SYMBOL
t1
t1
t1
t2 / t3
t2 / t3
t2 / t3
t2 / t3
t4
t5
t6
MIN
TYP
22.4
29.1
19.3
11.2
14.5
9.6
9.0
11.6
7.7
7
2
2
2
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13.4
17.4
11.5
6
NOTES
1
2
3
1
2
3
4, 5
NOTES:
1.
2.
3.
4.
T3 Mode
E3 Mode
STS-1 Mode
In Normal Mode, TPOS and TNEG are sampled on the rising edge of TCLK and RPOS and RNEG are
updated on the falling edge of RCLK
5. In Inverted Mode, TPOS and TNEG are sampled on the falling edge of TCLK and RPOS and RNEG
are updated on the rising edge of RCLK
AC TIMING DIAGRAM Figure 3A
t1
t2
t3
RCLK (normal mode) /
TCLK (inverted mode)
TCLK (normal mode) /
RCLK (inverted mode)
t4
t5
TPOS / TNEG
t6
RPOS / RNEG /
PRBS
ac_tim
16 of 22
DS3150
SECTION 4: PIN ASSIGNMENTS
RX+
LBKS*
2
1
28 27 26
VDD
EFE
3
LOS*
RX-
25
RPOS/RNRZ
6
24
RNEG
VDD
7
23
RCLK
VSS
8
22
VSS
TX+
9
21
RMON
ICE
10
20
ZCSE*
TX–
11
19
MCLK
TTS*
VDD
TCLK
TNEG
12 13 14 15 16 17 18
TPOS/TNRZ
VSS
4
TESS
5
LBO
TDS1/OFSEL
TDS0
28-LEAD PLCC PIN ASSIGNMENT Figure 4A
48
47
46
45
44
43
42
41
40
39
38
37
VSS
VSS
TDS0
VSS
RX–
EFE
RX+
VSS
LBKS*
LOS*
VDD
VDD
48-LEAD TQFP PIN ASSIGNMENT Figure 4B
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
LBO
VSS
TESS
TPOS/TNRZ
TNEG
TCLK
VSS
VDD
VDD
TTS*
VSS
VSS
VSS
TDS1/OFSEL
VSS
VSS
VDD
VDD
VSS
DM*
TX+
ICE
TX–
VSS
17 of 22
36
35
34
33
32
31
30
29
28
27
26
25
VSS
RPOS/RNRZ
RNEG
RCLK
VSS
VSS
VSS
PRBS
RMON
ZCSE*
MCLK
VSS
DS3150
49-LEAD CSBGA PIN ASSIGNMENT Figure 4C
1
2
3
4
5
6
7
A
B
C
D
E
F
G
TOP VIEW
A
1
NC
2
TDS0
3
RX-
4
RX+
5
LBKS*
6
NC
B
VSS
NC
EFE
LOS*
VDD
RNEG
7
RPOS/
RNRZ
NC
C
VSS
NC
TDS1
NC
NC
NC
RCLK
D
DM*
VDD
NC
NC
PRBS
NC
VSS
E
TX+
NC
NC
NC
NC
MCLK
RMON
F
TX-
ICE
LBO
TESS
TCLK
NC
ZCSE*
G
NC
NC
TPOS/
TNRZ
TNEG
VDD
TTS*
NC
18 of 22
DS3150
SECTION 5: MECHANICAL DIMENSIONS
28-LEAD PLCC PACKAGE Figure 5A
19 of 22
DS3150
48-LEAD TQFP PACKAGE Figure 5B
NOTES:
1. DIMENSIONS D1 AND E1 INCLUDE MOLD
MISMATCH, BUT DO NOT INCLUDE MOLD
PROTRUSION; ALLOWABLE PROTRUSION IS 0.25
MM PER SIDE.
2. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL
BUT MUST BE LOCATED WITHIN THE ZONE
INDICATED.
3. ALLOWABLE DAMBAR PROTRUSION IS 0.08 MM
TOTAL IN EXCESS OF THE B DIMENSION; AT
MAXIMUM MATERIAL CONDITION. PROTRUSION
NOT TO BE LOCATED ON LOWER RADIUS OR
FOOT OF LEAD.
4. CONTROLLING DIMENSIONS: MILLIMETERS.
DIM
A
A1
A2
D
D1
E
E1
L
e
B
C
MIN MAX
1.20
0.05 0.15
0.95 1.05
8.80 9.20
7.00 BSC
8.80 9.20
7.00 BSC
0.45 0.75
0.50 BSC
0.17 0.27
0.09 0.20
20 of 22
DS3150
49-LEAD CSBGA PACKAGE Figure 5C
21 of 22
DS3150
SECTION 6: APPLICATIONS
CHANNELIZED T3/E3 APPLICATION Figure 6A
8.192MHz
I/F
PCI
Bus
256
Channel
HDLC
Controller
DS3112
TEMPE
DS3120/
DS3124
DS3134
CHATEAU
8.192MHz
I/F
28/21
Channel
T1/E1
Framer
T1/E1
data
streams
T3/E3
Framer &
M13/
E13/
G747
Mux
bipolar
I/F
DS3150
T3/E3
Line
Interface
DUAL UNCHANNELIZED T3/E3 APPLICATION Figure 6B
DS3112
TEMPE
44.2Mbps (T3) or
34Mbps (E3)
datastream
PCI
Bus
DS3134
CHATEAU
256
Channel
HDLC
Controller
T3/E3
Framer &
M13/
E13/
G747
Mux
44.2Mbps (T3) or
34Mbps (E3)
datastream
DS3112
TEMPE
T3/E3
Framer &
M13/
E13/
G747
Mux
22 of 22
bipolar
I/F
bipolar
I/F
DS3150
T3/E3
Line
Interface
DS3150
T3/E3
Line
Interface
T3/E3
Line
T3/E3
Line
T3/E3
Line
