DS3170DK

DS3170DK DS3/E3 Single-Chip Transceiver Design Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3170DK is a fully integrated design kit for the DS3170 DS3/E3 single-chip transceiver (SCT). This design kit contains all the necessary circuitry to evaluate the DS3170 in all modes of operation. The design kit also includes an on-board microprocessor to run real-time code for further part evaluation. Expedites New Designs by Eliminating First-Pass Prototyping Demonstrates Key Functions of the DS3170 DS3/E3 Single-Chip Transceiver (SCT) Includes DS3170 Single-Chip Transceiver (SCT), Transformers, 75Ω BNC, and Termination Passives DESIGN KIT CONTENTS DS3170DK Board Download: ChipView Software DS3170DK.DEF Definition File DS3170DK Data Sheet Interfaces with Any PC with an RS-232 Serial Interface High Level Windows®-Based Software Provides Visual Access to All Registers Software Controlled (Register) Mapped Configuration Switches Facilitate Real-Time Clock and Signal Routing ORDERING INFORMATION PART DS3170DK DESCRIPTION Design Kit for the DS3170 DS3/E3 Single-Chip Transceiver Precision Test Points for All Clocks and Signals On-Board DS3 and E3 Crystal Oscillators for Stable Clock Generation Windows is a registered trademark of Microsoft Corp. Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDS 1 of 40 REV: 091205 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit COMPONENT LIST DESIGNATION C1, C4, C5, C10, C14, C15, C18, C19, C21, C24, C25–C32, C36C38, C39–C44, C47–C49, C50, C52–C56, C59–C61, C66, C68, C70, C73, C74 C2, C3, C16, C17, C20, C22, C23, C33, C34, C51, C57, C69, C75 QTY DESCRIPTION SUPPLIER PART NUMBER 44 0.1µF 20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT 13 1µF 10%, 16V ceramic capacitors (1206) Panasonic ECJ-3YB1C105K Panasonic ECJ-1VB1H102K Panasonic ECS-T1CD686R Phycomp 1206CG100J9B200 Panasonic ECJ-1VB1C103K AVX 06035C103KAT Panasonic ECJ-1VB1C563K General Semiconductor 1N4001 C6, C62, C65 3 C7, C8, C9, C11, C35, C58, C76 7 C12, C13 2 C45, C46 2 C63, C64, C67 3 C71, C72 2 D1, D2 2 0.001µF 10%, 50V ceramic capacitors (0603) 68µF 20%, 16V tantalum capacitors (D case) 10pF 5%, 50V ceramic capacitors (tall case) 10,000pF 10%, 16V ceramic capacitors (0603) 0.01µF 10%, 50V X7R ceramic capacitors (0603) 56,000pF 10%, 16V ceramic capacitors (0603) 1A 50V general-purpose silicon diodes DS1, DS2, DS6–DS10 DS3, DS4, DS5, DS11–DS19 J1, PWR_CONNBAN1 7 LED, green, SMD Panasonic LN1351C 12 LED, red, SMD Panasonic LN1251C 2 Banana plug sockets (horizontal, black) Mouser Electronics 164-6218 J2 1 DB9 right-angle connector (long case) AMP 747459-1 J3 1 50-pin, dual-row, vertical terminal strip Samtec TSW-125-07-T-D J4 1 Samtec NA J5 1 Trompeter CBJR220 J6, J7 2 Samtec NA J8, J9 2 Trompeter UCBJR220 Samtec TSW-102-07-T-S 1 100-mils 4-position jumper 50Ω BNC connector (5-pin right-angle header) Terminal strip, 10-pin, dual row, vertical 75Ω BNC connectors (5-pin rightangle) 2-pin headers, 0.100” centerline (vertical) 14-pin connector (dual row, vertical) Samtec NA 1 100-mils 3-position jumper Samtec NA L1 1 1.0µH 20% 2-pin surface-mount inductor Coiltronics UP1B-1R0 PWR_CONNBAN2 1 Banana plug socket (horizontal, red) Mouser Electronics 164-6219 JP1, JP2, JP3, JP5, JP7, JP8 JP4 JP6 6 2 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit DESIGNATION R1–R4, R12, R42, R43, R54–R56, R59, R63, R68, R69, R70, R73, R74, R83, R93, R107 R5–R8, R10, R15, R51, R57, R62, R71, R81, R85, R92, R94, R95, R100, R101, R103–R106, R109 R9, R11, R16, R22, R30, R32, R38, R46, R60, R61, R64, R65, R72, R77–R80, R89, R90, R91, R96 R13 R14, R17–R21, R23–R29, R31, R33–R37, R39, R40, R41, R44, R45, R47, R48, R49, R52, R53, R58, R67, R75, R76, R82, R86, R87, R98, R99, R102, R108, R110 R50 QTY DESCRIPTION SUPPLIER PART NUMBER 20 150Ω 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF1500V 22 33Ω 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ330V 22 330Ω 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V 1 1.0MΩ 5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ105V 41 10kΩ 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V 1 1.0kΩ 5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ102V R66, R88, R97 3 0Ω 1%, 1/16W resistors (0603) AVX CJ10-000F R84 1 51.1Ω 1%, 1/16W resistor (0603) Panasonic ERJ-3EKF51R1V SW1, SW2, SW5 3 Panasonic EVQPAE04M SW3, SW4 2 AMP 435668-7 SW6 1 Tyco SSA22 T1, T2 2 Pulse T3012 TP1–TP24 24 NA KIT1 U1, U5 2 4-pin single-pole switch MOM 8-position switch, 16-pin DIP, low profile Slide switch (DPDT) 6-pin through-hole 1:2 XFMR T3/E3/STS-1 (industrial) Test points, compensated, 3pF, 953Ω, 3 plated holes 8-pin power-µMAX (1.8V or Adj) Maxim MAX1792EUA18 U2 1 Motorola MMC2107 U3, U6 2 Xilinx XC2S200E-6FT256C U4, U11 2 1 Cypress Dallas Semiconductor CY62128V U7 U8 1 M-CORE 32-bit microcontroller Spartan-IIE 200K gate, 1.8V FPGA, 256 PIN BGA 128K x 8 SRAM DS3/E3 SCT 100-pin CSBGA (11mm x 11mm) 3.3V RS-232 20-pin SO Maxim MAX3233EEWP U9, U14, U16– U20, U23 8 High-speed buffer Fairchild NC7SZ86 3 of 40 DS3170 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit DESIGNATION QTY U10, U12 2 U13 1 U15, U21, U24 DESCRIPTION 3 2Mb flash-based configuration memory Quad 2-input NAND gate 14-pin SO Hex inverter, SO U22 1 X1 1 Y1 1 Y2 1 Y3 1 SUPPLIER PART NUMBER Xilinx XCF02SV020C Toshiba TC74HC00AFN Toshiba TC74HC04AFN SOT switch debouncer Maxim MAX6816 8.0MHz low-profile crystal 3.3V 51.840MHz oscillator, crystal clock 3.3V 34.368MHz oscillator, crystal clock 3.3V 44.736MHz oscillator, crystal clock Dove Electronic EC1-8.000M SaRonix NTH089AA3-51.840 SaRonix NTH089AA3-34.368 SaRonix NTH089AA3-44.736 BOARD FLOORPLAN JTAG CONTROL OSC STS1 OSC E3 OSC T3 ON-BOARD µC SERIAL CON TEST POINTS FPGA GENERALPURPOSE ADDRESS/CS DECODE TEST POINTS FPGA Tx/Rx CLOCK, DATA SWITCH/MUX DS3170 VDD DS3170 VCC BOARD GND BOARD TEST POINTS TEST POINTS SRAM SRAM RST DS3170 RST BOARD ADDRESS/DATA/CS/RD/WR CON 4 of 40 GPIO IO/LEDS XFMR Rx Rx BNC XFMR Tx Tx BNC DS3170DK DS3/E3 Single-Chip Transceiver Design Kit BASIC OPERATION This design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/telecom. See the DS3170DK QuickView page for files. The support files are used with an evaluation program called ChipView with is available for download at www.maxim-ic.com/telecom. HARDWARE CONFIGURATION Quick Start (Hardware Settings) • • • • • • For single power-supply operation, short jumpers JP1-JP3. This connects VDD of the DS3170 to the board VCC. Ensure that PROGRAM FLASH MICRO is selected (SW6). DS3 should not be on. Connect reference clock. See Table 1. DIP switches (SW3) can be in either the ON or OFF position depending on the desired configuration. See Table 6.. Connect serial cable from DS3170DK (J2) to PC. Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. Reference Clock Configuration The reference clock for the DS3170 (SCT) can be configured a number of ways depending on the application's need. This is done by shorting the REFCLK signal on J6 to the signal inputs, which are also connected to J6. Table 1: Reference Clock Configuration REFERENCE CLOCK GND BNC Input STS1 OSC E3 OSC T3 OSC DESCRIPTION Short pins J6.1 and J6.2 together. Open all other pins on J6. Short pins J6.3 and J6.4 together. Open all other pins on J6. Short pins J6.5 and J6.6 together. Open all other pins on J6. Short pins J6.7 and J6.8 together. Open all other pins on J6. Short pins J6.9 and J6.10 together. Open all other pins on J6. JTAG Configuration The JTAG chain is controlled by the following connectors: J4, JP4, and JP5. Depending on the function, such as programming the internal microcontroller flash or performing boundary scan operations, the three connectors can be configured to accomplish the desired task. For information on programming the internal flash of the microcontroller, refer to the microcontroller user manual and board schematic. For most purposes, having the complete JTAG chain is sufficient. Figure 1 shows the complete chain as well as what order the devices will appear during boundary scan. To set up this configuration, perform the following: • • • • • • • Connect JTDI to JP4.1 Connect JTDO to JP4.3 Connect JTMS to JP4.10 Connect JCLK to JP4.5 Connect J4.1 to J4.2 Connect J4.3 to J4.4 Connect JP5.1 to JP5.2 5 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit Figure 1. JTAG Chain JTMS JTCLK JTDI (U2) (U10) (U3) (U22) (U6) ON-BOARD µC FLASH MEM FOR GEN FPGA GEN FLASH MEM FOR PORT FPGA PORT FPGA (U7) DS3170 FPGA JTDO Address/Data BUS Connector The DS3170DK has a connector (J3) to monitor all local bus activity for the design kit. All the signals can be captured with a high-impedance probe and displayed on an oscilloscope or logic analyzer. Note: If FPGA_ENABLE (SW3.3) is logic 0, the on-board microcontroller will no longer drive any data onto the local bus. Therefore, the user can now connect the local bus of the DS3170 into another system without making any modifications to the hardware. See Table 2 for specific pin information for connector J3. Table 2. Address/Data Connector PIN NUM 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 PIN NAME A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CS3170 CSFPGA INT3170 RST3170 RDY TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 GND GND PIN NUM 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 DESCRIPTION Local Address Bit 0 Local Address Bit 1 Local Address Bit 2 Local Address Bit 3 Local Address Bit 4 Local Address Bit 5 Local Address Bit 6 Local Address Bit 7 Local Address Bit 8 Local Address Bit 9 Chip Select DS3170 Chip Select Port FPGA INT PIN DS3170 RST PIN DS3170 Ready Handshake DS3170 Generic I/O Bit 0 Generic I/O Bit 1 Generic I/O Bit 2 Generic I/O Bit 3 Generic I/O Bit 4 Generic I/O Bit 5 Generic I/O Bit 6 Generic I/O Bit 7 GND GND 6 of 40 PIN NAME D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SPI ALE RD_DS WR_W/R CS_OUT MODE WIDTH TEST HIZ DESCRIPTION Local Data Bit 0 Local Data Bit 1 Local Data Bit 2 Local Data Bit 3 Local Data Bit 4 Local Data Bit 5 Local Data Bit 6 Local Data Bit 7 Local Data Bit 8 Local Data Bit 9 Local Data Bit 10 Local Data Bit 11 Local Data Bit 12 Local Data Bit 13 Local Data Bit 14 Local Data Bit 15 DS3170 Serial/Parallel Bus Mode Address Latch Enable Read (Intel)/Data Strobe (MOT) Write (Intel)/Write_READ (MOT) Programmable CS_OUT Pin Mot/Intel Mode Data Bus Width Test Enable (Active Low) High Impedance (Active Low) DS3170DK DS3/E3 Single-Chip Transceiver Design Kit High Impedance and Compensated Test Points The test points for all the clock and data lines are unique for this board such that each test point listed in Table 3 have a relative high-impedance pin and a compensated pin. The compensated pin is part of a (20:1) voltage divider that when used with the standard 50Ω load of an oscilloscope provides a very clean signal. If you are making critical timing and or slew rate measurements, the compensated test points are very useful. Figure 2 shows the relationship between the high-impedance and compensated test point pins. Figure 2. Test Point Logical and Physical View SIGNAL_X 1 1 = HIGH-IMPEDANCE PIN 2 = COMPENSATED PIN 3 = GND 1 R = 950Ω 2 C = 3pF 2 3 3 LOGICAL VIEW PHYSICAL VIEW Table 3. Test Points REF DES TP5 TP6 TP4 TP20 TP19 TP10 TP12 TP16 TP17 TP19 TP22 SIGNAL NAME TCLKI TCLKO RCLKO TLCLK RLCLK TOHSOF ROHSOF TOHCLK ROHCLK TSOFO RSOFO REF DES TP7 TP8 TP2 TP3 TP11 TP9 TP13 TP14 TP15 TP23 TP21 SIGNAL NAME TNEG RNEG TPOS RPOS TSER RSER TOHEN TOH ROH REFCLK TSOFI 7 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit General Purpose Input/Output for DS3170 The DS3170 SCT has an 8-bit port that can be bit configured as either general-purpose I/O or specific alarms, a TEMI input, or PMU input. Refer to the DS3170 data sheet for specific questions about the operation of the DS3170 GPIO port. Each GPIO pin has two types of inputs and an LED for easy identification of the pin’s state. The first input type for the GPIO port is an 8-bit switch (SW4). Each pin on SW4 corresponds to the bit in the GPIO. When the switch is in the “On” position, the pin for the switch is grounded and provides logic 0 to the port. When the switch is in the “Off” position, the pin for the switch floats to VDD and provides logic 1 to the port. The second input type for the GPIO port is a straight 10-pin header (J7). This can be simply a monitoring pin for the GPIO port or used as input stimulus. Note: If you plan to drive a bit to a value other than GND, the GPIO bit in SW4 must be in the “Off” position. See the DS3170DK schematic for questions on the connection of the GPIO port. Table 4 provides a description of pin out of SW4 and J7. Table 4. GPIO Header and Switch Pinout PIN NUMBER SW4.1 J7.1 SW4.2 J7.2 SW4.3 J7.3 SW4.4 J7.4 SW4.5 J7.5 SW4.6 J7.6 SW4.7 J7.7 SW4.8 J7.8 PIN NAME GPIO Bit 1 GPIO Bit 2 GPIO Bit 3 GPIO Bit 4 GPIO Bit 5 GPIO Bit 6 GPIO Bit 7 GPIO Bit 8 TEMI and PMU Inputs GPIO Bit 6 and GPIO Bit 8 can be configured to be the TEMI and PMU inputs respectively. A pushbutton (SW5) and 3-position jumper (JP6) are available to provide a glitch-free input to either of these inputs. Note: When using the pushbutton (SW5) and 3-position jumper (JP6) as an input to the GPIO pins, you must have the appropriate switch in SW4 in the “Off” position. Table 5. TEMI and PMU Configuration SIGNAL NAME TEMI PMU SETUP PROCEDURE Set SW4.6 to the “Off” position Short (Jumper) JP6.3 and JP2 Set SW4.8 to the “Off” position Short (Jumper) JP6.1 and JP2 8 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit User Input Switch (SW3) SW3 is an 8-pin DIP switch that controls the function of the on-board microcontroller and the two on-board FPGAs, and offers a number of generic inputs for user programs. Table 6. User Input Switch Pinout PIN NAME FUNCTION 1 FPGA INPUT 1 Generic Input-Only Pin to the General-Purpose FPGA. Value of pin is copied to generalpurpose register XXXXXXXX. Can be used for user programs. This pin has no effect if FPGA ENABLE is logic 0. 2 FPGA INPUT 2 Generic Input-Only Pin to the General-Purpose FPGA. Value of pin is copied to generalpurpose register XXXXXXXX. Can be used for user programs. This pin has no effect if FPGA ENABLE is logic 0. 3 FPGA ENABLE Input-Only Pin to the General-Purpose FPGA (U3). When this pin is logic 1 (SW3.3 is OFF), the FPGA is enabled and will transfer data from the DS3170 and FPGA as directed from the on-board microcontroller. When this pin is logic 0 (SW3.3 is ON), the FPGA is disabled. All inputs and outputs to the DS3170 and port FPGA are tri-stated. Note: This pin does not cause a hardware enable for the PORT FGPA. 4 DATA BUS SELECT Input-Only Pin to the General-Purpose FPGA (U3). When this pin is logic 1 (SW3.4 is OFF), the DS3170 and the port FPGA are set up such that they use the 16-bit bus from the on-board microcontroller. When this pin is logic 0 (SW3.4 is ON), the DS3170 and the port FPGA are set up such that they use the 8-bit bus from the on-board microcontroller. This pin has no effect if FPGA ENABLE is logic 0. 5 BOOT SEL Input-Only Pin to the On-Board Microcontroller. When this pin is logic 1 (SW3.5 is OFF), the on-board microcontroller loads the firmware from an external source rather than the internal flash bank. When this pin is logic 0 (SW3.5 is ON), the microcontroller loads the firmware from the internal flash bank. If you choose to load code from an external source, refer to the user manual for the on-board microcontroller (U2) to ensure that all the timing and data are correct to run this program. This option should only be used by the advanced user. 6 KIT Input-Only Pin to the On-Board Microcontroller. Not implemented with the firmware shipped from Dallas Semiconductor. This pin can be used by a user program. 7 USER INPUT 1 Input/Output Pin to the General-Purpose FPGA (U3). This pin has an LED (DS4) to track the value of this signal. This pin has no effect if FPGA ENABLE is logic 0. Note: If you choose to use this as an output, USER INPUT 1 (SW3.7) must be in the off position. 8 USER INPUT 2 Input/Output Pin to the General-Purpose FPGA (U3). This pin has an LED (DS5) to track the value of this signal. This pin has no effect if FPGA ENABLE is logic 0. Note: If you choose to use this as an output, USER INPUT 1 (SW3.8) must be in the off position. 9 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit SOFTWARE CONFIGURATION Quick Start (Software—ChipView) • • • • • • • • Perform steps in the Quick Start (Hardware Settings). Load ChipView software. Select COM port. Select Register View. From the Programs menu, launch the host application named ChipView.EXE. If the default installation options were used, click the Start button on the Windows toolbar and select Programs → ChipView → ChipView. Load the DS3170DK.DEF file. Make sure that all the register settings are correct for the proper function desired for the DS3170DK. Refer to the DS3170 data sheet for all questions pertaining to device functionality. MEMORY MAP The on-board microcontroller is configured to start the user address space at 0x81000000. All offsets given in Table 7 are relative to the beginning of the user address space. All device registers can be easily modified using ChipView.EXE host-based user-interface software. Table 7. Relative Address Map REF DES U3 U6 U7 DEVICE General-purpose FPGA FPGA Tx/Rx clock, data switch/mux DS3170 DS3/E3 singlechip transceiver OFFSET 0x0000 0x1000 0x2000 Table 8. General-Purpose Memory Map OFFSET 0x00 0x02 0x03 0x04 0x05 0x06 0x07 0x08 REGISTER NAME BRDID DSIDH DSIDM DSIDL BRDREV ASMREV FPGAREV CTRL1 TYPE Read Only Read Only Read Only Read Only Read Only Read Only Read Only Control DESCRIPTION Board ID Dallas Extended ID Upper Nibble Dallas Extended ID Middle Nibble Dallas Extended ID Lower Nibble Board Rev Assembly Rev FPGA Firmware Rev Control Reg #1 ID REGISTERS BID: BOARD ID (Offset=0X0000) BID is read only with a value of 0xD. XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset=0X0002) XBIDH is read only with a value of 0x00. XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset=0X0003) XBIDM is read only with a value of 0x07. XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset=0X0004) XBIDL is read only with a value of 0x00. BREV: BOARD FAB REVISION (Offset=0X0005) BREV is read only and displays the current fab revision. AREV: BOARD ASSEMBLY REVISION (Offset=0X0006) AREV is read only and displays the current assembly revision. PREV: PLD REVISION (Offset=0X0007) PREV is read only and displays the current PLD firmware revision. 10 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit CONTROL REGISTERS Register Name: CTRL1 Register Description: Control Register 1 Register Offset: 0x0008 Bit # Name Default 7 SPI_CPOL 0 6 SPI_CPHA 0 5 SPI_SWAP 0 4 SPI 0 3 HIZ 1 2 WIDTH 0 1 MOT 0 0 MUX 0 Bit 7: SPI_CPOL: This bit controls the SPI Interface Clock Polarity pin, which is muxed with the D7 pin on the DS3170. Bit 7 is only active when bit 4 (SPI) is a logic 1. Refer to the DS3170 data sheet for pin operation. Bit 6: SPI_CPHA: This bit controls the SPI Interface Clock Phase pin, which is muxed with the D6 pin on the DS3170. Bit 6 is only active when Bit 4 (SPI) is a logic 1. Refer to the DS3170 data sheet for pin operation. Bit 5: SPI_SWAP: This bit controls the SPI Interface Bit Order Swap pin, which is muxed with the D5 pin on the DS3170. Bit 5 is only active when Bit 4 (SPI) is a logic 1. Refer to the DS3170 data sheet for pin operation. Bit 4: SPI: This bit controls the SPI Bus Mode bit. 0 = parallel bus mode 1 = SPI bus mode Bit 3: HIZ: This bit controls the high-impedance test-enable bit (active low). This signal puts all the digial outputs and bidirectional outputs to a high-impedance state when pulled low and also when the JTRST is pulled low. For nomal operation, keep it as a logic 1. Bit 2: WIDTH: This bit controls the databus width pin for parallel bus mode. 0 = 8-bit parallel mode 1 = 16-bit parallel mode Bit 1: MOT: This bit controls the MODE pin for the DS3170. 0 = RD/WR strobe mode (Intel) 1 = DS strobe mode (Motorola) Bit 0: MUX: This bit determines if the ALE pin on the DS3170 is in mux mode or nonmux mode (constantly high). 0 = nonmux mode 1 = mux mode 11 of 40 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit Register Name: CTRL2 Register Description: Control Register 2–Line IO Register Offset: 0x0009 Bit # Name Default 7 RNEG3 0 6 RNEG2 0 5 RNEG1 0 4 RNEG0 0 3 RPOS3 1 Bits 7 to 4: RNEGx: These bits control the source of the RNEG signal. Bits 3 to 0: RPOSx: These bits control the source of the RPOS signal. RPOSx 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08–0xFF DESCRIPTION HI-Z TPOS T3 OSC E3 OSC STS1 OSC BNC_INPUT Logic 0 Logic 1 HI-Z RNEGx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z TNEG T3 OSC E3 OSC STS1 OSC BNC_INPUT Logic 0 Logic 1 HI-Z 12 of 40 2 RPOS2 0 1 RPOS1 0 0 RPOS0 0 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit Register Name: CTRL3 Register Description: Control Register 3–Line RCLK Register Offset: 0x000A Bit # Name Default 7 — 0 6 — 0 5 — 0 4 — 0 3 RLCLK3 0 Bits 7 to 4: These bits are unused. Bits 3 to 0: RLCLKx: These bits control the source of the RLCLK signal. RLCLKx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z TLCLK T3 OSC E3 OSC STS1 OSC BNC_INPUT Logic 0 Logic 1 HI-Z 13 of 40 2 RLCLK2 0 1 RLCLK1 0 0 RLCLK0 0 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit Register Name: CTRL4 Register Description: Control Register 4 Overhead Interface Register Offset: 0x000B Bit # Name Default 7 TOHEN3 0 6 TOHEN2 0 5 TOHEN1 0 4 TOHEN0 0 3 TOH3 0 Bits 7 to 4: TOHENx: These bits control the source of the TOHEN signal. Bits 3 to 0: TOHx: These bits control the source of the TOH signal. TOHENx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z TOHSOF ROHSOF Not used Not used Not used Logic 0 Logic 1 HI-Z TOHx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z ROH Not used Not used Not used Not used Logic 0 Logic 1 HI-Z 14 of 40 2 TOH2 0 1 TOH1 0 0 TOH0 0 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit Register Name: CTRL5 Register Description: Control Register 5 Serial Data Overhead Interface Register Offset: 0x000C Bit # Name Default 7 — 0 6 — 0 5 — 0 4 — 0 3 TSER3 0 Bits 7 to 4: These bits are unused. Bits 3 to 0: TSERx: These bits control the source of the TSER signal. TSERx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z RSER Not Used Not Used Not Used Not Used Logic 0 Logic 1 HI-Z 15 of 40 2 TSER2 0 1 TSER1 0 0 TSER0 0 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit Register Name: CTRL6 Register Description: Control Register 6 Serial Data Overhead Interface Register Offset: 0x000D Bit # Name Default 7 TSOFI3 0 6 TSOFI2 0 5 TSOFI1 0 4 TSOFI0 0 3 TCLKI3 0 Bits 7 to 4: TSOFIx: These bits control the source of the TSOFI signal. Bits 3 to 0: TCLKIx: These bits control the source of the TCLKI signal. TSOFIx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z TSOFO RSOFO Not Used Not Used Not Used Logic 0 Logic 1 HI-Z TCLKIx 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08–0XFF DESCRIPTION HI-Z TCLKO RCLKO Not Used Not Used Not Used Logic 0 Logic 1 HI-Z 16 of 40 2 TCLKI2 0 1 TCLKI1 0 0 TCLKI0 0 DS3170DK DS3/E3 Single-Chip Transceiver Design Kit DS3170 INFORMATION For more information about the DS3170, refer to the DS3170 data sheet available on our website at www.maximic.com/DS3170. Software downloads are also available for this design kit. DS3170DK INFORMATION For more information about the DS3170DK including software downloads, consult the DS3170DK data sheet available on our website at www.maxim-ic.com/DS3170DK. TECHNICAL SUPPORT For additional technical support, e-mail your questions to telecom.support@dalsemi.com. SCHEMATICS The DS3170DK schematics are featured in the following 23 pages. 17 of 40 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.