DS33R11DK

DS33R11DK/DS33ZH11DK Ethernet Transport Design Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES Demonstrates Key Functions of DS33R11 and DS33ZH11 Ethernet Transport Chipsets DS33ZH11 Section Includes DS21348 T1E1 LIU and DS3150 T3E3 LIU, Transformers, BNC and RJ48 Network Connectors and Termination Provides Support for Hardware and Software Modes On-Board MMC2107 Processor and ChipView Software Provide Point-and-Click Access to DS33R11 Register Set All DS33R11 and DS33ZH11 Interface Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-of-Signal, Queue Overflow, Ethernet Link, Tx/Rx, and Interrupt Status Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs The DS33R11/DS33ZH11 design kit is an easy-touse evaluation board for the DS33R11 and the DS33ZH11 Ethernet transport-over-serial link devices. The DS33ZH11 section of the design kit contains an option for either T3E3 or T1E1 serial links. The DS33R11 chipset has an integrated T1E1 transceiver. All serial links are complete with line interface, transformers, and network connections. Dallas’ ChipView software is provided with the design kit, giving point-and-click access to configuration and status registers from a Windows-based PC. On-board LEDs indicate receive loss-of-signal, queue overflow, Ethernet link, Tx/Rx, and interrupt status. Windows is a registered trademark of Microsoft Corp. DESIGN KIT CONTENTS DS33R11DK/DS33ZH11DK Main Board (DS33R11 + DS33ZH11) CD ROM: ChipView Software and Manual DS33R11DK/DS33ZH11DK Data Sheet Configuration Files ORDERING INFORMATION PART DS33R11DK 1 of 44 DESCRIPTION Design Kit for DS33R11 and DS33ZH11 REV: 101405 DS33R11DK/DS33ZH11DK TABLE OF CONTENTS GENERAL DESCRIPTION ..........................................................................................................1 DESIGN KIT CONTENTS............................................................................................................1 ORDERING INFORMATION .......................................................................................................1 COMPONENT LIST .....................................................................................................................3 SYSTEM FLOORPLAN ...............................................................................................................8 PC BOARD ERRATA ..................................................................................................................8 FILE LOCATIONS .......................................................................................................................9 BASIC OPERATION..................................................................................................................10 POWERING UP THE DESIGN KIT ............................................................................................................... 10 General ............................................................................................................................................................... 10 BASIC DS33R11 INITIALIZATION .............................................................................................................. 10 Additional Configuration for DS33R11 ............................................................................................................... 10 BASIC DS33ZH11 INITIALIZATION ............................................................................................................ 11 Additional Configuration for DS33ZH11 ............................................................................................................. 11 MONITOR AND CAPTURE ETHERNET TRAFFIC ............................................................................... 11 LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS ..............................12 ADDRESS MAP (ALL CARDS) ................................................................................................16 DS33R11 INFORMATION .........................................................................................................16 DS33R11DK/DS33ZH11DK INFORMATION ............................................................................17 TECHNICAL SUPPORT ............................................................................................................17 SCHEMATICS ...........................................................................................................................17 2 of 44 DS33R11DK/DS33ZH11DK COMPONENT LIST DESIGNATION C01, C28, CB03, CB49, CB136, CB146, CB192, CP01, CP2, CP03 C02, C11, C30, CB36, CB37, CB40–CB43, CB45, CB153, CB195, CB197 C03–C06, C13, C14, C17, C20, C22, C26, C29, . . .incomplete listing (94 devices total) C07, C08, C09, C12, C16, C18, C19, C21, C23, C24, C31, . . . incomplete listing (81 devices total) C10, CB23, CB24, CB26, CB33, CB91, CB95, CB151, CB161, CB162, CB175, CB177, CB181, CB185, CB189, CB190 C15, CB76, CB77, CB169, CB179, CB188 C25, C27, CB154– CB156, CB158–CB160, CB166, CB173, CB174, CB182, CB183 QTY DESCRIPTION SUPPLIER/PART NUMBER 10 470µF ±20%, 6.3V tantalum capacitors (D case) KEM T491D477M006AS 13 1µF ±10%, 16V ceramic capacitors (1206) Panasonic ECJ-3YB1C105K 94 0.1µF ±10%, 16V ceramic capacitors (0603) Phycomp 06032R104K7B20D 81 10µF ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M 16 0.1µF ±20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT 6 10µF ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M 13 4.7µF, 6.3V ceramic multilayer capacitors (0603) UNK ECJ-1VB0J475M CB105 1 0.1µF ±10%, 16V ceramic capacitor (0805) CB180 1 1µF ±10%, 16V ceramic capacitor (1206) Phycomp 08052R104K7B20D Panasonic ECJ-3YB1C105K DB01 1 1A, 40V Schottky diode 5 Red LEDs (SMD) 4 Red LEDs (SMD) 4 Green LEDs (SMD) Panasonic LN1351C 8 Amber LEDs (SMD) Panasonic LN1451C 27 Standard ground clip Keystone 4954 9 Kit, 4-40 hardware, 0.5" nylon standoff and nylon hex-nut Lab stock 4-40KIT6 DS01, DS02, DS05, DS13, DS14 DS03, DS08, DS15, DS19 DS04, DS07, DS12, DS21 DS06, DS09, DS10, DS11, DS16, D17, DS18, DS20 GND_TP01, GND_TP02, GND_TP03, GND_TPB01, GND_TPP01– GND_TPP23 H01–H06, HB01, HB02, HB03 3 of 44 International Rectifier 10BQ040 Panasonic LN1251C Panasonic LN1251C DS33R11DK/DS33ZH11DK DESIGNATION QTY DESCRIPTION J01, J05, J06, J18, J36 5 Terminal strip (10-pin, dual row, vertical) Samtec TSW-105-07-T-D J02 1 DB9 right-angle connector (long case) AMP 747459-1 J03, J10, J11, J14–J17, J25, J26, J27, J32, J34, J35 13 100-mil, 2-position jumpers Lab stock Not applicable J04 1 100-mil, 2 x 7-position jumper Lab stock Not applicable J07, J08, J09 3 Not Populated 14-pin headers, dual row, vertical Samtec NOPOP-HDR-TSW-107-14-T-D J12, J13, J22, J23, J30, J33 6 J19, J24 2 J20, JB03 2 8-pin single-port RJ48 connectors J21, J37 2 8-pin connectors (fastjack single, for national PHY) J28, J29, J31 3 20-pin headers (dual row, vertical) J38, J39 2 5-pin BNC connectors (75Ω, right angle) J40, J41 2 5-pin BNC connectors (right angle) JB01, JB05 2 Sockets, banana plug, horizontal, black JB02, JB04 2 Sockets, banana plug, horizontal, red JP01–JP11, JPB01 12 100-mil, 3-position jumpers R1, R2 2 1.0kΩ ±5%, 1/16W resistors (0603) R01 1 1.0MΩ ±5%, 1/16W resistor (0603) R02 1 10kΩ ±1%, 1/10W resistor (0805) R03, R04, R05, R09, R14, R15, R21, RB35, RB52, RB53, RB58, RB69, RB70, RB73, RB77–RB86, RB89, RB90, RB93–RB96, RB101, RB132, RB133, RB137, RB138, RB144, RB151–RB155, RB159, RB162 43 30Ω, 1/16W resistors (0603) Panasonic ERJ-3GEYJ300V R06, R08, R23, R24 4 49.9Ω ±1%, 1/16W resistors (0603) Panasonic ERJ-3EKF49R9V L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO NOT POPLUATE Not Populated 5-pin connectors, BNC 75Ω, right angle 4 of 44 SUPPLIER/PART NUMBER DNP Trompetor NOPOP-UCBJR220 MOLEX 15-43-8588 Halo Electronics HFJ11-2450E Samtec HDR-TSW-110-14-T-D Trompetor UCBJR220 Trompetor UCBJR220 Mouser Electronics 164-6218 Mouser Electronics 164-6219 Lab stock Not applicable Panasonic ERJ-3GEYJ103V Panasonic ERJ-3GEYJ105V Panasonic ERJ-6ENF1002V DS33R11DK/DS33ZH11DK DESIGNATION QTY R07, R10, R12, R13, RB15 5 0Ω ±5%, 1/16W resistors (0603) R11, RB167 2 10.0kΩ ±1%, 1/16W resistors (0603 ) R16–R19 4 0Ω ±5%, 1/10W resistors (0805) R20, R22 2 330Ω ±5%, 1/8W resistors (1206) 19 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V 20 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V RB129 1 30Ω ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ300V RB14, RB19, RB44– RB47, RB49–RB51, RB54, RB97, RB98, RB102, RB104, RB116, RB178 16 2.0kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ202V RB148, RB149 2 61.9Ω ±1%, 1/10W resistors (0805) RB156 1 330Ω ±5%, 1/10W resistor (0805) RB16, RB20, RB48, RB66, RB67, RB68, RB71, RB74, RB75, RB135, RB142, RB146, RB157, RB161, RB165, RB169, RB174, RB176 18 330Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V RB177 1 51.1Ω ±1%, 1/10W resistor (0805) Panasonic ERJ-6ENF51R1V RB21, RB23 2 330Ω ±5%, 1/16W resistors (0603) RB24 1 1.0kΩ ±5%, 1/16W resistor (0603) RB26, RB103, RB105– RB115, RB117–RB128, RB130, RB131, RB134, RB136, RB139–RB141, RB143, RB163, RB166, RB170 36 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ102V RB29 1 0Ω ±5%, 1/8W resistor (1206) Panasonic ERJ-8GEYJ0R00V RB01–RB03, RB06– RB13, RB17, RB18, RB22, RB25, RB27, RB28, RB32, RB33 RB04, RB05, RB30, RB31, RB34, RB36– RB43, RB59–RB61, RB63, RB99, RB100, RB150 DESCRIPTION 5 of 44 SUPPLIER/PART NUMBER Panasonic ERJ-3GEY0R00V Panasonic ERJ-3EKF1002V Panasonic ERJ-6GEY0R00V Panasonic ERJ-8ENF3300V Panasonic ERJ-6ENF61R9V Panasonic ERJ-6GEYJ331V Panasonic ERJ-3GEYJ331V Panasonic ERJ-3GEYJ102V DS33R11DK/DS33ZH11DK DESIGNATION QTY DESCRIPTION RB55, RB56, RB57, RB62, RB64, RB65, RB72, RB76, RB145, RB147, RB158, RB160, RB164, RB168, RB173, RB175 16 5.1kΩ ±5%, 1/16W resistors (0603) RB87, RB91 2 60.4Ω ±1%, 1/10W resistors (0805) RB88, RB92, RB171, RB172 4 54.9Ω ±1%, 1/16W resistors (0603) SHORT01 1 2-position SMD jumper Do not populate. Intended to have solder bridge during assembly. Not populated SW01, SW02 2 4-pin single-pole switch Panasonic EVQPAE04M T01 1 16-pin dual SMT transformer T02, T03 2 6-pin SMT transformers (1:2CT, transmitter/receiver) Pulse Engineering TX1099 Pulse Engineering PE-65968 TB01 1 12-pin SMT transformer (1CT:1CT and 1CT:2CT) Pulse Engineering PE-68877 TP01–TP03, TPB01– TPB11, TPP01,TPP02 16 U01, U15 2 U02 1 U03 1 U04 1 U05, UB03 2 FPGA IC 1.2V, 20mm x 20mm, 144-pin TQFP Cypress SRAM, Lab Stock U06, U07 2 High-speed inverters U08, UB07 2 U09 1 U10, U14 2 Test points (one plated hole) Do not stuff. Microprocessor voltage monitors 2.93V reset, 4-pin SOT143 2Mb SPI serial EEPROM 8-pin SO, 2.7V to 3.6V MMC2107 Processor 1.8V or Adj 8-Pin µMAX/SO DS33R11, Z44/2156 MCM 27mm x 27mm, 256-pin BGA DsPHYTER II Single 10/100 Ethernet transceiver (65-pin LLP) 6 of 44 SUPPLIER/PART NUMBER Panasonic ERJ-3GEYJ512V Panasonic ERJ-6ENF60R4V Panasonic ERJ-3EKF54R9V — Maxim MAX811SEUS-T Atmel AT25F2048N-10SU-2.7 Motorola MMC2107 Lattice Semiconductor LFEC3E-3T144C Lab stock Fairchild Semiconductor NC7SZ86 Maxim MAX1792EUA18 Dallas Semiconductor DS33R11 National Semiconductor DP83847ALQA56A DS33R11DK/DS33ZH11DK DESIGNATION QTY DESCRIPTION U11 1 DS33ZH11 ELITE 10/100 Ethernet transport over serial link 10mm x 10mm, 100-pin CSBGA U12 1 DS21348 LIU 44-pin TQFP U13 1 UB01 1 UB02 1 UB04, UB05 2 UB06 1 High-speed buffer XB01 1 Low-profile 8.0MHz crystal Y01, YB05 2 Y02 1 Y03, YB03 2 Y04 1 Y05 1 YB01 1 YB02 1 YB04 1 DS3150 T3/E3/STS-1 LIU I/F 48-pin TQFP Dual RS-232 transceiver with 3.3V/5V internal capacitors LDO regulator with reset,1.20V output 300mA, 6-pin SOT23 Synchronous DRAM, 1Meg x 32 x 4 banks, 86-pin TSOP Oscillator, crystal clock 3.3V, 2.048MHz (needs socket) Not populated Oscillator, crystal clock 3.3V, 25.000MHz (low jitter) Oscillator, crystal clock 3.3V, 100.000MHz SPI serial EEPROM 2.7V, 16k, 8-pin DIP (needs socket) Oscillator, crystal clock, 3.3V, 34.368MHz (needs socket) Oscillator, crystal clock 3.3V, 44.736MHz (needs socket) Oscillator, crystal clock 3.3V, 1.544MHz (needs socket) Oscillator, crystal clock 3.3V, 25.000MHz (low jitter) 7 of 44 SUPPLIER/PART NUMBER Dallas Semiconductor DS33ZH11 Dallas Semiconductor DS21348 Dallas Semiconductor DS3150T Maxim MAX3233E Maxim MAX1963EZT120-T Micron MT48LC4M32B2TG-7 Fairchild Semiconductor NC7SZ86 ECL EC1-8.000M SaRonix NTH039A3-2.0480 SaRonix NTH089AA3-25.000 SaRonix NTH089A3-100.0000 Atmel AT25160A-10PI-2.7 SaRonix NTH089AA3-34.368 SaRonix NTH089AA3-44.736 SaRonix NTH039A3-1.5440 SaRonix NTH089AA3-25.000 DS33R11DK/DS33ZH11DK SYSTEM FLOORPLAN DS33R11/DS33ZH11 DESIGN KIT DS33R11 SECTION CONFIGURATION JUMPERS 10/100 ETHERNET PHY AND MAGNETICS DS33ZH11 SECTION DS3150 T3E3 LIU TRANSFORMER AND NETWORK CONNECTIONS (T3E3) LEDs DS33R11 SDRAM MICROPROCESSOR AND SERIAL PORT (57600-8-N-1) TEST POINTS TRANSFORMER AND NETWORK CONNECTIONS (T1E1) CONFIGURATION JUMPERS BACKPLANE JUMPERS—TO DS33ZH11 TSER RSER TCLK RCLK LEDs TEST POINTS TEST POINTS EEPROM (CONFIG) DS3150 T3E3 LIU TRANSFORMER AND NETWORK CONNECTIONS (T1E1) LEDs DS33ZH11 10/100 ETHERNET PHY AND MAGNETICS SDRAM PC BOARD ERRATA • • • • • Center tap of T02 was not pulled to V3_3 in DS33R11DK/DS33ZH11DK01A0 revision (page 23 in schematic). Pin T02.2 is pulled to V3_3 with a wire in the DS33R11DK/DS33ZH11DK01A0 revision. Reference designators were assigned for R1, R2 and R01, R02. R1 and R2 will be renamed in the next design. Component R1, R2 and Y05 are on bottom of the PC board but do not have the same prefix as other components on the bottom side. Silkscreen for J36.6 is mislabeled. It reads “RT0” but should read “RT1.” Oscillators Y03 and YB03 are not suitable for use as input clocks for the Ethernet PHY. Because of this, the oscillators will only be used as the SDRAM oscillators. These oscillators generate too much jitter to function as the input clock for the PHY. This requires that the PHY is driven by the default oscillator, YB04 and YB02. Jumpers JP03 and JP11 have been modified to prevent accidental selection of the wrong oscillator. 8 of 44 DS33R11DK/DS33ZH11DK FILE LOCATIONS This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file from the Maxim website at www.maxim-ic.com/DS33R11DK. All locations are given relative to the top directory of the CD/zip file. Table 1. DS33Z11 Register Definition and Configuration Files FILE NAME. FILE USAGE Top level definition file to select in ChipView’s register mode. This file autoloads the remaining definition files shown below. (Note: The DS33R11 is composed of an integrated DS33Z11 and an integrated DS2155.) Dependant files. These are called by the DS33Z11.def file, which is listed above. .\DS33R11_cfg_demo_gui\DS33Z11.def .\DS33R11_cfg_demo_gui\SU_LI_PORT1.def .\DS33R11_cfg_demo_gui\DS2155.def .\DS33R11_cfg_demo_gui\basic_Config.eset GUI interface for loading settings when running the Zchip plug-in (launched from the Tools menu of the ChipView program). .\DS33R11_cfg_demo_gui\basic_config.mfg .\DS33R11_cfg_demo_gui\e1_gapclk_crc4_hdb3_nocas.ini Files for manually configuring the DS33Z11 and DS2155 to convert Ethernet traffic to serial a T1E1 stream. .\DS33R11_cfg_demo_gui\DS2155_T1_BERT_ESF.ini .\DS33R11_cfg_demo_gui\gapclk_llb_DS2155_T1_ESF_LBO0_2.ini Stand-alone configuration files for evaluating the DS33R11’s integrated DS2155 T1E1 transceiver. These files are for evaluating DS2155 functionality, and disrupt the Ethernet to serial traffic flow. 9 of 44 DS33R11DK/DS33ZH11DK BASIC OPERATION Powering Up the Design Kit • • Connect PCB 3.3V and GND banana plugs to power supply. A 2A supply is recommended. At steady-state, the system should draw approximately 700mA. Verify that jumpers are configured as described in Table 2. General • • Upon power-up, the DS33R11 Queue overflow LED (DS02 red) will not be lit; also, the INT LED (DS01 red) will not be lit. PHY LINK LED (DS07 green) should be lit if the Ethernet is connected. Transceiver RLOS LED (DS05 red) will be lit. DS33ZH11 does not have Queue overflow or INT pins. DS21348 and DS3150 RLOS LEDs (DS15 and DS13 red) will be lit. Following are several basic system initializations. Basic DS33R11 Initialization This section covers two basic methods for configuring the DS33R11. 1. Device-Driver Based Configuration. If the pins J09.4+J09.6 are jumpered, the device driver autoconfigures the DS33R11 upon power-up. This enables traffic to pass from the Ethernet port to the serial port. Consult the device driver documentation for further details. 2. Register-Based Configuration. Launch ChipView.exe and select Register View. When prompted for a definition file, pick the file named DS33Z11.def. Three definition files will load: DS33Z11 control, DS33Z11 port, and DS2155 transceiver. Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted, select the file named basic_config.mfg. Following this, load the file e1_gapclk_crc4_hdb3_nocas.ini using the menu selection File→Initalization Config File→Load .INI file. Additional Configuration for DS33R11 • • • Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should cause the link LED to turn on. Place a loopback connector at the T1E1 network side; RLOS LED DS05 should go out. At this point any packets sent to the DS33R11 are echoed back. Incoming packets (i.e., ping) should cause the RX LED to blink, after which the TX LED should also blink. 10 of 44 DS33R11DK/DS33ZH11DK Basic DS33ZH11 Initialization This section covers the EEPROM methods for configuring the DS33ZH11. 1) If the HWMODE jumper is installed, the DS33ZH11 will retrieve configuration settings from the on-board EEPROM during power-up. 2) Select which serial device to use: either the DS3150 T3E3 LIU or the DS21348 T1E1 LIU can be selected. In making this selection the backplane jumpers JP05–JP08 must be installed to select between the two serial devices. Connecting pins 2+3 of each jumper selects the DS3150, connecting pins 1+2 of each jumper selects the DS21348. 3) Configure the serial device as shown in Table 2. Additional Configuration for DS33ZH11 • • • Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should cause the link LED to turn on. Place a loopback connector at the network side; the RLOS LED should go out. The RLOS LED is DS15 for T1E1 and DS13 for T3E3. At this point any packets sent to the DS33ZH11 are echoed back. Incoming packets (i.e., ping) should cause the RX LED to blink, after which the TX LED should also blink. Monitor and Capture Ethernet Traffic • • • • Although ping is mentioned, it is not recommended. The ping command goes through the computer’s TCPIP stack, and sometimes is not sent out the PC’s network connector (i.e., if the PC’s ARP cache is out of date). Additionally, ping requires two PCs, as a PC with only one adapter cannot ping itself (a local ping gets sent to a local host instead of out the connector). However, note that ping is still a valuable test once the prototyping stage is complete. Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-limited demo is available at the website www.tamos.com/products/commview. Ethereal is an excellent (and free) packet capture utility. Download at www.ethereal.com. Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This allows for end-to-end testing using a single PC. When using two adapters, the PC has a different IP address for each adapter. Test equipment allows selection of either adapter. Operating system-based network traffic is sent out the default adapter. Typically, this is the adapter that has recently had connection to a live network. 11 of 44 DS33R11DK/DS33ZH11DK LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS The DS33Z11DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a description of these signals, given in order of appearance on the PC board, from top to bottom then left to right (with the board held so that the RS232 connector is on the left edge). Table 2. Main Board PC Board Configuration FUNCTION BASIC SETTING SCHEMATIC PAGE Power supply ground — 2 VDD 3.3V (banana plug) Power supply VDD — 2 J01 JTAG — 17 — 14 SILKSCREEN REFERENCE GROUND (banana plug) SW01 RS-232 DB9 connector Reset DS01 LED DS02 LED J04 OnCe BDM — 14 J03 Flash VPP 3.3V 14 J05 JTAG — 10 J06 JTAG — 11 Y01 Clock — 11 J07, J08 Addr / Dat — 16 J09 Configuration pins (See next two rows for details.) Schematic Page16 J09.2+J09.4 Removed Not installed J09.4+J09.6 Driver Enable Installed J09.8+J09.10 RCLK select (FPGA) User selection Y02 Ethernet PHY Clock — JP03 Clock select Pins 1+2 Jumpered J10 Jumper Installed J11 Jumper Installed J02 12 — 15 7 12 of 44 DESCRIPTION System power. Always connected to power supply. Connectors are provided at the top left and bottom right of board. Connect either set to power supply. JTAG interface for Lattice EC3 FPGA. RS-232 DB9 connector, operates in ASCII mode at 57.6K baud, 8, N, 1. Drives reset controller U01. Displays interrupt status of DS33R11 (lit when interrupt is asserted). Displays Queue overflow status of DS33R11 (lit when Queue overflows). Debug connector for processor. Jumper for driving MMC2107 flash VPP to 5V . JTAG interface for DS2155 portion of DS33R11. JTAG interface for DS33Z11 portion of DS33R11. Oscillator for DS2155 portion of the DS33R11. Address and Databus Test points for DS33R11. Configuration switches for selecting device driver behavior. Additional detail given below. Pin J09.2 has been removed. Jumpering this pin to J09.4 causes a conflict with J09.6 FPGA pin. Enables device driver and interrupt handler when jumper is installed. Causes device to select serial link TCLK = RCLK when jumpered. When not jumpered TCLK = MCLK. 25.000MHz clock for DS33R11 3 Ethernet PHY. Must be set with pins 1+2 jumpered. SDRAM oscillator does 3 not meet jitter requirement of the Ethernet PHY. Connects DS33R11 receive serial 10 lines. Connects DS33R11 transmit serial 10 lines. DS33R11DK/DS33ZH11DK BASIC SETTING Pins 2+3 jumpered Pins 2+3 jumpered SCHEMATIC PAGE SILKSCREEN REFERENCE FUNCTION JP01 3-pin jumper JP02 3-pin jumper J18 Test points Pins 9+10 and 5+6 jumpered 10 J12, J13 Test points — 11 J14, J15, J16 Jumpers Not installed 4 DS06, DS07, DS08 LED — 4 DS10, DS11, DS09 LED — 4 J21 LAN network connection — 5 J22, J23 Test points — J19, J20 J24 WAN Network Connection — J17, J25 Jumper Not installed Y03 Clock — J28 Configuration pins (See next 10 rows for details.) Schematic Page 23 J28.20 DS3150 pin (ZCSE) Not installed J28.18 DS3150 pin (TTS) Installed J28.16 DS3150 pin (TESS) Installed J28.14 DS3150 pin (TDS1) Not installed J28.12 DS3150 pin (TDS0) Not installed J28.10 DS3150 pin (RMON) Not installed J28.8 DS3150 pin (LBKS) Installed J28.6 DS3150 pin (LBO) Installed 13 of 44 10 10 DESCRIPTION Drives DS33R11 TDEN pin to VCC. Drives DS33R11 RDEN pin to VCC. Test points, connecting RCLK and TCLK to channel clock pins of transceiver. Test points for integrated transceiver of DS33R11. Installation forces Ethernet PHY mode. When not installed the PHY autonegotiates its settings. Activity LEDs for Ethernet PHY. Tx lights when PHY sends a packet; Link lights when the PHY has found a link partner. Ethernet PHY mode LEDs. Used for display of Speed, Duplex, and Collision. RJ45 connector for Ethernet PHY. Test points for MII interface between PHY and DS33R11. T1E1 coax and RJ45 connectors 11 for network. Connects adjacent coax connector 11 to ground. 100MHz SDRAM clock for 10 DS33R11. Pin bias for DS3150. When not jumpered, this pin is pulled to ground, jumper drives pin to VCC. A basic description of the pin function is given below. Refer to the data sheet for full detail. 0 = B3ZS/HDB3 encoder/decoder enabled (NRZ interface enabled) 1 = B3ZS/HDB3 encoder/decoder disabled (bipolar interface enabled) 0 = tri-state the transmit output driver, disable the jitter attenuator in the transmit path 1 = enable the transmit output driver, disable the jitter attenuator in the transmit path 0 = E3 1 = T3 (DS3) 00=Transmit normal data clocked in on TPOS/TNRZ and TNEG 11=Transmit PRBS 0 = disable the monitor preamp, disable the jitter attenuator in the receive path 1 = enable the monitor preamp, disable the jitter attenuator in the receive path 0 = analog loopback enabled 1 = no loopback enabled 0 = cable length 225ft 1 = cable length < 225ft 4 DS33R11DK/DS33ZH11DK SILKSCREEN REFERENCE FUNCTION BASIC SETTING J28.4 DS3150 pin (ICE) — J28.2 DS3150 pin (EFE) Not installed JP09 Clock selection Pins 3+2 jumpered DS12, DS13, DS14 J38, J39 LED — BNC — JP05–JP08 Serial backplane User config J29 Configuration pins (See next 10 rows for details.) J29.1 J29.3 DS21348 pin (CS_EGL) DS21348 pin (RD_ETS) J29.5 DS21348 pin (WR_NRZ) J29.7 DS21348 pin (ALE/SCLKE) J29.9 DS21348 pin (VSM) J29.11 DS21348 pin (LO) J29.13 DS21348 pin (DJA) J29.15 DS21348 pin (JAMUX) J29.17 DS21348 pin (JAS) J29.19 DS21348 pin (HBE) Schematic Page 25 14 of 44 SCHEMATIC DESCRIPTION PAGE 0 = Normal RCLK/Normal TCLK: update RPOS/RNRZ and RNEG/RLCV on falling edge of RCLK; sample TPOS/TNRZ and TNEG on rising edge of TCLK 1 = Normal RCLK/Inverted TCLK: update RPOS/RNRZ and RNEG/RLCV on falling edge of RCLK; sample TPOS/TNRZ and TNEG on falling edge of TCLK 0 = enhanced features disabled 1 = enhanced features enabled Selects DS3150 MCLK. Jumper 23 pins 1+2 for MCLK = RCLK; jumper pins 3+2 for MCLK = OSC_YB01. DS3150 LEDs for PRBS, LOS and 23 DM. 23 DS3150 BNC network interface. Jumper pins 1+2 to select 18 DS21348 T1E1, jumper pins 2+3 to select DS3150. Pin bias for DS21348. When not jumpered, this pin is pulled to ground, jumper drives pin to VCC. A basic description of the pin function is given below. Refer to the data sheet for full details. 0 = -12dB (short haul) 1 = -43dB (long haul) 0 = E1 1 = T1 0 = Bipolar data at RPOS/RNEG and TPOS/TNEG 1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive-going pulse when device receives a BPV, CV, or EXZ 0 = disable 2.048MHz synchronization transmit and receive mode 1 = enable 2.048Hz synchronization transmit and receive mode Should be tied low for 3.3V operation. Transmit LIU waveshape select bits. (Refer to the DS21348 data sheet Table 7-1 and 7-2.) 0 = jitter attenuator enabled 1 = jitter attenuator disabled E1 (ETS = 0) JAMUX MCLK = 2.048MHz 0 T1 (ETS = 1) MCLK = 2.048MHz 1 MCLK = 1.544MHz 0 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side 0 = enable HDB3 (E1)/B8ZS (T1) 1 = disable HDB3 (E1)/B8ZS (T1) DS33R11DK/DS33ZH11DK SILKSCREEN REFERENCE FUNCTION J31 Configuration pins (See next 10 rows for details) J31.1 J31.3 J31.9 J31.11 DS21348 pin (MM1) DS21348 pin (MM0) DS21348 pin (LOOP1) DS21348 pin (LOOP0) DS21348 pin (TX1) DS21348 pin (TX0) J31.13 DS21348 pin (TPD) J31.15 DS21348 pin (CES) J31.5 J31.7 J31.17 J31.19 J36 SCHEMATIC DESCRIPTION PAGE Pin bias for DS21348. When not jumpered, this pin is pulled to ground, jumper drives pin to VCC. A basic description of the pin function is given below. Refer to the data sheet for full details. Monitor mode selection. See Table 2-11 in the DS21348 data sheet. Loop 1, Loop 0: 11 = RLB 10 = LLB 01 = ALB Schematic Page 25 Transmit data control (pattern vs. TPOS/TNEG) DS21348 pin (TEST) DS21348 pin (PBTS/RT0) DS21348 pin (L1) J36.4 DS21348 pin (L2) J36.6 DS21348 pin (RT1) 0 = normal transmitter operation 1 = powers down the transmitter and tri-states the TTIP and TRING pins 0 = update RNEG/RPOS on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK 1 = update RNEG/RPOS on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK Set high to tri-state all outputs and I/O pins. Selects receive termination in conjunction with RT1. Configuration pins (See next three rows for details.) J36.2 JP10 DS15 J40, J41 BASIC SETTING Schematic Page 25 Pin bias for DS21348. When not jumpered, this pin is pulled to ground, jumper drives pin to VCC. A basic description of the pin function is given below. Refer to the data sheet for full details. Transmit LIU waveshape select bits. (Refer to the DS21348 data sheet Table 7-1 and 7-2.) Transmit LIU waveshape select bits. (Refer to the DS21348 data sheet Table 7-1 and 7-2.) The silkscreen on this pin is mislabeled. Should read RT1 with a function of selecting receive termination. 25 — 25 — 24 — JPB01 Clock selection LED Network connection DS33ZH11 pin (MODEC1) DS33ZH11 pin (HWMODE) Jumper J30, J33 Test points JP11 Clock selection Pins 2+3 jumpered 18 J32, J35, J34 Jumpers Not installed 26 J27 J26 21 — 21 — 21 — Test points for MII interface between PHY and DS33ZH11. Must be set with pins 1+2 jumpered. SDRAM oscillator does not meet jitter requirement of the Ethernet PHY. Installation forces Ethernet PHY mode. When not installed, the PHY autonegotiates its settings 26 15 of 44 DS33R11DK/DS33ZH11DK SILKSCREEN REFERENCE FUNCTION BASIC SETTING SCHEMATIC PAGE DS19, DS20, DS21 LED — 19 DS16, DS17, DS18 LED — 19 Reset button — 19 Power supply ground — 2 Power supply VDD — 2 YB01 DS3150 MCLK — 23 YB02 DS21348 MCLK — 25 YB04 Ethernet clock — 18 YB03 SDRAM clock — 21 YB05 Spare oscillator — 25 Y05 Spare oscillator — 23 SW02 GROUND (banana plug) VDD 3.3V (banana plug) DESCRIPTION Activity LEDs for Ethernet PHY. Tx lights when PHY sends a packet; Link lights when the PHY has found a link partner. Ethernet PHY mode LEDs. Used for display of Speed, Duplex, and Collision. — Redundant power supply connection (see top left of board). Redundant power supply connection (see top left of board). 44.736MHz, for use with DS3150 in T3 mode (bottom side of PC board) 1.544MHz, for use with DS21348 in T1 mode (bottom side of PC board) 25.000MHz driver for DS33ZH11 Ethernet PHY (bottom side of PC board). 100MHz SDRAM clock for DS33ZH11 (bottom side of PC board). 2.048MHz, for use with DS21348 in E1 mode (bottom side of PC board). 34.368MHz for use with DS3150 in E3 mode (bottom side of PC board). ADDRESS MAP (ALL CARDS) The external device address space begins at 0x81000000. All offsets given below are relative to this offset. Table 3. Overview of Daughter Card Address Map OFFSET DEVICE 0X0000 to 0X0087 FPGA 0X1000 to 0X1FFF 0X4000 to 0X4FFF DS33R11 DESCRIPTION Processor board identification DS33R11 Ethernet to Serial Engine. Uses CS_X1. T1E1 portion of DS33R11. Uses CS_X4. Registers in the DS33R11 can be easily modified using the ChipView host-based user-interface software with the definition files previously mentioned. DS33R11 INFORMATION For more information about the DS33R11, refer to the DS33R11 data sheet available on our website at www.maxim-ic.com/DS33R11. 16 of 44 DS33R11DK/DS33ZH11DK DS33R11DK/DS33ZH11DK INFORMATION For more information about the DS33R11DK/DS33ZH11DK, including software downloads, refer to the data sheet available on the our website at www.maxim-ic.com/DS33R11DK. TECHNICAL SUPPORT For additional technical support, go to www.maxim-ic.com/support. SCHEMATICS The DS33R11/DS33ZH11DK schematics are featured in the following pages. As this is a hierarchal schematic some explanation is in order. The board is composed of two top-level hierarchal blocks: the DS33R11 block and the DS33ZH11, both of these are nested hierarchy blocks. The DS33R11 hierarchy block contains individual hierarchy blocks for the Ethernet PHY, DS33R11 and microprocessor portions of the design. The DS33ZH11 hierarchy block contains individual hierarchy blocks for the Ethernet PHY, DS33ZH11, T1E1 LIU, and the T3E3 LIU portions of the design. All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From here blocks are wired together as if they were ordinary components. The system diagram is shown again below, with schematic page numbers given for each functional block. DS33RZH11 PC BOARD LAYOUT & SCHEMATIC HIERARCY BLOCK PAGE LISTING DS33R11 SECTION PAGE 1 TOP LEVEL OF DESIGN CONTAINS 3 HIERARCHY BLOCKS ETHERNET PHY PAGE 3 SYMBOL SCHEMATIC PAGES 04-05 SCHEMATIC PAGES 03-17 DS33R11 SECTION PAGE 1 TOP LEVEL OF DESIGN DS3150 LIU BLOCK PAGE 18 SYMBOL SCHEMATIC PAGE 23 CONTAINS 34 HIERARCHY BLOCKS SCHEMATIC PAGES 18-27 DS33ZH11 BLOCK PAGE 3 SYMBOL DS21348 LIU BLOCK PAGE 18 SYMBOL SCHEMATIC PAGES 06-11 SCHEMATIC PAGES 24-25 µP BLOCK PAGE 3 SYMBOL DS33ZH11 BLOCK PAGE 18 SYMBOL ETHERNET PHY PAGE 18 SYMBOL SCHEMATIC PAGES 12-17 SCHEMATIC PAGES 20-22 SCHEMATIC PAGES 26-27 17 of 44 A B C D PAGES PAGES PAGE PAGES PAGES 8 03: 04-05: 06-11: 12-17: 18-19: 20-22: 23: 24-25: 26-27: DS33ZH11 PAGE PAGES PAGES PAGES DS33R11 HIERARCHY BLOCKS 5 (WAN) INTERFACE 7 BLOCK NAME: 6 _ztopdn_. PARENT BLOCK: 5 4 4 NOTES: EACH HIERARCHY BLOCK IS INDEPENDENT OF THE NEXT. ONLY SIGNALS WITH IMPORT/OUTPORT CONNECTORS HAVE CONNECTION OUTSIDE THE HIERARCHY BLOCK. THESE SIGNALS APPEAR AS PINS ON THE HIERARCHY BLOCK CONNECTOR HIERARCHY BLOCKS FOR DS33ZH11, ETHERNET AND SERIAL DS33ZH11 DS3150 LINE INTERFACE UNIT (LIU) DS21348 LINE INTERFACE UNIT (LIU) ETHERNET PHYSICAL INTERFACE (PHY) DESIGN HIERARCHY BLOCKS FOR DS33R11, PROCESSOR AND ETHERNET ETHERNET PHYSICAL INTERFACE (PHY) DS33R11 PROCESSOR CARD DESIGN: DS33R11 AND DS33ZH11 DESIGN TOP LEVEL DECOUPLING / MOUNTING HOLES CONTENTS ZMOSI ZSPISCK FPGA_SPICS _ds33zh11dk_design DS33ZH11 TOP LEVEL HIERARCHY BLOCK PAGES 18-27 FPGA_ZHMISO 6 ZMISO 7 FPGA_ZHMOSI FPGA_ZHSPISCK FPGA_ZHSPICS _ds33r11dk_design DS33R11 TOP LEVEL HIERARCHY BLOCK PAGES 03-17 PAGE 01: PAGE 02: 8 3 3 Fri SCULLY PRINTED STEVE 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: 2 Sep 23 11:01:48 01/05/2005 2005 1 1/27(TOTAL) PAGE: 1/2(BLOCK) DATE: 1 A B C D A B C 4 8 1 1 4 HB02 H06 1.00STANDOFF_NUT 4 H05 BLACK B A CONN_BANANA_2P JB05 B A CONN_BANANA_2P JB02 RED 1 1 2 1 2 4 H02 V3_3 1 7 4 H04 JB01 BLACK B A JB04 CONN_BANANA_2P 1 2 B A 1 4 HB01 1 1 4 6 1 _ztopdn_. 4 1 0.1UF CB61 1 2 10UF CB141 2 10UF C23 2 10UF CB142 2 10UF CB143 2 10UF CB02 0.1UF CB19 1 2 10UF CB138 0.1UF CB32 1 2 10UF CB46 2 10UF CB135 0.1UF CB118 1 2 10UF CB137 0.1UF CB38 1 2 10UF CB08 0.1UF CB139 1 2 10UF CB144 0.1UF CB10 1 2 10UF CB145 2 10UF C24 2 10UF C21 0.1UF CB27 1 2 10UF CB11 1 2 CB39 CB21 0.1UF CB30 1 0.1UF CB31 1 0.1UF CB140 1 0.1UF CB28 1 0.1UF CB59 1 0.1UF CB60 1 0.1UF CB124 1 0.1UF CB48 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF CB58 1 5 0.1UF CB64 1 2 10UF CB55 5 PARENT BLOCK: 0.1UF CB47 1 2 10UF CB07 V3_3 1.00STANDOFF_NUT H03 2 10UF CB147 6 HB03 BLOCK NAME: 4 H01 C17 2 10UF CB149 7 CONN_BANANA_2P 1 2 RED C20 2 10UF CB150 V3_3 0.1UF CB132 1 2 10UF CB134 D 0.1UF CB62 1 2 10UF CB133 2 0.1UF CB131 1 2 10UF CB107 0.1UF CB22 1 0.1UF CB20 1 2 0.1UF 1 0.1UF 4 10UF CB34 10UF CB05 2 CB03 1 470UF 10UF CB04 2 CB136 10UF C19 1 470UF 2 C28 10UF CB52 1 470UF 2 C01 10UF CB100 1 470UF 1 470UF 2 CP02 V3_3 2 CP01 10UF C16 10UF C18 1 470UF 3 1 470UF 10UF C08 STEVE V3_3 2 1 10UF CB50 1 SCULLY 1 10UF 10UF CB06 2 DS33ZH11-R11DK01A0 10UF CB51 10UF CB17 10UF C09 10UF CB75 CB74 CB125 10UF 2 CB127 10UF CB18 1 10UF C14 1 2 DB01 ENGINEER: 2 CP03 10UF C12 3 TITLE: 1 10UF CB01 0.1UF 10UF CB151 .1UF CB175 .1UF 1 01/05/2005 2/27(TOTAL) 1 PAGE: 2/2(BLOCK) DATE: GND_TPP02 GROUND TESTPOINTS GND_TPP01 GND_TPP03 GND_TPP04 GND_TPP05 GND_TPP06 GND_TPP07 GND_TPP08 GND_TPP09 GND_TPP10 GND_TPP11 GND_TPP12 GND_TPP13 GND_TPB01 GND_TPP14 GND_TPP15 GND_TPP16 GND_TP02 GND_TPP17 GND_TPP18 GND_TP03 GND_TPP19 GND_TPP20 GND_TPP21 GND_TPP22 GND_TP01 GND_TPP23 10UF CB14 4 0.1UF CB54 1 2 10UF CB116 10UF CB13 8 C22 2 10UF CB53 10UF CB57 2 10UF CB16 C03 2 10UF CB09 10UF CB15 10UF CB35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A B C D A B 8 RESET_AH a_dut_ D_DUT WR_DUT RD_DUT CS_X5 CS_X4 CS_X3 CS_X2 CS_X1 INT5 INT4 INT3 FPGA_ZHSPICS FPGA_ZHSPISCK FPGA_ZHSPISCK FPGA_ZHMISO FPGA_ZHMISO INT2 FPGA_ZHMOSI FPGA_ZHMOSI FPGA_ZHSPICS _motprocrescard_dn RESET RESET 7 4 1 I32 GND 1 OSC Y02 5 8 V3_3 6 I30 2 R04 30 5 PARENT BLOCK: TX_EN TX_CLK TXD3 TXD3 TXD3 TX_EN TXD2 TXD2 TXD2 TX_EN TXD1 TXD1 TX_CLK TXD0 TXD0 TX_CLK MII COL_DET TXD1 COL_DET TXD0 COL_DET RXDV RX_ERR RX_ERR RX_ERR RXDV RX_CRS RX_CRS RX_CRS RXDV RX_CLK RXD3 RXD3 RXD2 RXD2 RXD2 RX_CLK RXD1 RXD1 RXD1 RXD3 RXD0 RXD0 RXD0 I28 RX_CLK BLOCK _ds33r11dk_design. JP03 BLOCK NAME: OUT VCC HIERARCHY _z11andlan_dn PAGES 06-11 DAT ADDR RST_SERIAL WR RD CS_SER CS_ETH INT R11 NPOP-25.000MHZ_3.3V RST_SERIAL ADDR DAT WR RD CS_ETH CS_SER INT BLOCK I34 RST_ETH RESET PAGES 12-17 REF_CLK_IN PROCESSOR HIERARCHY MDC MDC C IN DESIGN 4 KIT \_ztopdn_\ 4 _mii_wan_dn 3 LED_RX_ADD4 LED_TX_ADD3 LED_GDLINK_ADD2 LED_COL_A1 LED_COL_ADD1 3 DESIGN, 2 Sat SCULLY PRINTED STEVE 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: LED_RX_A4 LED_TX_A3 LED_GDLINK_A2 LED_DPLX_A0 I25 BLOCK LED_DPLX_ADD0 PAGES 04-05 ETHERNET HIERARCHY RESET OUT DS33R11 5 RESET OUT 6 REF_CLK_IN R05 MDIO MDIO D 7 NOTES: ALL HIERARCHY BLOCK NAMES END IN _DN. PINS ON HIERARCHY BLOCKS DO NOT HAVE PIN NUMBERS (BUT PINS ON SYMBOLS DO). SIGNALS INSIDE A HIERARCHY BLOCK ARE LOCAL TO THAT BLOCK - THE SIGNAL TEMP IN BLOCK_A_DN IS DIFFERENT THAN TEMP IN BLOCK_B_DN. PAGE NUMBERS (BOTTOM RIGHT) ARE LISTED BY BOTH THE PAGE NUMBER IN THE BLOCK, AND BY THE PAGE NUMBER WITHIN THE ENTIRE DESIGN CROSS REFERENCE INDICATORS ARE REFERENCEING A GIVEN NET TO OTHER PAGES IN THE DESIGN (PAGE NUMBER GIVEN IS ACCORDING TO ENTIRE 8 REF_CLKO_PN REF_CLKO 3 1 MDIO MDIO 30 MDC MDC 1 Sep LED_DPLX_A0 17 15:05:43 V3_3 LED_RX_A4 LED_TX_A3 LED_GDLINK_A2 2 1 330 5.1K 1 RB75 RB72 1 RB67 1 RB66 01/05/2005 V3_3 2005 1 3/27(TOTAL) PAGE: 1/1(BLOCK) DATE: GND V3_3 RED 1 330 RB68 RB57 AMBER 1 330 5.1K RB55 1 GREEN 2 330 5.1K RB56 1 AMBER 5.1K 2 DS08 I20 1 DS06 I21 2 DS07 I15 1 I19 1 1 I22 1 1 1 DS09 I11 LED_COL_A11 330 I4 5.1K 1 AMBER RB71 RB76 1 NOT THE CURRENT BLOCK) 2 DS11 MII_CLK 1 1 OUT A B C D A B C CM78 8 V3_3 10UF CP07 RXD3 RXD2 RXD1 10 CONN_10P 9 8 6 7 4 3 2 5 1 JP24 RESERVED11 RESERVED10 X2 RESET* TPP02 X1 RBIAS C1 RESERVED1 RESERVED2 VDD/IO_VDD2 VDD/IO_VDD1 RESERVED5 RESERVED14 RESERVED4 RESERVED13 RX_CLK RX_ERR RX_CRS COL_DET RXDV CONTROL OUT OUT OUT OUT OUT IN OUT UP15 DP83847_U1 V3_3 MDC 2 TX_EN 10 ON Z44 TXD0 TXD1 TXD2 TXD3 5.1K 5.1K RM36 5.1K RM35 AN0 AN1 BLOCK NAME: 6 _mii_wan_dn. PARENT BLOCK: 5 ? IN IN IN IN 4 \_ds33r11dk_design\ 330 RM24 1 0.1UF CM98 CM32 V3_3 3 0.1UF CM75 0.1UF CM29 0.1UF CM89 OF MII 2 CM82 STEVE AN_V3_3 1 ANALOG SUPPLY CAPS TO BE PLACED CLOSE TO PIN 14 OF PHY 10UF CM77 10UF CP17 10UF SCULLY 2 PRINTED Fri Sep 01/05/2005 23 11:01:50 1 2005 1/2(BLOCK) 4/27(TOTAL) PAGE: DATE: ETHERNET HIERARCHY BLOCK 10UF CP09 DS33ZH11-R11DK01A0 ENGINEER: TITLE: BEGINNING LEDS NEED TO BE ATTACHED OUTSIDE OF MODULE DUE TO STRAP ADAPTING OPTION OF DP83847 AMBER V3_3 ? JMP_2 RM34 AN_ENJMP_2 ? CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMONCENTER LINE 7 IO IO IO IO IO JMP_2 LED_SPEED LED_TX_ADD3 LED_RX_ADD4 LED_GDLINK_ADD2 CONN_10P 9 8 6 7 4 3 5 1 JP25 AN_0 AN_1 AN_EN LED_SPEED LED_RX/PHYAD4 LED_TX/PHYAD3 LED_GDLNK/PHYAD2 LED_COL_ADD1 IO MDC IN MDIO 30 LED_COL/PHYAD1 RM02 LED_DPLX/PHYAD0 MDIO LED_DPLX_ADD0 TX_CLK GND2 PLACEMENT NOTE: TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW 0.2 BETWEEN CONNECTORS. OUT OUT OUT RXD0 RESET TPP01 RBIAS MII_CLK 10.0K RP11 C1PIN OUT IN IN 0.1UF COMPONETS FOR C1 AND RBIAS MUST BE PLACED CLOSE TO PIN GND1 AN_V3_3 VDD/ANA_VDD D RESERVED6 RESERVED15 RESERVED3 RESERVED12 RESERVED7 RESERVED16 VDD1 GND3 RESERVED8 RESERVED17 VDD2 GND4 RESERVED9 RESERVED18 VDD3 GND5 3 0.1UF 4 0.1UF CP15 5 CM67 6 CP08 0.1UF 7 0.1UF 8 1 A B C D A B C D RM14 RXD2 RXD3 8 RD_N RD_P RM12 30 30 30 RD- RD+ 7 RXD RXD RXD RXD TXD TXD3 30 TXD TXD2 RM09 TXD TXD1 RM13 TXD TXD0 TX_ER 6 BLOCK NAME: TD- TD+ COL CRS/LED_CFG* TX_CLK RX_CLK RX_DV RX_ER/PAUSE_EN* PORT DP83847_U1 TX_EN RXD1 7 UP15 TX_EN RXD0 8 6 30 30 30 30 RX_CRS COL_DET TX_CLK RX_CLK _mii_wan_dn. TD_N TD_P RM08 RM05 RM03 RM21 RXDV RX_ERR PARENT BLOCK: 5 5 4 \_ds33r11dk_design\ 4 RM10 TD_N TD_P RD_N RD_P .1UF JP21 SYM_1 SCULLY 2 DS33ZH11-R11DK01A0 STEVE 1 01/05/2005 1 5/27(TOTAL) PAGE: 2/2(BLOCK) DATE: ETHERNET HIERARCHY BLOCK RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY ENGINEER: SH2 J7,8 J4,5 J6 J3 J2 J1 SH1 CONN_HFJ11_2450_U P8 P6 P5 P3 P2 P4 P1 2 CAPS FOR XFRM CENTER TAP SHOULD BE PLACED CLOSE TO XFRM 49.9 RP06 49.9 RP08 54.9 RM06 54.9 .1UF CM59 END OF MII TITLE: 3 V3_3 .1UF CP12 3 CM63 A B C D A B C 8 S_RLOS 1 RED DS05 IO DAT IN ADDR 2 330 A A A A A A A A A A D D D D D D D D C11 A18 B18 C18 A17 B17 C17 A16 B16 C16 C15 A14 B14 C14 A13 B13 C13 A12 B12 WR 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 RB48 WR* B11 RD IN IN IN 7 INT* 6 B6 S_JTDI JTDI A6 S_JTCLK JTCLK 5 TESO D4 S_TESO TDATA A4 S_TDATA TCLKO C2 S_TCLKO TCLKI D1 S_TCLKI TCLK D2 S_TCLK BPCLK B1 S_BPCLK XTALD J4 PARENT BLOCK: 5 \_ds33r11dk_design\ CONTROL & TRANSCEIVER DS33R11_U1 PORT TNEGI C3 S_TNEGI U09 TNEGO D3 S_TNEGO BLOCK NAME: _z11andlan_dn. RD* ETH_CS* A11 SPI_CS CS_ETH A9 A10 OUT INT 0 ZSPICS TPB07 C5 S_JTDO JTDO TPOSI B3 S_TPOSI 6 B9 S_JTMS JTMS TPOSO E1 S_TPOSO 7 TEST1 C6 B2 S_LIUC LIUC TCHBLK A2 S_TCHBLK D 8 K4 S_8XCLK TPB09 B8 S_JTRST JTRST B5 S_RCL RCL H4 S_MCLK MCLK A1 S_RCHBLK RCHBLK G2 S_RCHCLK RCHCLK G3 S_RCLK RCLK TCHCLK G1 S_TCHCLK CS_SER D7 SER_CS* TEST2 D6 TPB08 TSTRST C4 RST_SERIAL 8XCLK IN M4 S_RCLKI RCLKI RCLKO TSSYNC A5 S_TSSYNC H3 S_RDATA RDATA TSYNC C1 S_TSYNC M3 S_RCLKO RSYNC G4 S_RSYNC IN S_RNEGO S_RPOSI S_RPOSO S_RSYSCLK RRING S_TSYSCLK S_TSER S_TSIG RTIP L4 N2 J3 N3 F4 M1 K1 T1 T2 R1 R2 E4 E3 B4 RNEGI RNEGO RPOSI RPOSO RSYSCLK RRING RTIP TRING1 TRING2 TTIP1 TTIP2 TSYSCLK TSER TSIG 4 TTIP TRING S_RMSYNC S_RNEGI U3 RMSYNC RLOS/LTC S_RFSYNC RFSYNC S_RLOS S_RSIGF P3 RSIGF N1 S_RSIG L3 RSIG A3 S_RSER H2 RSER 4 3 3 STEVE SCULLY 2 OF DS33R11 DS33ZH11-R11DK01A0 ENGINEER: TITLE: BEGINNING 2 01/05/2005 1 PAGE: 1/6(BLOCK) 6/27(TOTAL) DATE: HIERARCHY BLOCK 1 A B C D A B QOVF 1 8 TP01 330 RB20 DS02 OUT OUT OUT OUT IN IN IN IN IN IN TXD3 TXD2 TXD1 TXD0 TX_CLK RXD3 RXD2 RXD1 RXD0 7 SDATA SDATA SDATA SDATA Y4 Y2 Y5 Y3 1 2 3 4 SMASK3 SDATA V15 SD_DQM3 SMASK2 W2 V16 SD_DQM2 SMASK1 SMASK0 TXD0_3 TXD0_2 0 V7 E19 E20 30 TXD0_1 TXD0_0 F18 F19 Y6 RB81 RB79 SD_DQM1 30 TXCLK0 SD_DQM0 RB80 RB82 RXD0_3 H19 RXD0_1 L19 RXD0_2 RXD0_0 L18 L20 RXCLK0 M18 ZJTRST* M20 ZJTMS ZJTDO ZJTDI ZJTCLK C7 C8 B7 C9 A7 IN ETHERNET TO SERIAL U09 DS33R11_U1 4 ENGINE 0 1 2 3 4 5 6 7 8 9 10 11 W9 W10 W14 W12 Y15 W15 Y14 V13 W13 Y12 V12 Y10 V14 W11 SWE* SDA SDA SDA SDA SDA SDA SDA SDA SDA SDA SDA SDA V10 SCS* Y8 W7 SCAS* SRAS V11 SBA1 SDCLKO Y11 SBA0 V8 E18 STMD SD_DQ BLOCK NAME: 6 _z11andlan_dn. PARENT BLOCK: 5 \_ds33r11dk_design\ 4 3 SDCLKI D18 STEN W5 5 RX_CLK Z_JTRST Z_JTMS Z_JTDO Z_JTDI IN COL0 IN CRS0 V5 6 SDATA N18 COL_DET RX_CRS OUT REFCLK W6 7 REFCLKO V6 8 SDATA M19 REF_CLK_IN IN W4 9 SDATA A19 IN V4 10 RXERR0 A20 OUT V2 11 SDATA K18 REF_CLKO_PN RX_ERR RXDV K19 TX_EN F20 V3 12 RXDV0 V1 13 TXEN0 W3 14 SDATA IO W1 15 SDATA OUT C19 MDC QOVF Y16 SDATA Z_JTCLK G19 RMIIS MDC MDIO C20 MDIO IN A8 RST* H18 QOVF 5 B20 MODEC1 16 SDATA Y17 17 SDATA 6 B19 MODEC0 V18 SDATA Y19 18 SDATA K20 AFCS SDATA 19 SDATA G20 DCEDTE V19 20 SDATA N19 FULLH0 Y20 21 SDATA U19 22 SDATA W20 23 SDATA U20 24 SDATA T19 25 SDATA N20 H10S0 RST_ETH RMIIMIIS MODEC1 MODEC0 AFCS DCEDTES FULLDS H10S HWMODE C10 HWMODE T20 26 C 7 RSER0 SDATA H1 Z_RSER Z_RDEN Z_RCLKI Y18 SDATA F2 W19 27 RCLKI0 P2 RDEN0 SDATA 30 28 TCLKI0 F1 Z_TCLKI Z_TDEN Z_TSER V17 29 SDATA D5 W17 SDATA E2RB70 W16 30 TDEN0 30 TSER0 RB77 SDATA 30 SDATA RB96 SDATA R03 30 31 D 8 3 SCANEN 2 STEVE SCULLY 2 DS33ZH11-R11DK01A0 SD_WE SD_RAS SD_CLKO SD_CLKI SD_CS SD_CAS SD_BA1 SD_BA0 SCANMOD ENGINEER: TITLE: SD_A 01/05/2005 1 7/27(TOTAL) PAGE: 2/6(BLOCK) DATE: 1 A B C D A B 8 7 DQ DQ DQ 51 53 28 29 VDD3 VDD4 0 - VSS2 VSS3 VSS4 _z11andlan_dn. 1 MEG X 32 VSSQ8 X 4 BANKS PARENT BLOCK: 5 4 SD_DQM1 SD_DQM2 SD_DQM3 SD_BA0 SD_BA1 28 59 22 23 DQM DQM BA BA 1 2 3 4 5 6 7 8 9 10 11 26 27 60 61 62 63 64 65 66 24 21 A A A A A A A A A A A \_ds33r11dk_design\ 0 25 A SD_A SD_DQM0 19 RAS* 16 18 CAS* 71 SD_RAS 17 WE* DQM SD_WE SD_CAS 20 CS* DQM SD_CS 67 FROM Z11 SD_CLKO 68 CKE 4 CLK V3_3 SYNCHRONOUS DRAM DQ MT48LC4M32B2 VSSQ7 1 6 VDDQ8 MT48LC4M32B2_TSOP_U UB04 VDDQ7 4 2 BLOCK NAME: DQ 50 DQ 37 20 48 DQ 36 19 27 DQ 34 18 26 DQ 33 17 DQ DQ 31 16 47 DQ 85 15 25 DQ 83 14 DQ DQ 82 13 45 DQ 80 12 24 DQ 79 11 DQ DQ 77 10 42 DQ 76 9 23 DQ 74 8 DQ DQ 13 7 DQ DQ 11 6 39 DQ 10 5 40 DQ 8 4 22 DQ 7 3 21 DQ 5 2 VDDQ6 VSSQ6 SD_DQ VDD2 5 VDDQ5 VSSQ5 6 VDDQ4 VSSQ4 C 7 VSSQ3 D 8 VSSQ2 DQ DQ VDDQ3 43 29 15 1 VDD1 VSS1 86 72 58 44 DQ 31 54 56 30 VDDQ2 81 75 55 49 41 35 9 3 VDDQ1 VSSQ1 84 78 52 46 38 32 12 6 3 2 STEVE SCULLY 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: V3_3 SYSCLKO 3 01/05/2005 1 8/27(TOTAL) PAGE: 3/6(BLOCK) DATE: 1 A B C D A B C RVSS2 RVSS3 RVSS4 RVSS5 TVSS1 TVSS2 TVSS3 TVSS4 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 K2 J1 L2 M2 P1 R3 T3 U2 Y7 W18 U4 U5 U6 U9 8 RVSS1 J2 U7 DVSS4 VSS7 DVSS3 VSS8 P20 T4 VSS9 U8 W8 B10 1.8VDD2 B15 1.8VDD1 J20 1.8VDD4 F3 1.8VDD3 VSS10 7 VSS11 Y1 6 BLOCK NAME: _z11andlan_dn. POWER & GROUND D8 U09 VSS15 DS33R11_U1 V1_8ZCHIP VSS12 VSS13 VSS14 VSS16 D9 VSS17 Y13 1.8VDD9 P18 1.8VDD8 R20 1.8VDD7 P19 1.8VDD6 V9 1.8VDD5 R19 1.8VDD13 J18 1.8VDD12 C12 1.8VDD11 Y9 1.8VDD10 DVDD2 VSS21 D19 VSS20 J19 VSS19 H20 VSS18 U11 DVDD1 DVDD4 DVDD7 VSS26 DVDD6 VSS25 U14 DVDD5 VSS24 A15 E17 D16 D17 6 D15 D11 D12 D13 D14 G17 R18 F17 3VDD13 3VDD14 3VDD15 3VDD16 V3_3 PARENT BLOCK: D20 3VDD12 5 H17 G18 3VDD11 L17 J17 M17 3VDD8 3VDD10 T18 3VDD7 3VDD9 N17 3VDD6 R17 3VDD3 K17 T17 3VDD2 P17 U17 TVDD 3VDD1 3VDD5 U1 RVDD2 3VDD4 L1 K3 RVDD1 5 CB109 1 2 DVDD3 VSS22 U12 VSS23 DVDD8 VSS27 U15 U16 7 0.1UF CB117 1 2 U13 0.1UF DVSS2 1 CB120 1 2 R4 0.1UF CB108 1 2 0.1UF CB97 1 2 P4 0.1UF CB96 2 0.1UF CB82 1 2 DVSS1 1 2 0.1UF CB121 1 2 N4 0.1UF CB111 1 2 0.1UF CB88 1 2 V1_8ZCHIP 0.1UF CB112 1 2 0.1UF 0.1UF CB92 1 2 D 0.1UF CB123 1 2 0.1UF 0.1UF CB83 1 2 V20 U18 D10 10UF 0.1UF CB70 1 2 8 CB66 CB103 1 2 CB68 10UF CB130 10UF CB85 10UF CB129 U10 10UF CB99 0.1UF CB80 1 2 \_ds33r11dk_design\ 0.1UF 2 CB49 1 470UF 0.1UF CB71 1 2 1 C04 2 0.1UF CB113 1 2 0.1UF CB101 1 2 1 2 4 0.1UF CB86 1 2 CB45 0.1UF 1 1 1 3 4 STEVE SHDN IN SCULLY GND SET OUT DS33ZH11-R11DK01A0 ENGINEER: TITLE: 1 1UF RST 5 7 6 2 1 2 3 0.1UF CB90 1 2 2 0.1UF CB114 1 2 8 0.1UF CB102 1 2 OUT 0.1UF CB104 1 2 IN 0.1UF CB128 1 2 1 0.1UF CB81 1 2 U08 MAX1792 0.1UF CB79 1 V3_3 0.1UF CB106 1 2 2 0.1UF CB73 2 2 1UF CB36 2 1UF CB42 2 1UF CB43 1 470UF CB93 1 2 3 0.1UF CB115 1 2 4 0.1UF CB94 1 2 V3_3 CB69 0.1UF CB110 1 2 2 0.1UF 2 CB146 0.1UF CB84 1 2 CB44 1 2 10UF CB37 1 0.1UF CB148 2 1 01/05/2005 PAGE: 4/6(BLOCK) 9/27(TOTAL) DATE: CB40 1 2 1 V1_8ZCHIP 1UF 10UF CB67 10UF CB98 10UF CB63 1UF 10UF CB119 CB41 1 10UF CB89 2 1UF 10UF A B C D A B C D 8 8 Z_JTRST 4 1 9 7 5 3 1 10 8 6 4 2 OSC CONN_10P 9 7 5 3 1 J05 GND 1 Y03 10 8 6 4 2 OUT VCC 5 8 7 30 V3_3 1 3 5 7 9 S_TCLK S_TCLKO S_TCHCLK S_RCLK S_RCHCLK SD_CLKI 6 10 8 6 4 2 CONN_10P 9 7 5 3 1 J18 10 8 6 4 2 Z_RCLKI Z_TCLKI 5 MDC MDIO Z_TDEN Z_RDEN Z_TSER Z_RSER 4 2 2 BLOCK NAME: 6 _z11andlan_dn. PARENT BLOCK: 5 \_ds33r11dk_design\ 4 V3_3 TP02 TP03 S_TCHBLK JP01 V3_3 S_RCHBLK JP02 S_TSER S_RSER JUMPER 1 J11 1 J10 JUMPERS FOR ETHERNET RSER RCLK RDEN - VALID COMBINATIONS: E_RDEN=S_RCHBLK AND E_RCLKI=S_RCLK E_RDEN=VCC AND E_RCLKI=S_RCHCLK SERIAL SIGNALS WITH OFF PORT FLAGS GOTO THE 140 PIN WAN CONNECTORS PLACE TESTPOINTS FOR ETHERNET DATAEN AND CLK NEAR CORRESPONDING 3 PIN Z_JTDI Z_JTDO Z_JTCLK Z_JTMS R14 V3_3 100.000MHZ_3.3V 7 RB30 10K RB31 10K 3 3 STEVE SCULLY 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: 2 1 DCEDTES 1 1 SCANMOD SCANEN 1 1 1 1 H10S AFCS RMIIMIIS FULLDS 1 1 HWMODE MODEC1 1 MODEC0 RB45 2.0K RB44 2.0K RB51 2.0K RB19 2.0K RB54 2.0K RB50 2.0K RB14 2.0K RB49 2.0K RB46 2.0K RB47 2.0K 2 2 2 2 2 2 2 2 2 2 01/05/2005 1 10/27(TOTAL) PAGE: 5/6(BLOCK) DATE: V3_3 V3_3 V3_3 V3_3 1 A B C D A B C D 10 S_8XCLK 9 7 5 3 S_RDATA 1 8 8 6 4 2 10 8 6 4 2 10 8 6 4 2 10 8 6 4 2 S_LIUC S_TCLKO S_TESO S_TNEGO S_TPOSO S_RCLKO S_RNEGO 7 S_TSYSCLK S_RFSYNC 30 30 30 30 30 30 S_RNEGI S_TCLKI S_TDATA S_TNEGI S_TPOSI S_RCLKI 6 V3_3 OSC OUT VCC S_TSIG S_RSYNC S_RMSYNC S_RLOS GND 1 BLOCK NAME: _z11andlan_dn. RB53 RB69 RB58 RB73 RB52 RB83 10K 10K 10K 10K 10K 10K S_RPOSI S_TSER R09 RB59 30 RB39 S_LIUC S_RSYSCLK RB61 S_TSYNC 10K RB60 S_TSIG RB37 RB38 S_TSSYNC S_TSYSCLK RB63 S_RPOSO V3_3 S_JTDO S_JTDI S_JTCLK S_JTMS S_RSYSCLK RB34 10K RB36 10K CONN_10P 9 7 5 3 1 J12 CONN_10P 9 7 5 3 1 S_BPCLK 9 7 5 3 1 S_TSYNC S_JTRST J06 4 1 10 8 6 4 2 5 10 8 6 4 2 30 CONN_10P 9 7 5 3 1 J13 RB35 V3_3 0.0 R13 0.0 R12 UNMARKED BIAS 60.4 \_ds33r11dk_design\ ALL S_RSIGF S_RSIG S_TSSYNC S_RCL RRING RTIP TRING TTIP S_MCLK PARENT BLOCK: 9 7 5 3 1 5 8 2 RB91 1 4 4 0.0 R10 0.0 R07 1UF C11 3 2 1 10 11 12 ARE 10K S_TCLK 1:1 TB01 7 6 9 8 1:2 TB01 5 4 RESISTORS CB105 Y01 5 60.4 0.1UF 2 RB87 21 1 2.048MHZ_3.3V STEVE SCULLY TPB03 RJ_PIN5 RJ_PIN2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: 3 RJ_PIN1 RJ_PIN2 2 RJ_PIN4 END OF DS33R11 S_MCLK JP04 S_RCLK 3 2 B D F H A C E G J20 1 TPB04 U07 NC7SZ86_U RJ_PIN4 J24 J19 1 4 INVERTER TPB06 2 2 01/05/2005 TPB05 1 PAGE: 6/6(BLOCK) 11/27(TOTAL) DATE: 1 1 J25 J17 SPARE INVERTERS U06 NC7SZ86_U 4 INVERTER 1 CONN_BNC_5P 1 RJ_PIN5 1 1 RJ_PIN1 3 5 7 CONN_BNC_5P CONN_RJ48 2 4 6 8 HIERARCHY BLOCK RB32 6 10K 7 10K 8 RB33 2 3 4 5 2 3 4 5 A B C D A B 54 55 56 57 58 61 ICOC21 ICOC20 ICOC13 ICOC12 ICOC11 ICOC10 70 8 69 SCI1_IN 68 SCI2_IN SCI1_OUT 66 SCI2_OUT TEST 63 53 ICOC22 GND 52 ICOC23 TIM_16H_8L INT6* ICOC10 ICOC11 ICOC12 ICOC13 ICOC20 ICOC21 RXD1 TXD1 RXD2 TXD2 MMC2107 CONTROL INT7* 89 ICOC22 TEST EB3 EB2 96 EB3* INT5* 84 98 EB2* INT4 82 88 EB1 EB0 EB1* INT3* 79 100 INT2* 75 ICOC23 7 CS0* CS1* CS2* CS3* TC1 TC2 CSE0 CSE1 6 BLOCK NAME: 3 2 6 4 1 SW01 VCC 4 V3_3 24 CS2 83 94 143 93 120 1 3 GND MR* 5 2 1.0K RESET RB26 PARENT BLOCK: RESET* MAX811_U U01 2.93V SS ONCE_DE_B SCK PROC_RESET_OUT CPUCLK_OUT 1 27 30 31 34 35 14 13 12 11 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 U03 \_ds33r11dk_design\ 4 PROC_RESET 25 22 21 20 17 16 15 12 10 7 5 4 3 2 144 16 4 15 17 18 19 20 21 PROC_RESET 118 128 22 CS0 86 23 25 CS3 81 CS1 26 TC1 85 27 TC2 28 29 30 31 78 CSE1 CSE0 5 67 62 60 _motprocrescard_dn. SS* DE* SCK RSTOUT* CLKOUT RESET* 80 104 PQB3 INT1* 72 USER_LED1 USER_LED2 INT3 INT4 RUN_KIT_USR KIT_STATUS INT2 C U03 YC0 YCO MOSI MISO D MOSI 90 101 EB0* PQB3 PQB2 PQB1 PQA3 MISO 91 105 PQB2 INT0* 71 PQB0 PQA4 PQA1 XTAL 106 PQB1 109 PQA3 110 PQA1 111 PQA0 ONCE_TDI 2107_TDO 124 133 PQA0 107 PQB0 135 EXTAL 108 PQA4 7 3 MMC2107 PORT 3 2 STEVE VDDSYN A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 V3_3 14 13 12 11 10 9 8 7 6 5 4 136 137 139 6 11 13 14 23 24 26 28 1 15 134 0 16 132 50 17 131 49 18 122 3 19 121 2 20 119 47 21 117 29 22 116 1 2 PRINTED SCULLY Fri Sep 23 01/05/2005 11:01:52 1 2005 12/27(TOTAL) PAGE: 1/6(BLOCK) DATE: OF PROCESSOR HIERARCHY BLOCK PD DS33ZH11-R11DK01A0 ENGINEER: TITLE: BEGINNING 36 10 TCLK 59 RW 37 9 D9 38 8 D8 102 RW 95 OE* OE RCON 97 SHS* TA TEA 99 TA* 39 7 D7 40 TEA* 41 6 D6 92 5 125 113 VRH D4 42 4 VSTBY VRH 112 VRL D3 43 3 D5 FLASH_VPP 87 VPP D2 46 130 115 VDDA D1 2 D10 103 48 VSS7 74 51 VSS5 VDDF 1 VSS4 VDDH 0 TDI 123 VDDSYN VSSF 73 TDO 141 VDD8 VSSSYN 126 TRST* 129 VDD7 VSS8 140 TMS 77 VDD6 VSS6 76 142 65 VDD5 127 138 XTAL OSC_MCU ONCE_TCLK ONCE_TRST_B ONCE_TMS 45 VDD4 RB29 33 VDD3 64 D0 0.0 CB33 .1UF 19 VDD2 44 VSSA 114 C02 1UF 9 VDD1 VSS3 32 VSS1 8 VSS2 18 8 PA A B C D A B 23 26 27 11 10 9 PA 4 14 25 28 15 13 3 16 12 2 31 17 8 ENABLE A8 A9 A10 A11 A12 A13 A14 A15 A16 U05 CY62128V V3_3 INTERN/EXTERN BOOT FLASH PD PD PD PD PD PD PD PD CY62128V 5 8 C W/ PLL XTAL INTERNAL DRIVE FULL MASTER MODE PD 32 VCC 6 7 A6 7 6 A5 D 7 1 N_C 7 8 A4 9 5 8 29 WE* CS0 4 A7 24 OE* EB0 OE 30 CE2 10 3 A3 16 GND 22 CE1* A2 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 1 1 10K 1 30 29 28 27 26 25 24 19 18 17 15 14 13 2 2 2 2 2 1 2 6 V3_3 2 1 10K RB13 1 5 2 27 26 23 25 4 28 3 31 V3_3 A8 A9 A10 A11 A12 A13 A14 A15 A16 UB03 CY62128V 4 4 CY62128V \_ds33r11dk_design\ PA PARENT BLOCK: 9 10 11 12 13 14 15 16 17 WHEN SET FOR BOOT INTERNAL D18 HAS A 10K LOAD TO GND BOOT EXT D18 HAS A 10.5K LOAD TO V3V RCON _motprocrescard_dn. PD BLOCK NAME: 31 20 2 21 10K RB07 1 10K 2 1 10K RB22 RB10 10K 1 10K RB18 1 10K RB17 RB11 10K RB09 10K 1 RB08 RB12 1 1 1 1 1 2 1 5 RESET CONFIGURATION 6 32 VCC 5 8 A1 11 1 N_C 6 7 A6 7 6 A5 8 5 A4 9 4 A3 10 3 A0 12 1 2 29 WE* A7 24 OE* EB1 OE 30 CE2 CS0 22 CE1* A2 16 GND A1 11 A0 12 1 2 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 21 20 19 18 17 16 20 19 18 17 15 14 13 3 RESET AND CHIP 2 STEVE SCULLY 2 DS33ZH11-R11DK01A0 PD ENGINEER: TITLE: 23 22 21 3 01/05/2005 1 13/27(TOTAL) PAGE: 2/6(BLOCK) DATE: CONFIGURATION 1 A B C D A B 8 RB03 PRT1_IN PRT1_OUT PRT1_IN PRT1_OUT SCI1_IN SCI1_OUT 1 10 9 8 7 6 5 4 3 2 1 V3_3 E D C B A J02 V3_3 J H G F FORCEOFF* VCC R1IN T1OUT R1OUT FORCEON T1IN T2IN INVALID* R2OUT 9 8 7 6 7 1 V+1 V+2 C1+ C1- C2+ C2- V- GND T2OUT R2IN UB01 MAX3233E 11 12 13 14 15 16 17 18 19 20 1 1 1.0M 6 _motprocrescard_dn. 5 5 PARENT BLOCK: TDI 4 4 \_ds33r11dk_design\ ...FPGA+FLASH... CONFIGURATION ONCETDO PIN JTAG MMC2107 XTAL OSC_MCU ONCETDI PIN PLACE PADS FOR CAP BUT DO NOT POPULATE BLOCK NAME: 2 R01 10K 6 3 3 1 PROC_RESET USER_LED1 2 2 1 1 330 RB23 330 RB21 1 J03 13 11 9 7 5 3 1 2 ENGINEER: STEVE 1 SCULLY 2 DS03 FLASH_VPP 2 1 2 1 1 01/05/2005 RB28 10K RB27 10K 1 14/27(TOTAL) PAGE: 3/6(BLOCK) DATE: ONCE_TRST_B 14 RED DS04 1 GREEN 1 ONCE_DE_B 12 V3_3 ALIGN KEY ONCE_TMS 10 8 6 4 2 CON14P J04 CON14P 2 V3_3 DS33ZH11-R11DK01A0 KIT_STATUS TITLE: V3_3 ONCE_TCLK 2107_TDO ONCE_TDI 2 1 2 CONN_DB9P 5 4 3 2 1 10K RB25 8.0MHZ RB06 C 1 2 10K D 10K 1 XB01 1 2 RB24 2 1 7 RB01 1.0K 8 2 1 2 1 1 2 A B C D A 8 PL7B PL8A PL8B PL9A/PCLKT7_0 PL9B/PCLKC7_0 5 6 7 8 9 0 1 27 28 29 PL15A/LDQS15 PL15B PL16A PL16B PL18A/VREF1_6 PL18B/VREF2_6 31 32 33 34 35 12 13 14 15 16 BANK 5 7 6 BLOCK NAME: D_DUT PB10B 40 30 PB11A 41 FPGA_ZHMOSI CS_X1 CS_X2 11 42 7 PL14B PL14A 27 9 43 6 PB10A 39 U04 97_IO I/O PORT LFEC_T144_U 45 5 29 PL13B PLL INPUT BANK 0 46 4 10 PL13A 26 PL12B/LLM0_PLLC_FB_A 23 6 8 PL12A/LLM0_PLLT_FB_A 22 5 25 PL11B/LLM0_PLLC_IN_A 21 4 7 PL11A/LLM0_PLLT_IN_A 20 PLL INPUT 3 2 PL7A CPUCLK_OUT 4 23 47 3 B PA 30 PL2B/VREF1_7 22 48 2 C 31 142 PT10A 141 PT10B 140 PT12A 139 PT12B BANK 7 BANK 6 PB11B 26 PB14A/BDQS14 138 25 PB14B PT13A PB13B 137 PT13B 135 24 134 PT14B PB15A PL2A/VREF2_7 BANK 4 BANK 5 PLL INPUT 1 79 PR14A/RLM0_PLLT_FB_A PR14B/RLM0_PLLC_FB_A _motprocrescard_dn. A_DUT_ PARENT BLOCK: RUN_DRV TCLKEQRCLK EN_INTS MEM_CS RB15 INT5 USERFPGA2 FPGA_ZHSPICS 0.0 OUT MEM_SCK OUT RUN_DRV EN_INTS TCLKEQRCLK INSTALL INSTALL INSTALL 3 STEVE 1 FOR TQFP144 SCULLY 2 01/05/2005 1 15/27(TOTAL) PAGE: 4/6(BLOCK) DATE: JUMPER TO RUN DEVICE DRIVER JUMPER TO ENABLE INTERRUPT SERVICE JUMPER TO SET TCLK=RCLK 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: MEM_SCK MUST BE AT PIN77 MEM_SO / MEM_CS / MEM_SI / 3 V3_3 MEM_SO FPGA_ZHSPISCK 4 IN RB16 MEM_SI RESET_AH RD_DUT WR_DUT ALE_DUT 330 FPGA_ZHMISO DS01 INT_LED INT2 \_ds33r11dk_design\ 74 75 PR18A/VREF1_3 76 PR16A 77 PR16B PR15B 78 81 PR13B/RLM0_PLLC_IN_A PR15A/RDQS15 82 85 PR12B/DI/CSSPI* 83 87 PR13A/RLM0_PLLT_IN_A 88 PR11A/D7/SPID0 PR9B/PCLKC2_0 PR11B/BUSY/SISPI 100 86 101 102 PR9A/PCLKT2_0 103 PR7B PR8A 104 PR8B 105 106 PR2B/VREF1_2 PR7A 107 4 PR2A/VREF2_2 PR12A/DOUT/CSO* PLL INPUT PB17A/PCLKT5_0 51 3 PB17B/PCLKC5_0 53 2 PB18A/WRITE* 56 0 RESET 57 1 PT14A/TDQS14 PD 58 2 133 21 49 1 5 59 3 PT15A PB15B 6 60 4 7 61 5 PLL INPUT 62 132 19 PB21B/D1/SPID6 64 7 6 PT15B PB16A/VREF2_5 131 20 130 PT16B/VREF1_0 129 PT17A/PCLKT0_0 127 PT17B/PCLKC0_0 18 124 PT18A 17 122 PT19A/VREF1_1 PB20A/VREF2_4 123 PB18B/CS1* 120 PT20A PB20B/D0/SPID7 PT18B PB19A/VREF1_4 119 PT20B 16 121 PT19B/VREF2_1 PB19B/CS* 118 PT21A PB22A/BDQS22 65 8 D 8 PB23A 67 PT16A/VREF2_0 PB16B/VREF1_5 50 0 OUT PB23B/D4/SPID3 68 116 OE RW CS0 115 PT22A/TDQS22 PB22B/D3/SPID4 66 9 BANK 3 PB24B/D5/SPID2 PT21B PB21A/D2/SPID5 114 PT22B CS1 113 PT23A BANK 2 112 PT25A CS2 EB0 EB1 111 PT25B PB25B/D6/SPID1 70 69 PLL INPUT CS_X3 CS_X4 CS_X5 CS_X6 A B C D A B C 8 CS_X1 7 9 11 13 4 5 6 7 7 5 3 13 11 9 7 5 3 1 14 12 10 8 6 4 2 J07 NOPOP 14 12 10 8 6 4 2 14 12 10 8 6 4 2 13 11 9 7 5 3 1 14 12 10 8 6 4 2 14 12 10 8 6 4 2 0 1 R1 R2 10K 0 1 2 INT2 INT3 6 BLOCK NAME: J08D_DUT NOPOP 1 6 2 2 V3_3 _motprocrescard_dn. V3_3 TCLKEQRCLK 10K EN_INTS RUN_DRV A_DUT_ CONN_14P 3 13 3 1 11 4 1 9 5 2 7 14 12 10 8 6 4 2 CONN_14P 5 7 3 8 6 1 9 13 11 9 7 5 3 1 J09 NOPOP CONN_14P 13 7 9 CS_X3 WR_DUT 5 CS_X4 11 3 CS_X2 RD_DUT 1 RESET 7 5 5 RB41 2 1 10K RB40 PARENT BLOCK: INT2 INT3 INT4 INT5 2 10K RB42 V3_3 4 10K 10K RB43 \_ds33r11dk_design\ 1 4 2 1 D 8 2 1 3 3 INT5 INT4 INT3 INT2 STEVE SCULLY 2 DS33ZH11-R11DK01A0 D_DUT ENGINEER: TITLE: WR_DUT RD_DUT CS_X1 CS_X2 CS_X3 RESET_AH RESET CS_X4 CS_X5 A_DUT_ IN IN IN IN 2 IO OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 01/05/2005 1 16/27(TOTAL) PAGE: 5/6(BLOCK) DATE: 1 A B C D A B C 8 2 3 1 1 U02 I26 2.7V 6 10 8 7 GND SHDN* IN I28 RST* IC 4 5 4 7 3 8 V3_3 V3_3 V1_2 L_TDO L_TDI L_TCK L_TMS 6 BLOCK NAME: OUT UB02 MAX1963 6 GND HOLD* WP* VCC AT25160A_U CS* SO SI MEM_CS 2 5 SCK V3_3 VCC TDO TDI CONN_10P GND 7 5 MEM_SCK 6 MEM_SO MEM_SI 9 7 5 4 2 CB29 CB25 10UF CB12 10UF CB26 .1UF _motprocrescard_dn. 5 PARENT BLOCK: \_ds33r11dk_design\ 4 RESET L_TMS L_TDO L_TDI L_TCK CFG1 CFG0 90 91 SPI3 MODE 54 126 VCCJ VCCAUX1 VCCAUX2 DONE INIT* CCLK 97 95 94 10 19 VCC3 XRES 99 VCC2 RESISTOR 13 92 VCC1 V3_3 PLACE CLOSE TO PIN NEEDS 10K,1% STEVE SCULLY 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: 3 CONTROL U04 LFEC_T144_U I10 97_IO 2 10K TPB01 I6 TPB02 I5 MEM_SCK R02 V3_3 V1_2 1 01/05/2005 RB02 1 6/6(BLOCK) 17/27(TOTAL) PAGE: DATE: END OF PROCESSOR HIERARCHY BLOCK ALL LOW FOR PROGRAM* CFG2 89 93 TMS TDO TDI TCK 17 18 16 14 128 TCK GND3A/GND4 72 TMS 80 3 GND3B 1 GND4 63 RB05 10K RB04 10K 3 GND5 4 GND8 15 3 5 136 VCCIO0A GND0 73 VCCIO3A GND9 96 1 .1UF 143 VCCIO0B GND1 84 VCCIO3B GND6A 52 44 VCCIO5B 98 I24 CB24 110 VCCIO1A 117 55 VCCIO4A 37 28 24 VCCIO6A GND10 J01 6 .1UF 125 VCCIO1B GND2/GND1 71 VCCIO4B GND6B/GND5 1 VCCIO7 NC1 11 7 CB23 108 VCCIO2 109 38 VCCIO5A GND7/GND0 144 36 VCCIO6B NC2 12 1 1 D 8 10K 10UF A B C D A B 5 4 8 RST_PRF ZSPISCK ZSPISCK HIERARCHY TCLKI TPOS RCLK 7 TE1_TCLK TE1_TPOS TE1_RCLK TE1_RPOS BLOCK RPOS _TE1LIU_WAN_DN 1 3 JP07 1 _zh11_dn 3 6 1 JP05 BLOCK NAME: 1 JP06 FPGA_SPICS ZMOSI ZMOSI FPGA_SPICS ZMISO ZMISO PAGES 24-25 LIU RST T1E1 IN IN IN REF_CLKO REF_CLKO OUT RST_ZCHIP RST_ZCHIP HIERARCHY PAGES 20-22 DS33ZH11 30 3 RB138 NC7SZ86_U BUFFER TE3_TCLK TE3_TPOS 30 1 RB129 30 5 TX_CLK PAGE 23 PARENT BLOCK: TCLK TPOS RCLK BLOCK 4 _mii_wan_dn \_ztopdn_\ HIERARCHY TX_EN _te3liu_wan_dn RPOS T3E3 BUFFER FOR DELAY 3 TE3_RCLK RB132 4UB06 TE3_RPOS _ds33zh11dk_design. JP08 30 LIU TXD3 ZH_TX_EN TXD3 ZH_TXD3 TXD2 TX_EN TXD2 ZH_TXD2 TXD1 ZH_TX_CLK TXD1 ZH_TXD1 TXD0 TX_CLK TXD0 ZH_TXD0 HIERARCHY 3 V3_3 GND V3_3 3 JP11 30 R21 1 V3_3 5 8 Fri OUT VCC 2 Sep 23 GND 1 11:01:54 OSC YB04 REF_CLKO SCULLY PRINTED STEVE 1 4 1 01/05/2005 2005 1 18/27(TOTAL) PAGE: 1/2(BLOCK) DATE: NOT THE CURRENT BLOCK) 25.000MHZ_3.3V DESIGN, 2 DS33ZH11-R11DK01A0 2 JMP_3 LED_RX_A4 LED_TX_A3 ENGINEER: TITLE: PHY_CLK LED_RX_ADD4 LED_TX_ADD3 LED_GDLINK_A2 LED_COL_A1 LED_COL_ADD1 LED_GDLINK_ADD2 LED_DPLX_A0 BLOCK LED_DPLX_ADD0 PAGES 26-27 ETHERNET KIT MII COL_DET RXDV RX_ERR ZH_RX_ERR RX_ERR ZH_RXDV RX_CRS ZH_RX_CRS RX_CRS RXDV RX_CLK RXD3 RXD3 RXD2 ZH_RXD2 RXD2 ZH_RX_CLK RXD1 ZH_RXD1 RXD1 RX_CLK RXD0 ZH_RXD0 RXD0 ZH_RXD3 BLOCK DESIGN MDIO DS33ZH11 MDC C 6 MII_CLK D 7 NOTES: ALL HIERARCHY BLOCK NAMES END IN _DN. PINS ON HIERARCHY BLOCKS DO NOT HAVE PIN NUMBERS (BUT PINS ON SYMBOLS DO). SIGNALS INSIDE A HIERARCHY BLOCK ARE LOCAL TO THAT BLOCK - THE SIGNAL TEMP IN BLOCK_A_DN IS DIFFERENT THAN TEMP IN BLOCK_B_DN. PAGE NUMBERS (BOTTOM RIGHT) ARE LISTED BY BOTH THE PAGE NUMBER IN THE BLOCK, AND BY THE PAGE NUMBER WITHIN THE ENTIRE DESIGN CROSS REFERENCE INDICATORS ARE REFERENCEING A GIVEN NET TO OTHER PAGES IN THE DESIGN (PAGE NUMBER GIVEN IS ACCORDING TO ENTIRE 8 TSER RB101 ZH_TSER 2 TCLKI ZH_TCLKI 2 RSER ZH_RSER 2 RESET RST_PRF RCLKI ZH_RCLKI 2 3 1 A B C D A 8 470UF I35 C34 SW02 4 1 3 0.1UF U15 RESET* 2 4 RST_ZCHIP V3_3 C35 7 BLOCK NAME: 6 1 2.0K 1 2 CB192 1 10UF CB167 RST_PRF 1 V3_3 _ds33zh11dk_design. FOR RB178 C27 4.7UF CB166 4.7UF CB173 4.7UF CB174 4.7UF CB183 4.7UF DS33ZH11 MII CLK IS GATED BY RESET MII PHY REQUIRES MII CLK TO BE STABLE 160 US BEFORE RESET DEACTIVATES GND MR* MAX811_U VCC CB158 4.7UF CB156 4.7UF CB182 4.7UF C25 4.7UF I34 SOT143 2.93V MAX811SEUS-T 1 1 1 1 2 1 1 0.1UF CB196 1 2 1 0.1UF CB191 1 2 1 1 0.1UF CB152 1 2 B 0.1UF CB176 1 2 C 0.1UF CB186 1 2 6 10UF C33 7 10UF CB172 CB194 D 8 10UF CB164 1 1 5 10UF 5 PARENT BLOCK: 4 \_ztopdn_\ 4 3 3 LED_RX_A4 STEVE SCULLY 2 1 1 2 1 RB176 330 1 RB174 RED Fri 330 RB169 1 RB168 AMBER 1 330 5.1K RB173 1 GREEN 2 1 RB175 5.1K 5.1K 2 DS19 I20 1 DS20 330 5.1K 1 RB165 RB164 1 330 AMBER DS21 I15 1 I18 1 1 2 DS18 PRINTED LED_TX_A3 LED_GDLINK_A2 1 RB158 1 I8 5.1K 1 AMBER RB157 I11 LED_COL_A11 DS33ZH11-R11DK01A0 ENGINEER: TITLE: LED_DPLX_A0 2 2 DS16 0.1UF 1 1 10UF CB165 Sep 01/05/2005 23 11:01:54 1 2005 19/27(TOTAL) PAGE: 2/2(BLOCK) DATE: V3_3 1 A B C D A B C K10 K3 F4 G3 SD_CLKI SD_RAS SD_CAS SD_WE 7 6 OUT OUT OUT OUT IN BLOCK NAME: 6 IN OUT ZSPISCK ZMISO ZMOSI _zh11_dn. DS33ZH11_U1 U11 5 PARENT BLOCK: 5 FUT_A0 8 TXD3 TXD2 TXD1 TXD0 UNMARKED RESISTORS ON THIS PAGE ARE 30 OHM SWE* SCAS* SRAS* SYSCLKI SDCLKO SDCS* SDMASK SDMASK SDMASK OMITTED H3 J3 SD_CLKO C5 SD_DQM3 SD_CS J6 SDA K4 11 E3 SDA H5 10 SD_DQM2 SDA F5 9 SD_DQM1 SDA F8 SDMASK SDA G4 7 8 F3 SDA SD_DQM0 SDA SDA C4 4 H4 SDA F9 3 G5 SDA H6 6 SDA K5 1 2 5 SDA J5 MII TX PINS USUALY HAVE SERIES TERMINATION ZH11 PACKAGE ALLOWS FOR CLOSE PLACEMENT, RESISTORS SD_A SBA J4 SD_BA1 SBA F7 SD_BA0 0 IN D9 RXD A8 TXD D 7 IN D10 RXD TXD 8 IN C9 RXD B7 JMP_3 IN C10 RXD IN A10 RX_DV TX_CLK A6 TXD B8 IN B10 RX_CLK TX_EN B6 TXD A9 IN C8 D/MOSI RX_CRS/CRS_DV G10 E8 B9 TX_CLK IN SPI_CS* B5 RX_ERR TX_EN IN RST* C1 RB133 OUT HWMODE A3 REF_CLKO D/MISO B2 RCLKI D/SPICK IN B3 RSER MODEC A4 MODEC1 HWMODE RST_ZCHIP ZSPICS IN E9 A7 0VDD3.3 V3_3 4 A0) VSS0 (FUTURE A5 IN B1 TCLKI E10 D4 1VDD3.3 A2) VSS1 (FUTURE D6 3VDD3.3 VSS2 B4 A1) \_ds33zh11dk_design\ (FUTURE A2 TSER D5 2VDD3.3 FUT_A1 E4 D7 4VDD3.3 VSS3 E5 H10 5VDD3.3 VSS4 E6 D8 6VDD3.3 VSS5 F6 0VDD1.8 SDATA 31 E7 H2 C6 F10 1VDD1.8 SDATA 30 G6 J10 2VDD1.8 SDATA G8 29 3VDD1.8 SDATA A1 4VDD1.8 SDATA G9 RXD3 RXD2 RXD1 RXD0 C7 RX_CRS RX_ERR RX_CLK RXDV 28 REF_CLKO 4 27 TSER RSER TCLKI RCLKI FUT_A2 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 E2 C2 F1 G1 D1 D2 E1 K6 G7 J7 K8 K7 J8 H7 K9 J9 H8 SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA SDATA 26 9 10 D3 SDATA H9 7 8 C3 SDATA SDATA 6 SDATA 5 K1 SDATA K2 3 4 G2 SDATA J2 1 2 J1 SDATA SDATA 0 H1 F2 SDATA V1_8LVREG 3 3 OF DS33ZH11 STEVE SCULLY 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: BEGINING SD_DQ 2 HIERARCHY BLOCK 01/05/2005 1 20/27(TOTAL) PAGE: 1/3(BLOCK) DATE: 1 A B C D A B IN 2 1UF CB197 CB153 1 8 IN 3 1 1 1 4 3 2 CS* 1 V3_3 SCK 6 ZSPISCK Y04 2.7V SHDN RST IN IN 7 GND SET OUT OUT UB07 MAX1792 5 6 7 8 GND HOLD* WP* VCC AT25160A_U SO 2 JMP_3 SI 5 ZMISO ZMOSI JPB01 IN 1UF 2 FPGA_SPICS 1UF CB195 OUT C30 ZSPICS 2 1 1 2 1 10K RB100 6 1 V3_3 BLOCK NAME: 4 7 3 8 RB99 CB157 C 1UF 1 1 2 1 2 10K 10UF _zh11_dn. CB193 D 10UF 6 V1_8LVREG 5 CB160 CB159 4.7UF PARENT BLOCK: 5 4.7UF 7 4.7UF 8 CB154 .1UF \_ds33zh11dk_design\ 4 1 2.0K 1 V3_3 2.0K RB98 2.0K RB97 R15 V3_3 FOR Z11 RB102 2.0K RB104 2.0K RB116 MODEC1 LOW SWITCHES FUT_A2 5 8 HWMODE OUT VCC LOW FUT_A1 J27 1 J26 GND 1 OSC YB03 100.000MHZ_3.3V FUT_A0 2 2 CONFIG 4 1 4 JMP_2 CB161 JMP_2 CB155 4.7UF 3 V3_3 3 SD_CLKI STEVE SCULLY 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: 30 2 PAGE: DATE: 01/05/2005 1 2/3(BLOCK) 21/27(TOTAL) 1 A B C D A B 8 7 DQ DQ DQ 51 53 28 29 VDD3 VDD4 0 - VSS4 _zh11_dn. 1 MEG X 32 VSSQ8 VSS2 VSS3 X 4 BANKS PARENT BLOCK: 5 4 SD_DQM1 SD_DQM2 SD_DQM3 SD_BA0 SD_BA1 28 59 22 23 DQM DQM BA BA 1 2 3 4 5 6 7 8 9 10 11 26 27 60 61 62 63 64 65 66 24 21 A A A A A A A A A A A \_ds33zh11dk_design\ 0 25 A 2 3 ENGINEER: TITLE: STEVE SCULLY 2 DS33ZH11-R11DK01A0 APPEAR THAT THEY SHOULD V3_3 SYSCLKO 3 SWAPABLE SD_A BE NON- ADDRESS PINS SD_DQM0 19 RAS* 16 SD_RAS 18 CAS* 71 SD_CAS 17 WE* DQM SD_WE 20 CS* DQM SD_CS 67 FROM Z11 SD_CLKO 68 CKE 4 CLK V3_3 SYNCHRONOUS DRAM DQ MT48LC4M32B2 VSSQ7 1 6 VDDQ8 MT48LC4M32B2_TSOP_U UB05 VDDQ7 4 2 BLOCK NAME: DQ 50 DQ 37 20 27 DQ 36 19 26 DQ 34 18 48 DQ 33 17 DQ DQ 31 16 47 DQ 85 15 25 DQ 83 14 DQ DQ 82 13 45 DQ 80 12 24 DQ 79 11 DQ DQ 77 10 42 DQ 76 9 23 DQ 74 8 DQ DQ 13 7 DQ DQ 11 6 39 DQ 10 5 40 DQ 8 4 22 DQ 7 3 21 DQ 5 2 VDDQ6 VSSQ6 SD_DQ VDD2 5 VDDQ5 VSSQ5 6 VDDQ4 VSSQ4 C 7 VSSQ3 D 8 VSSQ2 DQ DQ VDDQ3 43 29 15 1 VDD1 VSS1 86 72 58 44 DQ 31 54 56 30 VDDQ2 81 75 55 49 41 35 9 3 VDDQ1 VSSQ1 84 78 52 46 38 32 12 6 01/05/2005 1 22/27(TOTAL) PAGE: 3/3(BLOCK) DATE: 1 A B C D A B C 4 1 35 RPOS 34 33 44 RX_MINUS RCLK 42 17 RX_PLUS 10K RB150 18 TCLK TPOS 16 11 TX_MINUS GND 1 8 OUT VCC 34.368MHZ_3.3V OSC Y05 5 8 SPARE (SOCKETED) OSCILLATOR USE 44.736 MHZ FOR T3 USE 34.368 MHZ FOR E3 OUT OUT IN OUT 9 TX_PLUS VSS 3 VSS 1 4 1 RNEG OUT 7 YB01 44.736MHZ_3.3V GND 1 5 8 VSS 4 VCC VSS 7 6 2 _te3liu_wan_dn. JP09 JMP_3 DS3150T BLOCK NAME: V3_3 VSS 12 OSC VSS 14 U13 VDD VSS 19 38 VDD VSS 23 37 VSS 24 RPOS/RNRZ RCLK RX- RX+ TNEG MCLK 26 MCLK V3_3 RCLK 5 ZCSE* TTS* TESS RMON LBKS* ICE EFE RMON TESS TTS ZCSE 28 15 22 27 2 2 PRBS 2 LOS DM 1 3 BEGINING RECEIVE V3_3 RXRING RXTIP 6 4 6 TXRING 1:2 1.0K 1.0K 1.0K 1.0K 1.0K T03 PE-65968 1:2 T02 PE-65968 4 GRN 1 330 3 Thu SCULLY PRINTED STEVE 2 Sep AND END OF T3E3 DS33ZH11-R11DK01A0 ENGINEER: TITLE: 1.0K 1.0K 1.0K 1.0K RB135 J39 4 1.0K 330 RB142 1 CONN_BNC_5P OHM RA 1 GREEN 1 330 RB146 75 TRANSMIT J38 1 V3_3 OHM (1%) 19 17 15 13 11 9 7 5 3 1 1 20 18 16 14 12 10 8 6 4 2 01/05/2005 V3_3 1 1/1(BLOCK) 23/27(TOTAL) PAGE: DATE: 2005 20 18 16 14 12 10 8 6 4 2 BLOCK CONN_20P 19 17 15 13 11 9 7 5 3 1 J28 RX_PLUS RX_MINUS TX_MINUS TX_PLUS HIERARCHY ZCSE TTS TESS TDS1 TDS0 RMON LBKS LBO ICE EFE 16:21:49 LIU RB118 RB119 RB125 RB120 RB121 RB122 RB123 RB124 RB126 RB127 22 2 3 1 2 3 NETWORK INTERFACE TXTIP OHM RA CONN_BNC_5P 75 2 RED DS12 RED DS13 RED RED DS14 \_ds33zh11dk_design\ ICE LBKS EFE 43 10 TDS1 2 40 TDS0 46 PARENT BLOCK: TCLK MCLK 4 NOTE: CENTER TAP OF T02 WAS NOT PULLED TO V3_3 IN DS33RZH11DK01A0 REVISION. PIN T02.2 IS PULLED TO V3_3 WITH A WIRE IN THE DS33RZH11DK01A0 REVISION TDSO 5 TDSI/OFSEL VSS 6 VSS 36 21 VDD VSS 25 DM 41 39LOS LOS* VSS 45 8 DM* VSS 47 20 VDD VSS 30 13LBO LBO 29PRBS PRBS VSS 48 6 VDD VSS 31 TPOS/TNRZ TCLK TX- TX+ 7 CB181 CB185 D 8 5 4 3 2 2 3 4 5 5 VDD VSS 32 3 1 .1UF .1UF 330 R22 330 OHM (1%) 330 R20 330 A B C D A B 8 7 1 TRING RRING RTIP 1 TTIP 1 0.0 R17 1 0.0 R16 1 0L_SMT0603_20PCT 0603YC104MAT 2 2 1 2 1 1 1 6 0.0 R18 1 0.0 R19 1 1UF CB180 BLOCK NAME: .1UF C DS21348 CB177 2 2 14 15 16 11 10 9 _te1liu_wan_dn. 1 LIU, T01 5 6 7 8 T01 1:0.8 1:1 1:1 1:0.8 1 4 3 2 1 5 PARENT BLOCK: 51.1 4 3 2 B D F H J40 A C E G JB03 J41 \_ds33zh11dk_design\ 4 1 CONN_BNC_5PIN CONN_RJ48 2 4 6 8 1 1 3 5 7 CONN_BNC_5PIN 3 OF T1E1 LIU STEVE SCULLY 2 DS33ZH11-R11DK01A0 ENGINEER: TITLE: BEGINING HIERARCHY TRANSFORMERS AND CONNECTORS 5 2 D 2 6 RB177 7 1 2 1 2 61.9 2 61.9 RB149 1 8 RB148 / BLOCK 01/05/2005 1 24/27(TOTAL) PAGE: 1/2(BLOCK) DATE: 1 A B C D A B 4 1 8 OSC YB02 GND 1 1.0K OUT VCC V3_3 5 8 7 CLK1544 JMP_3 TCLKI RCLK 6 39 40 RNEG 41 TPOS 2 37 TTIP RTIP TCLK TNEG TPOS TRING TTIP INT* RCLK RNEG RPOS AD2_LOOP1 DS21348 A1_JAS A0_HBE L1 L2 RRING AD1_MM0 L2 L1 L1, _te1liu_wan_dn. 43 42 34 TRING 23 38 RPOS BLOCK NAME: MCLK JP10 RCLK MCLK OUT IN RT1 OUT 28 AD3_LOOP0 OUT 27 RTIP RRING A2_JAMUX U12 A4_LO 1.0K RB141 1.544MHZ_3.3V BIS1 AD4_TX1 C HARDWARE AD5_TX0 6 5 AD0_MM1 HBE JAS JAMUX DJA LO A3_DJA 11 10 9 8 7 AD6_TPD RB139 L2, RCL_LOTC PBEO VSM HRST* WR* RD* CS* V3_3 4 30 MCLK PBTS 44 31 ALE RLOS_LIU 4 25 GND 1 4 OSC YB05 OUT VCC \_ds33zh11dk_design\ 4 1 1 8 5 2.048MHZ_3.3V 330 RB156 2 1 2 LIU 3 STEVE SCULLY 2 OHM PBTS TEST CES TPD TX0 TX1 19 17 15 13 11 9 7 5 3 1 19 17 15 13 11 9 7 5 3 1 9 7 5 3 1 BLOCK LOOP0 LOOP1 MM0 MM1 HBE JAS JAMUX DJA LO VSM ALE WR_NRZ RD_ETS CS_EGL RT1 L2 L1 HIERARCHY 1.0K 1.0K RB103 1.0K RB115 1.0K RB117 1.0K RB128 1.0K RB130 1.0K RB131 1.0K RB134 1.0K RB136 1.0K RB140 RB143 1.0K 1.0K RB114 1.0K RB113 1.0K RB112 1.0K RB111 1.0K RB110 1.0K RB109 DS33ZH11-R11DK01A0 ENGINEER: TITLE: END OF T1E1 DS15 1 VSM 20 24 RST 1.0K RB108 1.0K RB106 1.0K RB107 WR_NRZ 3 29 RB105 1.0K 1.0K RB170 1.0K RB166 RB163 RD_ETS IN 2 ARE 1.0K CS_EGL RED RESISTORS 1 1 UNMARKED BIAS 3 2 SPARE (SOCKETED) OSCILLATOR USE 1.544MHZ FOR T1 USE 2.048MHZ FOR E1 MCLK BPCLK PBTS_RT0 ALE_SCLKE BPCLK = NC PARENT BLOCK: 5 PBEO, BIS0 BIS0 V3_3 5 CONFIGURED FOR HW MODE 6 BIS1 7 3 1 VDD D 8 AD7_CES 19 18 17 16 15 14 13 12 MM1 MM0 LOOP1 LOOP0 TX1 TX0 TPD CES VSS 32 BIS0 33 BIS1 TEST TEST 26 VDD1 21 36 VSS1 22 35 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2 10 8 6 4 2 01/05/2005 V3_3 1 25/27(TOTAL) PAGE: 2/2(BLOCK) DATE: CONN_20P 19 17 15 13 11 9 7 5 3 1 J31 CONN_20P 19 17 15 13 11 9 7 5 3 1 J29 CONN_10P 9 7 5 3 1 J36 1 A B C D A B C 2 CB179 1 10UF 8 V3_3 2 CB178 1 0.1UF OUT OUT OUT OUT IN IN 9 7 5 3 1 10 8 6 4 2 CONN_10P 9 7 5 3 1 CONTROL U14 DP83847_U1 RESERVED5 RESERVED14 RESERVED4 RESERVED13 RXDV RX_CRS COL_DET RX_ERR RX_CLK 2 10 8 6 4 VDD/IO_VDD1 OUT OUT OUT OUT OUT V3_3 IN OUT MDC MDC IN MDIO IO 17 16 15 AN_EN AN_1 AN_0 TX_EN TX_CLK 9 7 5 3 10 8 6 4 CONN_10P 9 7 5 3 1 2 18 LED_SPEED 1 19 J30 20 LED_TX/PHYAD3 LED_RX/PHYAD4 10 8 6 4 2 TXD1 TXD0 TXD3 TXD2 AN0 AN1 IN IN IN IN 1 1 BLOCK NAME: _mii_wan_dn. 6 1 V3_3 4 V3_3 2 2 CB169 1 10UF 10UF 2 CB170 1 1 AN_V3_3 1 ANALOG SUPPLY CAPS TO BE PLACED CLOSE TO PIN 14 OF PHY 3 STEVE SCULLY 2 PRINTED DS33ZH11-R11DK01A0 ENGINEER: TITLE: 01/05/2005 Fri Jun 30 02:47:52 2006 1 1/2(BLOCK) 26/27(TOTAL) PAGE: DATE: BEGINNING OF MII ETHERNET HIERARCHY BLOCK LEDS NEED TO BE ATTACHED OUTSIDE OF MODULE DUE TO STRAP ADAPTING OPTION OF DP83847 PARENT BLOCK: \_ds33zh11dk_design\ 5 ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE 7 J352 J342 IO IO IO IO IO JMP_2 RB161 LED_SPEED 1 2 330 JMP_2 AMBER DS17 RB145 J32 1 2 AN_ENJMP_2 5.1K RB160 5.1K RB147 5.1K LED_TX_ADD3 LED_RX_ADD4 21 LED_GDLINK_ADD2 LED_COL_ADD1 22 LED_GDLNK/PHYAD2 LED_DPLX_ADD0 23 30 LED_COL/PHYAD1 24 25 RB162 LED_DPLX/PHYAD0 MDIO PLACEMENT NOTE: TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW 0.2 BETWEEN CONNECTORS. RXD2 RXD3 RXD0 RXD1 RESERVED11 J33 RESERVED10 47 X2 44 48 TPB10 RESET* 46 RBIAS 49TPB11 X1 3 MII_CLK RBIAS C1 RESERVED1 RESET RB167 10.0K 42 1 RESERVED2 RESERVED6 RESERVED15 RESERVED3 RESERVED12 RESERVED7 AN_V3_3 28 56 14 VDD/IO_VDD2 4 5 8 9 12 13 34 RESERVED16 COMPONETS FOR C1 AND RBIAS MUST BE PLACED CLOSE TO PIN 2 C1PIN GND2 RESERVED8 RESERVED17 VDD1 GND3 RESERVED9 RESERVED18 50 51 52 53 54 55 61 GND4 VDD/ANA_VDD GND1 VDD2 57 59 63 VDD3 GND5 58 60 62 64 65 D 0.1UF 2 CB171 1 3 0.1UF 2 CB168 1 0.1UF 2 C29 1 0.1UF 4 0.1UF 2 C32 1 2 C26 5 0.1UF CB163 10UF C31 6 CB188 2 1 10UF 2 CB184 1 7 0.1UF CB187 2 1 0.1UF 8 1 A B C D A B C D 8 RD_P RD_N RXD0 RXD1 RXD2 RXD3 8 RB151 RB159 RB152 30 30 30 RD+ RD- 6 7 RXD RXD RXD 7 26 27 29 RXD TXD 41 30 TXD 40 30 TXD 39 RB153 TXD 38 TXD0 TXD1 TXD2 TXD3 TX_EN 37 TX_ER TX_EN 35 11 10 43 45 36 32 31 33 6 6 30 30 30 30 TD_P TD_N RB155 RB154 RB137 RB144 RXDV RX_ERR RX_CRS COL_DET RX_CLK TX_CLK BLOCK NAME: _mii_wan_dn. TD- TD+ COL CRS/LED_CFG* TX_CLK RX_CLK RX_DV RX_ER/PAUSE_EN* PORT DP83847_U1 U14 7 4 4 PARENT BLOCK: \_ds33zh11dk_design\ 5 5 3 RB172 54.9 RB171 54.9 TD_N TD_P RD_N RD_P .1UF CB190 P4 P2 P3 P5 P6 4 2 3 5 6 8 J37 SYM_1 SH2 J7,8 J4,5 J6 J3 J2 J1 SH1 1 CONN_HFJ11_2450_U P8 P1 1 2 10 9 ENGINEER: STEVE SCULLY 2 DS33ZH11-R11DK01A0 01/05/2005 1 27/27(TOTAL) PAGE: 2/2(BLOCK) DATE: END OF MII ETHERNET HIERARCHY BLOCK RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY CAPS FOR XFRM CENTER TAP SHOULD BE PLACED CLOSE TO XFRM R23 49.9 R24 49.9 TITLE: V3_3 .1UF CB189 3 CB162 .1UF A B C D