Rev: 031008
DS33X162 Demo Kit
Features
General Description
The DS33X162 demo kit (DK) is an easy-to-use
evaluation board for the DS33X162 Ethernet-overPDH device. The demo kit contains an option for
either T3/E3 or T1/E1 serial links. All serial links are
complete with line interface, transformers, and
network connections. Maxim’s ChipView software is
provided with the demo kit, giving point-and-click
access to configuration and status registers from a
Windows®-based_PC.
On-board LEDs indicate receive loss-of-signal, queue
overflow, Ethernet link, Tx/Rx, and interrupt status.
♦
Demonstrates Key Functions of DS33X162
Ethernet Transport Chipset
♦
Includes DS26528 T1/E1 Transceiver, DS3174
T3/E3 Transceiver, Transformers, BNC, and
RJ48 Network Connectors and Termination
♦
Includes Ethernet PHY Supporting 10/100 and
Gigabit Modes
♦
Provides Support for Hardware and Software
Modes
♦
On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
the DS33X162, DS26528, DS3174, and PHY
Registers
♦
All DS33X162 Interface Pins are Easily
Accessible for External Data Source/Sink
♦
LEDs for Loss-of-Signal, Ethernet Link, Tx/Rx,
and Interrupt Status
♦
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
Windows is a registered trademark of Microsoft Corp.
Ordering Information
PART
DS33X162DK
TYPE
Demo card, T3/E3, T1/E1
Demo Kit Board
Demo Kit Contents
DS33X162DK Main Board
Dual-Port 10/100Mb Ethernet Card
Single-Port 10/100/1000Mb Ethernet Card
5V 2.5A Power Supply
USB Cable, RS232 Cable
T3/E3 BNC-to-2-Pin Adapter
CD-ROM
ChipView Software and Manual
DS33X162DK Data Sheet
Configuration Files
Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
________________________________________________________________ DS33X162DK
Table of Contents
1.
SYSTEM FLOORPLAN ......................................................................................................4
2.
PCB ERRATA.....................................................................................................................5
3.
FILE LOCATIONS ..............................................................................................................5
4.
BASIC OPERATION...........................................................................................................7
4.1
POWERING UP THE DEMO KIT ..........................................................................................................7
4.1.1
4.2
4.2.1
4.3
General .................................................................................................................................................. 7
BASIC DS33X162 INITIALIZATION ....................................................................................................7
Additional Configuration for DS33X162 ................................................................................................. 8
MONITOR AND CAPTURE ETHERNET TRAFFIC ...................................................................................8
5.
LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS .......................9
6.
REGISTER ACCESS........................................................................................................14
6.1
6.2
6.3
6.4
7.
ADDRESS MAP ..............................................................................................................................14
CONTROL THROUGH EXTERNAL PROCESSOR .................................................................................14
SPI MODE .................................................................................................................................... 14
MAC AND PHY REGISTERS ...........................................................................................................14
ADDITIONAL INFORMATION/RESOURCES ..................................................................15
7.1
7.2
7.3
DS33X162 INFORMATION .............................................................................................................15
DS33X162DK INFORMATION ........................................................................................................15
TECHNICAL SUPPORT ....................................................................................................................15
8.
COMPONENT LIST ..........................................................................................................16
9.
SCHEMATICS ..................................................................................................................23
Rev: 031008
2 of 78
________________________________________________________________ DS33X162DK
List of Figures
Figure 1-1. DS33X162 System Floorplan.................................................................................................................... 4
Figure 1-2. DS33X162DK Board Floorplan—Main Board ........................................................................................... 4
List of Tables
Table 3-1. File Details.................................................................................................................................................. 5
Table 5-1. Main Board PCB Configuration .................................................................................................................. 9
Table 5-2. Dual-Port PHY Card Configuration........................................................................................................... 12
Table 5-3. Single-Port PHY Card Configuration ........................................................................................................ 13
Table 6-1. Overview of Daughter Card Address Map................................................................................................ 14
Table 8-1. Component List ........................................................................................................................................ 16
Rev: 031008
3 of 78
________________________________________________________________ DS33X162DK
1.
System Floorplan
Figure 1-1. DS33X162 System Floorplan
DUAL 10/100 PHY CARD
10/100
MAGNETICS
10/100
MAGNETICS
DP83848
DP83848
SINGLE 10/100/1000 PHY CARD
10/100/1000
MAGNETICS
DP83865
PHY CONFIG, TEST POINTS
PHY CONFIG, TEST POINTS
PHY CONNECTOR
PHY CONNECTOR
Figure 1-2. DS33X162DK Board Floorplan—Main Board
PHY CONNECTOR
POWER
(5V)
DRIVER
CONFIGURATION
DS33X162
DDR
FET SWITCH + TEST POINTS
SPI CONFIG
JUMPERS
USB
SERIAL PORT
(57600-8-N-1)
ETHERNET AND
CLOCK SELECT
JUMPERS
DS26528 T1/E1
TRANSFORMER AND NETWORK
CONNECTIONS (T1/E1)
MICROPROCESSOR
LEDs
DS26528 T1/E1
TRANSFORMER AND NETWORK
CONNECTIONS (T1/E1)
Rev: 031008
TEST POINTS
DS3174 T3/E3
DS3174 T3/E3
TRANSFORMER AND NETWORK
CONNECTIONS (T3/E3)
TRANSFORMER AND NETWORK
CONNECTIONS (T3/E3)
4 of 78
________________________________________________________________ DS33X162DK
2.
PCB Errata
DS33X162DK02A0 board errata:
• There are no errata associated with the DS33X162DK02A0.
3.
File Locations
This demo kit relies upon several supporting files, which are provided on the CD-ROM and are available as a zip
file from the Maxim website at www.maxim-ic.com/DS33X162DK.
All locations are given relative to the top directory of the CD-ROM/zip file DS33X162_cfg_demo_gui. The
DS33X162, DS3174, and DS26528 register definition files and configuration files are listed in Table 3-1.
Table 3-1. File Details
FILE NAME
. \_DS33X162_GlobalMicroport.def
.\DS33X162_Lan.def
.\DS33X162_BufferMan.def
.\DS33X162_EncapDecap.def
.\DS33X162_Vcat.def
.\DS33X162_SerialPort.def
.\DS33X162_lan_T3wan_ext.mfg
.\DS33X162_lan_T1wan_ext.mfg
.\x162_wan1.eset
.\te3_ds3174\DK_ports*\ds3174_evbrd.def
Note that there are two folders: DK_ports_4to1_CS4 and
DK_ports_8to5_CS3.
.\te3_ds3174\ DK_ports*\misc1_p1.def
.\te3_ds3174\ DK_ports*\feac_frac_p1.def
.\te3_ds3174\ DK_ports*\ttrace_p1.def
.\te3_ds3174\ DK_ports*\ds3_p1.def
.\te3_ds3174\ DK_ports*\e3751_p1.def
.\te3_ds3174\ DK_ports*\e3832_p1.def
.\te3_ds3174\ DK_ports*\port1.def
.\te3_ds3174\ DK_ports_8to5_CS5 \ t3_config_dlb.mfg
.\te3_ds3174\ DK_ports_8to5_CS5 \t3_config_AlignedSync_dlb.mfg
.\te3_ds3174\DK_ports_8to5_CS5\ds33x162_no_lb_vcat_ports_5to8_T3.mfg
.\te3_ds3174\DK_ports_4to1_CS4\t3_config_dlb.mfg
Rev: 031008
FILE USAGE
Top-level definition file to select in
ChipView’s register mode. This file
will autoload the remaining
definition files for the DS33X162.
(Note that the wan files still need to
be loaded (either DS).)
DS33X162 dependent files. These
are called by the
ds33x162_GlobalMicroport.def file
listed above.
File for manually configuring the
DS33X162 to interface with the
DS3174.
File for manually configuring the
DS33X162 to interface with the
DS26528.
GUI interface for loading settings
when running the Xchip plug-in
(launched from the Tools menu of
the ChipView program).
Top-level definition file to select the
DS3174 T3/E3 transceiver. This
file will autoload the remaining
definition files for the DS3174.
DS3174 dependent files. These
are called by the ds3174_evbrd.def
file listed above. Files for port 1 are
shown; other ports are not listed
here.
DS3174 configuration file for T3
mode.
DS3174 configuration file for T3
mode. Aligns sync pulses by use of
bulk write feature.
DS33X162 configuration file for
vcat T3 mode.
DS3174 configuration file for T3
mode.
5 of 78
________________________________________________________________ DS33X162DK
FILE NAME
.\te3_ds3174\DK_ports_4to1_CS4\t3_config_AlignedSync_dlb.mfg
.\te3_ds3174\DK_ports_4to1_CS4\ds33x162_no_lb_vcat_ports_1to4_T3.mfg
.\ds26528\....\DS26528_GLOBAL_T1.def
Note that groups of definition files exist for both T1 and E1 modes and also
for ports 1 to 8 and ports 9 to 16. This results in a total of four file groups.
Only one group is shown here.
.\ds26528\...\DS26528_1_LIU_BERT.def
.\ds26528\....\DS26528_1_T1.def
.\ds26528\ DK_wan_8to1_CS2\T1\DS26528_t1_config.mfg
.\ds26528\ DK_wan_8to1_CS2\T1\ds26528…_t1_config_master_bulkWr.mfg
.\ds26528\ DK_wan_8to1_CS2\T1\ds33x162_no_lb_vcat_4ports.mfg
.\ds26528\ DK_wan_8to1_CS2\T1\ds33x162_16ports_vcg.mfg
.\ds26528\ DK_wan_8to1_CS2\disable_framer_lb.mfg
.\ds26528\ DK_wan_8to1_CS2\looptime.mfg
*.eset
.\ds26528\ DK_wan_8to1_CS2\E1\*.*
.\ds26528\ DK_wan_9to16_CS2\[E1 | T1]\*.*
Rev: 031008
FILE USAGE
DS3174 configuration file for T3
mode. Aligns sync pulses by use of
bulk write feature.
DS33X162 configuration file for
vcat T3 mode.
Top-level definition file to select the
DS26528 T1/E1 transceiver. This
file will autoload the remaining
definition files for the DS26528.
DS26528 dependent files. These
are called by
DS26528_GLOBAL_T1.def file
listed above. Files for port 1 are
shown; other ports are not listed
here.
DS26528 configuration file for T1
mode.
DS26528 configures all 8 ports
identically using bulk write mode.
Places device in master mode,
where TSYNC is an output.
DS33X162 configuration file for
vcat mode (ports 1 to 4).
DS33X162 configuration file for
vcat mode (ports 1 to 16).
DS26528 partial configuration files.
These files should be run after a
full configuration is made.
GUI interface for loading settings
when running the Xchip plug-in
(launched from the Tools menu of
the ChipView program).
Similar files exist for ports 1 to 8 E1
mode.
Similar files exist for ports 9 to 16
E1 and T1 mode.
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________________________________________________________________ DS33X162DK
4.
Basic Operation
Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items directly
from the demo kit (DK) software. Text in bold and underlined refers to items from the Windows operating system.
4.1
•
•
•
Powering Up the Demo Kit
Connect the PCB power jack to the wall adapter. A 2.5A supply is recommended.
Connect the RS232 serial cable or USB cable between the host PC and the demo kit.
Verify that the jumpers are configured as described in Table 5-1.
4.1.1 General
•
•
Upon power-up the power LEDs (DS01, DS02, DS03 green) will be lit. The DS3174 transceiver LEDs will
not be lit. The DS26528 transceiver RLOS + LTC LED will be lit if the device drivers are disabled.
PHY LINK LED should be lit if an Ethernet cable is connected.
Following are several basic system initializations.
4.2
Basic DS33X162 Initialization
This section covers three basic methods for configuring the DS33X162.
1) Device Driver-Based Configuration. If the pins J02.1+J02.2 are unjumpered, the device driver will auto
configure the DS33X162 upon power-up. This enables traffic to pass from the Ethernet port to the serial port.
Refer to the device driver documentation for further details. To load the GUI interface for the device drivers, go
to the ChipView register mode Tools menu and select Tools→Plugins→DS33XW Device Driver Demo.
2) Register-Based Configuration—Port 1 T1 Mode
a) Install jumper J02.1+J02.2 to disable device drivers, and then reset the board. Ensure that
J01.1+J01.2 is not installed.
b) Launch ChipView.exe and select Register View.
c) When prompted for a definition file, pick the file named _DS33X162_GlobalMicroport.def. Six
additional definition files will load.
d) Go to the File menu and select File→Definition File. When prompted, select
DK_wan_8to1_CS2\T1\DS26528_GLOBAL_T1.def.
e) Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted, select
the file named DS33X162_lan_T1wan_ext.mfg.
f)
3)
Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted, select
the file named DK_wan_8to1_CS2\T1\ds26528_t1_config.mfg.
Register-Based Configuration—Port 1 T3 Mode
a) Install jumper J02.1+J02.2 to disable device drivers, and then reset the board. Ensure that
J01.1+J01.2 is installed.
b) Launch ChipView.exe and select Register View.
c) When prompted for a definition file, pick the file named _DS33X161_GlobalMicroport.def. Six
additional definition files will load.
d) Go to the File menu and select File→Definition File. When prompted select ds3174_evbrd.def.
e) Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted,
select the file named DS33X162_lan_T3wan_ext.mfg.
f)
Rev: 031008
Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted,
select the file named DK_ports_4to1_CS4\t3_config_dlb.mfg.
7 of 78
________________________________________________________________ DS33X162DK
4.2.1 Additional Configuration for DS33X162
•
Using either a patch or crossover cable, connect the Ethernet connector to an ordinary PC or network test
equipment. This should cause the link LED to turn on.
•
Place a loopback connector at the T1/E1 network side; RLOS and LTC LEDs should go out.
•
At this point any packets sent to the DS33X162 are echoed back. Incoming packets (i.e., ping) should
cause the Activity LED to blink.
•
Note that ChipView.exe display settings can be changed using the Options→Settings menu.
4.3
Monitor and Capture Ethernet Traffic
•
Although ping is mentioned, it is not the recommended frame source for testing. The ping command goes
through the computer’s TCPIP stack and sometimes will not be sent out the PC’s network connector (i.e., if
the PC’s ARP cache is out of date). Additionally, ping requires two PCs, as a Windows PC with only one
adapter cannot ping itself (a local ping gets sent to “local host” instead of out the connector). However, ping
is still a valuable test once the prototyping stage is complete.
•
Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-limited
demo is available at www.tamos.com/products/commview.
•
Wireshark is an excellent (and free) packet capture utility. Download is available at www.wireshark.org.
•
Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This
allows for end-to-end testing using a single PC. When using two adapters the PC has a different IP
address for each adapter. Test equipment allows selection of either adapter. Operating -system-based
network traffic is sent out of the default adapter; usually this is the adapter that has recently had connection
to a live network.
Rev: 031008
8 of 78
________________________________________________________________ DS33X162DK
5.
LEDs, Configuration Switches, Jumpers, and Connectors
The DS33X162DK has several configuration switches, oscillators, and jumpers. Table 5-1 provides a description of
these signals, given in order of appearance on the PCB, from top to bottom and then left to right (with the board
held so that the RS232 and USB connectors are on the right-hand side of the board).
Table 5-1. Main Board PCB Configuration
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SCHEMATIC
PAGE
YB01
(bottom of PCB)
125MHz Oscillator
—
52
JB01, JB02
(bottom of PCB)
PHY/Ethernet
Interface
J01
Mode select for Ports
1 to 8
J02
Configuration.
All Jumpered.
Schematic page 53.
SW01
System Reset
—
DS01, DS02,
DS03
LED
ON
J03
USB
—
58
J04
RS232 DB9
Connector
—
58
J15
Power Jack
—
54
JP01
DS33X162 Pin
Jumper P2+3
53
JP02
DS33X162
Bias RMII
Jumpered
P1+2 (low)
JP03
DS33X162
Bias DCE
Jumpered
P1+2 (low)
JP08
PHY Clock In
Jumper
P2+3
Rev: 031008
DESCRIPTION
DS33X162 SysClock.
Connector and Test Points for PHY
Card Connector. A PHY card
Card Installed
88
(provided) should be installed in
this connector.
Install jumper to enable T3/E3
mode; remove jumper to set T1/E1
Not Installed
mode. This jumper controls FET
(set for T1/E1
53
switches U04 to UB20. There are a
mode)
total of 8 jumpers used for
controlling ports 1 to 8.
• P1+P2: Jumper to disable drivers (remove to enable drivers).
• P3+P4: Jumper to disable interrupt handlers (this jumper is only
valid when drivers are enabled).
• P5+P6: Jumper to set for SourceTime—WAN ports 1 to 8 TxClock
driven by oscillator. Remove to set for LoopTime—WAN TxClock
driven by RxClk. (This jumper is only valid when drivers are
enabled.)
• P7+P8: Jumper to set for SourceTime—WAN ports 9 to 16
TxClock driven by oscillator. Remove to set for LoopTime WAN
TxClock driven by RxClock. (This jumper is only valid when
drivers are enabled.)
54
52
System reset.
Power OK LEDs for 1.8V, 2.5V,
and 3.3V power supplies. All three
LEDs must be lit.
USB Interface. See folder marked
USBdrivers FT245 for drivers.
RS232 DB9 Connector. Operates
in ASCII mode at 57.6K,8,N,1.
System Power. Always connected
to 5V wall adapter (provided).
DS33X162 HIZ pin.
Jumper P1+2 for MII Mode. Jumper
P2+3 for RMII Mode. (RMII mode is
not available in this demo kit.)
Jumper P1+2 for DTE Mode.
Jumper P2+3 for DCE Mode. (This
demo kit does not support DCE
mode.)
PHY Clock Input. Set for P2+3 in
10/100 mode, driving PHY with
25MHz oscillator. Setting P2+1
drives with DS33X162 RefClk with
PHY 125MHz clock (1000Mb mode
only).
9 of 78
________________________________________________________________ DS33X162DK
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SCHEMATIC
PAGE
YB02
(Bottom of PCB)
25MHz Oscillator
—
52
YB02
PHY RefClk
25MHz
52
DS04, DS05,
DS06
Interrupt LED
—
44
DS08
Kit Status LED
Off
58
JP07,
JP09 to JP12
DS33X162
SPI Test Points
All Jumpered
P1+2
43
JP05
DS33X162
Bias SPI SWAP
Jumpered
P1+2
43
JP04, JP06
DS33X162
Bias SPI CPHA
Bias SPI CPOL
Both Jumpered
P1+2
43
J05, J06
Test Points
Not used
59
J09
JTAG
Not Used
60
J16
RJ45 T1E1
User option
63
DS09 to DS16
RLOS LED
—
69
J08
J07
J11
J10
RSYNC Test Points
RDATA Test Points
RGCLK Test Points
TDATA Test Points
—
—
—
—
45
45
45
45
J14
DS33X162 JTAG
Jumpered
P1+3
P7+9
53
JP13
DS26528 TCLK
Jumpered
P1+2
44
JP14
DS26528 TCLK
Jumpered
P1+2
44
Rev: 031008
DESCRIPTION
25MHz Oscillator. Used for PHY
clock in (MII+GMII). Used for
DS33X162 RefClk in MII mode.
PHY Reference Clock. Populated
with 25MHz clock in MII mode.
Interrupt LEDs for X162, T3. and
T1 Devices.
Kit Status LED. Currently not
assigned to any software function.
SPI Test Points for DS33X162.
Jumpers are installed to connect
the DS33X162 to the processor
Data port to the FPGA data pins.
Connecting pins 2+3 connects
DS33X162 to processor SPI port.
Processor default is to transfer
MSB first. Jumper P1+2 to match
this setting.
Processor default is to have normal
phase and idle high. See Section
6.3 for further SPI detail.
Address Data Bus Test Points. See
Section 6.2 regarding control by
external processor. Silkscreen for
these signals is provided a few
inches to the left of the signals.
JTAG connector for programming
Lattice FPGA
T1/E1 Connectors for Ports 9 to 16.
RLOS LED for DS26528 Ports 9 to
16.
Test Points for DS33X162 RSYNC.
Test Points for DS33X162 RDATA.
Test Points for DS33X162 RGCLK.
Test Points for DS33X162 TDATA.
JTAG for DS33X162, DS26528,
and DS3174. DS33X162 can be
isolated from DS26528 and
DS3174. Jumpers on P1+3 and
P7+9 prevent the devices from
entering JTAG mode.
DS26528 TCLK Selection for Ports
5 to 8. Jumper pins 1+2 to drive
TCLK with RefClk. Jumper pins
2+3 to drive TCLK with TCLK
oscillator.
DS26528 TCLK Selection for Ports
12 to 16. Jumper pins 1+2 to drive
TCLK with RefClk. Jumper pins
2+3 to drive TCLK with TCLK
oscillator.
10 of 78
________________________________________________________________ DS33X162DK
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SCHEMATIC
PAGE
DESCRIPTION
Join reference clocks on DS26528
ports 1 to 8 and ports 9 to 16. This
jumper should only be installed
when one of the DS26528 devices
is in slave mode, and can be a
source of bit errors if it is installed
with both devices in master mode.
Jumpered such that all DS26528
ports receive the same TSYNC.
Test Points for DS26528 TGCLK.
Test Points for DS3174 TGCLK.
Test Points for DS3174 TSOFO.
Oscillator for T3/E3 MCLK.
Silkscreen and target are provided
on topside of PCB.
Oscillator for T3/E3 TCLK.
Silkscreen and target are provided
on top side of PCB.
J19
Join DS26528
REFCLKs
Not Jumpered
44
J13
J18
J8, J7, J3, J4
J17, J9
J20, J12
DS26528 TSYNC
DS26528 TSYNC
DS26528 TGCLK
DS3174 TGCLK
DS3174 TSOFO
Jumpered
Jumpered
Not Jumpered
Not Jumpered
Not Jumpered
76
68
68, 76
81,86
81, 86
YB05
Oscillator
—
46
YB06
Oscillator
—
46
RLOS LED
—
69
RLOS led for DS26528 ports 1-8
RJ45 T1E1
User option
63
T1E1 connectors for ports 9-16
LED
User setting
(OFF)
J26 to J41
WAN Network
Connection
—
J42
OnCe
Not used
J25
Flash VPP
Not used
DS22, DS27,
DS29, DS31,
DS23, DS28,
DS30, DS32
J24
DS17,
DS18,DS26,
DS20, DS24,
DS19, DS25,
DS21
Rev: 031008
DS3174 General-Purpose I/O LED.
Not configured by ini files.
80, 85
T3/E3 Jumpers for Network
Interface. Used with 2-pin coax
adapter (provided).
OnCe debug connector for
MMC2107 microcontroller.
For programming flash memory.
11 of 78
________________________________________________________________ DS33X162DK
Table 5-2. Dual-Port PHY Card Configuration
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SCHEMATIC
PAGE
J91, J92
Ethernet Connection
—
109, 111
RJ45 Ethernet Connector. Used in
10/100 modes.
DS65, DS63
DS64, DS66
LED Link
1 of each pair
should be lit
(when linked)
109, 111
LED to Indicate Link.
LED Speed
—
109, 111
LED Activity
—
109, 111
DS67,DS68,
DS70, DS69
DS74, DS72,
DS73, DS71
JP68 JP67
JP69, JP70
JP71, JP72
PHY CONFIG
Lit for 100Mb; off when in 10Mb
mode.
Blinks when a packet is transmitted
or received
FORCED MODE
AN_EN
AN1
AN0
0
0
0
10BASE-T, Half-Duplex
0
0
1
10BASE-T, Full-Duplex
0
1
0
100BASE-T, Half-Duplex
0
1
1
100BASE-T, Full-Duplex
1
0
0
10BASE-T, Half-/Full-Duplex
1
0
1
10BASE SE-Tx, Half-/Full-Duplex
1
1
0
100BASE-T , Half-Full Duplex
1
1
1
JP73, JP75
RMII
Jumpered
P1+2
JP74, JP76
MDIX
Jumpered
P2+3
Rev: 031008
DESCRIPTION
100BASE-T, Half-Full Duplex
Jumper Pins 1+2 for MII Mode.
When in RMII mode, the PHY
109, 111
RefClk must be 50MHz. This clock
is sourced from YB02 on the main
board.
109, 111
Jumper pins 2+3 to enable MDIX.
12 of 78
________________________________________________________________ DS33X162DK
Table 5-3. Single-Port PHY Card Configuration
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SCHEMATIC
PAGE
DESCRIPTION
RJ45 Ethernet Connector. Used in
10/100 and Gigabit modes.
DS75
LED Duplex
—
LED is on in full-duplex mode.
Jumper
Jumper P2+3 to enable IEEEJP77
Bias PHY Non-IEEE
P2+3 (high)
compliant operation.
Default MDIX setting P1+2 PHY is
Jumper
JP78
Bias PHY ManMDIX
set to straight mode; P2+3 PHY is
P1+2 (high)
in crossover mode.
DS76
LED Activity
—
Flashes for PHY Tx-Rx activity.
LED to indicate link speed: 1000,
100, or 10Mbps. Only 1 of the 6
DS78+79
1 of the 6
DS80+81
LED Link Speed
should be lit
LEDs should be lit. See JP15 +
DS82+83
(when linked)
JP101 description for setting in
GMII mode vs. MII mode.
If autonegotiation is enabled, this
Jumper
setting advertises capability for
P1+2 (low)
10/100/1000 speeds. If
autonegotiation is disabled, this
P1+2 (low)
setting forces 10Mb mode.
If autonegotiation is enabled, this
Jumper
Bias PHY
setting advertises capability for
JP82 + JP81
P2+3 (high)
Speed1 + Speed0
10/100 speeds. If autonegotiation is
P2+3 (high)
disabled, this setting is not legal.
If autonegotiation is enabled, this
Jumper
setting advertises capability for
1000 speeds. If auto negotiation is
P2+3(high)
P1+2 (low)
disabled, this setting forces
1000Mb mode.
Note: When the PHY is in GMII mode, the REFCLK pin on DS33X162 must be driven with 125MHz (JP08_2+1).
Additionally, MacClkEn must be enabled (JP82_2+3). In MII mode, RefClk must be driven with 25MHz (JP08_2+1).
Here MacClkEn does not matter, but could be disabled to save power and reduce noise.
Jumper
Jumper P2+3 to enable full duplex;
JP89
Bias PHY Duplex
P2+3 (high)
jumper P1.2 to force half duplex.
Jumper
Jumper P2+3 to enable
JP86
Bias PHY ANEN
P2+3 (high)
autonegotiation.
PHY Advertisement Setting. P2+3
Jumper
selects multiple node priority
JP79
Bias PHY MultiEn
(switch or hub). P1+2 selects single
P1+2 (high)
node priority (NIC).
Jumper
P2+3 enables pair swap mode,
JP80
Bias PHY MdixEn
P2+3 (low)
P1+3 disables pair swap mode
P2+3 PHY clock to MAC output is
enabled; P1+2 PHY clock to MAC
Jumper
JP82
Bias PHY MacClkEn
output is disabled. MAC clock only
P2+3 (low)
needs to be enabled in Gigabit
mode.
TP17
Test Point
MAC Clock Test Point.
J1
Rev: 031008
Ethernet Connection
13 of 78
________________________________________________________________ DS33X162DK
6.
Register Access
6.1
Address Map
The external device address space begins at 0x81000000. All offsets given in Table 6-1 are relative to this offset.
Table 6-1. Overview of Daughter Card Address Map
OFFSET
DEVICE
0X0000 to
0X0087
FPGA
0X1000 to
0X1FFF
DESCRIPTION
Processor board identification .
DS33X162 DS33X162 uses CS1.
0X4000 to
0X5FFF
DS26528
DS26528 T1/E1 device, ports 1 to 8. Uses CS_X2.
0X6000 to
0X7FFF
DS26528
DS26528 T1/E1 device, ports 9 to 16. Uses CS_X3.
0X8000 to
0X9FFF
DS3174
DS3174 T3/E3 device ports 1 to 4. Uses CS_X4.
0XA000 to
0XBFFF
DS3174
DS3174 T3/E3 device, ports 5 to 8. Uses CS_X5.
All device registers can be easily modified using the ChipView host-based user-interface software with the
definition files previously mentioned.
6.2
Control Through External Processor
The demo kit is intended to be controlled using the on-board microcontroller and a host PC. However, the demo kit
has jumper points to allow it to be controlled by an external processor. The DS33X162 can be controlled in SPI
mode by attaching to the signals at JP09, JP10, JP11, and JP12. Alternately, the DS33X162 and transceivers
(DS26528 and DS3174) can be controlled by jumpering J05.12+14 and then connecting to J05 and J06. Doing so
pulls up the tristate_bus signal and places the FPGA in a high-impedance mode (see the Address Map section).
6.3
SPI Mode
The DS33X162 has an option to use both parallel and SPI mode. SPI mode is addressed differently than devices
that use a parallel address/data bus. In SPI mode, the DS33X162 does not have an address offset; its base
address starts at 0x00.
Table 5-1 details the default bias levels for SPI configuration pins. To change these settings the processor’s SPI
settings must also change. A special set of definition files must be used when in SPI mode. These are contained in
the subfolder .\DS33X162_spi\. The processor SPI settings can be changed in ChipView’s terminal mode using the
SPISG S function.
6.4
MAC and PHY Registers
The MAC and PHY are accessed indirectly. This process is automated by the indirect register module. To load this
module, first select the DS33X162 device driver demo plugin using the Tools→Plugins menu. Once the device
driver demo loads, select the indirect register module from the Tools→Indirect register menu. The first tab of the
menu has a selection for the device bus mode. Select SPI mode when using the DS33X162.
To test that the indirect register section is working, try to reset the PHY. Select the PHY tab, change the Padd field
to 00001 to select the PHY at MDIO address 1. In the Data write field enter 00 00 80 00. Click the Write PHY
button. At this point the link LED of the PHY should go out (and turn back on within a few seconds).
Rev: 031008
14 of 78
________________________________________________________________ DS33X162DK
7.
Additional Information/Resources
7.1
DS33X162 Information
For more information about the DS33X162, refer to the DS33X162 data sheet available on our website at
www.maxim-ic.com/DS33X162.
7.2
DS33X162DK Information
For more information about the DS33X162DK, including software downloads, refer to the DS33X162DK data sheet
available on the our website at www.maxim-ic.com/DS33X162DK.
7.3
Technical Support
For additional technical support, go to www.maxim-ic.com/support.
Rev: 031008
15 of 78
________________________________________________________________ DS33X162DK
8.
Component List
Table 8-1 shows the component list for the DS33X11 and DS33X162 demo kits and resource cards. This BOM
contains the part listing for four boards. These boards are the DS33X11DK, DS33X162DK, DualPhyRC, and
GigPhyRC. Each reference designator is only used once. For example, U25 only appears on the DS33X11DK and
is not used on any of the other boards. See Table 5-1.
Table 8-1. Component List
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
C02, C22, C145, CB19, CB23,
D CASE TANT 470uF
CB42, CB95, CB129, CB303,
15
KEM
T491D477M006AS
6.3V 20%
CB319, CB445, CB447, CB452,
CB460, CB463
Reference designators shown on
0603 CERAM 4.7uF 6.3V
231
UNK
ECJ-1VB0J475M
next row
MULTILAYER
C03, C08, C11, C14, C15, C16, C17, C21, C24, C29, C33, C45, C49, C51, C52, C91, C92, C96, C97, C115, C119, C120, C122,
C123, C129, C137, C138, C141, C142, C146, C149, C151, C153, C158, C258, C263, C265, CB01, CB04, CB06, CB09, CB13,
CB16, CB17, CB21, CB24, CB26, CB27, CB28, CB36, CB37, CB41, CB44, CB45, CB46, CB47, CB48, CB58, CB60, CB66, CB67,
CB74, CB75, CB76, CB78, CB80, CB84, CB92, CB93, CB98, CB99, CB100, CB104, CB107, CB114, CB115, CB116, CB118,
CB123, CB125, CB126, CB137, CB138, CB141, CB144, CB151, CB155, CB158, CB163, CB164, CB166, CB170, CB171, CB172,
CB179, CB181, CB183, CB185, CB186, CB188, CB189, CB191, CB192, CB193, CB195, CB197, CB198, CB201, CB204, CB209,
CB215, CB218, CB221, CB222, CB227, CB229, CB230, CB231, CB234, CB235, CB239, CB243, CB249, CB251, CB255, CB258,
CB263, CB264, CB267, CB270, CB271, CB273, CB276, CB277, CB278, CB284, CB287, CB293, CB294, CB297, CB298, CB302,
CB304, CB306, CB307, CB320, CB322, CB327, CB328, CB341, CB343, CB344, CB345, CB347, CB348, CB351, CB352, CB353,
CB357, CB358, CB364, CB365, CB366, CB367, CB369, CB370, CB371, CB375, CB376, CB379, CB380, CB388, CB392, CB393,
CB395, CB396, CB399, CB400, CB401, CB404, CB405, CB406, CB407, CB408, CB409, CB415, CB416, CB423, CB424, CB425,
CB427, CB431, CB436, CB438, CB441, CB442, CB446, CB449, CB453, CB454, CB462, CB467, CB760, CB766, CB768, CB777,
CB779, CB789, CB790, CB791, CB792, CB793, CB795, CB798, CB802, CB804, CB805, CB807, CB808, CB810, CB812, CB813,
CB815, CB816, CB817, CB818, CB824, CB827, CB856, CB857, CB859
Reference designators shown on
L_0603 CERAM .01uF
114
AVX
06035C103KAT
next row
50V 10% X7R
C04, C05, C06, C07, C09, C10, C18, C20, C32, C37, C40, C41, C42, C50, C57, C70, C89, C98, C104, C113, C114, C118, C125,
C133, C134, C136, C148, C150, C261, C266, CB03, CB11, CB14, CB20, CB30, CB34, CB52, CB55, CB61, CB69, CB71, CB73,
CB83, CB103, CB109, CB112, CB119, CB120, CB128, CB139, CB150, CB157, CB161, CB167, CB173, CB187, CB194, CB205,
CB206, CB207, CB213, CB216, CB217, CB219, CB223, CB224, CB225, CB228, CB240, CB256, CB259, CB261, CB275, CB285,
CB295, CB300, CB308, CB332, CB350, CB354, CB359, CB361, CB381, CB385, CB391, CB398, CB402, CB413, CB414, CB419,
CB428, CB432, CB435, CB439, CB443, CB444, CB448, CB451, CB466, CB468, CB761, CB765, CB770, CB771, CB772, CB776,
CB794, CB803, CB806, CB811, CB819, CB823, CB853, CB855
L_0603 CERAM 22pF
C110, C112, CB86, CB87
4
AVX
06033A220JAT
25V 5% NPO
C156, C259, CB51, CB762, CB763,
CB764, CB767, CB769, CB773,
0603 CERAM 0.1uF 16V
16
Phycomp
06032R104K7B20D
10%
CB774, CB775, CB780, CB782,
CB786, CB787, CB788
C25, C126, CB10, CB31, CB33,
CB88, CB89, CB102, CB145,
L_1206 CERAM 10uF
CB146, CB147, CB315, CB333,
20
Panasonic
ECJ-3YB1A106M
10V 20%
CB338, CB363, CB368, CB383,
CB417, CB418, CB437
C28, C31, C132, CB25, CB32,
CB35, CB38, CB40, CB43, CB56,
CB68, CB81, CB85, CB96, CB105,
0603 CERAM .1uF 16V
CB313, CB321, CB324, CB372,
28
Panasonic
ECJ-1VB1C104K
10%
CB373, CB384, CB394, CB397,
CB410, CB411, CB412, CB422,
CB450
C39, C44, C54, C55, C56, C60,
C61, C64, C99, C100, C101, C102,
1206 CERAM 10uF 10V
18
Panasonic
ECJ-3YB1A106M
20%
C103, C105, C106, C107, C108,
C109
Rev: 031008
16 of 78
________________________________________________________________ DS33X162DK
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
C58, C63, C67, C69, C73, C76,
C77, C86, C87, CB108, CB153,
1206 CERAM 0.1uF 25V
16
Panasonic
ECJ-3VB1E104K
10%
CB208, CB238, CB252, CB253,
CB254
C59, C62, C65, C66, C68, C71,
1206 CERAM 560pf 50V
C72, C75, C78, C79, C80, C81,
17
AVXZ
12065A561JAT2A
5%
C82, C83, C84, C85, C116
Reference designators shown on
L_0603 CERAM .1uF
226
AVX
0603YC104MAT
next row (begins with C01)
16V 20% X7R
C01, C12, C13, C19, C23, C26, C27, C30, C34, C35, C36, C38, C43, C46, C47, C48, C53, C74, C88, C90, C93, C94, C95, C111,
C117, C121, C124, C127, C128, C130, C131, C135, C139, C140, C143, C144, C147, C152, C154, C155, C157, C260, C262,
C264, CB02, CB05, CB07, CB12, CB18, CB22, CB29, CB39, CB49, CB53, CB57, CB59, CB62, CB63, CB64, CB65, CB70, CB72,
CB77, CB79, CB82, CB90, CB91, CB94, CB97, CB101, CB106, CB110, CB111, CB113, CB117, CB121, CB122, CB124, CB130,
CB131, CB132, CB133, CB134, CB135, CB136, CB140, CB142, CB148, CB149, CB152, CB154, CB156, CB159, CB160, CB162,
CB165, CB168, CB169, CB174, CB175, CB176, CB177, CB178, CB180, CB182, CB184, CB190, CB196, CB199, CB200, CB202,
CB203, CB210, CB211, CB212, CB214, CB220, CB226, CB232, CB233, CB236, CB237, CB241, CB242, CB244, CB245, CB246,
CB247, CB248, CB250, CB257, CB260, CB262, CB266, CB268, CB269, CB272, CB274, CB280, CB282, CB283, CB286, CB288,
CB289, CB296, CB299, CB301, CB305, CB309, CB310, CB311, CB312, CB314, CB316, CB317, CB318, CB323, CB325, CB326,
CB329, CB330, CB331, CB334, CB335, CB336, CB337, CB339, CB340, CB342, CB346, CB349, CB355, CB356, CB360, CB362,
CB374, CB377, CB378, CB382, CB386, CB387, CB389, CB390, CB403, CB420, CB421, CB426, CB430, CB433, CB434, CB440,
CB455, CB456, CB457, CB458, CB459, CB461, CB464, CB465, CB469, CB470, CB757, CB758, CB759, CB778, CB781, CB783,
CB784, CB785, CB796, CB797, CB799, CB800, CB801, CB809, CB814, CB820, CB821, CB822, CB825, CB826, CB828, CB829,
CB852, CB854, CB858
CB08, CB15, CB54, CB127, CB143,
L_D CASE TANT 68uF
CB279, CB281, CB290, CB291,
10
Panasonic
ECS-T1CD686R
16V 20%
CB292
L_1206 CERAM 1uF 16V
CB265, CB429
2
Panasonic
ECJ-3YB1C105K
10%
SCHOTTKY DIODE, 1
International
DB01, DB02, DB03
3
10BQ040
AMP 40 VOLT
Rectifier
DS01, DS02, DS03, DS33, DS34,
DS35, DS41, DS42, DS43, DS44,
DS45, DS46, DS47, DS48, DS49,
24
LED, GREEN, SMD
Panasonic
LN1351C
DS75, DS76, DS77, DS78, DS79,
DS80, DS81, DS82, DS83
DS04, DS05, DS06, DS07, DS17,
DS18, DS19, DS20, DS21, DS24,
17
L_LED, RED, SMD
Panasonic
LN1251C
DS25, DS26, DS36, DS37, DS38,
DS39, DS40
DS08, DS50, DS63, DS64, DS65,
6
L_LED, GREEN, SMD
Panasonic
LN1351C
DS66
DS09, DS10, DS11, DS12, DS13,
DS14, DS15, DS16, DS22, DS23,
20
LED, RED, SMD
Panasonic
LN1251C
DS27, DS28, DS29, DS30, DS31,
DS32, DS71, DS72, DS73, DS74
DS67, DS68, DS69, DS70
4
LED, AMBER, SMD
Panasonic
LN1451C
KIT, 4-40 HARDWARE,
H01, H02, H03, H04, H05, H06,
12
.50 NYLON STANDOFF
NA
4-40KIT4
H07, H08, H09, H10, H11, H12
AND NYLON HEX-NUT
TERMINAL STRIP, 16
J01, J12, J13, J17, J18
5
Samtec
TSW-108-07-T-D
PIN, DUAL ROW, VERT
J02, J50
2
J03, J43
2
J04, J51
2
J05, J06, J48, J49
4
J07, J08, J10, J11
4
Rev: 031008
TERMINAL STRIP, 10
PIN, DUAL ROW, VERT
TYPE B SINGLE RT
ANGLE, BLACK
L_CONN, DB9 RA,
LONG CASE
NON POPULATED
HEADER, 14 PIN, DUAL
ROW, VERT
NOPOP TERMINAL
STRIP, 16 PIN, DUAL
ROW, VERT
NA
NA
MOL
NA
AMP
747459-1
Samtec
NOPOP-HDR-TSW-107-14-T-D
Samtec
NOPOP-TSW-108-07-T-D
17 of 78
________________________________________________________________ DS33X162DK
DESIGNATION
QTY
J09, J14, J20, J21, J22, J23, J52,
J53, J57
9
J15, J46
2
J16, J24
2
J19, J25, JB06
J26, J27, J28, J29, J30, J31, J32,
J33, J34, J35, J36, J37, J38, J39,
J40, J41, J44, J45
3
18
J42, J58
2
J47
1
J54, J93, J94, J95, J96
5
J55
1
J56, J98
2
J91, J92
2
J97, J99
2
JB01, JB05
2
JB02, JB04
2
JB03
1
Reference designators shown on
next row (begins with JP01)
49
DESCRIPTION
L_TERMINAL STRIP, 10
PIN, DUAL ROW, VERT
CONN 2.1MM/5.5MM
PWRJACK RT ANGLE
PCB, closed frame, high
current 24VDC@5A also
requires 5V ACDC
adapter INPUT 100240VAC 50-60HZ 0.6A
OUTPUT DC 5V 2.6A.
PN DMS050260-P5P-SZ.
MODEL 3Z-161WP05
CONNECTOR,
STACKED OCTAL JACK,
64-PIN, SHIELDED
100 MIL 2 POS JUMPER
L_2 PIN HEADER, .100
CENTERS, VERTICAL
100 MIL 2*7 POS
JUMPER
L_RJ48 8 PIN SINGLE
PORT CONNECTOR
L_TERMINAL STRIP, 10
PIN, DUAL ROW, VERT
DO NOT POPULATE
HEADER, 14 PIN, DUAL
ROW, VERT
CONNECTOR,
PULSEJACK, 16 PIN
CONNECTOR,
FASTJACK SINGLE, 8
PIN FOR NATIONAL
PHY
SOCKET, SMD, 50 PIN,
2 ROW VERTICAL
PLUG, SMD, 50 PIN, 2
ROW VERTICAL
TEST POINTS FOR SMD
50 PIN, 2 ROW
VERTICAL
100 MIL 2 POS JUMPER
DO NOT POPULATE
100 MIL 3 POS JUMPER
SUPPLIER
PART
Samtec
TSW-105-07-T-D
DIGIKEY
CP-002AH-ND
MOL
SD-44520-001
NA
NA
Samtec
TSW-102-07-T-S
NA
NA
MOLEX
15-43-8588
DNP
DNP
Samtec
HDR-TSW-107-14-T-D
Pulse
JK0654218Z
Halo
Electronics
HFJ11-2450E
Samtec
TFM-125-02-S-D-LC
Samtec
SFM-125-L2-S-D-LC
NA
NA_NOTPOPULATED
NOPOP
NA
NA
NA
JP01, JP02, JP03, JP04, JP05, JP06, JP07, JP08, JP09, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19, JP20,
JP21, JP22, JP23, JP24, JP25, JP26, JP27, JP28, JP29, JP67, JP68, JP69, JP70, JP71, JP72, JP73, JP74, JP75, JP76, JP77,
JP78, JP79, JP80, JP81, JP82, JP83, JP84, JP85, JP86
R01, R02, R42, R43, RB01, RB02,
RB04, RB39, RB46, RB47, RB62,
RB87, RB88, RB89, RB90, RB91,
RB107, RB128, RB231, RB232
R03, R05, RB09, RB10, RB12,
RB14, RB26, RB28, RB96, RB97,
RB100, RB113, RB114, RB115,
RB116, RB118, RB120, RB122,
RB123
R04, RB03, RB05, RB07, RB13,
RB18, RB23, RB24, RB25, RB92,
RB99, RB101, RB104, RB106,
RB121
Rev: 031008
20
RES 0603 0.0 Ohm
1/16W 5%
Panasonic
ERJ-3GEY0R00V
19
RES 0603 30 Ohm
1/16W 5%
Panasonic
ERJ-3GEYJ300V
15
L_RES 0603 330 Ohm
1/16W 5%
Panasonic
ERJ-3GEYJ331V
18 of 78
________________________________________________________________ DS33X162DK
DESIGNATION
QTY
R06, R07, R39, R41
4
R08, RB06, RB15, RB17, RB19,
RB20, RB21, RB43, RB45
R09, R10, R11, R12, R14, R15,
R16, R17, R18, R19, R20, R21,
R22, R23, R24, R25, R26, R27,
R28, R29, R30, R31, R32, R33,
R34, R35, RB32, RB33, RB48,
RB49, RB50, RB51
R13, RB30, RB31, RB60, RB61,
RB109, RB110, RB111, RB127
32
R36, R40
2
R37, R38
2
RB08, RB41, RB98, RB108
4
RB11, RB95
2
RB119, RB246
2
RB125, RB126, RB129, RB245,
RB248, RB249
6
RB16, RB22, RB131, RB132
4
RB233, RB234, RB235, RB236,
RB239, RB241
6
RB237, RB238
2
RB27, RB124, RB130, RB247
4
RB29, RB34, RB35, RB36, RB37,
RB38
6
RB40, RB44, RB112, RB240,
RB242, RB243, RB244
7
RB42, RB117
2
RB52, RB53, RB54, RB55, RB56,
RB57, RB58, RB59, RB63, RB64,
RB65, RB66, RB67, RB68, RB69,
RB70, RB103, RB105
RB71, RB72, RB73, RB74, RB75,
RB76, RB77, RB78, RB79, RB80,
RB81, RB82, RB83, RB84, RB85,
RB86, RB93, RB94, RB102
RP01, RP02, RP03, RP04, RP05,
RP06, RP41, RP42, RP43, RP44,
RP48, RP49, RPB07, RPB10,
RPB109, RPB110
RP07, RP08, RP09, RP10, RP12,
RP45, RP46, RP47, RP50, RP51,
RPB15, RPB19, RPB93, RPB98,
RPB107, RPB108, RPB131,
RPB132, RPB144, RPB145
See next row (begins with RP11)
Rev: 031008
9
DESCRIPTION
RES 0603 24.3 Ohm
1/16W 1%
L_RES 0603 1.0K Ohm
1/16W 5%
RES 1206 61.9 Ohm
1/8W 1%
SUPPLIER
PART
Panasonic
ERJ-3EKF24R3V
Panasonic
ERJ-3GEYJ102V
Panasonic
ERJ-8ENF61R9V
Panasonic
ERJ-3GEYJ103V
Panasonic
ERJ-3GEYJ105V
Panasonic
ERJ-6ENF61R9V
Panasonic
ERJ-3GEYJ103V
Panasonic
ERJ-3GEYJ152V
Panasonic
ERJ-3EKF9761V
L_RES 0603 10K Ohm
1/16W 5%
RES 0603 1.0M Ohm
1/16W 5%
RES 0805 61.9 Ohm
1/10W 1%
RES 0603 10K Ohm
1/16W 5%
RES 0603 1.5K Ohm
1/16W 5%
RES 0603 9.76K Ohm
1/16W 1%
RES 0603 2.0K Ohm
1/16W 5%
L_RES 0603 0 Ohm
1/16W 1%
RES 0603 2.2K Ohm
1/16W 5%
RES 0603 4.87K Ohm
1/16W 1%
RES 0603 330 Ohm
1/16W 5%
RES 0603 51 Ohm
1/10W 5% - SEE
SPECIAL
INSTRUCTIONS
RES 0603 30 Ohm
1/16W
RES 0805 10K Ohm
1/10W 1%
Panasonic
ERJ-3GEYJ202V
AVX
CJ10-000F
Panasonic
ERJ-3GEYJ222V
Panasonic
ERJ-3EKF4871V
Panasonic
ERJ-3GEYJ331V
Panasonic
ERJ-3GEY0R00V
Panasonic
ERJ-3GEYJ300V
Panasonic
ERJ-6ENF1002V
18
RES 0603 332 Ohm
1/16W 1%
Panasonic
ERJ-3EKF3320V
19
RES 0603 51 Ohm
1/16W 5%
Panasonic
ERJ-3GEYJ510V
16
4 PACK RESISTOR 24
OHM 2 PCT
KOA
CN1J4TTD240G
20
4 PACK RESISTOR 50
OHM 2 PCT
KOA
CN1J4TTD500G
62
4 PACK RESISTOR 30
OHM 5% QUAD 0402
PANASONIC
EXB-N8V300JX
9
19 of 78
________________________________________________________________ DS33X162DK
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
RP11, RP13, RP15, RP16, RP17, RP18, RP19, RP20, RP25, RP26, RP27, RP28, RP29, RP30, RP31, RP32, RP33, RP34, RP35,
RP36, RP37, RP38, RP39, RP84, RP85, RP86, RP87, RP88, RP89, RP91, RP92, RP93, RP94, RPB05, RPB08, RPB09, RPB11,
RPB13, RPB16, RPB18, RPB21, RPB24, RPB25, RPB30, RPB35, RPB43, RPB44, RPB51, RPB52, RPB58, RPB59, RPB60,
RPB61, RPB62, RPB63, RPB64, RPB65, RPB84, RPB87, RPB91, RPB99, RPB143
RP14, RPB04, RPB06, RPB14,
RPB20, RPB22, RPB54, RPB55,
RPB56, RPB66, RPB77, RPB79,
4 PACK RESISTOR 10K
22
PANASONIC
EXB-N8V103JX
RPB89, RPB92, RPB94, RPB95,
OHM 5% QUAD 0402
RPB96, RPB97, RPB100, RPB101,
RPB103, RPB150
RP21, RP22, RP23, RP24, RPB26,
RPB27, RPB28, RPB29, RPB31,
RPB32, RPB33, RPB34, RPB36,
4 PACK RESISTOR 20
24
PANASONIC
EXB-N8V200JX
RPB38, RPB39, RPB40, RPB41,
OHM 5% QUAD 0402
RPB42, RPB45, RPB46, RPB47,
RPB49, RPB50, RPB53
RP40, RP90, RPB01, RPB02,
RPB03, RPB12, RPB17, RPB37,
RPB57, RPB67, RPB68, RPB69,
4 PACK RESISTOR 1K
23
PANASONIC
EXB-N8V102JX
RPB70, RPB71, RPB74, RPB78,
OHM 5% QUAD 0402
RPB80, RPB82, RPB83, RPB85,
RPB90, RPB104, RPB149
RPB23, RPB48, RPB72, RPB73,
4 PACK RESISTOR 330
RPB75, RPB76, RPB81, RPB86,
13
PANASONIC
EXB-N8V331JX
OHM 5% QUAD 0402
RPB102, RPB105, RPB133,
RPB135, RPB147
RPB88, RPB106, RPB134,
RPB136, RPB137, RPB138,
4 PACK RESISTOR 2.2K
12
PANASONIC
EXB-N8V222JX
OHM 5% QUAD 0402
RPB139, RPB140, RPB141,
RPB142, RPB146, RPB148
SWITCH MOM 4PIN
SW01
1
Panasonic
EVQPAE04M
SINGLE POLE
XFMR, OCTAL T3/E3, 1
T01, T02, T03
3
Pulse
T3049
TO 2, SMT 32 PIN
XFMR, XMIT/RCV, 1 TO
TB01, TB02, TB03, TB04
4
2 AND 1 TO 1, SMT 32
Pulse
TX1475
PIN
XFMR, 1CT_1CT &
TB05
1
Pulse
TX1277
1CT_2CT, 12P SMT
TP01, TPB01, TPB02, TPB07,
TEST POINT, 1 PLATED
NA
NA
6
TPB08, TPB09
HOLE, DO NOT STUFF
U01, U19
2
USB UART (USB - 8 bit
FIFO), 32 PIN LQFP
FTD
FT245BM
U02
1
ETHERNET EXTENSION
DEVICE 16 WAN 2 LAN
DALLAS
SEMICONDUC
TOR
NA
U03, UB29
2
Atmel
AT25F2048N-10SU-2.7
U04, U05, U06, U07, U11, U22,
UB12, UB14, UB15, UB17, UB19,
UB34
12
Philips
CBT3244APW
U08, U15
2
Dallas
Semiconductor
DS26528N
U09, U10, U12, UB13, UB18, UB20
6
Philips
CBT3244APW-T
U13, U23, UB22, UB33
4
NA
NA
U14, U24
2
Lattice
LFEC3E-3T144C
Rev: 031008
SPI SERIAL EEPROM
2M 8 PIN SOIC 2.7V to
3.6V
IC, OCT BUFFER FET
SWITCH 5V 20-PIN
TSSOP
IC, OCTAL
TRANSCEIVER 0-70C
256P BGA
BAD PARTNUM IC, OCT
BUFFER FET SWITCH
5V TSOP
CYPRESS SRAM, LAB
STOCK
IC, FPGA, 1.2V, 20X20
TQFP, 144 PIN
20 of 78
________________________________________________________________ DS33X162DK
DESIGNATION
QTY
U16, U17
2
U18, U27
2
U20
1
U21
1
U25
1
U26, U33
2
U31, U32
2
UB01, UB28, UB70
3
UB02, UB36
2
UB03, UB35
2
UB04, UB30
2
UB05, UB06, UB37, UB38
4
UB07, UB08, UB09, UB11, UB16,
UB23, UB24, UB25, UB26, UB27
10
UB10, UB31
2
UB21, UB32
2
XB01, XB02
2
Y01, YB07
2
YB01, YB03, YB09, YB11
4
YB02, YB10
2
YB04
1
YB05
1
Rev: 031008
DESCRIPTION
QUAD TRIPLE DUAL
SINGLE ATM PACKET
PHYs FOR DS3 E3 STS1
0-70C 400P BGA
MMC2107 PROCESSOR
DS3/E3 SCT, 11X11
CSBGA, 100 PIN
IC, SINGLE T1 E1 J1
TRANSCEIVER, 10X10
LQFP, 64-PIN
ETHERNET EXTENSION
DEVICE 1 WAN 2 LAN
GIG PHYTER V,
10/100/1000 ETHERNET
PHYSICAL LAYER, 128
PIN QFP
IC, DP83848C PHYTER
10/100 ETHERNET
TRANSCEIVER, 48 PIN
TQFP
HIGH SPEED BUFFER
SINK SOURCE DDR
TERMINATION
REGULATOR
DOUBLE DATA RATE
(DDR) SDRAM 2-2-2
TIMING 256MBITX16
TSSOP
IC, LINEAR REG 1.5W,
1.8V or Adj, 1A,
16TSSOP-EP
IC, LINEAR REG 1.5W,
2.5V or Adj, 1A,
16TSSOP-EP
IC, LINEAR REG 1.5W,
3.3V or Adj, 1A,
16TSSOP-EP
Dual RS-232 transceivers
with 3.3V/5V internal
capacitors
IC, LDO REGULATOR
WITH RESET,1.20V
OUTPUT 300 MA, 6 PIN
SOT23
XTAL LOW PROFILE
8.0MHZ
XTAL, LOW PROFILE,
6.00 MHZ
SOCKETED
OSCILLATOR,
CRYSTAL CLOCK, 3.3V
- 125.000 MHZ
SOCKETED
OSCILLATOR,
CRYSTAL CLOCK, 3.3V
- 25.000 MHZ
OSCILLATOR,
CRYSTAL CLOCK, 5.0V
- 44.736 MHZ
OSCILLATOR + Socket,
CRYSTAL CLOCK, 3.3V
- 2.048 MHZ
SUPPLIER
PART
Dallas
Semiconductor
DS3184
Motorola
MMC2107
Dallas
Semiconductor
DS3170
Dallas
Semiconductor
DS26521
Dallas
Semiconductor
NA
National
Semiconductor
DP83865BVH
National
Semiconductor
DP83848C
FAIRCHILD
NC7SZ86
AVNET
LP2995M
MICRON
NA
Maxim
MAX1793EUE-18
Maxim
MAX1793EUE-25
Maxim
MAX1793EUE-33
MAXIM
NA
Maxim
MAX1963EZT120-T
ECL
EC1-8.000M
Pletronics
LP49-26-6.00M
ECLIPTEK
EC1325HSTS-125.000M+SOCKET
SaRonix
NTH089AA3-25.000+SOCKET
SaRonix
NTH089AA-44.736
SaRonix
SOCKET+NTH039A3-2.0480
21 of 78
________________________________________________________________ DS33X162DK
DESIGNATION
QTY
YB06
1
YB08
1
YB12
1
YB13
1
Rev: 031008
DESCRIPTION
OSCILLATOR + Socket,
CRYSTAL CLOCK, 5V 1.544 MHZ
OSCILLATOR,
CRYSTAL CLOCK, 3.3V
- 44.736 MHZ
OSCILLATOR,
CRYSTAL CLOCK, 3.3V
- 1.544 MHZ
OSCILLATOR,
CRYSTAL CLOCK, 3.3V
- 2.048 MHZ
SUPPLIER
PART
SaRonix
SOCKET+NTH039A-1.5440
SaRonix
NTH089AA3-44.736
SaRonix
NTH039A3-1.5440
SaRonix
NTH039A3-2.0480
22 of 78
________________________________________________________________ DS33X162DK
9.
Schematics
The DS33X162DK schematics are featured in the following pages. As this is a hierarchal schematic some
explanation follows. The schematic contains nine hierarchal blocks: the microcontroller, DS26528, DS3174,
Ethernet PHY, Ethernet Test Points, and Power Supply.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
DS33X162 PCB LAYOUT AND SCHEMATIC HIERARCHY BLOCK PAGE LISTING
ETHERNET PHY #2
TEST POINTS
PAGE 3 SYMBOL
ETHERNET PHY #1
TESTPOINTS
PAGE 3 SYMBOL
SCHEMATIC
PAGES 70–71
SCHEMATIC
PAGES 73–74
DS26528 BLOCK
PAGE 25 SYMBOL
PORTS 9–16
SCHEMATIC
PAGES 49–56
DS26528 BLOCK
PAGE 25 SYMBOL
PORTS 1–8
SCHEMATIC
PAGES 41–48
POWER SUPPLY
PAGE 34 SYMBOL
DS33X162 SECTION
CONTAINS
9 HIERARCHY
BLOCKS
SCHEMATIC
PAGE 67
DS33X162
SCHEMATIC
PAGES 24–35
DS3174 BLOCK
PAGE 25 SYMBOL
PORTS 1–3
SCHEMATIC
PAGE 62–66
DS3174 BLOCK
PAGE 25 SYMBOL
PORTS 6, 7
SCHEMATIC
PAGE 57–61
µP BLOCK
PAGE 24 SYMBOL
SCHEMATIC
PAGES 36–40
Rev: 031008
23 of 78
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
A
B
C
4
8
10K
5
6
7
2
3
RPB22 8
1
CS_X3
CS_X4
CS_X5
RD_DUT
WR_DUT
TE1_H_CS
TE3_L_CS
TE3_H_CS
RD
WR
DATA
D7_SPI_CPOL
D6_SPI_CPHA
D5_SPI_SWAP
RESET_SYS
ADDR
CS_X2
TE1_L_CS
DATA
DATA
DATA
2
2
7
5
6
JP06
SPI_MISO
SPI_SCK
SPI_SS
SPI_MOSI
L11
K12
L12
G10
L13
5
6
7
8
9
6
4
_ds33x162dk_dn.
5
6
2
1K
7
1
3
V3_3
RPB17 8
PARENT BLOCK:
DATA
D1_SPI_MOSI
SPI_MOSI
DATA
D0_SPI_MISO
1
JMP_3
4
VSS
E10
VDD_3.3V
F8
VSS
E9
VDD_3.3V
F9
VSS
M8
VDD_3.3V
H9
VSS
K5
VDD_3.3V
A10
VSS
G5
VDD_3.3V
P4
VDD_3.3V
WR*
RD*
INT*
CS*
ALE
DATA
CSX1_DUT
X162_CS
2
2
2
D[7]/SPI_CPOL
D[6]/SPI_CPHA
D[5]/SPI_SWAP
D[4]
D[3]
D[2]/SPI_SCLK
D[1]/SPI_MOSI
D2_SPI_CLK
SPI_SS
E12
VDD_3.3V
JMP_3
3
ENGINEER:
SYSCLK
RESET_SYS 1
NC_VCC
2
P.24,36-40
STEVE SCULLY
DUT_HIZ_N
RESET_SYS
DUT_JTMS
DUT_JTCLK
DUT_JTDI
DUT_JTDO
DUT_JTRST_N
DUT_SYSCLK
H16
E8
C1
A1
D2
E2
B1
E16
U4
NC7SZ86_U
F7
5
6
7
V3_3
06/07/2006
STMD
1K
1
24/76(TOTAL)
PAGE: 1/12(BLOCK)
DATE:
4
INVERTER
4
1
T5
2
G6
G9 STMD
3
RPB12 8
DUT_SPI_SEL
J6
H6
H8
T2
DUT_BMODE
J16
1
J12
OF DS33X162DK
DS33X42X82X162EE01A0
BEGINNING
MICROPORT.
TITLE:
JMP_3
DS33X162_U
JTRST*
JTDO
JTDI
JTCLK
JTMS
RST*
HIZ*
SPI_SEL
BMODE
V1_8
NC_GND
NC_GND
NC_GND
VSS
C7
NC_DNU
NC_DNU
NC_DNU
NC_DNU
INTERFACE
T14
VDD_3.3V
MICROPORT
VSS
F6
U02
E3
VDD_1.8V
V3_3
VSS
H5
D[0]/SPI_MISO
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
SPI_SCK
J10
WR
JMP_3
J9
J11
J8
J7
RD
\_rc_top_dn_\
2
0
X162_INT
X162_CS
1.0K
K9
M9
K8
D7_SPI_CPOL
V3_3
RB17
4
D6_SPI_CPHA
DATA
K7
D2_SPI_CLK
L7
L6
D1_SPI_MOSI
3
K6
LOOP_SOURCETIME_B
5
K13
4
L8
2
L10
3
D5_SPI_SWAP
SPI_MISO
K11
2
10 G11
L9
1
D0_SPI_MISO
ADDR
K10
0
LOOP_SOURCETIME_A
ENABLE_CALLBACKS_H
ENABLE_DRIVER_H
TE1_ENL
BLOCK NAME:
_motprocrescard_dn
RESET_IN
2
MISC_IO
MISC_IO
MISC_IO
MISC_IO
A_DUT_
7
SPI_MISO
SPI_SCK
SPI_CS
SPI_MOSI
BLOCK
MISC_IO
D_DUT
INT5
CS_X1
INT4
TE3_INT
CSX1_DUT
INT3
TE1_INT
PHY_INT
INT2
X162_INT
HIERARCHY
MICROPROCESSOR
SCHEMATICS FOR GIGABIT
AND DUAL PHY CARDS AT
ARE PLACED AT THE END OF THE DS33X162DK SCHEMATIC
P.24,36-40
P.25-30
P.26,41-48(T1),62-66(T3)
P.25,49-56(T1),57-61(T3)
P.51,87
P.31-32
P.51
P.33
P.34-35,67
M3
VDD_1.8V
D
MICROPORT.
WAN SECTION.
LSB WAN.
MSB WAN.
ETHERNET.
DDR MEMORY.
OSCILLATORS.
BIAS+CONFIG.
POWER.
INDEX
VSS
F16
CONTENTS /
E4
VDD_1.8V
2
VSS
M13
3
D11
VDD_1.8V
F10
4
VSS
F11
DS33X162DK
5
H11
VDD_1.8V
6
VSS
H10
7
3
1
3
JP04
3 1
F12
VDD_1.8V
3
R13
VDD_1.8V
FLOAT
GND
8
JP09
1
VSS
R4
1
3
1
3
G12
VDD_1.8V
3
JP05
JP12
1
JP10
1
H12
VDD_1.8V
JP11
A
B
C
D
A
B
C
D
JTDI
JTDO84
JTRST
WAN_TDI
WANJTD_A
WAN_JTRST
WR
WR
ADDR
WR
WR
ADDR
RB24
330
RB13
330
RB18
330
8
V3_3
RESET_SYS
DATA
RD
RD
TE3_INT
JTRST
WAN_JTRST
7
BLOCK NAME:
6
4
_ds33x162dk_dn.
PARENT BLOCK:
WR
DATA
\_rc_top_dn_\
RESET_SYS
CPU_RESET
ENGINEER:
RT
LFT
JP14
2
PRINTED
STEVE SCULLY
P.25-30
Mon May 14
11:04:02
1
2007
PAGE: 2/12(BLOCK)
25/76(TOTAL)
DATE:
06/07/2006
JMP_3
P.26,41-48(T1),62-66(T3)
P.25,49-56(T1),57-61(T3)
TE1_TDATA[16..9]
WAN_TSYNC[16..9]
WAN_TGCLK[16..9]
WAN_RSYNC[16..9]
WAN_RDATA[16..9]
JP13
TE1WANREFCLK_8_1
2
TE1WANREFCLK_16_9
2
1
TE1_TCLKOSC_8_1
TE1_TCLKOSC_16_9
WAN_RGCLK[16..9]
RT
LFT
TE1WANMCLK_16_9
TE1WANREFCLK_16_9
J19
TE1WANREFCLK_8_1
TE1_TDATA[8..1]
TE1_TSYNC[8..1]
TE1_TGCLK[8..1]
TE1_RSYNC[8..1]
TE1_RDATA[8..1]
TE1_RGCLK[8..1]
TE1_TCLK
TE1WANREFCLK_8_1
TE1WANMCLK_8_1
TE1_RCLK
2
DS33X42X82X162EE01A0
WAN SECTION.
TITLE:
3
TSER528_
TSYNC528_
TCHCLK528_
RSYNC528_
RSER528_
RCHCLK528_
BPCLK528
RSYSCLK528
TSYSCLK528
TSSYNC528
TCLK528_
REFCLK528
MCLK528
RCLK528_
TSER528_
TSYNC528_
TCHCLK528_
RSYNC528_
RSER528_
RCHCLK528_
BPCLK528
RSYSCLK528
TSYSCLK528
TSSYNC528
TCLK528_
REFCLK528
MCLK528
RCLK528_
LSB WAN.
MSB WAN.
_te1_ds26528_dn
ADDR528_
DAT528_
WR_RW528
RD
TE3_TSER
ADDR
RD_DS528
TE1_H_CS
TE3_TDATA[8..5]
CS528
INT528
JTRST
WAN_JTRST
TE1_INT
JTDO
WAN_TDO
JTDI
JTCLK
WAN_TCK
WANJTD_C
JTMS
WAN_TMS
TE3_TSYNC[8..5]
TE3_TGCLK[8..5]
TE3_RSYNC[8..5]
TE3_RDATA[8..5]
TE3_RGCLK[8..5]
TE3_OSC
CPU_RESET
3
_te1_ds26528_dn
ADDR528_
DAT528_
WR_RW528
RD_DS528
CS528
TE3_TSOFO
TE3_TGCLK
TE3_RSOFO
TE3_RSER
TE3_RGCLK
TE3_MCLK
RESET_SYS
ADDR
RD
TE1_L_CS
TE3_TDATA[4..1]
5
JTDO
WANJTD_C
TE3_TSER
X162_INT
2DS05 TE1_INT
2
DS04 RED
1
1
RED
DS06
RESET_B
DAT
JTDI
WANJTD_B
INT528
JTCLK
WAN_TCK
TE1_INT
JTMS
4
WAN_TMS
TE3_TSYNC[4..1]
5
WR
DATA
TE3_TGCLK[4..1]
TE3_RSYNC[4..1]
TE3_RDATA[4..1]
TE3_RGCLK[4..1]
TE3_OSC
6
TE3_TSOFO
TE3_TGCLK
TE3_RSOFO
TE3_RSER
_QUADTE3WAN_DN
ADDR
CS
TE3_H_CS
T3_INT
JTRST
WAN_JTRST
TE3_INT
JTDI
JTDO84
WANJTD_B
JTCLK
WAN_TCK
WANJTD_A
JTMS
RESET_B
WAN_TMS
RESET_SYS
DAT
TE3_MCLK
TE3_RGCLK
_QUADTE3WAN_DN
ADDR
RD
RD
DATA
CS
TE3_L_CS
T3_INT
JTCLK
WAN_TCK
TE3_INT
JTMS
WAN_TMS
7
1
2
8
3
1
3
1
JMP_3
A
B
C
D
A
B
WAN_RGCLK[16..1]
13
15
15
11
11
13
9
9
5
5
7
3
3
7
1
1
16
14
12
10
8
6
4
2
8
CONN_16P
15
13
11
9
7
5
3
1
J11
8
16
14
12
10
8
16
14
12
10
8
6
4
4
6
2
2
1
TE1_RDATA[8..1]
5
5
15
13
11
9
3
3
7
15
13
11
9
7
1
1
7
2
TE1_RDATA[8..1]
16
14
12
10
8
6
4
2
16
14
12
10
8
6
4
2
3
5
7
9
8
6
4
2
CONN_16P
15
13
11
9
7
5
3
1
J08
2
TE1_RSYNC[8..1]
1
3
5
7
9
8
6
4
2
19
V3_3
2
2
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
2
TE1_TGCLK[8..1]
TE1_ENL
1
TE1_RSYNC[8..1]
1
19
V3_3
1
1
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
1
TE1_TGCLK[8..1]
TE1_ENL
7
VCC
2A4
2A3
2A2
2A1
1Y4
15
2 13
WAN_RDATA[16..1]
13 2
15
2 11
WAN_RSYNC[16..1]
11 2
15
13
11
9
6
5
5
15
13
11
9
7
3
3
7
1
1
16
14
12
10
8
6
4
2
CONN_16P
15
13
11
9
7
5
3
1
J07
16
14
12
10
8
6
4
2
16
14
12
10
8
6
4
2
17 PORT2_TE3_ENL
17
2A4
PORTX_TE3_ENL=~PORTX_TE1_ENL
(OPEN DRAIN INVERTER)
2A3
2A2
2A1
1Y4
2 12
WAN_RGCLK[16..1]
14
16
18
12 2
14
2
WAN_TSYNC[16..1]
2
16
1Y2
1Y3
2
WAN_TGCLK[16..1]
2
18
10
10
1Y1
20
V5_0
17
15
13
11
12
14
16
18
20
17
BLOCK NAME: _ds33x162dk_dn.
16
14
12
10
8
6
4
2
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
GND
VCC
OCTAL
FET SWITCH
2OE*
1OE*
1
WAN_RDATA[16..1]
13 1
PORT1_TE3_ENL
1
WAN_RSYNC[16..1]
11 1
15
1
WAN_RGCLK[16..1]
12 1
14
1
WAN_TSYNC[16..1]
1
16
1Y2
1Y3
1
WAN_TGCLK[16..1]
1
10
10
18
20
V5_0
20
6
1Y1
CBT3244A_U
UB14
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
GND
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
UB15
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE1_I2@\_RC_LIB\.\_DS33X162_DN\(SCH_1):PAGE2
WAN_RSYNC[16..1]
C
:
WAN_RDATA[16..1]
5
GND
2
2
2Y4
2A4
2OE*
GND
15
13
11
9
5
5
15
13
11
9
7
3
3
7
1
1
16
14
12
10
8
6
4
16
14
12
10
8
6
16
14
12
10
8
6
4
TE3_RDATA[4..1]
TE3_RSYNC[4..1]
\_rc_top_dn_\
CONN_16P
15
13
11
9
7
5
3
3
4
2A4
4
2Y4
2A3
2
2Y3
2A2
1
2
7
2Y2
2A1
5
2
9
1A4
2Y1
2
8
1Y4
J10
1A3
1Y3
TE3_RGCLK[4..1]
TE3_TSYNC[4..1]
2
4
1A2
1Y2
6
TE3_TGCLK[4..1]
2
2
1A1
19
1
1Y1
OCTAL
FET SWITCH
1OE*
CBT3244A_U
VCC
3
TE3_RDATA[4..1]
TE3_RSYNC[4..1]
TE3_RGCLK[4..1]
PORT2_TE3_ENL
2Y3
2A3
U05
1
7
2Y2
2A2
5
1
2A1
9
1A4
1Y4
6
2Y1
1A3
1Y3
TE3_TSYNC[4..1]
1
4
1
1A2
1Y2
TE3_TGCLK[4..1]
1
PORT1_TE3_ENL
2
19
1
8
1A1
1Y1
PARENT BLOCK:
5
2OE*
VCC
OCTAL
FET SWITCH
1OE*
CBT3244A_U
U04
4
3
3
TE1_ENL[8..1]
STEVE SCULLY
WAN SECTION.
2
P.25-30
DS33X42X82X162EE01A0
ENGINEER:
TITLE:
2
PBWAN_TDATA[16..1]
PBWAN_TDATA[16..1]
D
CR-5
TE1_TDATA[16..1]
9
8
4
RPB18 8
7
6
5
1
2
11
10
9
8
7
8 RP11
7
6
8
7
6
30
7
6
5
2
1
3
1
2
5
10K
1
PAGE: 1/8(BLOCK)
26/76(TOTAL)
06/07/2006
5
6
7
RPB04 8
DATE:
4
3
2
1
4
5
4
3
6
6
7
2
7
10K
RPB06 8
1
2
3
4
5
6
1
4
3
2
1
4
3
7
8
1
2
8
30
8 RP13
3
4
5
1
2
4
1
5
5
3
3
7
2
3
2
6
4
1
4
30
5
RPB21 8
6
5
3
4
5
6
7
10
11
12
6
30
3
2
7
12
30
1
8 RPB16
13
5
3
4
13
14
15
16
14
6
7
2
15
30
RPB13 8
1
16
1
TE1_TDATA[16..1]
TE3_TDATA[8..1]
A
B
C
D
A
B
C
D
8
8
7
3
TE1_RDATA[8..1]
4
4
TE1_RDATA[8..1]
V3_3
4
TE1_RSYNC[8..1]
4
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
4
TE1_TGCLK[8..1]
TE1_ENL
3
TE1_RSYNC[8..1]
V3_3
3
3
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
3
TE1_TGCLK[8..1]
TE1_ENL
7
3
5
7
9
8
6
4
2
19
1
3
5
7
9
8
6
4
2
19
1
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
3
13 4
11 4
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
WAN_RGCLK[16..1]
WAN_TSYNC[16..1]
WAN_TGCLK[16..1]
4
4
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
WAN_RGCLK[16..1]
WAN_TSYNC[16..1]
WAN_TGCLK[16..1]
V5_0
4
4
3
3
15
4 13
4 11
4 12
14
16
18
10
20
17
15
3 13
3 11
3 12
14
16
18
10
20
17
6
_ds33x162dk_dn.
17
PORT4_TE3_ENL
PORTX_TE3_ENL=~PORTX_TE1_ENL
(OPEN DRAIN INVERTER)
15
3
3
V5_0
PORT3_TE3_ENL
12 4
14
16
18
10
20
17
15
13 3
11
12 3
14
16
18
10
20
BLOCK NAME:
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
GND
VCC
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
UB20
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
GND
VCC
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
U06
6
UB13
U09
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
PARENT BLOCK:
5
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2OE*
1OE*
OCTAL
FET SWITCH
GND
VCC
CBT3244A_U
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2OE*
1OE*
OCTAL
FET SWITCH
GND
VCC
CBT3244A_U
5
3
5
7
9
8
6
4
2
19
1
3
5
7
9
8
6
4
2
19
1
TE3_RDATA[4..1]
TE3_RSYNC[4..1]
TE3_RGCLK[4..1]
TE3_TSYNC[4..1]
TE3_TGCLK[4..1]
4
4
TE3_RDATA[4..1]
TE3_RSYNC[4..1]
TE3_RGCLK[4..1]
TE3_TSYNC[4..1]
TE3_TGCLK[4..1]
\_rc_top_dn_\
4
4
4
4
PORT4_TE3_ENL
3
3
3
3
3
PORT3_TE3_ENL
4
3
3
OUT
VCC
TE1_TCLKOSC
5
8
V3_3
OSC
OUT
VCC
TE1_MCLKOSC
5
8
V3_3
ENGINEER:
STEVE SCULLY
2
P.25-30
DS33X42X82X162EE01A0
GND
1
5 TE3_OSC
8
2.048MHZ_3.3VS
OSC
YB05
GND
1
OUT
VCC
V3_3
1.544MHZ_5.0VS
YB06
GND
1
WAN SECTION.
TITLE:
4
1
4
1
4
1
OSC
YB04
44.736MHZ_5.0V
2
4
3
2
1
30
06/07/2006
1
27/76(TOTAL)
PAGE: 1/8(BLOCK)
DATE:
5 TE1WANMCLK_16_9
6 TE1WANMCLK_8_1
7 TE1_TCLKOSC_8_1
RPB65 8 TE1_TCLKOSC_16_9
1
A
B
C
D
A
B
C
D
CR-5
:
8
8
5
TE1_RDATA[8..1]
6
6
TE1_RSYNC[8..1]
TE1_RDATA[8..1]
1
3
5
7
9
8
6
4
2
3
5
7
9
8
6
4
2
19
V3_3
6
6
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
6
TE1_TGCLK[8..1]
TE1_ENL
5
1
19
V3_3
5
TE1_RSYNC[8..1]
5
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
5
TE1_TGCLK[8..1]
TE1_ENL
7
7
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
GND
13 6
11 6
5
WAN_TSYNC[16..1]
6
6
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
WAN_RGCLK[16..1]
WAN_TSYNC[16..1]
WAN_TGCLK[16..1]
V5_0
6
6
6
6
5
5
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
5
WAN_RGCLK[16..1]
6
5
WAN_TGCLK[16..1]
15
13
11
12
14
16
18
10
20
17
15
13
11
12
14
16
18
10
20
6
17 PORT6_TE3_ENL
17
PORTX_TE3_ENL=~PORTX_TE1_ENL
(OPEN DRAIN INVERTER)
15
5
5
V5_0
PORT5_TE3_ENL
12 6
14
16
18
10
20
17
15
13 5
11 5
12 5
14
16
18
10
20
6
BLOCK NAME: _ds33x162dk_dn.
VCC
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
UB18
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
GND
VCC
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
UB19
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE1_I2@\_RC_LIB\.\_DS33X162_DN\(SCH_1):PAGE2
U10
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
5
3
5
7
9
8
6
4
2
19
1
3
5
7
9
8
6
4
2
19
1
TE3_RDATA[8..5]
TE3_RSYNC[8..5]
TE3_RGCLK[8..5]
TE3_TSYNC[8..5]
TE3_TGCLK[8..5]
6
6
6
6
6
\_rc_top_dn_\
TE3_RDATA[8..5]
TE3_RSYNC[8..5]
TE3_RGCLK[8..5]
TE3_TSYNC[8..5]
TE3_TGCLK[8..5]
PORT6_TE3_ENL
5
5
5
5
5
PORT5_TE3_ENL
PARENT BLOCK:
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
2OE*
1OE*
OCTAL
FET SWITCH
GND
VCC
CBT3244A_U
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2OE*
1OE*
OCTAL
FET SWITCH
GND
VCC
CBT3244A_U
U12
5
4
4
3
3
ENGINEER:
STEVE SCULLY
2
P.25-30
DS33X42X82X162EE01A0
WAN SECTION.
TITLE:
2
03/28/2006
1
PAGE: 1/8(BLOCK)
28/76(TOTAL)
DATE:
1
A
B
C
D
A
B
C
D
CR-5
:
7
TE1_RDATA[8..1]
8
8
TE1_RDATA[8..1]
1
3
5
7
9
8
6
4
2
19
V3_3
8
TE1_RSYNC[8..1]
8
TE1_TDATA[8..1]
8
8
TE1_TSYNC[8..1]
TE1_RGCLK[8..1]
8
TE1_TGCLK[8..1]
TE1_ENL
7
TE1_RSYNC[8..1]
1
3
5
7
9
8
6
4
2
19
V3_3
7
TE1_RGCLK[8..1]
7
7
TE1_TSYNC[8..1]
TE1_TDATA[8..1]
7
TE1_TGCLK[8..1]
TE1_ENL
8
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
7
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
GND
VCC
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
UB12
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
GND
15
13 8
11 8
12 8
14
16
18
10
20
17
15
7
7
7
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
WAN_RGCLK[16..1]
8
8
8
8
8
WAN_TSYNC[16..1]
WAN_TDATA[16..1]
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
WAN_RGCLK[16..1]
8
WAN_TGCLK[16..1]
V5_0
8
8
8
7
7
WAN_TSYNC[16..1]
WAN_TDATA[16..1]
7
WAN_TGCLK[16..1]
V5_0
PORT7_TE3_ENL
13 7
11 7
12 7
14
16
18
10
20
6
7
7
7
15
13
11
12
14
16
18
10
20
17
15
13
11
12
14
16
18
10
20
U11
U07
2Y4
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2Y4
2Y3
2Y2
2Y1
1A4
1A3
1A2
1A1
2OE*
1OE*
OCTAL
FET SWITCH
GND
VCC
2Y2
2Y1
1A4
1A3
1A2
1A1
2Y3
CBT3244A_U
2A4
2A3
2A2
2A1
1Y4
1Y3
1Y2
1Y1
2OE*
OCTAL
FET SWITCH
GND
1OE*
CBT3244A_U
VCC
BLOCK NAME: _ds33x162dk_dn.
6
17 PORT8_TE3_ENL
17
PORTX_TE3_ENL=~PORTX_TE1_ENL
(OPEN DRAIN INVERTER)
VCC
OCTAL
FET SWITCH
2OE*
1OE*
CBT3244A_U
UB17
7
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE1_I2@\_RC_LIB\.\_DS33X162_DN\(SCH_1):PAGE2
5
TE3_RDATA[8..5]
TE3_RSYNC[8..5]
TE3_RGCLK[8..5]
TE3_TDATA[8..5]
TE3_TSYNC[8..5]
TE3_TGCLK[8..5]
8
8
8
8
8
8
\_rc_top_dn_\
TE3_RDATA[8..5]
TE3_RSYNC[8..5]
TE3_RGCLK[8..5]
TE3_TDATA[8..5]
TE3_TSYNC[8..5]
TE3_TGCLK[8..5]
PORT8_TE3_ENL
7
7
7
7
7
7
PORT7_TE3_ENL
PARENT BLOCK:
3
5
7
9
8
6
4
2
19
1
3
5
7
9
8
6
4
2
19
1
5
4
4
3
3
ENGINEER:
STEVE SCULLY
2
P.25-30
DS33X42X82X162EE01A0
WAN SECTION.
TITLE:
2
03/28/2006
1
PAGE: 1/8(BLOCK)
29/76(TOTAL)
DATE:
1
A
B
C
D
A
B
C
D
11
11
11
12
12
12
12
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
PBWAN_TDATA[16..1]
WAN_RGCLK[16..1]
WAN_RDATA[16..1]
WAN_RSYNC[16..1]
PBWAN_TDATA[16..1]
8
9
11
WAN_RGCLK[16..1]
WAN_TSYNC[16..1]
10
PBWAN_TDATA[16..1]
9
10
WAN_RSYNC[16..1]
WAN_TGCLK[16..1]
10
9
PBWAN_TDATA[16..1]
WAN_RDATA[16..1]
9
WAN_RSYNC[16..1]
10
9
WAN_RGCLK[16..1]
9
T12
T11
R12
P1
L4
N2
N11
L3
N1
M2
R11
M1
K3
J2
N10
K4
K2
J3
5
5
WAN_TGCLK[16..1]
TE1_TCLK
WAN_RDATA[16..1]
WAN_RDATA[16..1]
5
5
WAN PORTS 9-16
DS33X162_U
6
5
6
5
1
3
1
3
7
1
3
1
3
1
3
2
RB38
RB29
2
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
WAN_RGCLK[16..1]
15
15
15
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
WAN_RGCLK[16..1]
14PBWAN_TDATA[16..1]
14
14
14
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
WAN_RGCLK[16..1]
N14 13
PARENT BLOCK:
5
WAN_TSYNC[16..1]
WAN_TGCLK[16..1]
16PBWAN_TDATA[16..1]
16
16
16
M10 13
P11
T3
N4
R3
N12 15PBWAN_TDATA[16..1]
P3
N3
T4
P12
R2
R1
T1
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
WAN_RGCLK[16..1]
DS33X162_U
WAN PORTS 5-8
4
RCLK7
\_rc_top_dn_\
4
PBWAN_TDATA[16..1]
WAN_TSYNC[16..1]
WAN_TGCLK[16..1]
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
WAN_RGCLK[16..1]
PBWAN_TDATA[16..1]
WAN_TSYNC[16..1]
WAN_TGCLK[16..1]
WAN_RSYNC[16..1]
WAN_RDATA[16..1]
WAN_RGCLK[16..1]
2
2
2
2
2
2
1
1
1
1
1
1
SIGNALS)
TDATA8
TSYNC8
TCLK8
RSYNC8
RDATA8
RCLK8
TDATA7
TSYNC7
TCLK7
RSYNC7
RDATA7
NOT USED FOR X42,X41,X11,W41,W11
THAT W41,W11 USE RV* AND TV*
TDATA6/TVDEN1*
TSYNC6
TCLK6
RSYNC6
RDATA6/RVDAT1
RCLK6
TDATA5/TVDAT1
TSYNC5/TMSYNC2/TVSYNC1
TCLK5/TMCLK2/TVCLK1
RSYNC5/RVDEN1*
RDATA5/RVCLK1
RCLK5/RVSYNC1
(NOTE
N6
P8
P10
H3
F2
J1
M5
R7
M7
G3
F3
F4
U02
5
13PBWAN_TDATA[16..1]
13
13
13
_ds33x162dk_dn.
TMSYNC4
TMCLK4
TDATA16
RSYNC16
RDATA16
RCLK16
TDATA15
RSYNC15
RDATA15
RCLK15
TDATA14
RSYNC14
RDATA14
RCLK14
TDATA13
P14
M4
P2
L5
6
WAN_TSYNC[16..1]
RES3P
0
6
6
6
5
5
WAN_TGCLK[16..1]
RSYNC13
BLOCK NAME:
2
WAN_RGCLK[16..1]
RDATA13
6
2
RB36
WAN_RSYNC[16..1]
0
2
RB35
RB34
2
0
RB37
0
0
0
RES3P
PBWAN_TDATA[16..1]
RCLK13
RES3P
5
5
WAN_RDATA[16..1]
TE1_RCLK
WAN_RSYNC[16..1]
WAN_RGCLK[16..1]
1
3
WAN_TSYNC[16..1]
5
5
6
WAN_RGCLK[16..1]
WAN_RSYNC[16..1]
PBWAN_TDATA[16..1]
WAN_TGCLK[16..1]
7
NOT USED FOR X82,X81,X42,X41,X11,W41,W11
TMSYNC3
TMCLK3
TDATA12
RSYNC12
RDATA12
RCLK12
TDATA11
RSYNC11
RDATA11
RCLK11
TDATA10
RSYNC10
RDATA10
RCLK10
TDATA9
RSYNC9
RDATA9
RCLK9
U02
DS26528
RSYNC5
RCLK5, NOT GAPPED
RGCLK/RCHBLK5
TCLK5,
NOT GAPPED
TSYNC5
TDATA5
RDATA5
TGCLK/TCHBLK5
DS26528
RGCLK5
RDATA5
RSYNC5
TGCLK5
TSYNC5
TDATA5
RDATA6
TDATA6
WAN_RGCLK[16..1]
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