Rev: 032609
DS34S101, DS34S102, DS34S104, DS34S108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standardsbased TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. The high level of
integration available with the DS34S10x devices
minimizes cost, board space, and time to market.
Applications
TDM Circuit Extension Over PSN
o Leased-Line Services Over PSN
o TDM Over GPON/EPON
o TDM Over Cable
o TDM Over Wireless
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Features
♦
Transport of E1, T1, E3, T3 or STS-1 TDM or
Other CBR Signals Over Packet Networks
♦
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
♦
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
♦
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
♦
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
♦
♦
64 Independent Bundles/Connections
♦
♦
♦
♦
VLAN Support According to 802.1p and 802.1Q
♦
♦
Glueless SDRAM Buffer Management
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Low-Power 1.8V Core, 3.3V I/O
See detailed feature list in Section 7.
Functional Diagram
PART
CPU
Bus
DS34S108
TDM
Interfaces
Circuit
Emulation
Engine
Buffer
Manager
SDRAM
Interface
Ordering Information
10/100
Ethernet
MAC
Clock
Adapters
Clock Inputs
xMII
Interface
DS34S101GN
DS34S101GN+
DS34S102GN
DS34S102GN+
DS34S104GN
DS34S104GN+
DS34S108GN
DS34S108GN+
PORTS TEMP RANGE PIN-PACKAGE
1
1
2
2
4
4
8
8
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
256 TECSBGA
256 TECSBGA
256 TECSBGA
256 TECSBGA
256 TECSBGA
256 TECSBGA
484 HSBGA
484 HSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package (explanation).
_________________________________________________________ Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Table of Contents
1. INTRODUCTION ................................................................................................................................. 7
2. ACRONYMS AND GLOSSARY .......................................................................................................... 8
3. APPLICABLE STANDARDS ............................................................................................................ 10
4. DETAILED DESCRIPTION ............................................................................................................... 11
5. APPLICATION EXAMPLES .............................................................................................................. 12
6. BLOCK DIAGRAM ............................................................................................................................ 14
7. FEATURES ....................................................................................................................................... 15
8. OVERVIEW OF MAJOR OPERATIONAL MODES ........................................................................... 17
9. PIN DESCRIPTIONS ......................................................................................................................... 18
9.1 SHORT PIN DESCRIPTIONS.............................................................................................................. 18
9.2 DETAILED PIN DESCRIPTIONS ......................................................................................................... 20
10. FUNCTIONAL DESCRIPTION ........................................................................................................ 28
10.1 POWER-SUPPLY CONSIDERATIONS ............................................................................................... 28
10.2 CPU INTERFACE .......................................................................................................................... 28
10.3 SPI INTERFACE ............................................................................................................................ 31
10.3.1 SPI Operation .................................................................................................................................... 31
10.3.2 SPI Modes ......................................................................................................................................... 32
10.3.3 SPI Signals ........................................................................................................................................ 33
10.3.4 SPI Protocol ....................................................................................................................................... 33
10.4 CLOCK STRUCTURE...................................................................................................................... 36
10.5 RESET AND POWER-DOWN ........................................................................................................... 37
10.6 TDM-OVER-PACKET BLOCK .......................................................................................................... 37
10.6.1 Packet Formats .................................................................................................................................. 37
10.6.2 Typical Application ............................................................................................................................. 47
10.6.3 Clock Recovery .................................................................................................................................. 48
10.6.4 Timeslot Assigner (TSA)..................................................................................................................... 49
10.6.5 CAS Handler ...................................................................................................................................... 50
10.6.6 AAL1 Payload Type Machine ............................................................................................................. 54
10.6.7 HDLC Payload Type Machine............................................................................................................. 57
10.6.8 RAW Payload Type Machine .............................................................................................................. 58
10.6.9 SDRAM and SDRAM Controller ......................................................................................................... 62
10.6.10 Jitter Buffer Control (JBC)................................................................................................................. 63
10.6.11 Queue Manager ............................................................................................................................... 66
10.6.12 Ethernet MAC................................................................................................................................... 78
10.6.13 Packet Classifier .............................................................................................................................. 81
10.6.14 Packet Trailer Support ...................................................................................................................... 84
10.6.15 Counters and Status Registers ......................................................................................................... 85
10.6.16 Connection Level Redundancy ......................................................................................................... 85
10.6.17 OAM Signaling ................................................................................................................................. 86
10.7 GLOBAL RESOURCES ................................................................................................................... 87
10.8 PER-PORT RESOURCES................................................................................................................ 87
10.9 DEVICE INTERRUPTS .................................................................................................................... 87
11. DEVICE REGISTERS...................................................................................................................... 89
11.1 ADDRESSING................................................................................................................................ 89
11.2 TOP-LEVEL MEMORY MAP ............................................................................................................ 90
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11.3 GLOBAL REGISTERS ..................................................................................................................... 91
11.4 TDM-OVER-PACKET REGISTERS ................................................................................................... 93
11.4.1 Configuration and Status Registers .................................................................................................... 94
11.4.2 Bundle Configuration Tables ............................................................................................................ 108
11.4.3 Counters .......................................................................................................................................... 117
11.4.4 Status Tables ................................................................................................................................... 120
11.4.5 Timeslot Assignment Tables............................................................................................................. 122
11.4.6 CPU Queues .................................................................................................................................... 124
11.4.7 Transmit Buffers Pool ....................................................................................................................... 129
11.4.8 Jitter Buffer Control .......................................................................................................................... 130
11.4.9 Transmit Software CAS .................................................................................................................... 134
11.4.10 Receive Line CAS .......................................................................................................................... 136
11.4.11 Clock Recovery .............................................................................................................................. 137
11.4.12 Receive SW Conditioning Octet Select ........................................................................................... 138
11.4.13 Receive SW CAS ........................................................................................................................... 139
11.4.14 Interrupt Controller ......................................................................................................................... 140
11.4.15 Packet Classifier ............................................................................................................................ 147
11.4.16 Ethernet MAC................................................................................................................................. 148
12. JTAG INFORMATION ....................................................................................................................158
13. DC ELECTRICAL CHARACTERISTICS ........................................................................................163
14. AC TIMING CHARACTERISTICS ..................................................................................................164
14.1 CPU INTERFACE TIMING ..............................................................................................................164
14.2 SPI INTERFACE TIMING ................................................................................................................165
14.3 SDRAM INTERFACE TIMING .........................................................................................................166
14.4 TDM-OVER-PACKET TDM INTERFACE TIMING ...............................................................................169
14.5 ETHERNET MII/RMII/SSMII INTERFACE TIMING .............................................................................172
14.6 CLAD AND SYSTEM CLOCK TIMING ..............................................................................................174
14.7 JTAG INTERFACE TIMING ............................................................................................................175
15. APPLICATIONS .............................................................................................................................176
15.1 CONNECTING A SERIAL INTERFACE TRANSCEIVER .........................................................................176
15.2 CONNECTING AN ETHERNET PHY OR MAC ...................................................................................177
15.3 IMPLEMENTING CLOCK RECOVERY IN HIGH SPEED APPLICATIONS ..................................................179
15.4 CONNECTING A MOTOROLA MPC860 PROCESSOR .......................................................................179
15.4.1 Connecting the Bus Signals.............................................................................................................. 179
15.4.2 Connecting the H_READY_N Signal ................................................................................................ 182
15.5 W ORKING IN SPI MODE ...............................................................................................................183
15.6 CONNECTING SDRAM DEVICES ...................................................................................................183
16. PIN ASSIGNMENTS ......................................................................................................................184
16.1 BOARD DESIGN FOR MULTIPLE DS34S101/2/4 DEVICES ...............................................................184
16.2 DS34S101 PIN ASSIGNMENT.......................................................................................................190
16.3 DS34S102 PIN ASSIGNMENT.......................................................................................................191
16.4 DS34S104 PIN ASSIGNMENT.......................................................................................................192
16.5 DS34S108 PIN ASSIGNMENT.......................................................................................................193
17. PACKAGE INFORMATION............................................................................................................197
18. THERMAL INFORMATION ............................................................................................................197
19. DATA SHEET REVISION HISTORY ..............................................................................................198
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List of Figures
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 12
Figure 5-2. TDMoP in Cellular Backhaul............................................................................................................... 13
Figure 6-1. Top-Level Block Diagram ................................................................................................................... 14
Figure 10-1. CPU Interface Functional Diagram .................................................................................................. 28
Figure 10-2. Write Access, 32-Bit Bus ................................................................................................................. 29
Figure 10-3. Read Access, 32-Bit Bus................................................................................................................. 30
Figure 10-4. Read/Write Access, 16-Bit Bus........................................................................................................ 30
Figure 10-5. Write Access to the SDRAM, 16-Bit Bus .......................................................................................... 31
Figure 10-6. Read Access to the SDRAM, 16-Bit Bus.......................................................................................... 31
Figure 10-7. SPI Interface with One Slave ........................................................................................................... 32
Figure 10-8. SPI Interface Timing, SPI_CP=0 ..................................................................................................... 32
Figure 10-9. SPI Interface Timing, SPI_CP=1 ..................................................................................................... 32
Figure 10-10. TDM-over-Packet Encapsulation Formats...................................................................................... 38
Figure 10-11. Single VLAN Tag Format............................................................................................................... 39
Figure 10-12. Stacked VLAN Tag Format............................................................................................................ 39
Figure 10-13. UDP/IPv4 Header Format.............................................................................................................. 39
Figure 10-14. UDP/IPv6 Header Format.............................................................................................................. 40
Figure 10-15. MPLS Header Format ................................................................................................................... 41
Figure 10-16. MEF Header Format...................................................................................................................... 41
Figure 10-17. L2TPv3/IPv4 Header Format ......................................................................................................... 42
Figure 10-18. L2TPv3/IPv6 Header Format ......................................................................................................... 43
Figure 10-19. Control Word Format ..................................................................................................................... 43
Figure 10-20. RTP Header Format ...................................................................................................................... 44
Figure 10-21. VCCV OAM Packet Format ........................................................................................................... 45
Figure 10-22. UDP/IP-Specific OAM Packet Format ............................................................................................ 46
Figure 10-23. TDM Connectivity over a PSN ....................................................................................................... 47
Figure 10-24. TDMoP Packet Format in a Typical Application ............................................................................. 47
Figure 10-25. TDMoMPLS Packet Format in a Typical Application ...................................................................... 48
Figure 10-26. CAS Transmitted in the TDM-to-Ethernet Direction ........................................................................ 50
Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces ..................................................... 51
Figure 10-28. Transmit SW CAS Table Format for T1-SF Interfaces.................................................................... 51
Figure 10-29. E1 MF Interface RSIG Timing Diagram (two_clocks=1) ................................................................. 51
Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0) ................................................................ 52
Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram ............................................................... 52
Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction ........................................................................ 53
Figure 10-33. E1 MF Interface TSIG Timing Diagram .......................................................................................... 54
Figure 10-34. T1 ESF Interface TSIG Timing Diagram ........................................................................................ 54
Figure 10-35. T1 SF Interface TSIG Timing Diagram ........................................................................................... 54
Figure 10-36. AAL1 Mapping, General ................................................................................................................ 55
Figure 10-37. AAL1 Mapping, Structured-Without-CAS Bundles .......................................................................... 56
Figure 10-38. HDLC Mapping ............................................................................................................................. 57
Figure 10-39. SAToP Unstructured Packet Mapping............................................................................................ 58
Figure 10-40. CESoPSN Structured-Without-CAS Mapping................................................................................. 59
Figure 10-41. CESoPSN Structured-With-CAS Mapping (No Frag, E1 Example) ................................................. 59
Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example) ......................................... 60
Figure 10-43. CESoPSN Structured-With-CAS Mapping (No Frag, T1-SF Example) ........................................... 60
Figure 10-44. CESoPSN Structured-With-CAS Mapping (Frag, E1 Example) ...................................................... 61
Figure 10-45. SDRAM Access through the SDRAM Controller............................................................................. 63
Figure 10-46. Loop Timing in TDM Networks....................................................................................................... 63
Figure 10-47. Timing in TDM-over-Packet ........................................................................................................... 64
Figure 10-48. Jitter Buffer Parameters................................................................................................................. 65
Figure 10-49. TDM-over-Packet Data Flow Diagram ........................................................................................... 67
Figure 10-50. Free Buffer Pool Operation ............................................................................................................ 71
Figure 10-51. TDM-to-Ethernet Flow ................................................................................................................... 72
Figure 10-52. Ethernet-to-TDM Flow ................................................................................................................... 73
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Figure 10-53. TDM-to-TDM Flow......................................................................................................................... 74
Figure 10-54. TDM-to-CPU Flow ......................................................................................................................... 75
Figure 10-55. CPU-to-TDM Flow ......................................................................................................................... 76
Figure 10-56. CPU-to-Ethernet Flow ................................................................................................................... 77
Figure 10-57. Ethernet-to-CPU Flow ................................................................................................................... 78
Figure 10-59. Ethernet MAC ............................................................................................................................... 79
Figure 10-60. Format of TDMoIP Packet with VLAN Tag ..................................................................................... 82
Figure 10-61. Format of TDMoMPLS Packet with VLAN Tag ............................................................................... 82
Figure 10-62. Format of TDMoMEF Packet with VLAN Tag ................................................................................. 82
Figure 10-63. Structure of Packets with Trailer .................................................................................................... 85
Figure 11-1. 16-Bit Addressing ............................................................................................................................ 89
Figure 11-2. 32-Bit Addressing ............................................................................................................................ 89
Figure 11-3. Partial Data Elements (shorter than 16 bits)..................................................................................... 89
Figure 11-4. Partial Data Elements (16 to 32 bits long) ........................................................................................ 90
Figure 12-1. JTAG Block Diagram ..................................................................................................................... 158
Figure 12-2. JTAG TAP Controller State Machine ............................................................................................. 159
Figure 14-1. RST_SYS_N Timing...................................................................................................................... 164
Figure 14-2. CPU Interface Write Cycle Timing ................................................................................................. 165
Figure 14-3. CPU Interface Read Cycle Timing ................................................................................................. 165
Figure 14-4. SPI interface Timing (SPI_CP = 0) ................................................................................................ 166
Figure 14-5. SPI interface Timing (SPI_CP = 1) ................................................................................................ 166
Figure 14-6. SDRAM Interface Write Cycle Timing ............................................................................................ 167
Figure 14-7. SDRAM Interface Read Cycle Timing ............................................................................................ 168
Figure 14-8. TDMoP TDM Timing, One-Clock Mode (Two_clocks=0, Tx_sample=1) ......................................... 169
Figure 14-9. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0) ......................................... 170
Figure 14-10. TDMoP TDM Timing, Two Clock Mode (Two_clocks=1, Tx_sample=1, Rx_sample=1) ................ 170
Figure 14-11. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=0)............... 170
Figure 14-12. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1)............... 171
Figure 14-13. TDMoP TDM Timing,Two Clocks Mode (Two_clocks=1, Tx_sample=1, Rx_sample=0)................ 171
Figure 14-14. MII Management Interface Timing ............................................................................................... 172
Figure 14-15. MII Interface Output Signal Timing............................................................................................... 172
Figure 14-16. MII Interface Input Signal Timing ................................................................................................. 173
Figure 14-17. RMII Interface Output Signal Timing ............................................................................................ 173
Figure 14-18. RMII Interface Input Signal Timing ............................................................................................... 173
Figure 14-19. SSMII Interface Output Signal Timing .......................................................................................... 174
Figure 14-20. SSMII Interface Input Signal Timing............................................................................................. 174
Figure 14-21. JTAG Interface Timing Diagram .................................................................................................. 175
Figure 15-1. Connecting Port 1 to a Serial Transceiver...................................................................................... 176
Figure 15-2. Connecting the Ethernet Port to a PHY in MII Mode ...................................................................... 177
Figure 15-3. Connecting the Ethernet Port to a MAC in MII Mode ...................................................................... 177
Figure 15-4. Connecting the Ethernet Port to a PHY in RMII Mode .................................................................... 177
Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode ................................................................... 178
Figure 15-6. Connecting the Ethernet Port to a PHY in SSMII Mode.................................................................. 178
Figure 15-7. Connecting the Ethernet Port to a MAC in SSMII Mode ................................................................. 178
Figure 15-8. External Clock Multiplier for High Speed Applications .................................................................... 179
Figure 15-9. 32-Bit CPU Bus Connections......................................................................................................... 180
Figure 15-10. 16-Bit CPU Bus Connections....................................................................................................... 181
Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin ....................................................... 182
Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock..................................... 182
Figure 16-1. DS34S101 Pin Assignment (TE-CSBGA Package) ........................................................................ 190
Figure 16-2. DS34S102 Pin Assignment (TE-CSBGA Package) ........................................................................ 191
Figure 16-3. DS34S104 Pin Assignment (TE-CSBGA Package) ........................................................................ 192
Figure 16-4. DS34S108 Pin Assignment (HSBGA Package) ............................................................................. 196
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List of Tables
Table 3-1. Applicable Standards ......................................................................................................................... 10
Table 9-1. Short Pin Descriptions ........................................................................................................................ 18
Table 9-2. TDM-over-Packet Engine TDM Interface Pins..................................................................................... 20
Table 9-3. SDRAM Interface Pins........................................................................................................................ 22
Table 9-4. Ethernet PHY Interface Pins (MII/RMII/SSMII) .................................................................................... 23
Table 9-5. Global Clock Pins ............................................................................................................................... 24
Table 9-6. CPU Interface Pins............................................................................................................................. 25
Table 9-7. JTAG Interface Pins ........................................................................................................................... 27
Table 9-8. Reset and Factory Test Pins .............................................................................................................. 27
Table 9-9. Power and Ground Pins ..................................................................................................................... 27
Table 10-1. CPU Data Bus Widths ...................................................................................................................... 29
Table 10-2. SPI Write Command Sequence ........................................................................................................ 34
Table 10-3. SPI_ Read Command Sequence ...................................................................................................... 35
Table 10-4. SPI Status Command Sequence ...................................................................................................... 36
Table 10-5. Reset Functions ............................................................................................................................... 37
Table 10-6. Ethernet Packet Fields ..................................................................................................................... 38
Table 10-7. IPv4 Header Fields (UDP) ................................................................................................................ 40
Table 10-8. UDP Header Fields .......................................................................................................................... 40
Table 10-9. IPv6 Header Fields (UDP) ................................................................................................................ 41
Table 10-10. MPLS Header Fields ...................................................................................................................... 41
Table 10-11. MEF Header Fields ........................................................................................................................ 41
Table 10-12. IPv4 Header Fields (L2TPv3).......................................................................................................... 42
Table 10-13. L2TPv3 Header Fields .................................................................................................................... 42
Table 10-14. IPv6 Header Fields (L2TPv3).......................................................................................................... 43
Table 10-15. Control Word Fields........................................................................................................................ 43
Table 10-16. RTP Header Fields ......................................................................................................................... 44
Table 10-17. VCCV OAM Payload Fields ............................................................................................................ 45
Table 10-18. UDP/IP-Specific OAM Payload Fields ............................................................................................. 46
Table 10-19. CAS – Supported Interface Connections for AAL1 and CESoPSN .................................................. 51
Table 10-20. CAS Handler Selector Decision Logic ............................................................................................. 52
Table 10-21. AAL1 Header Fields ....................................................................................................................... 55
Table 10-22. SDRAM Access Resolution ............................................................................................................ 62
Table 10-23. SDRAM CAS Latency vs. Frequency .............................................................................................. 62
Table 10-24. Buffer Descriptor First Dword Fields (Used for all Paths) ................................................................. 68
Table 10-25. Buffer Descriptor Second Dword Fields (TDM ETH and CPU ETH) ........................................ 69
Table 10-26. Buffer Descriptor Second Dword Fields (ETH CPU) ................................................................... 69
Table 10-27. Buffer Descriptor Third Dword Fields (ETH CPU) ....................................................................... 70
Table 10-29. Start of an 802.3 Pause Packet ...................................................................................................... 80
Table 10-30. Handling IPv4 and IPv6 Packets ..................................................................................................... 81
Table 10-31. TDMoIP Port Number Comparison for TDMoIP Packet Classification.............................................. 83
Table 10-32. Bundle Identifier Location and Width............................................................................................... 83
Table 11-1. Top-Level Memory Map.................................................................................................................... 90
Table 11-2. Global Registers............................................................................................................................... 91
Table 11-3. TDMoP Memory Map ....................................................................................................................... 93
Table 11-4. TDMoP Configuration Registers ....................................................................................................... 94
Table 11-5. TDMoP Status Registers .................................................................................................................. 94
Table 11-6. Counters Types .............................................................................................................................. 117
Table 11-7. CPU Queues .................................................................................................................................. 124
Table 11-8. Jitter Buffer Status Tables .............................................................................................................. 130
Table 11-9. Bundle Timeslot Tables .................................................................................................................. 130
Table 11-10. Transmit Software CAS Registers ................................................................................................ 134
Table 11-11. Receive Line CAS Registers......................................................................................................... 136
Table 11-12. Clock Recovery Registers ............................................................................................................ 137
Table 11-13. Receive SW Conditioning Octet Select Registers ......................................................................... 138
Table 11-14. Receive SW CAS Registers.......................................................................................................... 139
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Table 11-16. Interrupt Controller Registers ........................................................................................................ 140
Table 11-17. Packet Classifier OAM Identification Registers.............................................................................. 147
Table 11-18. Ethernet MAC Registers ............................................................................................................... 148
Table 11-19. Ethernet MAC Counters................................................................................................................ 153
Table 12-1. JTAG Instruction Codes ................................................................................................................. 161
Table 12-2. JTAG ID Code ................................................................................................................................ 161
Table 13-1. Recommended DC Operating Conditions ....................................................................................... 163
Table 13-2. DC Electrical Characteristics .......................................................................................................... 163
Table 14-1. Input Pin Transition Time Requirements ......................................................................................... 164
Table 14-2. CPU Interface AC characteristics.................................................................................................... 164
Table 14-3. SPI Interface AC Characteristics..................................................................................................... 165
Table 14-4. SDRAM Interface AC Characteristics.............................................................................................. 166
Table 14-5. TDMoP TDM Interface AC Characteristics ...................................................................................... 169
Table 14-6. TDMoP TDM Clock AC Characteristics........................................................................................... 169
Table 14-7. MII Management Interface AC Characteristics ................................................................................ 172
Table 14-8. MII Interface AC Characteristics ..................................................................................................... 172
Table 14-9. MII Clock Timing ............................................................................................................................ 172
Table 14-10. RMII Interface AC Characteristics ................................................................................................. 173
Table 14-11. RMII Clock Timing ........................................................................................................................ 173
Table 14-12. SSMII Interface AC Characteristics............................................................................................... 173
Table 14-13. SSMII Clock Timing ...................................................................................................................... 173
Table 14-14. CLAD1 and CLAD2 Input Clock Specifications.............................................................................. 174
Table 14-15. JTAG Interface Timing.................................................................................................................. 175
Table 15-1. SPI Mode I/O Connections ............................................................................................................. 183
Table 15-2. List of Suggested SDRAM Devices................................................................................................. 183
Table 16-1. Common Board Design Connections for DS34S101/2/4 (Sorted by Signal Name) .......................... 184
Table 16-2. DS34S108 Pin Assignment (Sorted by Signal Name) ..................................................................... 193
1. Introduction
The DS34S101/2/4/8 family of products provide single and multiport TDM-over-packet circuit emulation. Dedicated
payload-type engines are included for TDMoIP (AAL1), CESoPSN, SAToP, and HDLC.
Products in the DS34S10x family provide the mapping/demapping ability to enable the transport of TDM data
(Nx64kbps, E1, T1, J1, E3, T3, STS-1) over IP, MPLS or Ethernet networks. These products enable service
providers to migrate to next generation networks while continuing to provide legacy voice, data and leased-line
services. They allow enterprises to transport voice and video over the same IP/Ethernet network that is currently
used only for LAN traffic, thereby minimizing network maintenance and operating costs.
Packet-switched networks, such as IP networks, were not designed to transport TDM data and have no inherent
clock distribution mechanism. Therefore, when transporting TDM data over packet switched networks, the TDM
demapping function needs to accurately reconstruct the TDM service clock(s). The DS34S10x devices perform this
important clock recovery task, creating recovered clocks with jitter and wander levels that conform to ITU-T
G.823/824 and G.8261, even for networks which introduce significant packet delay variation and packet loss.
The circuit emulation technology in the DS34S10x products that makes this possible is called TDM-over-Packet
(TDMoP) and complements VoIP in those cases where VoIP is not applicable or where VoIP price/performance is
not sufficient. Most importantly, TDMoP technology provides higher voice quality with lower latency than VoIP.
Unlike VoIP, TDMoP can support all applications that run over E1/T1 circuits, not just voice. TDMoP can also
provide traditional leased-line services over IP and is transparent to protocols and signaling. Because TDMoP
provides an evolutionary, as opposed to revolutionary approach, investment protection is maximized.
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2. Acronyms and Glossary
Acronyms
AAL1
AAL2
ATM
BGA
BW
CAS
CBR
CCS
CE
CESoP
CESoPSN
CLAD
CPE
CSMA
CSMA/CD
DS0
DS1
DS3
HDLC
IEEE
IETF
IP
JBC
IWF
LAN
LOF
LOS
MAC
MEF
MFA
MII
MPLS
OC-3
OCXO
OFE
OSI
OSI-RM
PDH
PDU
PDV
PE
PRBS
PSN
PSTN
PWE3
QoS
RMII
Rx or RX
SAR
SAToP
SDH
SMII
SN
SONET
Rev: 032609
ATM Adaptation Layer Type 1
ATM Adaptation Layer Type 2
Asynchronous Transfer Mode
Ball Grid Array
Bandwidth
Channel Associated Signaling
Constant Bit-Rate
Common channel signaling
Customer Edge
Circuit Emulation Service over Packet
Circuit Emulation Services over Packet Switched Network
Clock Rate Adapter
Customer Premises Equipment
Carrier Sense Multiple Access
Carrier Sense Multiple Access with Collision Detection
Digital Signal Level 0
Digital Signal Level 1
Digital Signal Level 3
High-Level data Link Control
Institute of Electrical and Electronics Engineers
Internet Engineering Task Force
Internet Protocol
Jitter Buffer Control
Interworking Function
Local Area Network
Loss of Frame (i.e. loss of frame alignment)
Loss of Signal
Media Access Control
Metro Ethernet Forum
MPLS / Frame Relay Alliance (Now called IP/MPLS Forum)
Medium Independent Interface
MULTI PROTOCOL LABEL SWITCHING
Optical Carrier Level 3
Oven Controlled Crystal Oscillator
Optical Front End
Open Systems Interconnection
Open Systems Interconnection—Reference Model
Plesiochronous Digital Hierarchy
Protocol Data Unit
Packet Delay Variation
Provider Edge
Pseudo-Random Bit Sequence
Packet Switched Network
Public Switched Telephone Network
Pseudo-Wire Emulation Edge-to-Edge
Quality of Service
Reduced Medium Independent Interface
Receive
Segmentation and Reassembly
Structure-Agnostic TDM over Packet
Synchronous Digital Hierarchy
Serial Media Independent Interface
Sequence Number
Synchronous Optical Network
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SS7
SSMII
STM-1
TDM
TDMoIP
TDMoP
TSA
Tx or TX
UDP
VoIP
VPLS
WAN
Signaling System 7
Source Synchronous Serial Media Independent Interface
Synchronous Transport Module Level 1
Time Division Multiplexing
TDM over Internet Protocol
TDM over Packet
Timeslot Assigner
Transmit
User Datagram Protocol
Voice over IP
Virtual Private LAN Services
Wide Area Network
Glossary
bundle – a virtual path configured at two endpoint TDMoP gateways to carry TDM data over a PSN.
CLAD – Clock Rate Adapter, an analog PLL that creates an output clock signal that is phase/frequency locked to
an input clock signal of a different frequency. A CLAD is said to “convert” one frequency to another or “adapt”
(change) a clock’s rate to be a frequency that is useful to some other block on the chip.
dword – a 32-bit (4-byte) unit of information (also known as a doubleword)
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3. Applicable Standards
Table 3-1. Applicable Standards
SPECIFICATION
IEEE
IEEE 802.3
IEEE 1149.1
IETF
RFC 4553
RFC 4618
RFC 5086
RFC 5087
ITU-T
G.823
G.824
G.8261/Y.1361
I.363.1
I.363.2
I.366.2
O.151
O.161
Y.1413
Y.1414
Y.1452
Y.1453
MEF
MEF 8
MFA
MFA 4.0
MFA 5.0.0
MFA 8.0.0
Rev: 032609
SPECIFICATION TITLE
Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and
Physical Layer Specifications (2005)
Standard Test Access Port and Boundary-Scan Architecture, 1990
Structure-Agnostic Time Division Multiplexing (TDM) over Packet (SAToP) (06/2006)
Encapsulation Methods for Transport of PPP/High-Level Data Link Control (HDLC) over
MPLS Networks (09/2006)
Structure-Aware Time Division Multiplexed (TDM) Circuit Emulation Service over Packet
Switched Network (CESoPSN) (12/2007)
Time Division Multiplexing over IP (TDMoIP) (12/2007)
The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps
Hierarchy (03/2000)
The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps
Hierarchy (03/2000)
Timing and Synchronization Aspects in Packet Networks (05/2006)
B-ISDN ATM Adaptation Layer Specification: Type 1 AAL (08/1996)
B-ISDN ATM Adaptation Layer Specification: Type 2 AAL (11/2000)
AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services (11/2000)
Error Performance Measuring Equipment Operating at the Primary Rate and Above (1992)
In-service Code Violation Monitors for Digital Systems (1993)
TDM-MPLS Network Interworking – User Plane Interworking (03/2004)
Voice Services–MPLS Network Interworking (07/2004)
Voice Trunking over IP Networks (03/2006)
TDM-IP Interworking – User Plane Networking (03/2006)
Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet Networks
(10/2004)
TDM Transport over MPLS Using AAL1 (06/2003)
I.366.2 Voice Trunking Format over MPLS Implementation Agreement (08/2003)
Emulation of TDM Circuits over MPLS Using Raw Encapsulation – Implementation
Agreement (11/2004)
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4. Detailed Description
The DS34S108 is an 8-port TDM-over-Packet (TDMoP) IC. The DS34S104, DS34S102 and DS34S101 have the
same functionality as the DS34S108, except they have only 4, 2 or 1 ports, respectively. These sophisticated
devices can map and demap multiple E1/T1 data streams or a single E3/T3/STS-1 data stream to and from IP,
MPLS or Ethernet networks. A built-in MAC supports connectivity to a single 10/100 Mbps PHY over an MII, RMII
or SSMII interface. The DS34S10x devices are controlled through a 16 or 32-bit parallel bus interface or a highspeed SPI serial interface.
The TDM-over-Packet (TDMoP) core is the enabling block for circuit emulation and other network applications. It
performs transparent transport of legacy TDM traffic over Packet Switched-Networks (PSN). The TDMoP core
implements payload mapping methods such as AAL1 for circuit emulation, HDLC method, structure-agnostic
SAToP method, and the structure-aware CESoPSN method.
The AAL1 payload-type machine maps and demaps E1, T1, E3, T3, STS-1 and other serial data flows into and out
of IP, MPLS or Ethernet packets, according to the methods described in ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1
and IETF RFC 5087 (TDMoIP). It supports E1/T1 structured mode with or without CAS, using a timeslot size of 8
bits, or unstructured mode (carrying serial interfaces, unframed E1/T1 or E3/T3/STS-1 traffic).
The HDLC payload-type machine maps and demaps HDLC dataflows into and out of IP/MPLS packets according
to IETF RFC 4618 (excluding clause 5.3 – PPP) and IETF RFC 5087 (TDMoIP). It supports 2-, 7- and 8-bit timeslot
resolution (i.e. 16, 56, and 64 kbps respectively), as well as N × 64 kbps bundles (n=1 to 32). Supported
applications of this machine include trunking of HDLC-based traffic (such as Frame Relay) implementing Dynamic
Bandwidth Allocation over IP/MPLS networks and HDLC-based signaling interpretation (such as ISDN D-channel
signaling termination – BRI or PRI, V5.1/2, or GR-303).
The SAToP payload-type machine maps and demaps unframed E1, T1, E3 or T3 data flows into and out of IP,
MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553. It supports
E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing this to be the
simplest mapping/demapping method. The size of the payload is programmable for different services. This
emulation suits applications where the provider edges have no need to interpret TDM data or to participate in the
TDM signaling. The PSN network must have almost no packet loss and very low packet delay variation (PDV) for
this method.
The CESoPSN payload-type machine maps and demaps structured E1, T1, E3 or T3 data flows into and out of IP,
MPLS or Ethernet packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453,
MEF 8, MFA 8.0.0 and the IETF RFC 5086 (CESoPSN). It supports E1/T1/E3/T3 while taking into account the
TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e.
frame or multiframe). This method is less sensitive to PSN impairments but lost packets could still cause service
interruption.
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5. Application Examples
In Figure 5-1, a DS34S10x device is used in each TDMoP gateway to map TDM services into a packet-switched
metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc.
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network
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Figure 5-2. TDMoP in Cellular Backhaul
Other Possible Applications
Point-to-Multipoint TDM Connectivity over IP/Ethernet
The DS34S10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel
Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used
as a virtual cross-connect. Any bundle of timeslots can be directed to another remote location on the packet
domain.
HDLC Transport over IP/MPLS
TDM traffic streams often contain HDLC-based control channels and data traffic. These data streams, when
transported over a packet domain, should be treated differently than the time-sensitive TDM payload. DS34S10x
devices can terminate HDLC channels in the TDM streams and optionally map them into IP/MPLS/Ethernet for
transport. All HDLC-based control protocols (ISDN BRI and PRI, SS7 etc.) and all HDLC data traffic can be
managed and transported.
Using a Packet Backplane for Multiservice Concentrators
A communications device with all the above-mentioned capabilities can use a packet-based backplane instead of
the more expensive TDM bus option. This enables a cost-effective and future-proof design of communication
platforms with full support for both legacy and next-generation services.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
6. Block Diagram
SD_D[31:0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
SD_CLK
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
Data
Byte Enable Mask
Address
Bank Select
Control
CLK_HIGH
CLK_CMN
Figure 6-1. Top-Level Block Diagram
CLAD1
38.88MHz
2.048/1.544MHz
TDMoP Block
CLAD2
all 8 ports
TDMn_ACLK
TDMn_TX
TDMn_TCLK
Payload Type
Machines
Clock
Recovery
Machines
RAW
SAToP
TDMn_TX_SYNC
CESoPSN
TDMn_TX_MF_CD
TDMn_TSIG_CTS
Timeslot
Assigner
AAL1
TDMn_RCLK
CLK_SYS
Ethernet
MAC
10/100
MII_TX_ERR
MII_TX_EN
MII_TXD[3:0]
CLK_SSMII_TX
CLK_MII_TX
MII_CRS
MII_COL
MII_RX_ERR
MII_RX_DV
MII_RXD[3:0]
CLK_MII_RX
SDRAM
Controller
Jitter
Buffer
Control
HDLC
Packet
Classifier
Counters
& Status
Registers
Queue
Manager
TDMn_RX
CLK_SYS_S
50 or 75MHz
TDMn_RX_SYNC
Rev: 032609
JTAG
SCAN
MBIST
RST_SYS_N
H_CS_N
H_R_W_N
H_WR_BE[0]_N / SPI_CLK
H_WR_BE[1]_N / SPI_MOSI
H_WR_BE[2]_N / SPI_SEL_N
H_WR_BE[3]_N / SPI_CI
H_READY_N
H_INT[1:0]
H_AD[24:1]
H_D[0] / SPI_MISO
H_D[31:1]
H_CPU_SPI_N
DATA_31_16_N
CPU
Interface
MDIO
MDC
HIZ_EN
SCEN
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
CAS
Handler
JTMS
JTCLK
JTDI
JTDO
JTRST_N
TDMn_RSIG_RTS
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7. FEATURES
Global Features
•
•
•
•
•
•
•
•
•
•
•
•
TDMoP Interfaces
o DS34S101: 1 E1/T1/serial TDM interface
o DS34S102: 2 E1/T1/serial TDM interfaces
o DS34S104: 4 E1/T1/serial TDM interfaces
o DS34S108: 8 E1/T1/serial TDM interfaces
o All four devices: optionally 1 high-speed E3/DS3/STS-1 TDM interface
o All four devices: each interface optionally configurable for serial operation for V.35 and RS530
Ethernet Interface
o One 10/100 Mbps port configurable for MII, RMII or SSMII interface format
o Half or full duplex operation
o VLAN support according to 802.1p and 802.1Q including stacked tags
o Fully compatible with IEEE 802.3 standard
End-to-end TDM synchronization through the IP/MPLS domain by on-chip, per-port TDM clock recovery
64 independent bundles/connections, each with its own:
o Transmit and receive queues
o Configurable jitter-buffer depth
o Connection-level redundancy, with traffic duplication option
Packet loss compensation and handling of misordered packets
Glueless SDRAM interface
Complies with MPLS-Frame Relay Alliance Implementation Agreements 4.1, 5.1 and 8.0
Complies with ITU-T standards Y.1413 and Y.1414.
Complies with Metro Ethernet Forum 3 and 8
Complies with IETF RFC 4553 (SAToP), RFC 5086 (CESoPSN) and RFC 5087 (TDMoIP)
IEEE 1146.1 JTAG boundary scan
1.8V and 3.3V Operation with 5.0V tolerant I/O
Clock Synthesizers
•
•
Clocks to operate the TDMoP clock recovery machines can synthesized from a single clock input (10MHz,
19.44MHz, 38.88MHz or 77.76MHz on the CLK_HIGH pin)
Clock to operate TDMoP logic and SDRAM interface (50MHz or 75MHz) can be synthesized from a single
25MHz clock on the CLK_SYS pin
TDM-over-Packet Block
•
•
•
•
•
Enables transport of TDM services (E1, T1, E3, T3, STS-1) or serial data over packet-switched networks
SAToP payload-type machine maps/demaps unframed E1/T1/E3/T3/STS-1 or serial data flows to/from IP,
MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553.
CESoPSN payload-type machine maps/demaps structured E1/T1 data flows to/from IP, MPLS or Ethernet
packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453, MEF 8, MFA
8.0.0 and IETF RFC 5086.
AAL1 payload-type machine maps/demaps E1/T1/E3/T3/STS-1 or serial data flows to/from IP, MPLS or
Ethernet packets according to ITU-T Y.1413, MEF 8, MFA 4.1 and IETF RFC 5087. For E1/T1 it supports
structured mode with/without CAS using 8-bit timeslot resolution, while implementing static timeslot allocation.
For E1/T1, E3/T3/STS-1 or serial interface it supports unstructured mode.
HDLC payload-type machine maps/demaps HDLC-based E1/T1/serial flow to/from IP, MPLS or Ethernet
packets. It supports 2-, 7- and 8-bit timeslot resolution (i.e. 16, 56, and 64 kbps respectively), as well as N x 64
kbps bundles. This is useful in applications where HDLC-based signaling interpretation is required (such as
ISDN D channel signaling termination, V.51/2, or GR-303), or for trunking packet-based applications (such as
Frame Relay), according to IETF RFC 4618.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
TDMoP TDM Interfaces
•
•
•
•
•
Supports single high-speed E3, T3 or STS-1 interface on port 1 or one (DS34S101), two (DS34S102), four
(DS34S104) or eight (DS34S108) E1, T1 or serial interfaces
For single high-speed E3, T3 or STS-1 interface, AAL1 or SAToP payload type is used
For E1 or T1 interfaces, the following modes are available:
o Unframed – E1/T1 pass-through mode (AAL1, SAToP or HDLC payload type)
o Structured – fractional E1/T1 support (all payloads)
o Structured with CAS – fractional E1/T1 with CAS support (CESoPSN or AAL1 payload type)
For serial interfaces, the following modes are available:
o Arbitrary continuous bit stream (using AAL1 or SAToP payload type)
o Single-interface high-speed mode on port 1 up to STS-1 rate (51.84 Mbps) using a single
bundle/connection.
o Low-speed mode with each interface operating at N x 64 kbps (N = 1 to 63) with an aggregate rate of
18.6Mbps
o HDLC-based traffic (such as Frame Relay) at N x 64 kbps (N = 1 to 63) with an aggregate rate of
18.6Mbps).
All serial interface modes are capable of working with a gapped clock.
TDMoP Bundles
•
•
•
•
•
•
•
•
•
64 independent bundles, each can be assigned to any TDM interface
Each bundle carries a data stream from one TDM interface over IP/MPLS/Ethernet PSN from TDMoP source
device to TDMoP destination device
Each bundle may be for N x 64kbps, an entire E1, T1, E3, T3 or STS-1, or an arbitrary serial data stream
Each bundle is unidirectional (but frequently coupled with opposite-direction bundle for bidirectional
communication)
Multiple bundles can be transported between TDMoP devices
Multiple bundles can be assigned to the same TDM interface
Each bundle is independently configured with its own:
o Transmit and receive queues
o Configurable receive-buffer depth
o Optional connection-level redundancy (SAToP, AAL1, CESoPSN only).
Each bundle can be assigned to one of the payload-type machines or to the CPU
For E1/T1 the device provides internal bundle cross-connect functionality, with DS0 resolution
TDMoP Clock Recovery
•
•
•
Sophisticated TDM clock recovery machines, one for each TDM interface, allow end-to-end TDM clock
synchronization, despite the packet delay variation of the IP/MPLS/Ethernet network
The following clock recovery modes are supported:
o Adaptive clock recovery
o Common clock (using RTP)
o External clock
o Loopback clock
The clock recovery machines provide both fast frequency acquisition and highly accurate phase tracking:
o Jitter and wander of the recovered clock are maintained at levels that conform to G.823/G.824 traffic or
synchronization interfaces. (For adaptive clock recovery, the recovered clock performance depends on
packet network characteristics.)
o Short-term frequency accuracy (1 second) is better than 16 ppb (using OCXO reference), or 100 ppb
(using TCXO reference)
o Capture range is ±90 ppm
o Internal synthesizer frequency resolution of 0.5 ppb
o High resilience to packet loss and misordering, up to 2% without degradation of clock recovery
performance
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
o
o
Robust to sudden significant constant delay changes
Automatic transition to holdover when link break is detected
TDMoP Delay Variation Compensation
•
•
•
•
Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network
Large maximum jitter buffer depths:
o E1: up to 256 ms
o T1 unframed: up to 340 ms
o T1 framed: up to 256 ms
o T1 framed with CAS: up to 192 ms
o E3: up to 60 ms
o T3: up to 45 ms
o STS-1: up to 40 ms.
Packet reordering is performed for SAToP and CESoPSN bundles within the range of the jitter buffer
Packet loss is compensated by inserting either a pre-configured conditioning value or the last received value.
TDMoP CAS Support
•
•
On-chip CAS handler terminates E1/T1 CAS when using AAL1/CESoPSN in structured-with-CAS mode.
CPU intervention is not required for CAS handling.
Test and Diagnostics
•
•
IEEE 1149.1 JTAG support
MBIST (memory built-in self test)
CPU Interface
•
•
•
•
•
•
•
32 or 16-bit parallel interface or optional SPI serial interface
Byte write enable pins for single-byte write resolution
Hardware reset pin
Software reset supported
Software access to device ID and silicon revision
On-chip SDRAM controller provides access to SDRAM for both the chip and the CPU
CPU can access transmit and receive buffers in SDRAM used for packets to/from the CPU (ARP, SNMP, etc.)
8. OVERVIEW OF MAJOR OPERATIONAL MODES
Globally, the resources of the device can be committed to either one high-speed E3, T3 or STS-1 TDM stream
(high-speed mode) or one or more E1, T1 or serial streams (normal low-speed mode). In high-speed mode, the
TDM signal is carried using an unstructured AAL1 or SAToP mapping. High-speed mode is enabled by setting
General_cfg_reg0.High_speed=1.
In normal, low-speed mode, each port can be configured for E1, T1 or serial (e.g. V.35) operation. Ports configured
for E1 or T1 can be further configured for unframed, framed, or multiframed interface. In addition, each port can be
configured to have the transmit and receive directions clocked by independent clocks (two-clock mode) or to have
both directions clocked by the transmit clock (one-clock mode). All of this configuration is specified in the per-port
Port[n]_cfg_reg register.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
9. PIN DESCRIPTIONS
9.1 Short Pin Descriptions
Table 9-1. Short Pin Descriptions
PIN NAME(1)
TYPE(2)
TDM Interface
TDMn_ACLK
TDMn_TCLK
TDMn_TX
TDMn_TX_SYNC
TDMn_TX_MF_CD
TDMn_TSIG_CTS
TDMn_RCLK
TDMn_RX
TDMn_RX_SYNC
TDMn_RSIG_RTS
SDRAM Interface
SD_CLK
SD_D[31:0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
O
Ipu
O
Ipd
IOpd
O
Ipu
Ipu
Ipd
Ipu
O
IO
O
O
O
O
O
O
O
PIN DESCRIPTION
TDMoP Recovered Clock Output
TDMoP Transmit Clock Input (here transmit means “away from Ethernet MII”)
TDMoP Transmit Data Output
TDMoP Transmit Frame Sync Input
TDMoP Transmit Multiframe Sync Input or Carrier Detect Output
TDMoP Transmit Signaling Output or Clear to Send Output
TDMoP Receive Clock Input (here receive means “toward Ethernet MII”)
TDMoP Receive Data Input
TDMoP Receive Frame/Multiframe Sync Input
TDMoP Receive Signaling Input or Request To Send Input
SDRAM Clock
SDRAM Data Bus
SDRAM Byte Enable Mask
SDRAM Address Bus
SDRAM Bank Select Outputs
SDRAM Chip Select (Active Low)
SDRAM Write Enable (Active Low)
SDRAM Row Address Strobe (Active Low)
SDRAM Column Address Strobe (Active Low)
Ethernet PHY Interface (MII/RMII/SSMII)
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[3:0]
MII_TX_EN
MII_TX_ERR
CLK_MII_RX
MII_RXD[3:0]
MII_RX_DV
MII_RX_ERR
MII_COL
MII_CRS
MDC
MDIO
Global Clocks
CLK_SYS_S
CLK_SYS
CLK_CMN
CLK_HIGH
CPU Interface
I
O
O
O
O
I
I
I
I
I
I
O
IOpu
I
I
I
I
MII Transmit Clock Input
SSMII Transmit Clock Output
MII Transmit Data Outputs
MII Transmit Enable Output
MII Transmit Error Output
MII Receive Clock Input
MII Receive Data Inputs
MII Receive Data Valid Input
MII Receive Error Input
MII Collision Input
MII Carrier Sense Input
PHY Management Clock Output
PHY Management Data Input/Output
System Clock Selection Input
System Clock Input: 25, 50 or 75MHz
Common Clock Input (for common clock mode also known as differential mode)
Clock High Input (for adaptive clock recovery machines and E1/T1 master clocks)
H_CPU_SPI_N
Ipu
Host Bus Interface (1=Parallel Bus, 0=SPI Bus)
DAT_32_16_N
H_D[31:1]
H_D[0] / SPI_MISO
H_AD[24:1]
H_CS_N
H_R_W_N / SPI_CP
H_WR_BE0_N / SPI_CLK
H_WR_BE1_N / SPI_MOSI
Ipu
IO
IO
I
I
I
I
I
Data Bus Width (1=32-bit , 0=16-bit)
Host Data Bus
Host Data LSb or SPI Data Output
Host Address Bus
Host Chip Select (Active Low)
Host Read/Write Control or SPI Clock Phase
Host Write Enable Byte 0 (Active Low) or SPI Clock
Host Write Enable Byte 1 (Active Low) or SPI Data Input
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PIN NAME(1)
H_WR_BE2_N / SPI_SEL_N
H_WR_BE3_N / SPI_CI
H_READY_N
H_INT
TYPE(2)
JTAG Interface
JTRST_N
JTCLK
JTMS
JTDI
JTDO
Reset and Factory Test Pins
RST_SYS_N
HIZ_N
SCEN
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
TEST_CLK
TST_CLD
Power and Ground
DVDDC
DVDDIO
DVSS
ACVDD1, ACVDD2
ACVSS1, ACVSS2
I
I
Oz
O
PIN DESCRIPTION
Host Write Enable Byte 2 or SPI Chip Select (Active Low)
Host Write Enable Byte 3 (Active Low) or SPI Clock Invert
Host Ready Output (Active Low)
Host Interrupt Output.
Ipu
I
Ipu
Ipu
Oz
JTAG Test Reset
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Ipu
I
Ipd
Ipd
I
O
O
O
I
System Reset (Active Low)
High Impedance Enable (Active Low)
Used for factory tests.
Used for factory tests.
Used for factory tests.
Used for factory tests.
Used for factory tests
Used for factory tests.
Used for factory tests. DS34S108 only.
P
P
P
P
P
1.8V Core Voltage for TDM-over-Packet Digital logic (17 pins)
3.3V for I/O Pins (16 pins)
Ground for TDM-over-Packet logic and I/O Pins (31 pins)
1.8V for CLAD Analog Circuits
Ground for CLAD Analog Circuits
Note 1:
In pin names, the suffix “n” stands for port number: n=1 to 8 for DS34S108; n=1 to 4 for DS34S104; n=2 for DS34S102; n=1 for
DS34S101. All pin names ending in “_N” are active low.
Note 2:
All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description.
PIN TYPES
I = input pin
IPD = input pin with internal 50kΩ pulldown to DVSS
IPU = input pin with internal 50kΩ pullup to DVDDIO
IO = input/output pin
IOPD = input/output pin with internal 50kΩ pulldown to DVSS
IOPU = input/output pin with internal 50kΩ pullup to DVDDIO
O = output pin
OZ = output pin that can be placed in a high-impedance state
P = power-supply or ground pin
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9.2 Detailed Pin Descriptions
Table 9-2. TDM-over-Packet Engine TDM Interface Pins
In this table, the transmit direction is the packet-to-TDM direction while the receive direction is the TDM-to-packet direction. See Figure 6-1.
(1)
PIN NAME
TDMn_ACLK
TDMn_TCLK
(2)
TYPE
O
8mA
Ipu
PIN DESCRIPTION
TDMoP Recovered Clock Output
The clock recovered by the TDMoP clock recovery machine is output on this pin.
TDM1_ACLK (port 1) is used in high speed E3/T3/STS1 mode.
TDMoP Transmit Clock Input
This signal clocks the transmit TDM interface of the TDMoP engine. Depending on
the value of Port[n]_cfg_reg:tx_sample, outputs TDMn_TX and TDMn_TSIG_CTS
are updated on the either the rising edge (0) or falling edge (1) of TDMn_TCLK.
Inputs TDMn_TX_SYNC and TDMn_TX_MF_CD are latched on the opposite
edge. See the timing diagrams in Figure 14-8 and Figure 14-9.
In one-clock mode, TDMn_TCLK also clocks the receive TDM interface of the
TDMoP engine. Depending on the value of Port[n]_cfg_reg:tx_sample, outputs
TDMn_RX, TDMn_RX_SYNC and TDMn_RSIG_RTS are updated on the either
the rising edge (0) or falling edge (1) of TDMn_TCLK.
TDMn_TX
TDMn_TX_SYNC
O
8mA
Ipd
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE=1).
Only TDM1_TCLK (port 1) is used in high speed E3/T3/STS1 mode
(General_cfg_reg0.High_speed=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Transmit Data Output
Serial data from the TDMoP engine is output on this pin.
This signal is clocked by TDMn_TCLK.
Only TDM1_TX (port 1) is used in high speed E3/T3/STS1 mode (i.e. when
General_cfg_reg0.High_speed=1).
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Transmit Frame Sync Input
Frame sync information is provided to the TDMoP engine from this pin. In twoclock mode, this signal specifies only transmit frame sync. In one-clock mode, this
signal specifies frame sync for both the transmit and receive directions.
The signal on this pin must pulse high for one TDMn_TCLK cycle when the first bit
of a frame is expected to present on the TDMn_TX pin (and the TDMn_RX pin in
one-clock mode). This pulse must be repeated every N*125µs where N is a
positive integer (example: if N=16, it pulses every 2ms).
TDMn_TX_MF_CD
IOpd
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Transmit Multiframe Sync Input
When the interface type is configured for E1 or T1, multiframe sync is provided to
the TDMoP engine from this pin. The signal on this pin must pulse high for one
TDMn_TCLK cycle when the first bit the multiframe is expected to be present on
the TDMn_TX pin.
TDMoP Transmit Carrier Detect Output
When the interface type is configured for serial, the carrier detect function of this
pin is active. When Port[n]_cfg_reg.CD_en=1, the state of this pin is controlled by
the value stored in Port[n]_cfg_reg.CD.
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PIN NAME(1)
TDMn_TSIG_CTS
TYPE(2)
O
8mA
PIN DESCRIPTION
Port[n]_cfg_reg.Int_type=specifies serial (00), E1 (01) or T1 (10).
Port[n]_cfg_reg.Int_type=specifies serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Transmit Signaling Output
When the interface type is configured for E1 or T1, the transmit signaling function
of this pin is active. Functional timing is shown in Figure 10-33 and Figure 10-34.
TDMoP Clear to Send Output
When the interface type is configured for serial, the clear-to-send function of this
pin is active. In this mode, the state of this pin is controlled by the value stored in
Port[n]_cfg_reg.CTS.
TDMn_RCLK
Ipu
Port[n]_cfg_reg.Int_type specifies serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Receive Clock Input
In two-clock mode, this signal clocks the receive TDM interface of the TDMoP
engine: TDMn_RX, TDMn_RX_SYNC and TDMn_RSIG_RTS.
In one-clock mode, this signal is ignored, and the TDMn_TCLK signal clocks both
the transmit and receive interfaces of the TDMoP engine.
TDMn_RX
TDMn_RX_SYNC
Ipu
Ipd
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
Port[n]_cfg_reg.Rx_sample specifies latching on the rising (1) or falling (0) edge.
TDM1_RCLK (port 1) is used in high speed E3/T3/STS1 mode.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Receive Data Input
Serial data to the TDMoP engine is input on this pin.
In two-clock mode, this signal is clocked by TDMn_RCLK.
In one-clock mode, this signal, is clocked by TDMn_TCLK.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
TDM1_RX (port 1) is used in high speed E3/T3/STS1 mode.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Receive Frame/Multiframe Sync Input
In two-clock mode, this signal is clocked by TDMn_RCLK and specifies frame or
multiframe alignment for the receive interface of the TDMoP engine. The signal on
this pin must pulse high for one TDMn_RCLK cycle when the first bit of a frame is
present on the TDMn_RX pin. This pulse must be repeated every N*125µs where
N is a positive integer (example: if N=16, it pulses every 2ms).
In one-clock mode, this signal is ignored and TDMn_TX_SYNC specifies frame
alignment for both the transmit and receive interfaces of the TDMoP engine.
TDMn_RSIG_RTS
Rev: 032609
Ipu
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
TDMoP Receive Signaling Input
When the interface type is configured for E1 or T1, the transmit signaling function
of this pin is active.
In two-clock mode, this signal is clocked by TDMn_RCLK.
In one-clock mode, this signal, is clocked by TDMn_TCLK.
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PIN NAME(1)
TYPE(2)
PIN DESCRIPTION
TDMoP Request To Send Input
When the interface type is configured for serial, the request-to-send function of this
pin is active. In this mode, the real-time status of this pin can be read from
Port[n]_stat_reg1.RTS_P.
Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0).
Port[n]_cfg_reg.Int_type specifies serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE=1).
See the timing diagrams in Figure 14-8 through Figure 14-13.
Table 9-3. SDRAM Interface Pins
(1)
(2)
PIN NAME
TYPE
PIN DESCRIPTION
SDRAM Clock
SD_CLK
O
8mA
All SDRAM interface pins are updated or latched on the rising edge of SD_CLK.
See the timing diagrams in Figure 14-6 and Figure 14-7.
SDRAM Data
SD_D[31:0]
IO
8mA
MSB is SD_D[31].
SDRAM Byte Enable Mask
SD_DQM[3:0]
O
8mA
SD_DQM[0] is associated with the least significant byte. SD_DQM[3] is associated
with the most significant byte. When a SD_DQM pin is high during a write cycle,
the associated byte is not written to SDRAM. When a SD_DQM pin is high during
a read cycle, the associated byte is not driven out of the SDRAM (the SD_D pins
remain high-Z).
SDRAM Address Bus
SD_A[11:0]
O
8mA
MSB is SD_A[11].
SDRAM Bank Select Outputs
SD_BA[1:0]
O
8mA
The external SDRAMs used by the device have their memory organized into four
banks. These pins specify the bank to be accessed. The bank must be specified
on the same SD_CLK edge that the row information is specified on SD_A[11:0].
SDRAM Chip Select (Active Low)
SD_CS_N
O
8mA
Driven low by the device to initiate a memory access (read or write) to the external
SDRAM.
SDRAM Write Enable (Active Low)
SD_WE_N
O
8mA
Driven low by the device when data is to be written to the external SDRAM. Left
high when data is to be read from the external SDRAM.
SDRAM Row Address Strobe (Active Low)
SD_RAS_N
O
8mA
Driven low by the device during SD_CLK cycles in which SD_A[11:0] indicates the
SDRAM row address.
SDRAM Column Address Strobe (Active Low)
SD_CAS_N
O
8mA
Driven low by the device during SD_CLK cycles in which SD_A[11:0] indicates the
SDRAM column address.
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Table 9-4. Ethernet PHY Interface Pins (MII/RMII/SSMII)
The PHY interface type is configured by General_cfg_reg0.MII_mode_select[1:0]. 00=MII, 01=Reduced MII (RMII), 11=Source Synchronous
Serial MII (SSMII). The MII interface is described in IEEE 802.3-2005 Section 22. The RMII interface is described in this document:
http://www.national.com/appinfo/networks/files/rmii_1_2.pdf. The Source Synchronous Serial MII is described in this document:
ftp://ftp-eng.cisco.com/smii/smii.pdf.
PIN NAME(1)
CLK_MII_TX
TYPE(2)
I
PIN DESCRIPTION
MII Transmit Clock Input
In MII mode a 25MHz clock must be applied to this pin to clock the transmit side of
the interface. MII_TXD[3:0], MII_TX_EN and MII_TX_ERR are clocked out of the
device on the rising edge of CLK_MII_TX. See the timing diagram in
Figure 14-15.
In RMII mode a 50MHz clock must be applied to this pin to clock the transmit side
of the interface. MII_TXD[3:2] and MII_TX_EN are clocked out of the device on the
rising edge of CLK_MII_TX. See the timing diagram in
Figure 14-17.
CLK_SSMII_TX
O
12ma
MII_TXD[3:0]
O
8mA
In SSMII mode, a 125MHz clock must be applied to this pin. This clock is the
reference for the CLK_SSMII_TX output.
SSMII Transmit Clock Output
In SSMII mode, the device provides a 125MHz clock on this pin to clock the
transmit side of the interface. MII_TXD[0] (SSMII_TXD) and MII_TXD[1]
(SSMII_TX_SYNC) are clocked out of the device on the rising edge of
CLK_MII_TX. See the timing diagram in Figure 14-19. This pin is not used in MII
and RMII modes.
MII Transmit Data Outputs
In MII mode, transmit data is passed to the PHY four bits at a time on
MII_TXD[3:0] on the rising edge of CLK_MII_TX. See the timing diagram in
Figure 14-15.
In RMII mode, transmit data is passed to the PHY two bits at a time on
MII_TXD[3:2] on the rising edge of CLK_MII_TX while MII_TXD[1:0] are not used.
See the timing diagram in
Figure 14-17.
MII_TX_EN
O
8mA
MII_TX_ERR
O
8mA
CLK_MII_RX
I
In SSMII mode, transmit data is passed to the PHY one bit at a time on MII_TXD[0]
(SSMII_TXD) on the rising edge of CLK_SSMII_TX. MII_TXD[1]
(SSMII_TX_SYNC) indicates 10-bit segment alignment of the serial data stream.
MII Transmit Enable Output
In MII mode and RMII, this pin serves as the transmit enable output. In SSMII
mode this pin is not used.
MI Transmit Error Output
In MII mode this pin serves as the transmit error output. In RMII and SSMII modes
this pin is not used.
MII Receive Clock Input
In MII mode a 25MHz clock must be applied to this pin. MII_RXD[3:0], MII_RX_DV,
and MII_RX_ERR are clocked into the device on the rising edge of CLK_MII_RX.
See the timing diagram in Figure 14-16.
In RMII mode this pin is not used, and a 50MHz clock applied to CLK_MII_TX
provides timing for both transmit and receive sides of the interface. MII_RXD[3:2],
MII_RX_DV and MII_RX_ERR are clocked into the device on the rising edge of
CLK_MII_TX. See the timing diagram in Figure 14-18.
In SSMII mode a 125MHz clock from the PHY must be applied to this pin.
MII_RXD[0] (SSMII_RXD) and MII_RXD[1] (SSMII_RX_SYNC) are clocked into
the device on the rising edge of CLK_MII_RX. See the timing diagram in
Figure 14-20.
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PIN NAME(1)
MII_RXD[3:0]
TYPE(2)
I
PIN DESCRIPTION
MII Receive Data Inputs
In MII mode, receive data comes from the PHY four bits at a time on MII_RXD[3:0],
on the rising edge of CLK_MII_RX. See the timing diagram in Figure 14-16.
In RMII mode, receive data comes from the PHY two bits at a time on
MII_RXD[3:2] and is latched on the rising edge of CLK_MII_TX. MII_RXD[1:0] are
not used. See the timing diagram in Figure 14-18.
MII_RX_DV
I
MII_RX_ERR
I
MII_COL
I
MII_CRS
I
MDC
O
8mA
MDIO
IOpu
8mA
In SSMII mode, received data comes from the PHY one bit at a time on
MII_RXD[0] (SSMII_RXD) on the rising edge of CLK_MII_RX. MII_RXD[1]
(SSMII_RX_SYNC) indicates 10-bit segment alignment of the serial data stream.
MII Receive Data Valid Input
In MII mode, this pin serves as the receive data valid input. In RMII mode, carrier
sense and receive data valid alternate on this pin. See the RMII spec for details. In
SSMII mode this pin is not used and should be pulled low or high.
MII Receive Error Input
In MII mode and RMII mode, this pin serves as the receive error input. In SSMII
mode this pin is not used and should be pulled low or high.
MII Collision Input
In MII mode this pin serves as the collision detection input. In RMII mode and
SSMII mode this pin is not used and should be pulled low or high.
MII Carrier Sense Input
In MII mode this pin serves as the carrier sense input. In RMII mode and SMII
mode this pin is not used and should be pulled low or high.
PHY Management Clock Output
This signal is the clock for the Ethernet PHY management interface, which
consists of MDC and MDIO. See the timing diagram in Figure 14-14.
PHY Management Data Input/Output
This signal is the serial data signal for the Ethernet PHY management interface,
which consists of MDC and MDIO. When MDIO is an output, it is updated on the
rising edge of MDC. When MDIO is an input, it is latched into the device on the
rising edge of MDC. See the timing diagram in Figure 14-14.
Table 9-5. Global Clock Pins
PIN NAME(1)
TYPE(2) PIN DESCRIPTION
System Clock Selection Input
CLK_SYS_S
Ipd
This pin specifies the frequency of the clock applied to the CLK_SYS pin. See
section 10.4.
0 = 50 or 75 MHz
1 = 25 MHz
System Clock Input
CLK_SYS
I
A 25 MHz, 50 MHz or 75 MHz clock (±50 ppm or better) must be applied to this pin
to clock TDM-over-Packet internal circuitry and the SDRAM interface (SD_CLK).
When a 25MHz clock is applied, it is internally multiplied by the CLAD2 block to
50MHz or 75MHz as specified by GCR1.SYSCLKS. The CLK_SYS_S pin specifies
whether the CLK_SYS signal is 25MHz (and therefore needs to multiplied up) or
50/75MHz (and therefore is used as-is). See section 10.4.
Common Clock Input
CLK_CMN
I
When the TDMoP engine is configured for common clock mode (also known as
differential mode), the common clock is applied to this pin. This clock signal has to
be a multiple of 8kHz and in the range of 1MHz to 25MHz. The frequency should
not be too close to an integer multiple of the service clock frequency. Based on
these criteria, the following frequencies are suggested:
For systems with access to a common SONET/SDH network, a frequency of 19.44
MHz (2430*8 kHz).
For systems with access to a common ATM network, 9.72 MHz (1215*8 kHz) or
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PIN NAME(1)
CLK_HIGH
TYPE(2)
I
PIN DESCRIPTION
19.44 MHz (2430*8 kHz).
For systems using GPS, 8.184 MHz (1023*8 kHz).
For systems connected by a single hop of 100 Mbit/s Ethernet where it is possible
to lock the physical layer clock, 25 MHz (3125*8 kHz).
For systems connected by a single hop of Gigabit Ethernet where it is possible to
lock to the physical layer clock, 10MHz (1250*8 kHz).
When a clock is not needed on this pin, pull it high or low. See section 10.4.
Clock High Input
A 10, 19.44, 38.88 or 77.76MHz clock can be applied to this pin. From the
CLK_HIGH signal, an on-chip frequency converter block (called a clock adapter or
CLAD, in this case CLAD1) produces the 38.88MHz reference clock required by
the clock recovery machines in the TDMoP block.
GCR1.FREQSEL specifies the frequency of the clock applied to CLK_HIGH.
When GCR1.CLK_HIGHD=1, the CLAD disables the 38.88MHz reference clock to
the clock recovery machines.
When clock recovery is not required (i.e. when none of the recovered clock outputs
TDMn_ACLK are used), CLK_HIGH can be held low.
The required quality of the CLK_HIGH signal is discussed in section 10.6.3.
Table 9-6. CPU Interface Pins
See the parallel interface timing diagrams in Figure 14-2 and Figure 14-3 and the SPI timing diagrams in Figure 14-4 and Figure 14-5.
PIN NAME(1)
H_CPU_SPI_N
TYPE(2)
Ipu
DAT_32_16_N
Ipu
H_D[31:1]
IO
8mA
H_D[0] /
SPI_MISO
IO
8mA
H_AD[24:1]
I
H_CS_N
I
H_R_W_N /
SPI_CP
I
PIN DESCRIPTION
Host Bus Interface
0 = SPI serial interface
1 = Parallel interface
Data Bus Width
0 = 16-bit
1 = 32-bit
In SPI bus mode this pin is ignored.
Host Data Bus
When the device is configured for a 32-bit parallel interface, H_D[31:0] are the
data I/O pins (HD[31] is the MSb). When the device is configured for a 16-bit
parallel interface, H_D[15:0] are the data I/O pins (HD[15] is the MSb) and
H_D[31:16] are ignored and should be pulled low or high. The DAT_32_16_N pin
specifies bus width. In SPI bus mode these pins are ignored.
H_D[0]: Host Data LSb
In parallel interface mode this pin is H_D[0], LSb of the data bus.
SPI_MISO: SPI Data Output (Master In Slave Out)
In SPI bus mode this pin is the SPI data output.
Host Address Bus
H_AD[24] is the MSb. When the host data bus is 32 bits (DAT_32_16_N=1),
H_AD[1] should be held low. In SPI bus mode these pins are ignored.
Host Chip Select (Active Low)
In parallel interface mode this pin must be asserted (low) to read or write internal
registers. In SPI bus mode this pin is ignored.
H_R_W_N: Host Read/Write Control
In parallel interface mode this pin controls whether an access to internal registers
is a read or a write.
SPI_CP: SPI Clock Phase
In SPI interface mode this pin specifies SPI clock phase. See the timing diagrams
in Figure 14-4 and Figure 14-5 for details.
0 = input data is latched on the leading edge of the SCLK pulse; output data is
updated on the trailing edge
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PIN NAME(1)
H_WR_BE0_N /
SPI_CLK
H_WR_BE1_N /
SPI_MOSI
H_WR_BE2_N /
SPI_SEL_N
H_WR_BE3_N /
SPI_CI
H_READY_N
TYPE(2)
I
I
I
I
O
8mA
PIN DESCRIPTION
1 = input data is latched on the trailing edge of the SCLK pulse; output data is
updated on the leading edge
H_WR_BE0_N: Host Write Enable Byte 0 (Active Low)
In parallel interface mode during a write access this pin specifies whether or not
byte 0 (H_D[7:0]) should be written to the device. This pin is active in both 32-bit
and 16-bit modes.
0 = write byte 0
1 = don’t write byte 0
SPI_CLK: SPI Clock
In SPI interface mode this pin is the clock for the interface.
H_WR_BE1_N: Host Write Enable Byte 1 (Active Low)
In parallel interface mode during a write access this pin specifies whether or not
byte 1 (H_D[15:8]) should be written to the device. This pin is active in both 32-bit
and 16-bit modes.
0 = write byte 1
1 = don’t write byte 1
SPI_MOSI: SPI Data Input (Master Out Slave In)
In SPI interface mode this pin is the data input pin for the interface.
H_WR_BE2_N: Host Write Enable Byte 2 (Active Low)
In 32-bit parallel interface mode during a write access this pin specifies whether or
not byte 2 (H_D[15:8]) should be written to the device. In 16-bit parallel interface
mode this pin is ignored and should be pulled high or low.
0 = write byte 2
1 = don’t write byte 2
SPI_SEL: SPI Chip Select (Active Low)
In SPI interface mode this pin must be asserted (low) to read or write internal
registers.
H_WR_BE3_N: Host Write Enable Byte 3 (Active Low)
In 32-bit parallel interface mode during a write access this pin specifies whether or
not byte 3 (H_D[15:8]) should be written to the device. In 16-bit parallel interface
mode this pin is ignored and should be pulled high or low.
0 = write byte 3
1 = don’t write byte 3
SPI_CI: SPI Clock Invert
In SPI interface mode this pin specifies the polarity of the SPI_CLK pin. See the
timing diagrams in Figure 14-4 and Figure 14-5 for details.
0 = SPI_CLK is normally low and pulses high (leading edge is rising edge)
1 = SPI_CLK is normally high and pulses low (leading edge is falling edge)
Host Ready Output (Active Low)
In parallel interface mode the device pulls this pin low during a read or write
access to signal that the device is ready for the access to be completed. The host
processor should not pull H_CS_N high (inactive) to complete the access until the device
has pulled H_READY_N low.
H_INT
Rev: 032609
O
8mA
This pin requires the use of an external pull-up resistor. The device actively drives
this pin high before allowing it to go high-impedance. See Figure 14-2.
Host Interrupt Output (Active Low)
This pin indicates interrupt requests from the device. When GCR1.IPI=1, H_INT is
forced high (inactive). See section 10.9.
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Table 9-7. JTAG Interface Pins
See the JTAG interface timing diagram in Figure 14-21.
PIN NAME(1)
JTRST_N
TYPE(2)
Ipu
JTCLK
I
JTMS
Ipu
JTDI
Ipu
JTDO
Oz
8mA
PIN DESCRIPTION
JTAG Test Reset (Active Low)
This signal is used to asynchronously reset the test access port controller. After
power up, JTRST_N must be toggled from low to high. This action sets the device
into the JTAG DEVICE ID mode. Pulling JTRST_N low restores normal device
operation. If boundary scan is not used, this pin should be held low.
JTAG Test Clock
This signal is used to shift data into JTDI on the rising edge and out of JTDO on
the falling edge.
JTAG Test Mode Select
This pin is sampled on the rising edge of JTCLK and is used to place the test
access port into the various defined IEEE 1149.1 states. If not used, JTMS should
be held high.
JTAG Test Data Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. If
not used, JTDI can be held low or high (DVDDIO).
JTAG Test Data Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK.
If not used, this pin should be left unconnected.
Table 9-8. Reset and Factory Test Pins
(1)
(2)
PIN NAME
TYPE
PIN DESCRIPTION
System Reset (Active Low)
RST_SYS_N
Ipu
When this pin is held low the entire device is reset. This pin should be held low
(active) for at least 200 µs before going inactive. CLK_SYS and CLK_HIGH should
be stable for at least 200 µs before RST_SYS_N goes inactive. See section 10.5
for more information on system resets and block-level resets.
High Impedance Enable (Active Low)
HIZ_N
I
When this signal is low while JTRST_N is low, all of the digital output and bidirectional pins are placed in the high impedance state. For normal operation this
signal is high. This is an asynchronous input.
SCEN
I
Used during factory test. This pin should be tied to DVSS.
STMD
I
Used during factory test. This pin should be tied to DVSS.
MBIST_EN
I
Used during factory test. This pin should be tied to DVSS.
MBIST_DONE
O
Used during factory test. This pin should be left floating.
MBIST_FAIL
O
Used during factory test. This pin should be left floating.
TEST_CLK
O
Used during factory test. This pin should be left floating.
TST_CLD
I
Used during factory test. This pin should be tied to DVSS.
Table 9-9. Power and Ground Pins
(1)
(2)
PIN NAME
TYPE
PIN DESCRIPTION
DVDDC
P
1.8V Core Voltage for TDM-over-Packet Digital Logic (17 pins)
DVDDIO
P
3.3V for I/O Pins (16 pins)
DVSS
P
Ground for TDM-over-Packet Logic and I/O Pins (31 pins)
ACVDD1
P
1.8V for CLAD Analog Circuits
ACVDD2
P
1.8V for CLAD Analog Circuits
ACVSS1
P
Ground for CLAD Analog Circuits
ACVSS2
P
Ground for CLAD Analog Circuits
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10. Functional Description
10.1 Power-Supply Considerations
Due to the dual-power-supply nature of the device, some I/Os have parasitic diodes between a 1.8V supply and a
3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes
because it could cause latchup. Two methods are available to prevent this. The first method is to place a Schottky
diode external to the device between the 1.8V supply and the 3.3V supply to force the 3.3V supply to be within one
parasitic diode drop below the 1.8V supply (i.e. VDD3.3 > VDD1.8 – 0.4V). The second method is to ramp up the
3.3V supply first and then ramp up the 1.8V supply.
10.2 CPU Interface
The CPU interface enables an external CPU to configure and control the device and collect statistics from the
device. The CPU interface block identifies accesses (read or write) to on-chip registers and to external SDRAM,
forwards accesses to the proper place, and replies to the CPU with the requested data during read accesses. See
Figure 10-1. AC timing for the CPU interface is specified in section 14.1.
Figure 10-1. CPU Interface Functional Diagram
SDRAM
DS34T10x
SDRAM
CONTROLLER
ACCESS
WITHIN CHIP
DATA
CONTROL
CPU BUS
ADDRESS
H_INT[1:0]
CPU INTERFACE
CPU
To configure the device for CPU interface mode, the H_CPU_SPI_N pin must be high when the RST_SYS_N
(system reset) pin is deasserted. The chip can be configured for 16-bit or 32-bit data bus width by wiring the
DAT_32_16_N pin as shown in Table 10-1:
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Table 10-1. CPU Data Bus Widths
Access to
DAT_32_16_N
Data Bus
Chip Internal
Value
Width
Resources
1
0
32 bits
16 bits
32 bit only
16 bit only
Access to
SDRAM
Data Bus
Bits
MSB
H_WR_BE
Pins Used
8, 16, 32 bit
8, 16 bit
H_D[31:0]
H_D[15:0]
H_D[31]
H_D[15]
3:0
1:0
Burst accesses are not supported. The device uses the big-endian byte order, as explained in section 11.1.
The CPU starts an access to the device by asserting the H_CS_N signal (active low), accompanied by the desired
read/write state on H_R_W_N, address on H_AD[24:1], write byte enables on the H_WR_BE pins and valid data
(for a write access) on the H_D[31:0] pins. In response, the device asserts H_READY_N to indicate that the access
has been carried out. The ready assertion indicates that data from the CPU has been written into the device
register or external SDRAM (for write access) or that valid data from register/SDRAM is present on the data bus
(for read access). In response to H_READY_N assertion, the CPU de-asserts H_CS_N. This causes the chip to
de-assert H_READY_N, and thereby finish the CPU access.
In order to make CPU operation more efficient, the device immediately asserts H_READY_N during a write access.
On successive accesses (write or read) H_READY_N is asserted only after the previous write has been completed.
In 32-bit bus mode, H_WR_BE0_N through H_WR_BE3_N serve as write byte enable signals, replacing the
functionality of H_AD[1:0] in the address bus. In 16-bit bus mode, H_WR_BE0_N and H_WR_BE1_N serve as
write byte enables, replacing the functionality of H_AD[0] in the address bus. These signals enable byte-resolution
write access to the external SDRAM.
When performing a write access to internal chip resources, all H_WR_BE pins should be asserted since write
access to device registers must be done at the full bus width only.
Examples of read and write accesses on 32- and 16-bit buses are shown in the figures below.
Figure 10-2. Write Access, 32-Bit Bus
DAT_32_16_N[0]
32 bit data bus
H_CS_N[0]
H_AD[24:1]
cpu_addr[[1]='don't care'
cpu_addr[1]='don't care'
cpu_addr[1]='don't care'
H_R_W_N[0]
H_READY_N[0]
[0]
H_D[31:24]
SDRAM WRITE ACCESS
data ignored
SDRAM WRITE ACCESS
valid
INTERNAL
valid
H_D[23:16]
data ignored
valid
valid
H_D[15:8]
valid
data ignored
valid
H_D[7:0]
data_ignored
data ignored
valid
H_WR_BE3_N[0]
H_WR_BE2_N[0]
H_WR_BE1_N[0]
H_WR_BE0_N[0]
Figure 10-2 shows two write accesses to the SDRAM, one to a byte (at address 2) and the other to a word (at
addresses 0 and 1), followed by a write access to the internal chip resources.
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The write access to the SDRAM is different than the write access to the chip. The SDRAM can be written with byte
resolution using the four byte write enables. In contrast, internal chip resources are always written at full CPU data
bus width (32 bits in Figure 10-2). The write byte enable signals should always be asserted when writing to internal
device registers.
For 32-bit CPU bus width, H_AD[1] is ignored, since accesses are always on an even 4-byte boundary.
Figure 10-3 shows a read access to the SDRAM followed by a read access to the internal chip resources. Read
accesses always occur at CPU data bus width and the H_WR_BE pins are not used (and must be held high). Bytes
that are not needed by the CPU can be ignored.
Figure 10-3. Read Access, 32-Bit Bus
DAT_32_16_N[0]
32bit cpu data bus
H_CS_N[0]
H_AD[24:1]
cpu_addr[1]='don't care'
cpu_addr[1]='don't care'
H_R_W_N[0]
H_READY_N[0]
[0]
SDRAM READ ACCESS
valid
H_D[31:0]
valid
H_WR_BE3_N[0]
H_WR_BE2_N[0]
H_WR_BE1_N[0]
H_WR_BE0_N[0]
Figure 10-4 shows a write access to the chip followed by a read access in 16-bit bus mode. In this mode the
H_AD[1] signal is used because accesses are on an even 2-byte boundary. Write access to the SDRAM can still
be at byte resolution, as illustrated in Figure 10-5.
Figure 10-4. Read/Write Access, 16-Bit Bus
16 bit cpu data bus
DAT_32_16_N[0]
H_CS_N[0]
H_AD[24:1]
H_R_W_N[0]
[0]
H_D[15:0]
INTERNAL
valid
INTERNAL
valid
H_READY_N[0]
H_WR_BE1_N[0]
H_WR_BE0_N[0]
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Figure 10-5. Write Access to the SDRAM, 16-Bit Bus
16 bit data bus
DAT_32_16_N[0]
H_CS_N[0]
H_AD[24:1]
H_R_W_N[0]
H_READY_N[0]
[0]
H_D[15:8]
SDRAM WRITE ACCESS
valid
H_D[7:0]
data ignored
H_WR_BE1_N[0]
H_WR_BE0_N[0]
In 16-bit bus mode, read accesses to SDRAM are always 16 bits, as in Figure 10-6.
Figure 10-6. Read Access to the SDRAM, 16-Bit Bus
16 bit data bus
DAT_32_16_N[0]
H_CS_N[0]
H_AD[24:1]
H_R_W_N[0]
H_READY_N[0]
[0]
H_D[15:8]
SDRAM READ ACCESS
H_D[7:0]
valid
valid
H_WR_BE1_N[0]
H_WR_BE0_N[0]
10.3 SPI Interface
The device optionally can be accessed by an external CPU through a Serial Peripheral Interface (SPI). To
configure the device for SPI interface mode, the H_CPU_SPI_N pin must be low when the RST_SYS_N (system
reset) pin is deasserted. In SPI mode, some of the parallel CPU bus pins take on an SPI-related function while the
rest are disabled. See the CPU interface section of Table 9-1 for details. The device functions as an SPI slave.
10.3.1 SPI Operation
The SPI is a 4-wire, full-duplex, synchronous interface. The SPI connects an SPI master (which initiates the data
transfer) and an SPI slave.
The SPI signal wires are as follows:
•
SPI_CLK is the clock for the serial data (gated clock).
•
SPI_MOSI is master data output, slave data input.
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•
SPI_MISO is master data input, slave data output.
•
SPI_SEL_N is the slave chip select.
The master initiates a data transfer by asserting SPI_SEL_N (low) and generating a sequence of SPI_CLK cycles
accompanied by serial data on SPI_MOSI. During read cycles the slave outputs data on SPI_MISO. Each
additional slave requires an additional slave chip-select wire. Figure 10-7 illustrates a typical connection between
an SPI master and a single SPI slave.
Figure 10-7. SPI Interface with One Slave
SPI_CLK
SPI
Master
SPI_MOSI
SPI_MISO
SPI
Slave
SPI_SEL_N
10.3.2 SPI Modes
Two configuration pins define the SPI mode of operation.
•
The polarity of SPI_CLK is specified by the SPI_CI (clock invert) input pin.
•
The SPI_CP (clock phase) input pin determines whether the first SPI_CLK transition is used to sample the
data on SPI_MISO/SPI_MOSI (which requires the first bit to be ready beforehand on these lines) or to
updated the data on the SPI_MISO/SPI_MOSI lines. See Figure 10-8 and Figure 10-9.
Figure 10-8. SPI Interface Timing, SPI_CP=0
SPI_SEL_N
SPI_CLK(CI=0)
SPI_CLK(CI=1)
SPI_MOSI(input)
msb
lsb
SPI_MISO(output)
msb
lsb
Figure 10-9. SPI Interface Timing, SPI_CP=1
SPI_SEL_N
SPI_CLK(CI=0)
SPI_CLK(CI=1)
SPI_MOSI(input)
msb
SPI_MISO(output)
msb
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10.3.3 SPI Signals
In SPI mode, the following CPU bus pins change their functionality and operate as SPI signals.
•
•
Inputs
o
SPI_CLK is shared with H_WR_BE0_N
o
SPI_MOSI is shared with H_WR_BE1_N
o
SPI_SEL_N is shared with H_WR_BE2_N.
Outputs
o
SPI_MISO is shared with H_D[0].
The SPI configuration is supplied on two external pins as follows:
•
SPI_CI (clock invert) is shared with H_WR_BE3_N
•
SPI_CP (clock phase) is shared with H_R_W_N.
In the SPI mode the device operates internally in 32-bit mode.
10.3.4 SPI Protocol
The external CPU communicates with the device over SPI by issuing commands. There are three command types:
1. Write – performs 32-bit write access
2. Read – performs 32-bit read access
3. Status – verifies that previous access has been finished
The SPI_SEL_N signal must be de-asserted between accesses to the device.
10.3.4.1 Write Command
The SPI write command proceeds as follows:
•
The SPI master (CPU) starts a write access by asserting SPI_SEL_N (low).
•
Then, during each SPI_CLK cycle a SPI_MOSI data bit is transmitted by the master (CPU), while a
SPI_MISO bit is transmitted by the slave (the device).
•
The first bit on SPI_MOSI and SPI_MISO is reserved (don’t care).
•
The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status
command. The value 01b represents a write command. At the same time, the slave transmits the opcode
bits of the previous command on SPI_MISO.
•
The next four bits the master transmits on SPI_MOSI are byte-enable values: byte_en_3, byte_en_2,
byte_en_1, and byte_en_0 which are equivalent to the function of the H_WR_BE3_N to H_WR_BE0_N
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signals in CPU bus mode (including being active low). At the same time, the slave transmits the byte
enable values of the previous access on SPI_MISO.
•
The next bit on SPI_MOSI and SPI_MISO is reserved (don’t care).
•
The next 24 bits the master transmits on SPI_MOSI are address bits, starting from A24 (MSB) and ending
with A1 (LSB). At the same time, the slave transmits the address bits of the previous access on SPI_MISO.
•
The next 32 bits the master transmits on SPI_MOSI are 32 bits of data, starting from D31 (MSB) and
ending with D0 (LSB). At the same time, the slave transmits 32 don’t-care bits on SPI_MISO.
•
Finally the master transmits 8 don’t care bits on SPI_MOSI. During these clock periods the slave transmits
th
8 bits on SPI_MISO. The first 7 SPI_MISO bits are don’t-care. The 8 bit is a status bit that indicates
whether the last access was completed successfully (1) or is still in progress (0). The 0 value indicates that
the current operation has not yet completed and that the status command must follow (see section
10.3.4.3).
•
The master ends the write access by deasserting SPI_SEL_N.
The total number of SPI_CLK cycles for a write command is 72. This is summarized in Table 10-2.
Table 10-2. SPI Write Command Sequence
Bit Number
SPI_MOSI
SPI_MISO
1
Reserved
Reserved
2–3
opcode 01 (write)
Previous access opcode
4
H_WR_BE3_N value
Previous access H_WR_BE3_N value
5
H_WR_BE2_N value
Previous access H_WR_BE2_N value
6
H_WR_BE1_N value
Previous access H_WR_BE1_N value
7
H_WR_BE0_N value
Previous access H_WR_BE0_N value
8
Reserved
Reserved
9–32
Address [24 to 1]
Previous access address [24 to 1]
33–64
Data (32 bits)
Don’t care (32 bits)
65–71
Don’t care (7 bits)
Idle (7 bits)
72
Don’t care (1 bit)
Status bit: 1=access has finished, 0=access has not finished
10.3.4.2 Read Command
The SPI read command proceeds as follows:
•
The SPI master (CPU) starts a write access by asserting SPI_SEL_N (low).
•
Then, during each SPI_CLK cycle a SPI_MOSI data bit is transmitted by the master (CPU), while a
SPI_MISO bit is transmitted by the slave (the device).
•
The first bit on SPI_MOSI and SPI_MISO is reserved (don’t care).
•
The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status
command. The value 10b represents a read command. At the same time, the slave transmits the opcode
bits of the previous command on SPI_MISO.
•
The next four bits the master transmits on SPI_MOSI are byte-enable values: byte_en_3, byte_en_2,
byte_en_1, and byte_en_0 which are equivalent to the function of the H_WR_BE3_N to H_WR_BE0_N
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signals in CPU bus mode (including being active low). For a read access, all four of these bits should be 1.
At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO.
•
The next bit on SPI_MOSI and SPI_MISO is reserved (don’t care).
•
The next 24 bits the master transmits on SPI_MOSI are address bits, starting from A24 (MSB) and ending
with A1 (LSB). At the same time, the slave transmits the address bits of the previous access on SPI_MISO.
•
Next the master transmits 8 don’t care bits on SPI_MOSI. During these clock periods the slave transmits 8
th
bits on SPI_MISO. The first 7 SPI_MISO bits are don’t-care. The 8 bit is a status bit that indicates whether
the current read access was completed successfully (1) or is still in progress (0). Status=0 indicates that
the current operation has not yet completed and that the status command must follow (see section
10.3.4.3).
•
Status=1 indicates that the current read was completed successfully and 32 bits of data follow on
SPI_MISO, starting from D31 (MSB) and ending with D0 (LSB). During these 32 clock cycles, the master
transmits 32 don’t-care bits on SPI_MOSI.
•
Status=0 indicates that the current read was not completed and that the status command must follow (see
section 10.3.4.3). During the next 32 clock cycles both the master and the slave must transmit don’t-care
bits to complete the read command. These 32 bits should be ignored.
•
The master ends the write access by deasserting SPI_SEL_N.
The total number of SPI_CLK cycles for a read command is 72.
Table 10-3. SPI_ Read Command Sequence
Bit Number
SPI_MOSI
SPI_MISO
1
Reserved
Reserved
2–3
opcode 10 (read)
Previous access opcode
4
1
Previous access H_WR_BE3_N value
5
1
Previous access H_WR_BE2_N value
6
1
Previous access H_WR_BE1_N value
7
1
Previous access H_WR_BE0_N value
8
Reserved
Reserved
9–32
Address [24 to 1]
Previous access Address [24 to 1]
33–39
Don’t care
Idle (7 bits)
40
41–72
Don’t care
Don’t care
Status bit: 1=access has finished, 0=access has not finished
Data (32 bits)
10.3.4.3 Status Command
The status command differs from read or write commands, since it does not initiate an internal access. Usually a
status command follows a read or write command that was not completed as described above.
The SPI status command proceeds as follows:
•
The SPI master (CPU) starts a status command by asserting SPI_SEL_N (low).
•
Then, during each SPI_CLK cycle a SPI_MOSI data bit is transmitted by the master (CPU), while a
SPI_MISO bit is transmitted by the slave (the device).
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•
The first bit on SPI_MOSI and SPI_MISO is reserved (don’t care).
•
The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status
command. The value 00b represents a status command. At the same time, the slave transmits the opcode
bits of the previous command on SPI_MISO.
•
The master then transmits 4 don’t care bits on SPI_MOSI. During these clock periods the slave transmits 4
th
bits on SPI_MISO. The first 3 SPI_MISO bits are don’t-care. The 4 bit is a status bit that indicates whether
the last access was completed successfully (1) or is still in progress (0). The 0 value indicates that the last
access has not yet completed and that another status command must follow (see section 10.3.4.3).
•
Status=1 indicates that the last access was completed successfully. If the last access was a read then 32
bits of data follow on SPI_MISO, starting from D31 (MSB) and ending with D0 (LSB). During these 32 clock
cycles, the master transmits 32 don’t-care bits on SPI_MOSI. If the last access was a write the during the
next 32 clock cycles both the master and the slave must transmit don’t-care bits to complete the status
command. These 32 bits should be ignored.
•
Status=0 indicates that the last access was not completed and that another status command must follow.
During the next 32 clock cycles both the master and the slave must transmit don’t-care bits to complete the
status command. These 32 bits should be ignored.
•
The master ends the write access by deasserting SPI_SEL_N.
The total number of SPI_CLK cycles for a status command is 40.
Table 10-4. SPI Status Command Sequence
Bit Number
SPI_MOSI
SPI_MISO
1
Don’t care
Don’t care
2–3
opcode 00 (status)
Previous access opcode
4
Don’t care
Don’t care
5
Don’t care
Don’t care
6
Don’t care
Don’t care
7
Don’t care
Don’t care
8
Don’t care
Status bit: 1=access has finished, 0=access has not finished
9–40*
Don’t care*
Data*
* only if previous access was a read (previous access opcode = 10b).
10.4 Clock Structure
When clock recovery is enabled (Clock_recovery_en=1 in General_cfg_reg0), the clock recovery machines of the
TDM-over-packet block require a 38.88MHz clock. This clock can come directly from the CLK_HIGH pin, or the
CLAD1 block (see Figure 6-1) can convert a 10MHz, 19.44MHz or 77.76MHz clock on CLK_HIGH to 38.88MHz
using an analog PLL. The frequency of CLK_HIGH must be specified in GCR1.FREQSEL.
When common clock (differential) mode is enabled (RTP_timestamp_generation_mode=1 in General_cfg_reg1),
the clock recovery block requires a clock on the CLK_CMN pin in addition to the clock on the CLK_HIGH pin. See
the CLK_CMN pin description for recommendations for the frequency of this clock. Often the same clock signal can
be applied to both CLK_CMN and CLK_HIGH, for example 19.44MHz.
When clock recovery is disabled (Clock_recovery_en=0 in General_cfg_reg0), CPU software can disable the
38.88MHz clock output from CLAD1 to save power by setting GCR1.CLK_HIGHD. Clock recovery must be enabled
whenever the TDMoP block must recover one or more service clocks from received packets using either adaptive
mode or common clock (differential) mode.
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The TDM-over-packet block also requires a 50 MHz or 75 MHz clock (±50 ppm or better) to clock its internal
circuitry and the SDRAM interface (SD_CLK). When the CLK_SYS_S pin is low, a 50 MHz or 75 MHz clock applied
to the CLK_SYS pin is passed directly to the TDMoP block. When the CLK_SYS_S pin is high, a 25 MHz clock on
the CLK_SYS pin is internally multiplied by an analog PLL in the CLAD2 block to either 50 MHz or 75 MHz as
specified by GCR1.SYSCLKS.
10.5 Reset and Power-Down
A hardware reset is issued by forcing the RST_SYS_N pin low. This pin resets the TDM-over-Packet block and the
MAC. Note that not all registers are cleared to 0x00 on a reset condition. The register space must be reinitialized to
appropriate values after hardware or software reset has occurred. This includes setting reserved locations to 0.
Several block-specific resets are also available, as shown in Table 10-5.
Table 10-5. Reset Functions
RESET FUNCTION
LOCATION
Hardware Device Reset
RST_SYS_N Pin
Hardware JTAG Reset
JTRST_N Pin
Resets TDMoP TX, RX paths
Rst_reg
Resets the SDRAM controller
General_cfg_reg0
COMMENTS
Transition to a 200us or more logic 0 level resets the
device. CLK_SYS and CLK_HIGH/MCLK are
recommended to be stable 200us before transitioning
out of reset.
Resets the JTAG test port.
Used to reset the transmit (TX) and receive (RX) paths
of the TDM-over-Packet block.
The Rst_SDRAM_n bit resets the SDRAM controller.
10.6 TDM-over-Packet Block
10.6.1 Packet Formats
To transport TDM data through packet switched networks, the TDM-over-Packet block encapsulates the TDM data
into Ethernet packets as depicted in Figure 10-10.
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Figure 10-10. TDM-over-Packet Encapsulation Formats
OPTIONAL OPTIONAL
PREAMBLE
START OF FRAME
DELIMITER
DESTINATION
SOURCE
VLAN
VLAN
ADDRESS
ADDRESS
TAG 1
TAG 2
7 BYTES
1 BYTE
6 BYTES
6 BYTES
4 BYTES
TYPE
DATA
FRAME CHECK
SEQUENCE
AND
PADDING
4 BYTES 2 BYTES 46-1500 BYTES
4 BYTES
UDP / IPv4
HEADER
OPTIONAL
28 BYTES
RTP
HEADER
TDMoIP
CONTROL WORD
12 BYTES
4 BYTES
or
UDP / IPv6
HEADER
TDMoIP
PAYLOAD
48 BYTES
or
L2TPv3 / IPv4
HEADER
24, 28 or 32
BYTES
or
L2TPv3 / IPv6
OPTIONAL
HEADER
44, 48 or 52
BYTES
or
MEF
TDMoIP
CONTROL WORD
RTP
HEADER
4 BYTES
12 BYTES
TDMoIP
PAYLOAD
HEADER
4 BYTES
or
MPLS
HEADER
4, 8 or 12 BYTES
Table 10-6. Ethernet Packet Fields
Field
Preamble
Start of Frame
Delimiter (SFD)
Destination
Address and
Source Address
Type
Data and Padding
Frame Check
Sequence (FCS)
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Description
A sequence of 56 bits (alternating 1 and 0 values) Gives components in the network time to detect the
presence of a signal and synchronize to the incoming bit stream.
A sequence of 8 bits (10101011) that indicates the start of the packet.
The Destination Address field identifies the station or stations that are to receive the packet. The
Source Address identifies the station that originated the packet. A Destination Address may specify
either an individual address destined for a single station, or a multicast address destined for a group of
stations. A Destination Address of all 1s refers to all stations on the LAN and is called the broadcast
address.
Ethertype. The type of payload contained in the Ethernet frame.
This field contains the payload data transferred from the source station to the destination station(s). The
maximum size of this field is 1500 bytes. If the payload to be transported is less than 46 bytes, then
padding is used to bring the packet size up to the minimum length. A minimum-length Ethernet packet
is 64 bytes from the Destination Address field through the Frame Check Sequence.
This field contains a 4-byte cyclical redundancy check (CRC) value used for error checking. When a
source station assembles a packet, it performs a CRC calculation on all the bits in the packet from the
Destination Address through the Pad fields (that is, all fields except the preamble, start frame delimiter,
and frame check sequence). The source station stores the calculated value in the FCS field and
transmits it as part of the packet. When the packet is received by the destination station, it performs an
identical check. If the calculated value does not match the value in the FCS field, the destination station
assumes an error has occurred during transmission and discards the packet.
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10.6.1.1 VLAN Tag
As specified in IEEE Standard 802.1q, the twelve-bit VLAN identifier's tagged packets, enables the construction of
a maximum of 4,096 distinct VLANs. For cases where this VLAN limit is inadequate VLAN stacking provides a twolevel VLAN tag structure, which extends the VLAN ID space to over 16 million VLANs. Each packet may be sent
without VLAN tags, with a single VLAN tag or with two VLAN tags (VLAN stacking).
Figure 10-11. Single VLAN Tag Format
0
0
1
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
3
4
5
VLAN Tag Protocol ID (TPID)
User
CFI
VLAN ID
Priority
Figure 10-12. Stacked VLAN Tag Format
0
0
1
1
2
3
4
5
6
7
8
9
0
1
2
VLAN Tag Protocol ID (TPID)
User
CFI
VLAN ID
Priority
VLAN Tag Protocol ID (TPID)
User
CFI
VLAN ID
Priority
The VLAN tag’s Protocol ID (TPID) can be either the typical value of 0x8100 or a value configured in the
vlan_2nd_tag_identifier field in Packet_classifier_cfg_reg7.
•
The User Priority field is used to assign a priority level to the Ethernet packet.
•
The CFI (Canonical Format Indicator) fields indicate the presence of a Router Information Field.
•
The VLAN ID, uniquely identifies the VLAN to which the Ethernet packet belongs.
10.6.1.2 UDP/IPv4 Header
Figure 10-13. UDP/IPv4 Header Format
0
0
1
1
2
UDP
HEADER
IP
HEADER
IPVER
Rev: 032609
3
4
5
6
7
8
9
0
IHL
2
1
2
3
4
5
7
8
0
9
TIME TO LIVE
DESTINATION
SOURCE PORT NUMBER
LENGTH
2
3
4
5
6
IP HEADER
7
8
9
0
1
LENGTH
FRAGMENT
PROTOCOL
SOURCE IP
1
TOTAL
FLAGS
IDENTIFICATION
UDP
6
IP TOS
3
OFFSET
CHECKSUM
ADDRESS
IP
ADDRESS
DESTINATION
UDP
PORT
NUMBER
CHECKSUM
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Table 10-7. IPv4 Header Fields (UDP)
Field
Description
IPVER
IHL
IP TOS
Total Length
Identification
Flags
Fragment Offset
Time To Live
Protocol
IP Header Checksum
Source IP Address
Destination IP Address
IP version number. IPv4 IPVER=4
Length in 32-bit words of the IP header, IHL=5
IP type of service
Length in octets of IP header and data
IP fragmentation identification
IP control flags; must be set to 010 to avoid fragmentation
Indicates where in the datagram the fragment belongs; not used for TDM-over-Packet
IP time-to-live field; datagrams with zero in this field are to be discarded
Must be set to 0x11 to signify UDP
Checksum for the IP header
IP address of the source
IP address of the destination
Table 10-8. UDP Header Fields
Field
Source Port Number,
Destination Port Number
Description
Either the source or the destination port number holds the bundle identifier. The unused field can
be set to 0x85E (2142), which is the user port number assigned to TDM-over-Packet by the
Internet Assigned Numbers Authority (IANA).
For UDP/IP-specific OAM packets, the bundle identifier is all ones.
Length in octets of UDP header and data
Checksum of UDP/IP header and data. If not computed it must be set to zero.
UDP length
UDP checksum
10.6.1.3 UDP/IPv6 Header
Figure 10-14. UDP/IPv6 Header Format
0
0
1
1
2
IPVER
3
4
5
6
7
8
9
0
2
1
2
3
4
5
6
7
TRAFFIC CLASS
IP
HEADER
UDP
HEADER
DESTINATION
Rev: 032609
LENGTH
3
1
0
2
3
4
5
6
7
8
9
0
1
FLOW LABEL
SOURCE IP
UDP
9
NEXT HEADER
PAYLOAD LENGTH
SOURCE PORT NUMBER
8
HOP LIMIT
ADDRESS
IP
ADDRESS
DESTINATION
UDP
PORT
NUMBER
CHECKSUM
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Table 10-9. IPv6 Header Fields (UDP)
Field
IPVER
Traffic Class
Flow Label
Description
IP version number, for IPv6 IPVER = 6
An 8-bit field similar to the type of service (ToS) field in IPv4.
The 20-bit Flow Label field can be used to tag packets of a specific flow to differentiate the
packets at the network layer.
Similar to the Total Length field in IPv4. This field indicates the total length of the IP header and
data in octets.
Similar to the Protocol field in IPv4. It determines the type of information following the basic IPv6
header. Must be set to 0x11 to signify UDP.
Similar to the Time to Live field in IPv4.
Similar to the Source Address field in IPv4, except that the field contains a 128-bit source address
for IPv6 instead of a 32-bit source address for IPv4.
Similar to the Destination Address field in IPv4, except that the field contains a 128-bit destination
address for IPv6 instead of a 32-bit destination address for IPv4.
Payload Length
Next Header
Hop Limit
Source IP Address
Destination Address
10.6.1.4 MPLS Header
Figure 10-15. MPLS Header Format
0
0
1
1
2
3
4
5
6
7
8
9
0
2
1
2
3
4
5
6
7
8
9
0
OUTER LABELS (NONE, ONE OR TWO)
INNER
LABEL = BUNDLE
INDENTIFIER
Table 10-10. MPLS Header Fields
Field
Outer Labels
3
1
2
3
4
5
6
7
8
EXP
S
TTL
EXP
S
TTL
9
0
1
Description
MPLS labels, which identify the MPLS LSP, used to tunnel the TDMoMPLS packets through the
MPLS network. Also known as tunnel label(s) or transport label(s). The label number can be
assigned either manually or using the MPLS control protocol. There can be zero, one or two outer
labels.
Experimental field
Stacking bit: S=1 indicates stack bottom (i.e. the inner label). S=0 for all outer labels.
MPLS time to live
MPLS inner label (also known as the PW label or the interworking label) contains the bundle
identifier used to multiplex multiple bundles within the same tunnel. It is always be at the bottom of
the MPLS label stack, and hence its stacking bit is set (S=1).
EXP
S
TTL
Inner Label
10.6.1.5 MEF Header
Figure 10-16. MEF Header Format
0
0
1
1
2
3
4
5
6
7
8
9
0
2
1
2
3
ECID = BUNDLE IDENTIFIER
Table 10-11. MEF Header Fields
Field
ECID
Rev: 032609
4
5
6
7
8
9
0
3
1
EXP
2
3
4
5
6
7
8
9
0
1
0x102
Description
The Emulated Circuit Identifier (ECID) field. Contains the bundle identifier.
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10.6.1.6 L2TPv3/IPv4 Header
Figure 10-17. L2TPv3/IPv4 Header Format
0
0
1
1
2
3
IP
HEADER
IPVER
4
5
6
7
8
9
0
2
1
2
3
4
5
SOURCE IP
3
1
2
3
TOTAL
4
5
7
8
9
0
1
LENGTH
FRAGMENT
IP HEADER
6
OFFSET
CHECKSUM
ADDRESS
IP
ADDRESS
L2TPv3
HEADER
COOKIE 1 (OPTIONAL)
COOKIE 2 (OPTIONAL)
Description
See Table 10-7.
Must be set to 0x73 to signify L2TPv3
See Table 10-7.
Table 10-13. L2TPv3 Header Fields
Field
Rev: 032609
0
SESSION ID = PW LABEL
Table 10-12. IPv4 Header Fields (L2TPv3)
Field
Cookie (32 or 64 bits)
9
PROTOCOL
DESTINATION
Session ID (32 bits)
8
FLAGS
IDENTIFICATION
IPVER
IHL
IP TOS
Total Length
Identification
Flags
Fragment Offset
Time To Live
Protocol
IP Header Checksum
Source IP Address
Destination IP Address
7
IP TOS
IHL
TIME TO LIVE
6
Description
Locally significant L2TP session identifier, Contains the bundle identifier. All bundle identifiers are
available for use except 0, which is reserved.
Optional field that contains a randomly selected value used to validate association of the packet
with the expected bundle identifier
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10.6.1.7 L2TPv3/IPv6 Header
Figure 10-18. L2TPv3/IPv6 Header Format
0
1
0
1
2
3
4
5
IPVER
6
7
8
9
2
0
1
2
3
4
5
6
7
8
TRAFFIC CLASS
3
0
9
1
2
3
4
5
6
7
8
0
9
1
FLOW LABEL
PAYLOAD LENGTH
NEXT HEADER
IP
HEADER
SOURCE IP
DESTINATION
HOP LIMIT
ADDRESS
IP
ADDRESS
L2TPv3
HEADER
SESSION ID = BUNDLE IDENTIFIER
COOKIE 1 (OPTIONAL)
COOKIE 2 (OPTIONAL)
Table 10-14. IPv6 Header Fields (L2TPv3)
Field
IPVER
Traffic Class
Flow Label
Payload Length
Next Header
Hop Limit
Source Address
Destination Address
Description
See Table 10-9.
Must be set to 0x73 to signify LTPv3
See Table 10-9.
10.6.1.8 Control Word
Figure 10-19. Control Word Format
0
0
1
1
2
RES
3
4
5
L
R
6
7
M
8
Table 10-15. Control Word Fields
Field
RES
L
R
Rev: 032609
9
FRG
0
2
1
2
3
LENGTH
4
5
6
7
8
9
3
0
1
2
3
SEQUENCE
4
5
6
7
8
9
0
1
NUMBER
Description
Reserved bits.
Must be set to zero.
Local loss of sync failure.
This bit is set by CPU software (Port[n]_cfg_reg.Loss) for packets transmitted out the Ethernet port. A
set L bit indicates that the source has detected or has been informed of a TDM physical layer fault
impacting the data to be transmitted. This bit can be used to indicate physical layer LOS that should
trigger AIS generation at the far end. Once set, if the TDM fault is rectified, the L bit must be cleared.
Remote receive failure.
This bit is set by CPU software (Tx_R_bit field in bundle configuration) for packets transmitted out the
Ethernet port.. A set R bit indicates that the source is not receiving packets at the Ethernet port, i.e.,
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Field
Description
there is a failure of that direction of the bi-directional connection. This indication can be used to signal
congestion or other network related faults. Receiving remote failure indication may trigger fall-back
mechanisms for congestion avoidance. The R bit must be set after a preconfigured number of
consecutive packets are not received, and must be cleared once packets are once again received.
Defect Modifier failure.
These bits are set by CPU software (Port[n]_cfg_reg.Tx_defect_modifier) for packets transmitted out
the Ethernet port.. This field is optional. When used it supplements the L-bit meaning.
Fragmentation field
This field is used for fragmenting multiframe structures into multiple packets in case of CESoPSN
structured with CAS bundles.
The field is used as follows:
00 = Indicates that the entire (unfragmented) multiframe structure is carried in a single packet.
01 = Indicates the packet carrying the first fragment.
10 = Indicates the packet carrying the last fragment.
11 = Indicates a packet carrying an intermediate fragment.
Length field
Includes control word, payload and RTP header (if present) unless it is a UDP/IP packet. It is only
used when the total length of these fields is less than 64 bytes. Otherwise, it must be set to zero.
TDM-over-Packet sequence number, defined separately for each bundle and incremented by one for
each TDMoP packet sent for that bundle. The initial value of the sequence number is random
(unpredictable) for security purposes, and the value is incremented in wrap-around manner separately
for each bundle. Used by the receiver to detect packet loss and restore packet sequence.
The HDLC payload type machine supports three different modes for this field: always zero,
incremented in wrap-around manner or incremented in wrap-around manner, but skips zero value.
For OAM packets, it uniquely identifies the message. Its value is unrelated to the sequence number of
the TDMoP data packets for the bundle in question. It is incremented in query messages, and
replicated without change in replies.
M
FRG
Length
Sequence Number
10.6.1.9 RTP Header
Figure 10-20. RTP Header Format
0
0
1
1
V=2
2
3
P
X
4
5
6
CC
7
8
M
9
0
2
1
2
3
4
5
6
7
PT
8
9
0
3
1
2
3
4
5
6
7
8
9
0
1
SN (SEQUENCE NUMBER)
TS (TIMESTAMP)
SSRC (SYNCHRONIZATION SOURCE)
Table 10-16. RTP Header Fields
Field
V
P
X
CC
M
PT
SN
TS
Description
RTP version. Must be set to 2.
Padding bit. Must be set to 0.
Extension bit. Must be set to 0.
CSRC Count. Must be set to 0.
Marker bit. Must be set to 0.
Payload Type. One PT value MUST be allocated from the range of dynamic values for each direction
of the bundle. The same PT value MAY be reused for both directions of the bundle, and also reused
between different bundles.
Sequence number. Identical to the sequence number in the control word.
Timestamp. The RTP header can be used in conjunction with the following modes of timestamp
generation:
Absolute mode: the chip sets timestamps using the clock from the incoming TDM circuit. As
a consequence, the timestamps are closely correlated with the sequence numbers. The
timestamp is incremented by one every 125 µs.
Differential (common clock) mode: The two chips at bundle edges have access to the same
high-quality network clock, and this clock source is used for timestamp generation.
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SSRC
Field
Description
Identifies the synchronization source. This identifier should be chosen randomly, with the intent that no
two synchronization sources within the same RTP session have the same SSRC identifier.
10.6.1.10 TDM-over-Packet Payload
This field can contain the following payload types:
•
AAL1
•
HDLC
•
RAW (SAToP or CESoPSN formats)
•
OAM (VCCV or UDP/IP-specific).
The AAL1, HDLC and RAW payload type details are provided in sections 10.6.6, 10.6.7 and 10.6.8, respectively.
The formats of the OAM payload types are described below.
10.6.1.10.1 VCCV OAM
When using inband performance monitoring, additional OAM packets are sent using the same bundle identifier as
the TDM data packets. The OAM packets are identified by having their first nibble (after the PSN specific layers)
equal to 0001 and must be separated from TDM data packets before further processing of the control word. The
PSN-specific layers are identical to those used to carry the TDM data.
Figure 10-21. VCCV OAM Packet Format
0
0
1
1
2
3
4
5
6
7
8
9
0
2
1
2
3
4
5
6
7
8
9
0
3
1
2
3
4
5
6
7
8
9
0
1
PSN-Specific Layers (with same Bundle Identifier as TDM Data Packets)
0001
OAM MSG
FMTID
Type
RES
OAM MSG
Channel Type
Code
Service Specific Information
Source Transmit Timestamp
Destination Receive Timestamp
Destination Transmit Timestamp
Table 10-17. VCCV OAM Payload Fields
Field
FMTID
RES
Channel Type
OAM Msg Type
OAM Msg Code
Source Transmit Timestamp
Destination Receive Timestamp
Destination Transmit Timestamp
Description
Must be set to zero
Reserved and must be set to zero
Must be set to the value allocated by IANA for TDM-over-Packet VCCV OAM
See Table 10-18.
10.6.1.10.2 UDP/IP-Specific OAM
When using a UDP/IP-Specific OAM, all OAM packet MUST use one of the bundle identifiers preconfigured to
indicate OAM (using OAM ID Table). The PSN-specific layers are identical for OAM packets (except for the bundle
identifier) to those used to carry the TDM data.
Rev: 032609
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Figure 10-22. UDP/IP-Specific OAM Packet Format
0
0
1
1
2
3
4
5
L
R
6
7
8
9
0
2
1
2
3
4
5
6
7
8
9
0
3
1
2
3
4
5
6
7
8
9
0
1
PSN-Specific Layers (with bundle identifier configured to identify OAM)
0000
OAM MSG Type
M
RES
Length
OAM Sequence Number
Service Specific Information
OAM MSG Code
Source Bundle Identifier
Destination Bundle Identifier
Source Transmit Timestamp
Destination Receive Timestamp
Destination Transmit Timestamp
Table 10-18. UDP/IP-Specific OAM Payload Fields
Field
L, R, M
Length
OAM Sequence
Number
OAM Msg Type
OAM Msg Code
Description
Identical to those of the bundle being tested
OAM message packet length (in bytes)
Uniquely identifies the message. Its value is unrelated to the sequence number of the TDM data
packets for the bundle in question. It is incremented in query messages, and replicated without change
in replies.
Indicates the function of the message. At present, the following are defined:
0: one way connectivity query message
8: one way connectivity reply message
Information related to the message; its interpretation depends on the message type.
For OAM Msg Type=0 (connectivity query) messages, the following codes are defined:
0: Validate connection
1: Do not validate connection
Service Specific
Information
Source Bundle
Identifier
Destination
Bundle Identifier
Source Transmit
Timestamp
Destination
Receive
Timestamp
Destination
Transmit
Timestamp
For OAM Msg Type=8 (connectivity reply) messages, the available codes are:
0: Acknowledge valid query
1: Invalid query (configuration mismatch)
Can be used to exchange configuration information between gateways. If not used, it must contain
zero. Its interpretation depends on the payload type. At present, the following is defined for AAL1
payloads:
Bits 16–23: Number of timeslots being transported, e.g. 24 for full T1
Bits 24–31: Number of 48-byte AAL1 PDUs per packet, e.g. 8 when packing 8 AAL1 AAL1 SAR PDUs
per packet
The bundle identifier used for TDM-over-Packet traffic from the source to the destination.
The bundle identifier used for TDM-over-Packet traffic from the destination to source.
The time the PSN-bound gateway transmitted the query message. This field and the following fields
only appear if delay is being measured. The resolution is configurable to 100 µs or 1 µs.
The time the destination gateway received the query message.
The time the destination gateway transmitted the reply message.
For more details about OAM Signaling, see Section 10.6.17.
Rev: 032609
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10.6.2 Typical Application
In the application below (Figure 10-23), the device is embedded in a TDMoIP gateway to achieve TDM connectivity
over a PSN. The TDM-over-Packet packet formats for both IP and MPLS are shown in Figure 10-24 and
Figure 10-25, respectively.
Figure 10-23. TDM Connectivity over a PSN
Figure 10-24. TDMoP Packet Format in a Typical Application
DA SA VLAN Tag Ethertype IP Header
Optional
IP
Src. IP=X
Dst. IP=Y
UDP or
L2TPv3
Header
Bundle ID=A
Control
Word
Payload Type
AAL1/
HDLC/SAToP/
CESoPSN/
OAM
CRC-32
DA SA VLAN Tag Ethertype IP Header
Optional
IP
Src. IP=Y
Dst. IP=X
UDP or
L2TPv3
Header
Bundle ID=A
Control
Word
Payload Type
AAL1/
HDLC/SAToP/
CESoPSN/OAM
CRC-32
3
DA SA VLAN Tag Ethertype IP Header
Optional
IP
Src. IP=X
Dst. IP=Z
UDP or
L2TPv3
Header
Bundle ID=B
Control
Word
Payload Type
AAL1/
HDLC/SAToP/
CESoPSN/OAM
CRC-32
4
DA SA VLAN Tag Ethertype IP Header
Optional
IP
Src. IP=Z
Dst. IP=X
UDP or
L2TPv3
Header
Bundle ID=B
Control
Word
Payload Type CRC-32
AAL1/
HDLC/SAToP/
CESoPSN/OAM
1
2
Rev: 032609
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Figure 10-25. TDMoMPLS Packet Format in a Typical Application
1
2
3
4
DA SA VLAN Tag Ethertype Outer MPLS Inner MPLS Control Payload Type CRC-32
Label(s)
Label
Word
Optional
MPLS
AAL1/
Bundle ID=A
Optional
HDLC/SAToP/
CESoPSN/OAM
DA SA VLAN Tag Ethertype Outer MPLS Inner MPLS Control Payload Type CRC-32
Label(s)
Label
Word
Optional
MPLS
AAL1/
Bundle ID=B
Optional
HDLC/SAToP/
CESoPSN/OAM
10.6.3 Clock Recovery
The TDM-over-Packet block’s innovative clock recovery process is divided into two successive phases. In the
acquisition phase, rapid frequency lock is attained. In the tracking phase, frequency lock is sustained and phase is
also tracked. During the tracking phase, jitter is attenuated to comply with the relevant telecom standards even for
packet-switched networks with relatively large packet delay variation. Packet loss immunity is also significantly
improved.
During the acquisition phase, a direct estimation of the frequency discrepancy between the far-end and near-end
service clocks continuously drives an internal frequency synthesis device through a band-limited control loop. As a
result, frequency acquisition is achieved rapidly (typically less than 10 seconds). The clock recovery capture range
is ±90 ppm around the nominal service clock for any supported clock rate.
Once the frequency-monitoring unit has detected a steady frequency lock, the system switches to its tracking
phase. During the tracking phase the fill level of the received-packet jitter buffer drives the internal frequency
synthesizer through a similar band-limited control loop.
While in the tracking phase, two tasks are performed. First, the far-end service clock frequency is slowly and
accurately tracked, while compelling the regenerated near-end service clock to have jitter and wander levels that
conform to ITU-T G.823/G.824 requirements, even for networks that introduce high packet delay variation and
packet loss. This performance can be attained due to a very efficient jitter attenuation mechanism, combined with a
high resolution internal digital PLL (∆ƒ=0.4 ppb). Second, the received-packet jitter buffer is maintained at its fill
level, regardless of the initial frequency discrepancy between the clocks. As a result, the latency added by the
mechanism is minimized, while immunity against overflow/underflow events (caused by extreme packet delay
variation events) is substantially enhanced.
The TDM-over-Packet block supports two clock recovery modes: common clock (differential) mode and adaptive
mode.
The common clock mode is used for applications where the TDMoP gateways at both ends of the PSN path have
access to the same high-quality reference clock. This mode makes use of RTP differential mode time-stamps and
therefore the RTP header must be present in TDMoP packets when this mode is used. The common reference
clock is provided to the chip on the CLK_CMN input pin. The device is configured for common clock mode when
Clock_recovery_en=1 in General_cfg_reg0 and RTP_timestamp_generation_mode=1 in General_cfg_reg1.
The adaptive clock mode is based solely on packet inter-arrival time and therefore can be used for applications
where a common reference clock is not available to both TDMoP gateways. This mode does not make use of timestamps and therefore the RTP header is not needed in the TDMoP packets when this mode is used. The device is
configured
for
adaptive
clock
mode
when
Clock_recovery_en=1
in
General_cfg_reg0
and
RTP_timestamp_generation_mode=0 in General_cfg_reg1.
In adaptive mode, for low-speed interfaces (up to 4.6 MHz), an on-chip digital PLL, clocked by a 38.88MHz clock
derived from the CLK_HIGH pin, synthesizes the recovered clock frequency. The frequency stability characteristics
Rev: 032609
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of the CLK_HIGH signal depend on the wander requirements of the recovered TDM clock. For applications where
the recovered TDM clock must comply with G.823/G.824 requirements for traffic interfaces, typically a TCXO can
be use as the source for the CLK_HIGH signal. For applications where the recovered clock must comply with
G.823/G.824 requirements for synchronization interfaces, the CLK_HIGH signal typically must come from an
OCXO.
In addition to performing clock recovery for up to eight low-speed (typically E1/T1) signals, the device can also be
configured in a high-speed mode in which it supports one E3, T3 or STS-1 signal in and out of port 1. In high-speed
mode, the on-chip digital PLL synthesizes the recovered clock frequency divided by 10 (for STS-1) or 12 (for E3 or
T3). This clock is available on the TDM1_ACLK output pin and can be multiplied by an external PLL to get the
recovered clock of the high-speed signal (see section 15.3). High-speed mode is enabled when High_speed=1 in
General_cfg_reg0.
For applications where the chip is used only for clock recovery purposes (i.e. data is not forwarded through the
chip) the external SDRAM is not needed.
10.6.4 Timeslot Assigner (TSA)
The TDM-over-Packet block contains one Timeslot Assigner for each TDM port (framed or multiframed). The TSA
is bypassed in high-speed mode (i.e. when High_speed=1 in General_cfg_reg0.) The TSA tables are described in
section 11.4.5.
The TSA assigns 2-, 7- or 8-bit wide timeslots to a specific bundle and a specific receive queue. 2-bit timeslots are
used for delivering 16K HDLC channels. The 2 bits are located at the first 2 bits (PCM MSbits, HDLC LSbits) of the
timeslot. The next 6 bits of the timeslot cannot be assigned. 7-bit timeslots are used for delivering 56kbps HDLC
channels. The 7 bits are located at the first 7 bits (PCM MSbits, HDLC LSbits) of the timeslot. The last bit of the
timeslot cannot be assigned. The 2-bit and 7-bit timeslots may be assigned only to the HDLC payload type
machine. The AAL1 and RAW payload type machines support only 8-bit timeslots. For unframed/Nx64 interfaces
all entries must be configured as 8-bit timeslots.
Each port has two TSA tables (banks): one active and the other one shadow. The TSA_int_act_blk status bit in
Port[n]_stat_reg1 indicates which bank is currently active. The CPU can only write to the shadow table. After TSA
entries are changed in the shadow table the TSA tables should be swapped by changing the TSA_act_blk bit in
Port[n]_cfg_reg so that the active table becomes the shadow table and the shadow table becomes the active table.
Changes take effect at the next frame sync signal. For an unframed interface the changes take effect up to 256
TDM clock cycles after the TSA_act_blk is changed. After the change occurs, the TSA_int_act_blk bit is updated by
the device.
Each table consists of 32 entries, one entry per timeslot. The first entry refers to the first timeslot, i.e. the first 8 bits
of the frame (where the frame sync signal indicates start-of-frame). The second entry refers to the second timeslot,
i.e. the 8 bits after the first 8 bits, and so on.
The format of a table entry is shown in section 11.4.5. If a port is configured for an unframed signal format, all 32
entries for that port must have the same settings for all fields.
A bundle can only be composed of timeslots from a single TDM port, but timeslots from a TDM port can be
assigned to multiple bundles.
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10.6.5 CAS Handler
10.6.5.1 CAS Handler, TDM-to-Ethernet Direction
In the TDM-to-Ethernet direction, the CAS handler receives the CAS bits (for structured-with-CAS AAL1/CESoPSN
bundles) on the TDMn_RSIG_RTS signal. Depending on the value of the per-bundle Tx_CAS_source
configuration bit in the Bundle Configuration Tables, the CAS handler inserts either the CAS bits from the
corresponding TDMn_RSIG_RTS signal or the values from the transmit SW CAS tables (section 11.4.9) into the
AAL1/CESoPSN packets, in order to deliver the signaling as part of the AAL1/CESoPSN payload packets. See
Figure 10-26.
The transmit SW CAS tables may contain conditioning bits set by CPU software during configuration (per timeslot).
If CAS bits received on the TDMn_RSIG_RTS signal change, a per-timeslot maskable interrupt is asserted. The
Tx_CAS_change registers in the Interrupt Controller indicate which timeslots have changed CAS bits. The
Tx_CAS_change_mask registers are available to selectively mask these interrupts. Upon notification that CAS bits
have changed, the CPU can read the CAS bits directly from the receive signaling registers of the neighboring
E1/T1 framer component, alter them if needed, and write them into the TDMoP block’s transmit SW CAS tables.
Figure 10-26. CAS Transmitted in the TDM-to-Ethernet Direction
AAL1/AAL2 PACKETS IN SDRAM
TDMoP
FRAMER
RECEIVE CAS
BITS INTERNAL
REGISTER
TDM1_RSIG_RTS
TDM2_RSIG_RTS
TDM3_RSIG_RTS
TDM4_RSIG_RTS
TDM5_RSIG_RTS
TDM6_RSIG_RTS
TDM7_RSIG_RTS
TDM8_RSIG_RTS
CAS HANDLER
TRANSMIT SW
CAS TABLES
MANIPULATED
CAS BITS
(PER TIMESLOT)
CONDITIONING
BITS
CPU
There is a transmit SW CAS table for each TDM port. Each table consists of 4 rows, and each row contains the
CAS bits of eight timeslots. For ports configured for E1, timeslots 1–15 and 17–31 are used and timeslots 0 and 16
are meaningless. For ports configured for T1, timeslots 0–23 are used and timeslots 24–31 are meaningless. Ports
configured for T1 SF have two copies of A and B CAS bits arranged A, B, A, B. Other port types have one copy of
bits A, B, C and D. These cases are illustrated in Figure 10-27 and Figure 10-28.
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Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces
0
31
ABCD
(TS7)
ABCD
(TS6)
ABCD
(TS5)
ABCD
(TS4)
ABCD
(TS3)
ABCD
(TS2)
ABCD
(TS1)
ABCD
(TS0)
ABCD
(TS15)
..
..
..
..
..
..
ABCD
(TS8)
ABCD
(TS23)
..
..
..
..
..
..
ABCD
(TS16)
ABCD
(TS31)
..
..
..
..
..
..
ABCD
(TS24)
Figure 10-28. Transmit SW CAS Table Format for T1-SF Interfaces
31
0
ABAB
(TS7)
ABAB
(TS6)
ABAB
(TS5)
ABAB
(TS4)
ABAB
(TS3)
ABAB
(TS2)
ABAB
(TS1)
ABAB
(TS0)
ABAB
(TS15)
..
..
..
..
..
..
ABAB
(TS8)
ABAB
(TS23)
..
..
..
..
..
..
ABAB
(TS16)
Table 10-19. CAS – Supported Interface Connections for AAL1 and CESoPSN
TDM-to-Packet
Packet-to-TDM
Transmitted Bits
Interface Format
Interface Format
E1 MF
T1 SF
T1 ESF
T1 ESF
T1 SF
E1 MF
T1 SF
T1 ESF
T1 SF
T1 ESF
CAS bits are transferred as-is.
Only A and B bits transferred.
A and B bits transferred. C and D bits sourced from the
SF_to_ESF_low_CAS_bits field in Port[n]_cfg_reg.
For structured-with-CAS bundles connecting two T1 SF/ESF interfaces, the per-bundle Tx_dest_framing bit in the
Bundle Configuration Tables indicates the destination interface framing type (SF or ESF).
The figures below shows the location of the CAS bits in the TDMn_RSIG_RTS data stream for each framing mode.
Figure 10-29. E1 MF Interface RSIG Timing Diagram (two_clocks=1)
TDMn_RCLK
once in 2 milliseconds
TDMn_RX_SYNC
TDMn_RSIG
A
B
C
D
Timeslot 30
Rev: 032609
A
B
C
Timeslot 31
D
Timeslot 0
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Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0)
TDMn_TCLK
Once in 3milliseconds
TDMn_RX_SYNC
TDMn_RSIG
A
B
C
D
A
Timeslot 22
B
C
D
A
Timeslot 23
B
C
D
Timeslot 0
Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram
TDMn_TCLK
Once in 1.5 milliseconds
TDMn_RX_SYNC
TDMn_RSIG
A
B
A
B
Timeslot 22
A
B
A
B
Timeslot 23
A
B
B
A
Timeslot 0
TDMn_RX_SYNC can be left unconnected or connected to ground if the neighboring E1/T1 framer IC cannot drive
it. The TDMoP block has an internal free running counter that generates this signal internally when not driven by an
external source. This internally generated multiframe sync signal is synchronized to the TDMn_RX_SYNC input
pulse when present.
10.6.5.2 CAS Handler, Ethernet-to-TDM Direction
In the Ethernet-to-TDM direction, the CAS is received from the incoming packets.
The AAL1/RAW payload type machine extracts the CAS bits from the TDM-over-packet payload and writes them
into the CAS jitter buffers in the SDRAM (for structured-with-CAS AAL1/CESoPSN bundles only). The CAS jitter
buffers store the CAS information of up to 128 timeslots of the eight ports.
Selectors in the CAS handler send the CAS bits either from the CAS jitter buffers or from the Receive SW CAS
tables to the line (next MF) CAS tables (see Figure 10-32). The selectors’ decision logic is shown in Table 10-20.
Table 10-20. CAS Handler Selector Decision Logic
Condition
Timeslot not assigned or assigned to a bundle which is not an
AAL1/CESoPSN structured bundle (Rx_assigned=0 or
Structured_type=0 for its TSA entry)
AAL1 bundle jitter buffer is in underrun state and
Rx_CAS_src=1
Timeslot assigned to an AAL1/CESoPSN structured bundle
(Rx_assigned=1 and Structured_type=1 for its TSA entry)
AAL1/CESoPSN bundle jitter buffer is in underrun state and
Rx_CAS_src=0
Rev: 032609
Source of CAS bits Driven on
TDMn_TSIG_CTS for this Timeslot
Receive SW CAS tables
Corresponding CAS jitter buffer in SDRAM (CAS value is
the latest received)
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Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction
CAS JITTER BUFFERS IN SDRAM
TDMoP
Framer
TDM1_TSIG_CTS
TDM2_TSIG_CTS
TDM3_TSIG_CTS
TDM5_TSIG_CTS
TDM6_TSIG_CTS
TDM7_TSIG_CTS
TDM8_TSIG_CTS
CAS BITS
MANIPULATED
CAS BITS
(PER TIMESLOT)
CAS
HANDLER
PORTn
RECEIVE
LINE (NEXT
MF) CAS
TABLES
INTERRUPT ON CHANGE
TRANSMIT
CAS BITS
INTERNAL
REGISTER
TDM4_TSIG_CTS
PORTn
RECEIVE
LINE CAS
TABLES
SELECTOR
PORTn
RECEIVE
AAL2/SW
CAS
TABLES
CPU
The Receive SW CAS tables contains CAS bits written by CPU software.
Each port’s Receive Line CAS table (section 11.4.10) is updated with the CAS bits stored in the Receive Line (Next
MF) CAS table when the TDMn_TX_MF_CD signal is asserted to indicate the multiframe boundary. For E1 ports,
CAS bits are updated every 2 milliseconds. For T1 SF ports, CAS bits are updated every 1.5 milliseconds. For T1
ESF ports, CAS bits are updated every 3 milliseconds.
There is a Receive Line CAS table for each TDM port. These tables hold the CAS information extracted from
received packets and subsequently transmitted on TDMn_TSIG signals. Each table contains 32 rows, and each
row holds the CAS bits of one timeslot. Only the first 24 rows are used for T1 interfaces. For E1 and T1 ESF
interfaces, each row holds the A, B, C and D bits. For T1 SF interface where only the A and B bits exist, each row
holds the A and B bits duplicated i.e. A, B, A, B.
If CAS bits change in the Receive Line CAS table, a per-timeslot interrupt is asserted. The Rx_CAS_change
registers in the Interrupt Controller indicate which timeslots have changed CAS bits. Upon notification that CAS bits
have changed, CPU software can read the CAS bits from the Receive Line (Next MF) CAS table, manipulate them
and then write them directly into the transmit signaling registers of the neighboring E1/T1 framer IC. In this case,
the framer should be configured to use the CAS information from its CAS registers and not from its signaling input
pin.
The bits in each Receive Line CAS table are transmitted on the TDMn_TSIG signal, as shown in the figures below.
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Figure 10-33. E1 MF Interface TSIG Timing Diagram
TDMn_TCLK
once in 2 milliseconds
TDMn_TX_MF_CD
TDMn_TSIG
A
B
C
D
A
Timeslot 30
B
C
Timeslot 31
D
Timeslot 0
Figure 10-34. T1 ESF Interface TSIG Timing Diagram
TDMn_TCLK
Once in 3 milliseconds
TDMn_TX_MF_CD
TDMn_TSIG
A
B
C
D
A
Timeslot 22
B
C
D
Timeslot 23
A
B
D
C
Timeslot 0
Figure 10-35. T1 SF Interface TSIG Timing Diagram
TDMn_TCLK
Once in 1.5 milliseconds
TDMn_TX_MF_CD
TDMn_TSIG
A
B
A
B
Timeslot 22
A
B
A
B
Timeslot 23
A
B
A
B
Timeslot 0
TDMn_TX_MF_CD can be left unconnected or connected to ground if the framer cannot drive it. The TDMoP block
has an internal free running counter that generates this signal internally when not driven by external source. This
internally generated multiframe sync signal is synchronized to the TDMn_TX_SYNC input pulse when present.
10.6.6 AAL1 Payload Type Machine
For the prevalent case for which the timeslot allocation is static and no activity detection is performed, the payload
can be efficiently encoded using constant bit rate AAL1 adaptation.
The AAL1 payload type machine converts E1, T1, E3, T3, STS-1 or serial data flows into IP, MPLS or Ethernet
packets, and vice versa, according to ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1 and IETF RFC 5087 TDMoIP. In this
mapping method, data is actually mapped into 48-byte AAL1 SAR PDUs as described in I.361.1 section 2.4.2.
10.6.6.1 TDM-to-Ethernet Direction
In the TDM-to-Ethernet direction, the AAL1 payload type machine concatenates the bundle’s timeslots into
structures and then slices and maps the structures into 46- or 47-octet AAL1 SAR PDU payloads. After adding the
AAL1 SAR PDU header and pointer as needed, the AAL1 SAR PDUs are concatenated and inserted into the
payload of the layer 2/layer 3 packet.
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Figure 10-36. AAL1 Mapping, General
The structure of the AAL1 header is shown in Table 10-21 below.
Table 10-21. AAL1 Header Fields
Length
Field
Description
(bits)
C
SN
CRC
P
1
3
3
1
E
Pointer
1
7
Indicates if there is a pointer in the second octet of the AAL1 SAR PDU. When set, a pointer exists.
AAL1 SAR PDU sequence number
Cyclic redundancy code on C and SN
Even parity bit on C, SN and CRC or the even byte parity LSB for the sequence number octet (P
format AAL1 SAR PDUs only)
(P format AAL1 SAR PDUs only) Even byte parity MSB for pointer octet
(P format AAL1 SAR PDUs only) Indicates the next structure boundary. It is always located at the first
possible position in the sequence number cycle in which a structure boundary occurs. The pointer
indicates one of 93 octets (46 octets of the current AAL1 SAR PDU + 47 octets of the next AAL1 SAR
PDU). P=0 indicates that the first octet of the current AAL1 SAR PDU’s payload is the first octet of the
structure. P=93 indicates that the last octet of the next AAL1 SAR PDU is the final octet of the
structure.
The AAL1 block supports the following bundle types:
• Unstructured
• Structured
• Structured-with-CAS.
Unstructured bundles, for E1/T1 interfaces, support rates of N × 64 kbps, where N is the number of timeslots
configured to be assigned to a bundle. Unstructured bundles may also carry traffic of the whole low-speed interface
(up to 4.6 Mbps), E1/T1 interface (2.048Mbps/1.544 Mbps) and high-speed interface (up to 51.84 Mbps). The AAL1
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SAR PDU payload contains 47 octets (376 bits) of TDM data without regard to frame alignment or timeslot byte
alignment. All AAL1 SAR PDUs are non-P format for unstructured bundles.
Structured bundles, for E1/T1 interfaces, support rates of N × 64 kbps, where N is the number of timeslots
configured to be assigned to a bundle. For this format, the N timeslots from one E1/T1 frame are sequentially
mapped into an N-octet structure. This N-octet structure is then mapped into the AAL1 SAR PDU payload, octetaligned. This process is repeated until all octets of the AAL1 SAR PDU payload are filled. The last octet of the
payload may contain a timeslot other than the last timeslot of the structure. The remaining timeslots of the structure
are mapped into the next AAL1 SAR PDU payload in the same manner and the process continues. This is
illustrated in Figure 10-37.
Figure 10-37. AAL1 Mapping, Structured-Without-CAS Bundles
TDM FRAME
TDM FRAME
1
2
3
4
5
6
7
8
9
10
OCTET
1
2
3
4
5
6
7
8
9
10
CELL
2
3
5
7
11
2
3
5
7
11
NEXT
CELL
5
7
11
2
3
5
7
11
2
3
11
12
...
32
1
2
3
...
41
42
43
44
45
46
47
...
2
3
5
7
11
2
3
...
5
7
11
2
3
5
7
STRUCTURE
With this mapping each AAL1 SAR PDU can start with a different timeslot. To enable the far end TDMoP function
to identify the start of a structure, a pointer to it is sent periodically in one of the even-numbered AAL1 SAR PDUs
of every SN cycle. When this pointer is sent, a P-format AAL1 SAR PDU is used. In a P-format AAL1 SAR PDU the
first byte of the payload contains the pointer while the last 46 bytes contain payload.
Structured-with-CAS bundles, for E1/T1 interfaces, support rates of N × 64 kbps, where N is the number of
timeslots configured to be assigned to a bundle. This mapping is similar to the structured-without-CAS mapping
described above except that the structure is an entire E1/T1 multiframe of the N timeslots assigned to the bundle,
and a CAS signaling substructure is appended to the end of the structure. The addition of CAS only affects the
structure arrangement and contents. CAS data of one timeslot is 4 bits long, meaning one octet can contain CAS
data of 2 timeslots. Bundles containing an odd number of timeslots need a padding of 4 zeroes in the last CAS
octet. For example, a 3-timeslot bundle of an E1 frame with CAS yields the following structure octet sequence:
TS1, TS2, TS3 repeated 16 times (a whole E1 multiframe) and then CAS1+CAS2, CAS3+padding.
10.6.6.2 Ethernet-to-TDM Direction
In the Ethernet-to-TDM direction, AAL1 SAR PDUs of a bundle are being received only after the synchronization
process. The synchronization process includes packet SN synchronization, AAL1 SAR PDU SN synchronization,
and pointer synchronization. AAL1 SAR PDUs with CRC or parity errors in their header are discarded. Pointer
mismatch imposes jitter buffer under-run and bundle resynchronization. AAL1 SAR PDU header errors or pointer
errors may be ignored depending on per-bundle configuration. Missing AAL1 SAR PDUs are detected and restored
in the jitter buffer.
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10.6.7 HDLC Payload Type Machine
Handling HDLC in TDM-over-Packet ensures efficient transport of CCS (common channel signaling, such as SS7),
embedded in the TDM stream or other HDLC-based traffic, such as Frame Relay, according to IETF RFC 4618
(excluding clause 5.3 – PPP) and RFC 5087 (TDMoIP).
For an E1 interface, each bundle supports the rates of 16 kbps or N × 64 kbps, where N is the number of timeslots
configured to be assigned to a bundle (between 1 to 32). For an T1 interface, each bundle supports the rates of 16
kbps, 56 kbps (not supported for T1 SF interface), full T1 (1.544 Mbps) or N × 64 kbps, where N varies from 1 to
24.
In the TDM-to-Ethernet direction, the HDLC block monitors flags until a frame is detected. It removes bit stuffing,
collects the contents of the frame and checks the correctness of the CRC, alignment and frame length. Valid frame
length is anything greater than 2 bytes and less than Tx_max_frame_size in HDLC_Bundle[n]_cfg[95:64].
Erroneous frames are discarded. Good frames are mapped as-is into the payload of the configured layer 2/3
packet type (without the CRC, flags or transparency zero-insertions).
In the Ethernet-to-TDM direction, when a packet is received, its CRC is calculated, and the original HDLC frame
reconstituted (flags are added, bit stuffing is performed, and CRC is added).
Figure 10-38. HDLC Mapping
HDLC FRAME
IN TDM
FLAGS
DATA
CRC-16
FLAGS
ZERO BIT
DELETION
L2/L3
HEADER
Rev: 032609
CONTROL
WORD
HDLC TYPE
TDMoIP PAYLOAD
CRC
ETHERNET
PACKET
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10.6.8 RAW Payload Type Machine
The RAW payload type machine support the following bundle types:
•
Unstructured
According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553 (SAToP).
•
Structured without CAS
According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN).
•
Structured with CAS
According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN).
10.6.8.1 Unstructured
Unstructured bundles usually carry the data of a whole TDM port. This port may be low-speed such as an E1, T1 or
Nx64k bit stream or high-speed such as an E3, T3 or STS1 signal. In an unstructured bundle, the packet payload is
comprised of N bytes of the TDM stream without regard for byte or frame alignment. In the receiving device, the
TDM data is extracted from the packet payload and inserted as a bit stream into the jitter buffer, from which it is
then extracted and sent to the TDM port.
Figure 10-39. SAToP Unstructured Packet Mapping
L2/L3
Header
Control
Word
TDM payload
CRC
Ethernet
packet
FRG bits = 00
(no fragmentation)
TDM
bitstream
N TDM bytes
The packetization delay of an unstructured (SAToP) bundle is: T = N x 8 x the bit time of the TDM interface.
The minimum packetization time of an Ethernet packet for an unstructured (SAToP) bundle is as follows:
•
•
60 µs for high speed mode
125 µs for low speed mode
10.6.8.2 Structured without CAS
In a structured-without-CAS bundle, the packet payload is comprised of the assigned timeslots from N TDM frames
as illustrated in Figure 10-40.
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Figure 10-40. CESoPSN Structured-Without-CAS Mapping
TDM payload
L2/L3
Header
Control
Word
FRG bits = 00
(no fragmentation)
4
4 25 4 25
4 25
Frame
1
Frame
N
Frame
2
25
4
Frame 1
CRC
Ethernet
packet
25
4
Frame 2
25
Frame N
The packetization delay of a CESoPSN structured-without-CAS bundle is: T = N x 125 µs (i.e. N x the frame rate)
The minimum packetization time of an Ethernet packet for a structured (with or without CAS) bundle is 125 µs.
10.6.8.3 Structured with CAS (without Fragmentation)
In a structured-with-CAS bundle, the packet payload is comprised of the assigned timeslots from all the TDM
frames in a multiframe (e.g. 16 frames for E1) followed by the CAS signaling substructure, which contains the CAS
info for the assigned timeslots.
Figure 10-41. CESoPSN Structured-With-CAS Mapping (No Frag, E1 Example)
TDM payload
L2/L3
Header
Control
Word
FRG bits = 00
(no fragmentation)
2
4
Frame 1
2 4 25 2 4 25
Frame
1
25
2 4 25
Frame
2
Frame
16
2
4
A
A
A
B
B
B
C
C
C
D
D
D
TS 2 TS 4 TS 25
1 byte
25
Frame 2
Multi-Frame boundary
1 byte
Ethernet
packet
CRC
4 bit
pading
2
4
25
Frame 16
The minimum packetization time of an Ethernet packet for a structured (with or without CAS) bundle is 125 µs.
The minimum TDM payload of an Ethernet packet for a structured (with or without CAS) bundle is 8 bytes.
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Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example)
TDM payload
L2/L3
Header
Control
Word
FRG bits = 00
Frame
(no fragmentation)
1
2
2 4
2 4 2 4
Frame
24
Frame
2
2
4
A
A
B
B
C
C
D
D
TS 2 TS 4
1 byte
2
4
4
Frame 24
Frame 2
Extended-Super-Frame boundary
Frame 1
Ethernet
packet
CRC
In T1 SF, the multiframe structure is composed of 2 superframes resulting total of 24 TDM frames. The CAS info at
the end of the structure contains the CAS info of the 2 corresponding superframes as well.
Figure 10-43. CESoPSN Structured-With-CAS Mapping (No Frag, T1-SF Example)
TDM payload
L2/L3
Header
Control
Word
1 4 24
1 4 24 1 4 24
FRG bits = 00
Frame
(no fragmentation)
11
1
4
24
Frame 1
1
4
Frame
122
Frame
12
Frame
121
24 1
Frame 12
Super-Frame 1
1 4 24
4
A1
A1
A1
B1
B1
B1
A2
A2
A2
B2
B2
B2
TS 1 TS 4 TS 24
1 byte
CRC
1 byte
24
4 bit
pading
4
1
24
Frame 12
Frame 1
Super-Frame 2
The packetization delay of a CESoPSN structured-with-CAS bundle (not fragmented) is as follows:
•
•
Multiframed E1: T = 2 ms
T1 SF, ESF: T = 3 ms
10.6.8.4 Structured-with-CAS (with Fragmentation)
In order to reduce the packetization delay of structured-with-CAS bundle, the CESoPSN standard supports the
option of fragmentation. In this mode, the multiframe data structure is fragmented among several packets. Each
packet contains M TDM frames of the assigned timeslots. The last packet also contains the entire multiframe CAS
substructure. Because of that, there is limited number of allowed “M” values:
•
•
•
For multiframed E1: M = 1, 2, 4, 8, 16 (16 means single packet with no fragmentation)
For T1 SF: M = 1, 2, 3, 4, 6, 8, 12, 24 (24 means single packet with no fragmentation)
For T1 ESF: M = 1, 2, 3, 4, 6, 8, 12, 24 (24 means single packet with no fragmentation)
The packetization delay of a CESoPSN structured-with-CAS bundle (with fragmentation) is: T = M x 125 µs.
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Figure 10-44. CESoPSN Structured-With-CAS Mapping (Frag, E1 Example)
TDM payload
L2/L3
Header
Control
Word
FRG bits = 01
(first fragment)
2 4 25 2 4 25
Frame
1
2 4 25
Frame
2
CRC
First Ethernet
packet
CRC
Intermediate
Ethernet packet
Frame
M
TDM payload
L2/L3
Header
Control
Word
2 4 25
2 4 25 2 4 25
FRG bits = 11
Frame
(intermediate fragment) M + 1
Frame
M+2
Frame
2M
TDM payload
L2/L3
Header
Control
Word
FRG bits = 10
(last fragment)
2
4
Frame 1
Rev: 032609
2 4 25 2 4 25
Frame
25
2 4 25
Frame
16
Frame
2
4
A
A
A
B
B
B
C
C
C
D
D
D
TS 2 TS 4 TS 25
1 byte
25
Frame 2
Multi-frame boundary
1 byte
Last
Ethernet
packet
CRC
4 bit
pading
2
4
25
Frame 16
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10.6.9 SDRAM and SDRAM Controller
The device requires an external SDRAM for its operation. The following describes how the TDMoP block and the
CPU use the SDRAM:
The TDMoP block accesses these sections of the SDRAM:
• Transmit buffers section
This area stores outgoing packets created by the payload-type machines. It is a 1-Mbyte area with
base address specified by the Tx_buf_base_add field in General_cfg_reg1. The actual amount of
SDRAM used in the transmit buffers section depends on the number of open bundles and the number
of buffers assigned to each bundle.
• Jitter buffer data section
This area stores incoming TDM data after it has been extracted from received packets by the payloadtype machines. It is a 2-Mbyte area with base address specified by the JBC_data_base_add field in
General_cfg_reg1. The actual amount of the SDRAM used in the jitter buffer data section depends on
the configuration (most applications allocate only 0.5 Mbyte).
• Jitter buffer signaling section:
This area stores incoming TDM signaling information after it has been extracted from received packets
by the payload-type machines. It is a 32-kbyte area, with base address specified by the
JBC_sig_base_add field in General_cfg_reg1. This section is used only when structured-with-CAS
bundles have been opened.
The CPU uses the SDRAM as follows:
• The CPU may utilize the sections of SDRAM not used by the TDMoP block in order to send/receive
packets through the CPU queues/pools.
• The CPU accesses the transmit buffers section in order to initialize the buffer headers before opening a
bundle.
The built-in SDRAM controller allows glueless connection to an external SDRAM (the TDMoP block supplies the
SDRAM clock). Supported SDRAM devices are listed in section 15.6.
The TDMoP block typically uses from 1.5 to 3 MB of SDRAM space, depending on configuration. The CPU may
use the rest of the memory.
The supported resolutions of CPU access to the SDRAM are shown below.
Table 10-22. SDRAM Access Resolution
Data Bus Width
Access to SDRAM
32 bits
16 bits
8, 16, 32 bit
8, 16 bit
Prior to operation, the SDRAM controller configuration bits (see the General_cfg_reg0 register) must be configured.
First, the CPU must set the configuration bits while maintaining the Rst_SDRAM_n bit low (0). Then, it should
deassert the Rst_SDRAM_n bit. The Rst_SDRAM_n bit must not be changed during operation.
The SDRAM Controller operates at either 50 or 75 MHz with the following CAS latency options:
Table 10-23. SDRAM CAS Latency vs. Frequency
Frequency
CAS Latency
[MHz]
[clock cycles]
50
75
2
2 or 3
During operation, the controller’s arbiter receives access requests from various internal hardware blocks and the
CPU and grants access permissions based on predefined priorities. The controller automatically refreshes the
external SDRAM approximately once every 15 µs.
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Figure 10-45. SDRAM Access through the SDRAM Controller
SDRAM
CLOCK
SDRAM CONTROLLER
ARBITER
ACCESS FROM
HW BLOCKS
RESET_N
CPU PORT
CONFIGURATION
BITS
OTHER PORTS
CONFIGURATION
REGISTER
TDMoPacket
CPU
10.6.10 Jitter Buffer Control (JBC)
10.6.10.1 Jitter Buffer Application
Routinely in TDM networks, destination TDM devices derive a clock from the incoming TDM signal and use it for
transmitting data as depicted in Figure 10-46. This is called loopback timing.
Figure 10-46. Loop Timing in TDM Networks
SOURCE
CLOCK
LOOPBACK
TIMING
SOURCE TDM
DEVICE
DESTINATION
TDM DEVICE
When replacing the physical TDM connection with an IP/MPLS network and two TDM-over-Packet devices as
shown in Figure 10-47 below, the receiving TDM-over-Packet device (slave) receives packets with variable delays
(packet delay variation). After processing, the slave TDMoP device should send TDM data to the destination TDM
device at the same clock rate at which the TDM data was originally sent by the source TDM device. To achieve
this, the device works in clock recovery mode to reconstruct the source TDM clock to allow the destination TDM
device to still work in loopback timing mode.
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Figure 10-47. Timing in TDM-over-Packet
SOURCE
CLOCK
LOOPBACK
TIMING
SOURCE TDM
DEVICE
CLOCK
RECOVERY
MASTER
TDMoP DEVICE
ETHERNET
SLAVE
TDMoP DEVICE
LOOPBACK
TIMING
DESTINATION
TDM DEVICE
The jitter buffer, located in the SDRAM, has two main roles:
•
Compensate for packet delay variation
•
Provide fill level information as the independent variable used by the clock recovery machines to
reconstruct the TDM clock on a slave TDMoP device.
The data enters the buffer at a variable rate determined by packet arrival times and leaves it at a constant TDM
rate. In clock recovery mode, the amount of data in the jitter buffer (the “fill level”) steers the clock recovery
mechanism.
10.6.10.2 Jitter Buffer Configuration
Separate areas are allocated in the external SDRAM for TDM data and for signaling, as described in section
10.6.9.
In low-speed mode (High_speed=0 in General_cfg_reg0) both data and signaling areas are divided into eight
identical sections, one for each E1/T1/Nx64 interface. These section are further divided as follows:
•
In E1/T1 structured mode, each per-port data section contains the data of 32 timeslots for E1 or 24
timeslots for T1 (a total of 32*8=256 timeslots for all eight interfaces). Each E1/T1 timeslot is allocated a
maximum of 4 kB of space (128kB per interface and a total of 1024 kB for all eight interfaces).
•
Each signaling section is divided into multiframe sectors, with each sector containing the signaling nibbles
of up to 32 timeslots (total of 64 kB for all 8 interfaces).
•
In serial interface mode or E1/T1 unstructured mode, there is no per-timeslot allocation. The jitter buffer is
divided into eight identical sections, one for each interface (each section is 512 kB for HDLC bundles or
128 kB for other bundle types).
In high-speed mode (E3, T3, STS-1), the jitter buffer is arranged as one large buffer without division into sections
(total of 512 kB).
The Jitter Buffer maximum depth in time units (seconds) is calculated according to the following formula:
½ x Buffer area per interface x
8
Rate
where:
½
Buffer area per interface
8
Rate
Rev: 032609
=
=
=
=
Two halves of the buffer
512 kB for a single high-speed interface or 128 kB for a low-speed interface
Number of bits per byte
Transmission rate (e.g., 2.048 Mbps)
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For T1 structured-with-CAS, multiply the above formula by 0.75.
The jitter buffer depth is defined by the Rx_max_buff_size parameter found in the Bundle Configuration Tables.
When the jitter buffer level reaches the value of Rx_max_buff_size, an overrun situation is declared.
The Rx_PDVT parameter (also found in the Bundle Configuration Tables) defines the amount of data to be stored
in the jitter buffer to compensate for network delay variation. This parameter has two implications:
•
Rx_PDVT defines the chip’s immunity to the Ethernet network delay variation.
•
The data arriving from the network is delayed by Rx_PDVT before it is read out of the jitter buffer and
transmitted on the TDM pins.
Rx_PDVT must be smaller than Rx_max_buff_size. Also, the difference between Rx_max_buff_size and Rx_PDVT
must be larger than the time that it takes to create a packet (otherwise an overrun may occur when the packet
arrives). Typically, the recommended value for Rx_max_buff_size is 2* Rx_PDVT + PCT (packet creation time).
This provides equal immunity for both delayed and bursty packets.
Configuring the jitter buffer parameters correctly avoids underrun and overrun situations. Underrun occurs when
the jitter buffer becomes empty (the rate data is entering the buffer is slower than the rate data is leaving). When an
underrun occurs the TDMoP block transmits conditioning data instead of actual data towards the TDM interface.
The conditioning data is specified by the Receive SW Conditioning Octet Select table for TDM data and the
location specified by Rx_CAS_src (SDRAM or Receive SW CAS) for signaling. Overrun occurs when the jitter
buffer is full and there is no room for new data to enter (the rate data is leaving the buffer is slower than the rate
data is entering). Underrun and overrun require special treatment from the TDMoP hardware, depending on the
bundle type.
Figure 10-48. Jitter Buffer Parameters
Rx_max_buff_size
This area is empty and
can be used to store
incoming bursts.
Rx_pdvt
This area is full and there
is still data to send on the
line if incoming data is
missing due to network
delays.
The JBC uses a 64 by 32 bit Bundle Timeslot Table to identify the assigned timeslots of each active bundle. The
index to the table is the bundle number. The CPU must configure each active bundle entry (setting a bit means that
the corresponding timeslot is assigned to this bundle). For unstructured bundles, the whole bundle entry (all 32
bits) must be set.
Jitter buffer statistics are stored in a 256-entry table called the Jitter Buffer Status Table. Each TDM port has 32
dedicated entries, one per timeslot. This table stores the statistics of the active jitter buffer for each active bundle. A
configurable parameter called Jitter_buffer_index located in the timeslot assignment tables (section 11.4.5) points
to the entry in the Jitter Buffer Status Table where the associated jitter buffer statistics are stored. The value of the
Jitter_buffer_index should be set as follows:
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•
For AAL1/HDLC/RAW structured bundles: the Jitter_buffer_index value is the number of the lowest
timeslot in the bundle. For example, if the bundle consists of timeslots 2, 4, 17 on port 3,
Jitter_buffer_index=0x2.
•
For unstructured bundles the Jitter_buffer_index value is 0x0.
10.6.10.3 Jitter Buffer Status and Statistics
The CPU accesses the Jitter Buffer Status Table using the Jitter_buffer_index as described above. The status table
contains the current jitter buffer status (such as, the current jitter buffer level and its current state (OK, underrun or
overrun).
The status table also contains two variables, Minimal_level and Maximal_level, which report the minimum and
maximum fill levels of the jitter buffer since the last time the two fields were read (available for AAL1/RAW bundles
only). These variables provide information about network packet delay variation. For example, using these values,
the CPU can calculate the margins from the top (Rx_max_buff_size) and the bottom of the jitter buffer. If there is
margin, CPU software may want to reduce Rx_PDVT to reduce the latency added by the jitter buffer to the
incoming TDM data.
10.6.10.4 Jitter Buffer Response to Packet Loss and Misordering
The payload-type machines detect that a packet was lost by sequence number error in AAL1/RAW. If a packet is
lost, conditioning data (specified by the receive software conditioning registers in section 11.4.12) is inserted into
the jitter buffer in place of the lost data to maintain bit integrity (i.e. the number of bits that are inserted into the jitter
buffer must equal the number of bits that were transmitted by the far end).
If a packet is misordered in a RAW bundle (for example, the packet with the sequence number N arrives after the
packet with sequence number N+1) it is reordered by the RAW payload-type machine, and its data is inserted into
the appropriate location in the jitter buffer, assuming that the data in this location has not been transmitted to the
TDM port yet.
10.6.11 Queue Manager
Data flows through the TDMoP block in the following directions:
•
•
•
•
•
•
•
TDM to Ethernet (implemented in HW)
Ethernet to TDM (implemented in HW)
TDM to TDM (cross-connect, implemented in HW)
TDM to CPU
CPU to TDM
CPU to Ethernet
Ethernet to CPU.
These data flows are illustrated in Figure 10-49. Each data flow is described in a subsection below.
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Figure 10-49. TDM-over-Packet Data Flow Diagram
SDRAM
AAL1
PAYLOAD
TYPE
MACHINE
TDM
TO
CPU
ETH
TO
TDM
CPU
POOL
QUEUE
POOL
TDM
TO
CPU
ETH
RX
PAYLOAD
TO
CPU
RETURN
CPU
QUEUE
QUEUE
QUEUE
CROSS -
HDLC
TO
CPU
RX
CONNECT
QUEUE
TYPE
RX FIFO
ARBITER
MACHINE
FREE
PACKET
CLASSIFIER
BUFFER
POOL
ETH
RAW
PAYLOAD
TYPE
MACHINE
ETH
TX
ETH
TX
QUEUE
CPU
TO
CPU
MAC
INTERFACE
TX
ETH
RETURN
QUEUE
QUEUE
10.6.11.1 Buffer Descriptor
Data is transferred between the Ethernet MAC, internal payload-type machines and the external CPU by means of
buffers in the SDRAM. Payload data is stored in 2 kB SDRAM buffers along with a buffer descriptor located in the
buffer’s first dwords. The buffer pointers are managed inside the TDMoP block and are stored in queues, pools,
and other internal blocks. Queues store pointers to SDRAM buffers containing packet data to be processed, while
pools store pointers to empty buffers. The pointers are passed from one block to another. Only the block owning
the pointer can access the associated buffer.
The size of the buffer descriptor size depends on the internal path it is used for:
TDM TDM, TDM CPU and CPU TDM: One dword
TDM ETH, CPU ETH and ETH TDM: Two dwords
ETH CPU: Three dwords
The fields of the buffer descriptor dwords are described in the sections below.
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10.6.11.2 Buffer Descriptor First Dword
Used for all paths. Located at offset 0x0 from the start of the buffer.
Table 10-24. Buffer Descriptor First Dword Fields (Used for all Paths)
Bits
Data Element
Description
[31]
[30]
MPLS/MEF/L2TIPV3
or UDP/IP-specific
OAM
RST
[29:27]
Buffer contents
[26:16]
Length/Rst_Ts
[15]
[14:8]
Reserved
Offset
For ETH TDM and for CPU TDM indicates that the buffer holds a packet with
MPLS / MEF / L2TPv3 Ethertype. For ETH CPU indicates that the buffer holds a
UDP/IP-specific OAM packet.
RX Reset command (the bundle is in reset process).
For ETHTDM and for CPUTDM: used by the Packet Classifier or by the CPU to
inform the next blocks in flow that the bundle was reset. The buffer contains no real data.
000: Backwards-compatible (experimental) format packet going to the AAL1 payloadtype machine
001: Standard format packet going to the AAL1 payload-type machine
010: Reserved
011: Non-TDMoP/MPLS packet (this buffer isn’t assigned to any bundle)
100: Standard format packet going to the HDLC payload-type machine
101: Reserved
110: Standard format packet going to the RAW payload-type machine
111: Backwards-compatible (experimental) format packet going to the HDLC payloadtype machine
Packet Length or Payload Length
For TDMCPU, TDMTDM, CPUTDM and ETHTDM: payload length in bytes
(received bytes + control word if present + RTP header bytes in case of MPLS/MEF
packet using RTP and control word)
For TDMETH, ETHCPU and CPUETH: packet length in bytes, without CRC
For Buffer Contents =101: total length of packets concatenated in the buffer, in bytes
For RST packets: the reset timeslot number
Note: Length must be less than 1951 bytes.
Note: Offset and Length sum must be less than 2000 bytes.
Must be set to zero.
For ETHCPU, TDMETH and CPUETH: offset in bytes from start of buffer to start
of packet
For ETHTDM, TDMCPU, CPUTDM: offset in bytes from start of buffer to start of
payload or to the control word if present
For TDMTDM: bits 13-8 hold the internal bundle number from which the buffer has
been transmitted
For CPUETH, when Buffer Content (above) is different than 011, must be calculated
as follows: tx_payload_offset – header_length
[7]
HW/SW Type
[6]
RTP
[5:0]
Bundle number
Rev: 032609
Note: Offset and Length sum must be less than 2000 bytes.
Note: header_length is the number of bytes from start of packet to the control word (or to
start of the payload if control word is not used).
The pool the buffer has been extracted from and should be returned to.
0: HW buffers pool
1: SW buffers pool
For packets coming from Ethernet:
0: destination = payload-type machines
1: destination = CPU
For ETHTDM, ETHCPU, TDMTDM and CPU TDM indicates whether the packet
includes an RTP header.
For TDM TDM: destination internal bundle number.
For any other bundle: packet internal bundle number
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10.6.11.3 Buffer Descriptor Second Dword
Located at offset 0x4 from the start of the buffer.
10.6.11.3.1 TDM ETH and CPU ETH Packets
Table 10-25. Buffer Descriptor Second Dword Fields (TDM ETH and CPU ETH)
Bits
Data Element
Description
31:15
14
Reserved
Stamp
13:7
Ts_offset
6:0
Hdr2_length
Must be set to zero.
Indicates whether the packet should be time-stamped. Valid only for OAM and for nonTDMoP packets. Otherwise ignored.
Indicates the number of dwords from start of buffer to timestamp location. Valid only for
OAM and for non-TDMoP packets where Stamp bit is set above.
The second header length in bytes not including control word or RTP header (The offset
to the second header from start of the buffer is 0x782). Limited to 122 bytes and valid
only for AAL1, CESoPSN and SAToP bundles where the Protection_mode setting of the
bundle equals to “11” or “10”.
10.6.11.3.2 ETH CPU Packets
Table 10-26. Buffer Descriptor Second Dword Fields (ETH CPU)
Bits
Data Element
Description
31:30
29
28
27
26
25:24
23
22
21
20
19
18
17
16
15
14
13:11
10
9
8
7
6
Reserved
Ipv6
Ipv4
MEF_OAM
VCCV_OAM
No. of MPLS labels
802.3
Ethernet
Reserved
L2TPv3/IP
Two_VLAN tag
VLAN tag
UDP/IP
IP
MEF
MPLS
Reserved
Mpls_over_3_lbls
Unicast_not_mine
cpu_dst_eth_type
OAM
bndl_num_not_exist
5
not_tdmoip
4
3
2
ip_not_udp_l2tpv3
arp_chip_ip
unknown_eth_type
1
0
not_chip_ip
arp_not_chip_ip
Rev: 032609
Must be set to zero.
IP packet with IP VER = 6
IP packet with IP VER = 4
MEF OAM packet, i.e. Ethertype equal to Mef_oam_ether_type setting
VCCV OAM packet
Number of MPLS labels. Equal to “11” for packet with more than 3 labels.
802.3 packet
Ethernet packet
Must be set to zero.
L2TPv3/IP packet
Packet with two VLAN tags
Packet with one/two VLAN tags
UDP/IP packet
IP packet (with any IP VER)
MEF packet, i.e. Ethertype equal to Mef_ether_type setting
MPLS packet, i.e. packet’s Ethertype equal to 0x8847 or 0x8848
MPLS packet with more than 3 labels
Unicast packet with destination address different than MAC addresses
Packet with Ethertype equal to CPU_dest_ether_type setting
OAM packet
A TDM-over-Packet/MPLS/MEF packet destined to the chip but with a bundle identifier
that does not match any of one of the chip’s OAM bundle numbers or one of the bundle
identifiers assigned to the chip’s internal bundles.
UDP/IP packet with destination/source UDP port number different than
TDMoIP_port_num1 and TDMoIP_port_num2
IP packet with protocol different than UDP or L2TPv3
ARP packet with destination IP address equal to one of the chip’s IPv4 addresses
A packet with Ethertype different than IP, MPLS, ARP, MEF, MEF OAM or CPU
Ethertypes.
IP packet with destination IP address different than the chip’s IP addresses
ARP packet with destination IP address different than the chip’s IP addresses
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10.6.11.4 Buffer Descriptor Third Dword
Used for ETH CPU packets. Located at offset 0x8 from start of the buffer.
Table 10-27. Buffer Descriptor Third Dword Fields (ETH CPU)
Bits
Data Element
Description
31:0
Timestamp
32 bits timestamp latched by the packet classifier upon packet reception. Timestamp
resolution is 100 µs or 1 µs as specified by the OAM_timestamp_resolution field in
General_cfg_reg0.
10.6.11.5 RX Arbiter
The RX arbiter constantly checks for available packets in the Rx FIFO, the CPU-to-TDM queue and the crossconnect queue. It can do one of the following:
•
•
•
•
Pass a packet from the Rx FIFO to the payload-type machines
Pass a packet from the Rx FIFO to the external SDRAM and insert its pointer into the ETH-to-CPU queue
Extract a pointer from the cross-connect queue and pass a packet from the external SDRAM into the
payload-type machines
Extract a pointer from the CPU-to-TDM queue and pass a packet from the external SDRAM into the
payload-type machines.
In general, the Rx arbiter handles packets according to the following priorities:
1. Cross-connect queue
2. Rx FIFO (i.e., packets that arrive from the Ethernet port)
3. CPU-to-TDM queue.
The Rx_fifo_priority_lvl field in General_cfg_reg0 specifies a priority level for the Rx FIFO. Whenever the fill level of
the Rx FIFO is above this threshold, the Rx FIFO becomes the highest priority for the Rx arbiter rather than the
Cross-connect queue until the fill level of the Rx FIFO drops below the threshold.
10.6.11.6 TX Ethernet Interface
The TX Ethernet interface first checks the Ethernet TX queue. If the queue is not empty, it extracts a pointer,
passes the buffer data from the SDRAM to the Ethernet MAC, and returns the pointer to the free buffer pool. If the
TX Ethernet queue is empty, the TX Ethernet Interface checks the status of the CPU-to-Ethernet queue. If the
queue is not empty, it extracts a pointer, transfers buffer data to the Ethernet MAC, and returns the buffer to the
CPU TX Return queue.
10.6.11.7 Free Buffer Pool
The free buffer pool mechanism explained below is used for the TDM-to-Ethernet and TDM-to-TDM flows.
Before the payload-type machines can process any data, the CPU must initialize the free buffer pool. The free
buffer pool contains pointers to SDRAM buffers that are used by the payload-type machines to store packets.
There are a total of 512 SDRAM buffers. The CPU needs to pre-assign (statically) these SDRAM buffers to each
bundle. The number of buffers allocated per specific bundle depends on the number of timeslots in the bundle. It is
recommended to assign 4 buffers per timeslot.
The buffers are located in a continuous area in the SDRAM. The buffer address consists of the base address, the
buffer number and the displacement within the buffer. The base address is specified by the Tx_buf_base_add field
in General_cfg_reg1. Free buffer numbers are contained in linked lists, with a head pointing to the first buffer, each
buffer pointing to the next buffer and the last buffer pointing to itself. There are 64 heads (one per bundle), each
one containing a validity indication bit (MSB) and another 9 bits pointing to the first free buffer in the linked list. The
register descriptions for the Per-Bundle Head Pointers and Per-Buffer Next-Buffer Pointers are in section 11.4.7.
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The CPU must define the number of buffers for each bundle by initializing the linked list for the bundle. Software
prepares these buffers by writing the Ethernet, IP/MPLS/L2TPv3/MEF headers in advance, so that the payloadtype machines need only to write the packet payload. Since the headers contain bundle-specific data (e.g.,
destination address), the same buffers are used for the same bundle until the bundle is closed by CPU software.
When closing a bundle, the CPU should check that all buffers have been returned, by following the linked list from
the head to the last buffer. The buffers of a closed bundle may be used for a different new bundle. The linked list
operation is depicted below.
Figure 10-50. Free Buffer Pool Operation
BUFFERS AREA
511
.
.
.
1
0
SDRAM
BUFFER
ADDRESS
BASE
BUFFER ID
DISPLACEMENT
4 BITS
9 BITS
11 BITS
TDMoPacket
PAYLOAD TYPE
MACHINE
BUFFER ID
FREE BUFFER
POOL
VALIDITY
BIT
9
.
.
.
2
.
.
.
Rev: 032609
10
9
9
8
63
0
.
.
.
BUFFER
ID
HEADS
1
LINKED LIST
511
7
6
9
5
4
3
2
6
1
0
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10.6.11.8 TDM to Ethernet Flow
Each payload-type machine receives the data of specific bundle timeslots and maps it into packets. To store a new
packet in preparation, the machine extracts a pointer from the free buffer pool (section 10.6.11.7) and fills the
associated buffer with TDM timeslot data, one by one. When a packet is completed in a buffer, the payload-type
machine places the buffer pointer in the Ethernet Tx queue. The Tx Ethernet interface polls the queue, extracts the
pointer, and transfers the packets from the buffer to the Ethernet MAC block, to be sent over the Ethernet network.
Then, it returns the pointer to the free buffer pool. The buffer can then be used again by the payload-type machine
to store subsequent TDM data for the bundle.
Figure 10-51. TDM-to-Ethernet Flow
SDRAM
DATA
TX
AAL1
TX
HDLC
TDMoP BLOCK
TX
RAW
Pointers
FREE
BUFFER
POOL
Rev: 032609
ETH TX
QUEUE
TX ETH
INTERFACE
ETH MAC
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10.6.11.9 Ethernet to TDM Flow
A packet arriving from the Ethernet port passes through the Ethernet MAC block. The MAC block does not store
the packet, but it does calculate the CRC to verify packet data integrity. If the packet is bad, the MAC signals this to
the packet classifier on the last word of the packet, and the packet classifier discards it.
The packet classifier examines the packet header and decides to either discard the packet or transfer it into the
chip based on the settings of the packet classifier configuration registers (see Table 11-4). The packet classifier
tags the buffer descriptor for one of the following destinations: ETH-to-CPU queue or payload-type machines. The
packet classifier stores the packet payload preceded by the buffer descriptor in the Rx FIFO and notifies the Rx
arbiter. The Rx arbiter then passes it to one of the payload-type machines. The payload-type machine extracts the
TDM data and inserts it into the jitter buffer in the SDRAM. From there, the data is transmitted serially out the TDM
port.
Figure 10-52. Ethernet-to-TDM Flow
SDRAM
ETH TO CPU
QUEUE
RX ARBITER
RX FIFO
PACKET
CLASSIFIER
RX RAW
RX AAL1
RX HDLC
ETH MAC
TDMoP BLOCK
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10.6.11.10 TDM to TDM (Cross-Connect) Flow
Each payload-type machine receives the data of bundle-specific TDM timeslots and maps the data into Ethernet
packets. To store a packet, the payload-type machine needs an SDRAM buffer which it gets by extracting a buffer
pointer from the free buffer pool. It then fills the buffer as it processes the TDM timeslots. When a packet is
completed in a buffer, the machine places the buffer pointer in the cross-connect queue. The RX arbiter polls the
cross-connect queue, extracts the pointer, transfers the buffer data to the appropriate payload-type machine, and
then returns the pointer to the free buffer pool. The payload-type machine then extracts the TDM data and inserts it
into the jitter buffer in the SDRAM. From there, the data is transmitted serially out the TDM port.
Figure 10-53. TDM-to-TDM Flow
SDRAM
TDMoP BLOCK
RX
ARBITER
DATA
AAL1
FREE
BUFFER
POOL
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RAW
CROSS - CONNECT
QUEUE
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10.6.11.11 TDM to CPU Flow
The payload-type machines identify the destination of their packets according to the per-bundle configuration.
Upon getting the first byte of a packet in a bundle destined to the CPU, the machine needs a buffer to store the
packet. It therefore checks whether a buffer is available in the TDM-to-CPU pool. If the pool is empty, the machine
discards the current data. If a buffer is available, the machine stores the packet payload in the buffer and then adds
the buffer pointer to the TDM-to-CPU queue. The CPU polls this queue to look for packets that need to be
processed, gets the buffer pointer, and reads the packet from the SDRAM. After processing the packet, the CPU
closes the loop by returning the pointer to the TDM-to-CPU pool.
The TDM-to-CPU pool and queue can contain up to 128 pointers each. Section 11.4.6 describes the pool and
queue registers.
Figure 10-54. TDM-to-CPU Flow
SDRAM
DATA
TX AAL1
TX HDLC
TX
RAW
TDMoP BLOCK
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10.6.11.12 CPU to TDM Flow
The Rx arbiter polls the CPU-to-TDM queue for new packets waiting in the SDRAM to be processed. If the queue
level is greater than zero and there are no buffers pending in the Rx FIFO or the cross-connect queue, the Rx
arbiter extracts the pointer and copies the relevant data from the SDRAM buffer to the appropriate payload-type
machine. The arbiter then checks whether the CPU Rx return queue is not full to return the pointer. If the return
queue is full, the arbiter keeps the pointer and does not poll the CPU-to-TDM queue until it succeeds in returning
the pointer. After returning the pointer to the CPU Rx return queue for reuse, the arbiter is ready to take another
pointer from the CPU-to-TDM queue.
The CPU-to-TDM queue and the CPU Rx return queue can contain up to 32 pointers each. Section 11.4.6
describes the pool and queue registers.
Figure 10-55. CPU-to-TDM Flow
SDRAM
TDMoP BLOCK
CPU TO TDM
QUEUE
CPU RX
RX
ARBITER
RETURN
QUEUE
DATA
RX AAL1
RX HDLC
RX RAW
LOOP CLOSED BY THE CPU
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10.6.11.13 CPU to Ethernet Flow
The Tx Ethernet interface polls the CPU-to-Ethernet queue for new packets waiting in the SDRAM to be processed.
If the queue level is greater than zero and no buffers from the payload-type machines are waiting in the Ethernet Tx
queue, the Tx Ethernet interface extracts the pointer and copies the relevant data from the SDRAM buffer to the
Ethernet MAC block. It then checks whether the CPU TX return queue is not full to return the pointer. If the return
queue is full, it keeps the pointer and does not poll the CPU-to-ETH queue until it succeeds in returning the pointer.
After returning the pointer to the CPU TX return queue for reuse, the Tx Ethernet interface is ready to take another
pointer from the CPU-to-ETH queue.
The CPU-to-Ethernet queue and the CPU Tx return queue can contain up to 32 pointers each. Section 11.4.6
describes the pool and queue registers.
Figure 10-56. CPU-to-Ethernet Flow
SDRAM
CPU TO ETH
QUEUE
TX ETH
INTERFACE
CPU TX
RETURN
QUEUE
ETH MAC
TDMoP Block
LOOP CLOSED BY THE CPU
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10.6.11.14 Ethernet to CPU Flow
Ethernet packets enter the chip via the Ethernet MAC block and the packet classifier into the Rx arbiter. When the
Rx arbiter identifies that a packet is destined to the CPU, it extracts a pointer from the Ethernet-to-CPU pool (if the
pool is empty, the Rx arbiter discards the packet) and stores the packet data into the SDRAM in the buffer
indicated by the pointer. Then, it sends the pointer to the Ethernet-to-CPU queue (processed by the CPU). If the
queue is full, the Rx arbiter keeps the pointer for itself for future use. The Ethernet-to-CPU queue and pool contain
up to 128 pointers each. Section 11.4.6 describes the pool and queue registers.
Figure 10-57. Ethernet-to-CPU Flow
SDRAM
RX ARBITER
ETH TO
CPU
POOL
ETH TO
CPU
QUEUE
PACKET
CLASSIFIER
ETH MAC
TDMoP Block
LOOP CLOSED BY CPU
10.6.12 Ethernet MAC
10.6.12.1 Introduction
The Ethernet MAC can operate at 10 or 100 Mbps. It supports MII, RMII (Reduced pin-count MII), and SSMII
(source-synchronous serial MII). The MAC interface to the physical layer must be configured by the CPU.
The UNH-tested Ethernet MAC complies with IEEE 802.3. Its counters enable the software to generate network
management statistics compatible with IEEE 802.3 Clause 5.
The Ethernet MAC supports physical layer management through an MDIO interface. The control registers drive the
MDIO interface and select modes of operation, such as full or half duplex. Half-duplex flow control is achieved by
forcing collisions on incoming packets. Full-duplex flow control supports recognition of incoming pause packets.
In the receive path, the MAC checks the incoming packets for valid preamble, FCS, alignment and length, and
presents received packets to the packet classifier. Although packets with physical errors are discarded by default,
the MAC can be configured to ignore errors and keep such packets.
In the transmit path, the MAC takes data from the Tx Ethernet interface, adds preamble and, if necessary, pad and
FCS, then transmits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol.
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In half-duplex mode the start of transmission is deferred if MII_CRS (carrier sense) is active. If MII_COL (collision)
becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random
back off. MII_CRS and MII_COL have no effect in full-duplex mode.
Figure 10-58. Ethernet MAC
TDMoPacket
TX ETHERNET
INTERFACE
TX MII
ETHERNET
MAC
PACKET
CLASSIFIER
RX MII
CPU
INTERFACE
RX FIFO
CONFIGURATION,
STATISTICS
CPU
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10.6.12.2 Pause Packet Support
Ethernet transmission pause in response to a received pause packet is enabled when Pause_enable=1 in the
MAC_network_configuration register.
When a valid pause packet is received, the MAC_pause_time register is updated with the packet’s pause time
regardless of its current contents and regardless of the state of Pause_enable bit. In addition, the Pause_packet_
Rxd interrupt in the MAC_interrupt_status is triggered if it is enabled in the MAC_interrupt_mask register.
If Pause_enable=1 and the value of the MAC_pause_time register is non-zero, no new packet is transmitted.
A valid pause packet is defined as having a destination address that matches 0x0180C2000001, an Ethertype of
0x8808, and the pause opcode of 0x0001 as shown in Table 10-28.
Table 10-28. Start of an 802.3 Pause Packet
Destination
Source
Ethertype (MAC Control
Address
Address
Frame)
0x0180C2000001
6 bytes
Pause opcode
Pause Time
0x0001
2 bytes
0x8808
Pause packets that have FCS or other errors are treated as invalid and discarded. Valid received pause packets
increment the Pause_packets_Rxd_OK counter.
The MAC_pause_time register decrements every 512 bit times after transmission has stopped. For test purposes,
the register decrements every MII receive clock cycle instead if Retry_test=1 in the MAC_network_configuration
register. If the Pause_enable bit is not set, the decrementing happens regardless of whether transmission has
stopped or not.
The Pause_time_zero interrupt in the MAC_interrupt_status register is asserted whenever the MAC_pause_time
register decrements to zero (assuming it is enabled in the MAC_interrupt_mask).
Automatic transmission of pause packets is supported through the transmit pause packet bits of the
MAC_network_control register. If either Transmit_pause_packet or Transmit_zero_quantum_pause_ packet is set,
a pause packet is transmitted only if Full_duplex=1 in the MAC_network_configuration register and
Transmit_enable=1 in the MAC_network_control register. Pause packet transmission takes place immediately if
transmit is inactive or if transmit is active between the current packet and the next packet due to be transmitted.
The transmitted pause packet comprises the items in the following list:
•
•
•
•
•
•
•
Destination address of 01-80-C2-00-00-01
Source address taken from the MAC_specific_address registers
Ethertype of 0x8808 (MAC control frame)
Pause opcode of 0x0001
Pause quantum
Fill of 0x00 to take the frame to minimum frame length
Valid FCS.
The pause quantum used in the generated packet depends on the trigger source for the packet as follows:
•
•
If Transmit_pause_packet=1, the pause quantum comes from the MAC_transmit_paulse_quantum
register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving a maximum pause
quantum as a default.
If Transmit_zero_quantum_pause_ packet=1, the pause quantum is zero.
After transmission, no interrupts
Transmitted_pause_packets.
are
generated
and
the
only
counter
incremented
is
the
Pause packets can also be transmitted by the MAC using normal packet transmission methods. It is possible to
transmit a pause packet while the transmitter is paused by resetting the Pause_enable bit.
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10.6.13 Packet Classifier
The Packet Classifier is part of the receive path, immediately following the Ethernet MAC block. It analyzes the
header of each incoming packet, by comparing the header fields to the chip’s configured parameters, and then
decides whether to discard the packet or add a buffer descriptor and forward the packet to the CPU or one of the
payload-type machines. Section 11.4.1 has register descriptions for the packet classifier configuration registers.
IP version:
•
•
•
Packets with IP version different than 4 or 6 are always discarded.
The chip has three IPv4 addresses and two IPv6 addresses (all software configurable)
The chip works in one of four modes defined by two bits in General_cfg_reg1, as described in Table 10-29.
Table 10-29. Handling IPv4 and IPv6 Packets
IP_version
Dual_stack
Transmitted
Packets IP Version
0
0
IPv4
1
0
IPv6
0
1
IPv4
1
1
IPv6
Received Packets IP Version
Receive only IPv4 packets (other IP
versions are discarded)
Receive only IPv6 packets (other IP
versions are discarded)
Receive both IPv4 and IPv6 packets (dual
stack mode)
Receive both IPv4 and IPv6 packets (dual
stack mode)
Although the chip has more than one IP address, in most cases all three IPv4 addresses should have the same
value and both IPv6 addresses should have the same value. The chip also has two configurable MAC addresses.
Packets with CRC errors are discarded regardless to their contents, unless the Ethernet MAC has been configured
to ignore them (in which case they are treated as correct packets).
IP Packets with IP checksum error are discarded, unless the Discard_ip_checksum_err configuration bit is cleared
in General_cfg_reg0.
Packets other than TDM-over-IP or TDM-over-MPLS or TDM-over-MEF packets destined to the chip are not
transferred to the payload-type machines. Instead, they are either discarded or transferred to the CPU according to
the nine Discard_switch configuration bits in Packet_classifier_cfg_reg3:
Discard_Switch_0: An ARP packet whose Ipv4 destination address is not identical to any of the chip’s
Ipv4 addresses is discarded if Discard_Switch_0 is set. Otherwise it is transferred to
the CPU.
Discard_Switch_1: An IP (both Ipv4 or Ipv6) packet whose IP destination address is not identical to any of
the chip’s IP addresses is discarded if Discard_Switch_1 is set. Otherwise it is
transferred to the CPU.
Discard_Switch_2: A packet whose Ethertype is not known by the block is discarded if Discard_Switch_2
is set. Otherwise it is transferred to the CPU.
Discard_Switch_3: An ARP packet whose Ipv4 destination address is identical to one of the chip’s Ipv4
addresses is discarded if Discard_Switch_3 is set. Otherwise it is transferred to the
CPU.
Discard_Switch_4: An IP packet destined to the chip whose protocol is different than UDP and L2TPv3 is
discarded if Discard_Switch_4 is set. Otherwise it is transferred to the CPU.
Discard_Switch_5: An IP/UDP packet destined to the chip whose UDP destination/source port number is
not identical to one of the chip’s TDM-over-Packet port numbers (according to
TDMoIP_port_num_loc in Packet_classifier_cfg_reg3) is discarded if
Discard_Switch_5 is set. Otherwise it is transferred to the CPU.
Discard_Switch_6: A TDMoP/MPLS/MEF packet destined to the chip whose bundle identifier is not
identical to one of the chip’s OAM Bundle Numbers or one of the bundle identifiers
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assigned to the chip’s internal bundles, is discarded if Discard_Switch_6 is set.
Otherwise it is transferred to the CPU.
Discard_Switch_7: A packet recognized as OAM packet (see section 10.6.13.3) is discarded if
Discard_Switch_7 is set. Otherwise it is transferred to the CPU.
Discard_Switch_8: A packet with Ethertype equal to CPU_dest_ether_type configuration is discarded
when Discard_Switch_8 is set. Otherwise it is transferred to the CPU.
A packet is identified as a TDM-over-Packet packet destined to the chip if it meets the following conditions:
•
•
•
•
•
•
It is unicast with its destination address identical to the chip’s MAC addresses, multicast or broadcast
It has either no VLAN tags, one VLAN tag or two VLAN tags (supports VLAN stacking). See section
10.6.13.4.
Its protocol is UDP/IP or L2TPv3
Its IP address is identical to one of the IP addresses of the chip
Its UDP destination port number is identical to one of the chip’s TDM-over-Packet port numbers (optional).
See section 10.6.13.1.
Its bundle identifier is identical to one of the bundle identifiers assigned to the chip’s internal bundles or the
packet is identified as an OAM packet. See section 10.6.13.2.
A packet is identified as a TDMoMPLS or TDMoMEF packet destined to the chip if it meets the following conditions:
•
•
•
•
It is unicast with its destination address identical to the chip’s MAC addresses, multicast or broadcast
It has either no VLAN tags, one VLAN tag or two VLAN tags (VLAN stacking)
Its Ethertype is MPLS unicast, MPLS multicast, or MEF (see section 10.6.13.5)
The bundle identifier located at the inner label is identical to one of the bundle identifiers assigned to the
chip’s internal bundles or the packet is identified as an OAM packet.
The structure of packets identified as TDM-over-Packet packets destined to a specific bundle of the chip or as
OAM packets destined to the chip is shown below.
Figure 10-59. Format of TDMoIP Packet with VLAN Tag
DA
MAC_add/
Broadcast/
Multicast
SA
VLAN
Tag
Eth Type
up to 2
IP
tags
IP Header
Dst. IP =
IP_Add1/
IP_Add2
UDP or L2TPv3
Header
Bundle no. =
Bundle_Identifier/
OAM_bundle_num
Control
Word
Optional
Payload Type
AAL1/HDLC/
OAM/RAW
CRC-32
Control
Word
Payload Type
AAL1/HDLC/
OAM/RAW
CRC-32
Figure 10-60. Format of TDMoMPLS Packet with VLAN Tag
DA
MAC_add/
Broadcast/
Multicast
SA
VLAN
Tag
Eth Type
up to 2 MPLS
tags
Up to 2
MPLS
Labels
Optional
MPLS Label
Bundle no. =
Bundle_Identifier/
OAM_bundle_num
Figure 10-61. Format of TDMoMEF Packet with VLAN Tag
DA
MAC_add/
Broadcast/
Multicast
SA
VLAN
Tag
Eth Type
up to 2 MEF
tags
ECID = Bundle_Identifier
Control
Word
Payload Type
AAL1/HDLC/
OAM/RAW
CRC-32
Packets that pass the classification process are temporarily stored in the Rx FIFO. This FIFO is used to buffer
momentary bursts from the network if the internal hardware is busy. The Rx arbiter transfers the packets from the
Rx FIFO to the payload-types machines or to external SDRAM.
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10.6.13.1 TDMoIP Port Number
The TDMoIP_port_num1 and TDMoIP_port_num2 configuration fields are used by the block to identify UDP/IP
TDMoIP packets. Although the chip has two of these fields, in most cases both fields should have the default value
(0x085E) as assigned by IANA for TDM-over-Packet. The UDP source
Both values are compared against the UDP_SRC_PORT_NUM or the UDP_DST_PORT_NUM of incoming
packets as specified by the TDMoIP_port_num_loc field in Packet_classifier_cfg_reg3 (see Table 10-30).
Table 10-30. TDMoIP Port Number Comparison for TDMoIP Packet Classification
TDMoIP_port_num_loc Value
Comparison
00
01
10
11
TDMoIP_port_num1/2 are ignored (no checking is performed)
TDMoIP_port_num1/2 are compared to source UDP port # of incoming packets
TDMoIP_port_num1/2 are compared to destination UDP port # of incoming packets
Reserved
10.6.13.2 Bundle Identifier Location and Width
The block determines the packet bundle identifier and its width after determining the packet type.
Table 10-31. Bundle Identifier Location and Width
Packet Type
Bundle Identifier Location
MPLS
MEF
L2TPv3/IP
UDP/IP
Inner label
Inner label
Session ID
Source UDP port number or destination UDP
port number, as specified by Ip_udp_bn_loc
in Packet_classifier_cfg_reg3
Bundle Identifier Width
20 bits
20 bits
32 bits
1-16 bits as specified by Ip_udp_bn_mask_n
in Packet_classifier_cfg_reg6.
10.6.13.3 OAM Packet Identification
The block identifies OAM packets according to one of the following criteria:
•
UDP/IP-specific OAM packets: Match between the packet’s bundle identifier and one of the values (up to 8
different) configured in the OAM_Identification registers.
•
VCCV OAM packets: Match between the packet’s control word bits 31:16 and a 1 to 16 bit value specified
by the combination of VCCV_oam_mask_n and VCCV_oam_value fields in Packet_classifier_cfg_reg18.
Such a match is taken into account only when OAM_ID_in_CW=1 in the Bundle Configuration Tables.
•
MEF OAM packets: Match
Packet_classifier_cfg_reg9.
between
packet
Ethertype
and
Mef_oam_ether_type
in
register
10.6.13.4 VLAN Tag Identification
A VLAN tag is identified according to one of the following criteria:
•
Tag protocol identifier = 0x8100
•
Tag protocol identifier = vlan_2nd_tag_identifier in Packet_classifier_cfg_reg7 (Created to support 0x9100
as a tag identifier)
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10.6.13.5 Known Ethertypes
The block considers the following Ethertypes as known Ethertypes:
•
•
•
•
•
•
•
•
IPv4 (0x800)
IPv6 (0x86DD)
MPLS unicast (0x8847)
MPLS multicast (0x8848)
ARP (0x806)
MEF Ethertype as configured in Mef_ether_type in Packet_classifier_cfg_reg9
MEF OAM Ethertype as configured in Mef_oam_ether_type in Packet_classifier_cfg_reg9
Specific Ethertype as configured in CPU_dest_ether_type in Packet_classifier_cfg_reg7
10.6.13.6 Received OAM Time-Stamping
For any received packet forwarded to the CPU (ETH CPU path) the third dword of the buffer descriptor holds the
timestamp as latched by the block as the packet was received. This timestamp can be used by the CPU for
network delays measurements. The timestamp is 1 µs or 100 µs as specified by the OAM_timestamp_resolution
field in General_cfg_reg0.
10.6.13.7 Neighbor Discovery (RFC 2461)
Where IPv4 has ARP, IPv6 has NDP, the neighbor discovery protocol. For the purposes of this discussion, NDP
and ARP are very similar: one node sends out a request packet (called a neighbor solicitation in NDP), and the
node it was looking for sends back a reply (neighbor advertisement) giving its link-layer address. NDP is part of
ICMPv6, unlike ARP, which doesn't run over IP. NDP also uses multicast rather than broadcast packets.
For NDP (ICMPv6) packets to be forwarded to the CPU, Discard_switch_4 must be cleared.
10.6.13.8 Packet Payload Length Sanity Check
The packet classifier performs a sanity check between the payload length of the received packet and the
AAL1/SAToP/CESoPSN bundle’s configuration. Discarding packets that fail the sanity check can be disabled per
bundle by setting Rx_ discard_sanity_fail=1 in the Bundle Configuration Tables.
10.6.14 Packet Trailer Support
There are Ethernet switch chips that in some of their modes transmit packets with a trailer and expect the incoming
packets to have a trailer. A trailer is an addition of several bytes at the end of the packet that helps the switch to
decide about the incoming packet destination and to tag out-going packets.
When the device operates opposite such a switch, the trailer is supported in the following manner:
•
Transmitted packets: A 1 to 12 byte trailer is added to all transmitted packets. The trailer contents that are
stored in the packet buffer (immediately after the buffer descriptor starting from offset 0x8) may be varied
per packet.
•
Received packets: The trailer content is ignored. It is removed from packets destined to the payload-type
machines and not transferred with packets destined to CPU.
•
Trailer size is set for all transmitted/received packets in the Packet_trailer_length field in General_cfg_reg0.
The structure of packets with trailer is illustrated in Figure 10-62.
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Figure 10-62. Structure of Packets with Trailer
HEADER
PAYLOAD
TRAILER
CRC32
(1-12 BYTES)
Packets with total size of 64 bytes or
more (including CRC32)
60 bytes
HEADER
PAYLOAD
PADDING
TRAILER
CRC32
(1-12 BYTES)
Packets with total size of less than
64 bytes (including CRC32)
The CRC is calculated over all packet bytes including over the trailer bytes. The transmitted bytes counter and the
received bytes counter (section 11.4.3.3) do not count the trailer bytes.
10.6.15 Counters and Status Registers
For information about counters and registers in the TDMoP block, see section 11.4.
10.6.16 Connection Level Redundancy
The TDMoP block provides optional connection level redundancy for AAL1, SAToP and CESoPSN bundles. In the
TDM-to-Ethernet direction, on a bundle basis, each packet may be transmitted once with certain headers, or twice,
each time with different headers. When transmitted twice, the packets have the same payload, same control word
and same RTP header (if used) but may have different packet headers (including layer 2, 3 and 4 headers).
For example, the chip can duplicate a bundle’s packets on transmission where the only difference between the
duplicated packets is their bundle number or their VLAN ID.
On the receive side, when two redundant streams use different bundle numbers, the chip can be configured to
receive only the packets with the first bundle number or the packets with the second bundle number.
To enable this feature, CPU software must initialize the transmit buffers of a bundle with both headers. The second
header must be located at offset 0x782 from start of the buffer and its length (in bytes) is indicated by the buffer
descriptor Hdr2_length field (not including the RTP header length neither the control word length). By changing the
Protection_mode configuration field of the bundle, the user can choose (per bundle) whether to transmit each of the
packets once with the first or the second header, or twice, each time with a different header.
On the receive side, only the packets with their bundle number configured in the Rx_bundle_identifier field of a
specific bundle, are forwarded. The CPU may change this value dynamically, in order to switch to the redundant
connection at any time.
On the receive side, when both streams use the same bundle number, switching from one stream to another is
almost seamless. No software intervention is needed as the payload-type machine discards the duplicated packets.
During this process the end-to-end delay may change because of different route delays and 1–2 packet of packet
loss may occur.
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The destination MAC/IP (and/or VLAN) of the duplicated packets can be different as the chip supports more than
one MAC/IP address in the packet classifier.
10.6.17 OAM Signaling
TDMoP bundles require a signaling mechanism to provide feedback regarding problems in the communications
environment. In addition, such signaling can be used to collect statistics related to the performance of the
underlying PSN. The OAM procedures detailed below are ICMP-like.
10.6.17.1 Connectivity Check Messages
In most conventional IP applications, a server sends some finite amount of information over the network after an
explicit request from a client. With TDM-over-Packet, the source sends a continuous stream of packets towards the
destination, without knowing whether the destination device is ready to accept them, leading to flooding of the
PSN. The problem may occur when a TDM-over-Packet gateway fails or is disconnected from the PSN, or the
bundle is broken. After an aging time, the destination gateway disappears from the routing tables, and intermediate
routers may flood the network with the TDM-over-Packet traffic in an attempt to find a new path.
The solution to this problem is to significantly reduce the number of TDM-over-Packet packets transmitted per
second when bundle failure is detected, and to return to full rate only when the bundle is restored. The detection of
failure and restoration is made possible by the periodic exchange of one-way connectivity check messages.
Connectivity is tested by periodically sending OAM messages from the source gateway to the destination gateway,
and having the destination reply to each message.
The connectivity check mechanism can also be useful during setup and configuration. Without OAM signaling, one
must ensure that the destination gateway is ready to receive packets before starting to send them. Since TDMover-Packet gateways operate full duplex, both must be set up and properly configured simultaneously to avoid
flooding. By using the connectivity mechanism, a configured gateway waits until it can detect its destination before
transmitting at full rate. In addition, errors in configuration can be readily discovered by using the service-specific
field.
10.6.17.2 Performance Measurements
In addition to one-way connectivity, the OAM signaling mechanism can be used to request and report on various
PSN metrics, such as one-way delay, round trip delay, packet delay variation, etc. It can also be used for remote
diagnostics, and for unsolicited reporting of potential problems (e.g. dying gasp messages).
10.6.17.3 Processing OAM Packets
In the Ethernet-to-CPU direction, the device identifies OAM packets as described in section 10.6.13.3.
In the CPU-to-Ethernet direction the chip timestamps packets when the Stamp field of the buffer descriptor field is
set. The timestamp location in the packet is specified by the Ts_offset buffer descriptor field. When the CPU
transmits an OAM packet, the buffer descriptor must identify the packet as a non-TDMoP/MPLS packet (i.e. is not
assigned to any bundle), as other packet types are not time-stamped in any case.
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
10.7 Global Resources
See the top-level block diagram in Figure 6-1. Global resources in the device include CLAD1, CLAD2 and the CPU
Interface block. These resources are configured in the global registers described in section 11.3. These registers
also handle device identification, top-level mode configuration, I/O pin configuration, global resets, and top-level
interrupts.
10.8 Per-Port Resources
See the top-level block diagram in Figure 6-1. Each port is independently configured in the Port[n]_cfg_reg register.
In addition to E1 and T1 modes, a port can also be configured as a serial data port that can connect to a serial
interface transceiver for V.35 or RS-530 support. This would usually be in a DCE application of some kind. The
port can be configured for this mode by setting Port[n]_cfg_reg:Int_type=00.
The device also features one 10/100 Ethernet port that can be configured to have an MII, RMII or SSMII interface.
The Ethernet port can work in half or full duplex mode and supports VLAN tagging and priority labeling according to
802.1p 802.1Q, including VLAN stacking. Section 11.4.16 describes the Ethernet port.
10.9 Device Interrupts
The H_INT pin indicates interrupt requests. The only source for interrupts in the DS34S10x devices is the TDMoP
block (which includes the MAC). The TDMoPIM bit in GTIMR must be set to 1 enable interrupts from the TDMoP
block. The Intpend register indicates the source(s) of interrupt(s) from the TDMoP block. If one of the Intpend bits is
set, it can be cleared only by writing 1 to it. At reset, all Intpend interrupts are disabled due to the Intmask register
default values. Writing 0 to an Intmask bit enables the corresponding Intpend interrupt.
The TDMoP interrupts indicated in the Intpend register are of two types. The first type consists of interrupts
generated by a single source. The second type consists of interrupts that can originate from any of several possible
interrupt sources including the ETH_MAC, CW_bits_change, Rx_CAS_change, Tx_CAS_Change, and
JB_underrun interrupts.
The JBC_underrun interrupts can be masked per timeslot by setting the appropriate bits in the
JBC_underrun_mask registers.
The Tx_CAS_change interrupts can be masked per timeslot by setting the appropriate bits in the
Tx_CAS_change_mask registers.
The CW_bits_change interrupts can be masked per bundle by setting the appropriate bits in the CW_bits_mask
registers. In addition, the fields of the control word that cause an interrupt when changed (L, R, M, FRG) can be
configured in the CW_bits_change_mask register.
When an interrupt is indicated on H_INT, the CPU should read the Intpend register to identify the interrupt source
and then proceed as follows:
Interrupt Type
Single-source Interrupts
Rx_CAS_change
Rev: 032609
Interrupt Procedure
1. Clear the pending interrupt(s) by writing 1 to the corresponding
Intpend bit(s).
2. Service the source of the interrupt.
1. Read the Rx_CAS_change bits in the Intpend register to determine
which port(s) are indicating Rx CAS change.
2. Clear the set Rx_CAS_change bits in the Intpend register by writing
1 to them.
3. Read the corresponding Rx_CAS_change register(s) to determine
which timeslot(s) have been changed.
4. Clear the set bits in the Rx_CAS_change register(s) by writing 1 to
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Interrupt Type
5.
Tx_CAS_change
1.
2.
3.
4.
5.
CW_bits_change
1.
2.
3.
4.
JB_underrun_Pn
1.
2.
3.
4.
ETH_MAC
5.
1.
2.
3.
Interrupt Procedure
them.
Read the corresponding Rx CAS information from the Rx Line CAS
registers (section 11.4.10).
Read the Tx_CAS_change bits in the Intpend register to determine
which port(s) are indicating Tx CAS change.
Clear the set Tx_CAS_change bits in the Intpend register by writing
1 to them.
Read the corresponding Tx_CAS_change register(s) to determine
which timeslot(s) have been changed.
Clear the set bits in the Tx_CAS_change register(s) by writing 1 to
them.
Read the appropriate Tx CAS information from neighboring framer
IC(s).
Clear the CW_bits_change bit in the Intpend register by writing 1 to
it.
Read the CW_bits_change_low_bundles and
CW_bits_change_high_bundles registers to determine which
bundles(s) have control bits that have changed.
Clear the set bits in the CW_bits_change_low_bundles and
CW_bits_change_high_bundles registers by writing 1 to them.
Read the state of the control word fields from the Packet Classifier
Status register in the per-bundle status tables (section 11.4.4.1).
Read the JBC_underrun bits in the Intpend register to determine
which port(s) are indicating jitter buffer underrun.
Clear the set JBC_underrun bits in the Intpend register by writing 1
to them.
Read the corresponding JBC_underrun register(s) to determine
which buffers had underruns.
Clear the set bits in the JBC_underrun register(s) by writing 1 to
them.
Service the underrun(s) as needed.
Clear the ETH_MAC bit in the Intpend register by writing 1 to it.
Read the MAC_interrupt_status register to determine the source(s)
of interrupts in the MAC (all bits are reset to 0 upon read).
Service the source(s) of the interrupt(s).
If a bit in the Intpend register is set and that interrupt is then masked, the device generates an interrupt immediately
after the CPU clears the corresponding mask bit. To avoid this behavior, the CPU should clear the interrupt from
the Intpend register before clearing the mask bit.
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11. Device Registers
11.1 Addressing
Device registers and memory can be accessed either 2 or 4 bytes at a time, as specified by configuration pin
DAT_32_16_N. In the 16-bit addressing mode, addresses are multiples of 2, while in 32-bit addressing, addresses
are multiples of 4.
The prefix “0x” indicates hexadecimal (base 16) numbering, as does the suffix “h” (Example: 2FFh). Addresses are
always indicated in hexadecimal format.
The byte order for both addressing modes is “big-endian” meaning the most significant byte has the lowest
address. See byte order numbers in grey in Figure 11-1 and Figure 11-2.
Figure 11-1. 16-Bit Addressing
ADD
15
6
4
2
0
H_WR_BE1_N
8 7
6
H_WR_BE0_N
0
7
5
3
3
1
4
4
2
2
0
Figure 11-2. 32-Bit Addressing
ADD
C
31
8
4
H_WR_BE3_N
24 23
4
0
0
H_WR_BE2_N
16 15
5
1
H_WR_BE1_N
8 7
6
2
H_WR_BE0_N
0
7
3
Partial data elements (shorter than 16 or 32 bits) are always positioned from LSb to MSb with the rest of the bits
left unused. Thus, the bit numbers of data elements shorter than 16 bits are identical for both addressing modes
(see bits [12:0] in Figure 11-3) and the CPU can access all bits by a single read/write.
Figure 11-3. Partial Data Elements (shorter than 16 bits)
ADD
ADD
31
24 23
15
8 7
0
2
15
8
7
0
0
31
24 23
16
16 15
8 7
0
0
Data elements 17 to 32 bits long need one read/write access in 32-bit addressing and two in 16-bit addressing. In
Figure 11-4, the 20-bit data element needs one 32-bit CPU access (bits [19:0]) and two 16-bit accesses (bits [15:0]
and then [3:0]).
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 11-4. Partial Data Elements (16 to 32 bits long)
15
8 7
0
2
15
8
7
0
0
31
24 23
16
8 7
0
ADD
ADD
24 23
31
16 15
0
SPI interface mode (H_CPU_SPI_N=0) always uses 32-bit addressing. See section 10.3.
11.2 Top-Level Memory Map
Table 11-1. Top-Level Memory Map
Address Range
0 –
7F,FFF
80,000 –
Contents
Page
TDM-over-Packet Registers
93
107,FFF
Reserved
---
108,000 –
108,FFF
Global Registers
91
109,000 –
FFF,FFF
Reserved
---
External SDRAM
---
1,000,000 – 1,FFF,FFF
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.3 Global Registers
Functions contained in the global registers include device ID, CLAD configuration and top-level interrupt masking.
The global register base address is 0x108,000.
Table 11-2. Global Registers
Addr
Register Name
Offset
0x00
08
0C
10
14
GCR1
GTRR
IDR
GTISR
GTIMR
R/W
R/W
R/W
RO
RO
R/W
GCR1 (Global Control Register) 0x00
Bits
Data Element Name
R/W
Description
Page
Global Control Register 1
Global Transceiver Reset Register
Identification Device Register
Global Transceiver Interrupt Status Register
Global Transceiver Interrupt Mask Register
Default
[31:15]
[14]
Not Used
SYSCLKS
R/W
0
0
[13:12]
FREQSEL
R/W
00
[11:9]
[8]
Not Used
CLK_HIGHD
R/W
0
0
[7:0]
Not Used
-
0
91
91
92
92
92
Description
Must be set to zero.
TDMoP System Clock Frequency Select
When a 25MHz clock is applied to the CLK_SYS pin (i.e. when
the CLK_SYS_S pin is high), this bit configures the CLAD2 block
to provide either a 50MHz clock or a 75MHz clock to the TDMoP
block. When CLK_SYS_S=0 this bit is a don’t care. See section
10.4.
0 = 50MHz
1 = 75MHz
Frequency Select
Specifies the frequency of the signal applied to the CLK_HIGH
pin.
00 = 38.88MHz (CLAD bypass; 38.88MHz in and out).
01 = 19.44MHz
10 = 10.000MHz
11 = 77.76MHz
Must be set to zero.
CLK_HIGH Disable
Disables the 38.88MHz master clock to the clock recovery
machines of the TDMoP block to save power. This bit should be
set only when not using any of the TDMn_ACLK signals. See
section 10.4.
0 = Enabled
1 = Disabled
Must be set to zero.
GTRR (Global Transceiver Reset Register) 0x08
Bits
Data Element Name
R/W
Default
[31:19]
[18]
Not Used
TOPRST
R/W
0
0
[17:0]
Not Used
-
0
Rev: 032609
Description
Must be set to zero.
TDMoP Core Software Reset
When set, this bit resets all of the TDMoP configuration registers
to their default value.
0 = Normal operation
1 = Reset the TDMoP core
Must be set to zero.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
IDR (Identification Device Register) 0x0C
Bits
Data Element Name
R/W
[31:16]
[15:4]
ID[31:16]
ID[15:4]
RO
RO
[3:0]
ID[3:0]
RO
Default
Description
0
These bits are always zero.
See
Device ID
JTAG ID. These bits have the same information as the lower 12 bits of the
Device ID portion of the JTAG ID register. See Table 12-2.
See
Device Revision
JTAG ID. These bits have the same information as the four REV bits of the
JTAG ID register. See Table 12-2.
GTISR (Global Transceiver Interrupt Status Register) 0x10
Bits
Data Element Name
R/W
Default
[31:25]
[24]
Not used.
TDMoPIS
RO
0
0
[23:0]
Not Used
-
0
Description
Must be set to zero.
TDM-over-Packet Interrupt Status
This status bit indicates when the TDM-over-Packet block is
signaling an interrupt request. Interrupt mask is
GTIMR.TDMoPIM.
0 = TDM-over-Packet has not issued an interrupt.
1 = TDM-over-Packet has issued an interrupt.
Must be set to zero.
GTIMR (Global Transceiver Interrupt Mask Register) 0x14
Bits
Data Element Name
R/W
Default
[31:25]
[24]
Not used.
TDMoPIM
R/W
0
[23:0]
Not Used
-
0
Rev: 032609
0
Description
Must be set to zero.
TDM-over-Packet Interrupt Mask
This bit is the interrupt mask for GTISR.TDMoPIS.
0 = Interrupt masked.
1 = Interrupt enabled.
Must be set to zero.
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11.4 TDM-over-Packet Registers
The base address for the TDMoP registers is 0x0.
Table 11-3. TDMoP Memory Map
Address Offset
0x0,000
8,000
10,000
12,000
18,000
20,000
28,000
30,000
38,000
40,000
48,000
50,000
58,000
68,000
70,000
72,000
Rev: 032609
Contents
Configuration and Status Registers
Bundle Configuration Tables
Counters
Status Tables
Timeslot Assignment Tables
CPU Queues
Transmit Buffers Pool
Jitter Buffer Control
Transmit Software CAS
Receive Line CAS
Clock Recovery
Receive SW Conditioning Octet Select
Receive SW CAS
Interrupt Controller
Packet Classifier
Ethernet MAC
Page
94
108
117
120
120
122
124
130
134
136
137
138
139
140
147
148
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.1 Configuration and Status Registers
The base address for the TDMoP configuration and status registers is 0x0,000.
Table 11-4. TDMoP Configuration Registers
Addr
Register Name
Offset
0x00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
80
D4
General_cfg_reg0
General_cfg_reg1
General_cfg_reg2
Port1_cfg_reg
Port2_cfg_reg
Port3_cfg_reg
Port4_cfg_reg
Port5_cfg_reg
Port6_cfg_reg
Port7_cfg_reg
Port8_cfg_reg
Rst_reg
TDM_cond_data_reg
ETH_cond_data_reg
Packet_classifier_cfg_reg0
Packet_classifier_cfg_reg1
Packet_classifier_cfg_reg2
Packet_classifier_cfg_reg3
Packet_classifier_cfg_reg4
Packet_classifier_cfg_reg5
Packet_classifier_cfg_reg6
Packet_classifier_cfg_reg7
Packet_classifier_cfg_reg8
Packet_classifier_cfg_reg9
Packet_classifier_cfg_reg10
Packet_classifier_cfg_reg11
Packet_classifier_cfg_reg12
Packet_classifier_cfg_reg13
Packet_classifier_cfg_reg14
Packet_classifier_cfg_reg15
Packet_classifier_cfg_reg16
Packet_classifier_cfg_reg17
Packet_classifier_cfg_reg18
CPU_rx_arb_max_fifo_level_reg
Table 11-5. TDMoP Status Registers
Addr
Register Name
Offset
0xE0
E4
E8
EC
F0
F4
F8
FC
100
104
108
10C
General_stat_reg
Version_reg
Port1_sticky_reg1
Port1_sticky_reg2
Port1_sticky_reg3
Port1_sticky_reg4
Port1_sticky_reg5
Port1_sticky_reg6
Port1_sticky_reg7
Port1_sticky_reg8
Port1_status_reg1
Port1_status_reg2
Rev: 032609
Description
General configuration register0
General configuration register1
General configuration register2
Port 1 configuration register
Port 2 configuration register
Port 3 configuration register
Port 4 configuration register
Port 5 configuration register
Port 6 configuration register
Port 7 configuration register
Port 8 configuration register
Reset register
TDM AAL1/SAToP conditioning data register
Ethernet AAL1/SAToP conditioning data register
Packet classifier configuration register0
Packet classifier configuration register1
Packet classifier configuration register2
Packet classifier configuration register3
Packet classifier configuration register4
Packet classifier configuration register5
Packet classifier configuration register6
Packet classifier configuration register7
Packet classifier configuration register8
Packet classifier configuration register9
Packet classifier configuration register10
Packet classifier configuration register11
Packet classifier configuration register12
Packet classifier configuration register13
Packet classifier configuration register14
Packet classifier configuration register15
Packet classifier configuration register16
Packet classifier configuration register17
Packet classifier configuration register18
Rx arbiter maximum FIFO level register
Description
General latched status register
TDMoP version register
Port 1 latched status register
Port 2 latched status register
Port 3 latched status register
Port 4 latched status register
Port 5 latched status register
Port 6 latched status register
Port 7 latched status register
Port 8 latched status register
Port 1 status bit register 1
Port 1 status bit register 2
Page
95
96
97
97
97
97
97
97
97
97
97
100
101
101
101
101
101
102
103
103
103
103
104
104
104
104
104
105
105
105
105
105
105
106
Page
107
107
107
107
107
107
107
107
107
107
108
108
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Addr
Offset
110
114
118
11C
120
124
128
12C
130
134
138
13C
140
144
Register Name
Port2_status_reg1
Port2_status_reg2
Port3_status_reg1
Port3_status_reg2
Port4_status_reg1
Port4_status_reg2
Port5_status_reg1
Port6_status_reg2
Port6_status_reg1
Port6_status_reg2
Port7_status_reg1
Port7_status_reg2
Port8_status_reg1
Port8_status_reg2
Description
Page
Port 2 status bit register 1
Port 2 status bit register 2
Port 3 status bit register 1
Port 3 status bit register 2
Port 4 status bit register 1
Port 4 status bit register 2
Port 5 status bit register 1
Port 5 status bit register 2
Port 6 status bit register 1
Port 7 status bit register 2
Port 7 status bit register 1
Port 7 status bit register 2
Port 8 status bit register 1
Port 8 status bit register 2
108
108
108
108
108
108
108
108
108
108
108
108
108
108
11.4.1.1 TDMoP Configuration Registers
General_cfg_reg0 0x00
Bits
Data Element Name
R/W
Reset
Value
[31]
Discard_ip_checksum_err
R/W
0x0
[30:27]
Packet_trailer_length
R/W
0x0
[26]
Clock_recovery_en
R/W
0x0
[25:16]
Rx_fifo_priority_lvl
R/W
0x100
[15:14]
MII_mode_select
R/W
0x0
[13:12]
Reserved
R/W
0x0
[11]
High_speed
R/W
0x0
[10]
OAM_timestamp_resolution
R/W
0x1
[9:8]
Reserved
R/W
0x0
[7]
Mem_size
R/W
0x0
Rev: 032609
Description
Indicates to discard packets received with a wrong IP
checksum. See section 10.6.13.
The length of the trailer attached to all received and
transmitted packets. Allowed values: 0–12 (decimal).
When set to zero no trailer is attached. See section
10.6.14.
0 = Clock recovery block is disabled (power saving mode)
1 = Normal operation
Should be cleared to reduce the chip power consumption
when adaptive clock recovery is not used. When cleared,
the clock recovery registers (offset 0x48,000) must not be
accessed by the CPU because the clock recovery block
does not assert H_READY_N. See section 10.4.
Rx FIFO threshold level in dwords. If the Rx FIFO level is
higher than this threshold, then the Rx_fifo receives the
higher priority instead of the cross-connect queue.
This parameter is relevant only when there are bundles
configured as cross-connect. The recommended value is
0x3FF (maximal value). See section 10.6.11.5.
00 = MII
01 = RMII
10 = Reserved
11 = Source sync SMII (SSMII)
Must be set to zero
0 = All ports active in E1/T1/J1 mode
1 = Port1 enabled in high-speed E3/T3/STS-1 mode, all
other ports disabled
0 = OAM timestamp is incremented every 1µs
1 = OAM timestamp is incremented every 100µs
See section 10.6.13.6.
Must be set to zero
SDRAM size:
0 = 64 Mb
1 = 128 Mb
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General_cfg_reg0 0x00
Bits
Data Element Name
R/W
Reset
Value
[6:5]
Fq
R/W
0x0
[4:3]
Col_width
R/W
0x0
[2:1]
CAS_latency
R/W
0x2
[0]
Rst_SDRAM_n
R/W
0x0
R/W
Reset
Value
General_cfg_reg1 0x04
Bits
Data Element Name
[31]
RTP_timestamp_generation_
mode
R/W
0x0
[30:24]
Sw_packet_offset
R/W
0x04
[23:19]
Tx_payload_offset
R/W
0x00
[18]
Reserved
R/W
0x0
[17:10]
JBC_sig_base_add
R/W
0x060
[9:6]
Tx_buf_base_add
R/W
0x2
[5]
IP_version
R/W
0x0
[4]
Dual_stack
R/W
0x0
[3]
Frames_count_check_en
R/W
0x1
[2]
Reserved
R/W
0x0
[1:0]
JBC_data_base_add
R/W
0x0
Rev: 032609
Description
SDRAM clock:
00 = 50 MHz
01 = 75 MHz
10 = Reserved
11 = Reserved for 100 MHz
SDRAM columns and rows
00 = 8 bit (256 columns)
01 = 9 bit (512 columns)
10 = 10 bit (1K columns)
11 = 11 bit (2K columns)
SDRAM CAS latency:
00 = {reserve value}
01 = 1
10 = 2
11 = 3
Resets SDRAM controller. Active low.
After all configuration bits of the SDRAM controller have
been written, the SDRAM controller must be reset by
taking this bit low then high.
Description
Indicates the RTP timestamp generation mode:
0 = Absolute mode
1 = Differential (common clock) mode
See the description of the TS field in Table 10-16 for more
details.
The offset from the first byte of the packet to the start of
the CPU buffer.
For the Ethernet-to-CPU packets, 8 bytes are added
automatically to each configured value. For example, if
you intend to set the offset to 20 bytes, configure this
value to 12 bytes.
Allowed values are in the range of 4–127 (decimal) bytes.
Number of 32-bit words between the start of transmit
buffer to the control word or to start of the TDM payload if
the control word does not exist
Must be set to zero
Base address (8 MSbits) of Rx jitter buffer signaling
section in SDRAM
Base address (4 MSbits) of transmit buffers in SDRAM
The IP version of transmitted TDMoP packets. See
section 10.6.13.
0 = Ipv4
1 = Ipv6
The IP version of received TDMoP packets . See section
10.6.13.
0 = Ipv4/Ipv6, according to IP_version field above
1 = Both Ipv4 and Ipv6 packets
Specifies whether to check received packets that are
CESoPSN structured with CAS bundles and discard those
that contain the wrong number of TDM frames
0 = Do not check
1 = Check
Must be set to zero
Base address (2 MSbits) of Rx jitter buffer data section in
SDRAM
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General_cfg_reg2 0x08
Bits
Data Element Name
R/W
Reset
Value
[31:29]
Rx_HDLC_min_flags
R/W
0x0
[28:24]
Reserved
R/W
0x0
[23:20]
Rx_SAToP/CESoPSN_discard_
mask
R/W
0x0
[19:0]
Reserved
R/W
0x0
Description
Minimum number flags between 2 adjacent HDLC frames
transmitted on the TDM pins. The number of flags is equal
to Rx_hdlc_min_flags + 1. Range: 1 – 8.
Must be set to zero
Each bit of this field determines whether a specific type of
discarded packet is to be counted by the
‘SAToP/CESoPSN _discarded_packets’ counter.
0 = don’t count
1 = count
bit 23: count packets that were discarded because of jump
operation that caused overflow in jitter buffer.
bit 22: count packets that were discarded due to incorrect
sequence number.
bit 21: count packets that were discarded due to over-run
state in jitter buffer.
bit 20: count packets that were discarded because they
were considered duplicated, or because they were
received too late to be inserted into the jitter buffer.
Must be set to zero
In the Port[n]_cfg_reg description below, the index n indicates port number: 1-8 for DS34S108, 1-4 for DS34S104,
1-2 for DS34S102, 1 only for DS34S101.
Port[n]_cfg_reg 0x08+n*4
Bits
Data Element Name
R/W
Reset
Value
[31:30]
Reserved
R/W
[29:24]
Unframed_int_rate
R/W
0x0
[23]
PCM_rate
R/W
0x0
Rev: 032609
0x0
Description
Must be set to zero.
The bit rate of an unframed interface type (Used only for
absolute mode RTP timestamping).
1 = 64 kbps
2 = 128 kbps
.
.
.
32 = 2.048 Mbps
33 =1.544 Mbps
34 = 34 Mbps (E3 rate)
45 = 45 Mbps (T3 rate)
52 = 51.84 Mbps (STS-1 rate)
Note: E3, T3 and STS-1 configurations are available for
Port 1 only in high-speed mode, i.e. when
General_cfg_reg0.High_speed=1.
Indicates the PCM frequency, i.e. the TDM rate in and out
of the TDMoP port. Only applies when int_frame_type
(bits 3:2 below) is set for frame, multiframe or ESF and
int_type (bits 1:0 below) is set for E1 or T1.
0 = 1.544 MHz
1 = 2.048 MHz
This bit is for enabling T1 data over an E1-rate port. The
combination of Int_type=E1 and PCM_rate=1.544 MHz is
not allowed.
97 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Port[n]_cfg_reg 0x08+n*4
Bits
Data Element Name
R/W
Reset
Value
[22:21]
Tx_defect_modifier
R/W
0x0
[20]
Port_Rx_enable
(Rx means from Ethernet MII)
R/W
0x0
[19]
CTS
R/W
0x1
[18]
CD_en
R/W
0x0
[17]
CD
R/W
0x1
[16]
Loss
R/W
0x0
[15:11]
Adapt_JBC_indx
R/W
0x00
[10:9]
SF_to_ESF_low_CAS_bits
R/W
0x0
[8]
TSA_act_blk
R/W
0x0
[7]
Port_Tx_enable
(Tx mean toward Ethernet MII)
R/W
0x0
[6]
Rx_sample
R/W
0x1
[5]
Tx_sample
R/W
0x0
Rev: 032609
Description
Used in the control word M field for packets in all bundles
associated with TDMoP port n.
0 = Outgoing TDM traffic from Port n of the TDMoP block
is discarded (TDMn_TX and TDMn_TSIG are held high)
1 = Outgoing TDM traffic from Port n of the TDMoP block
is enabled.
Note: (Port 1 only) This bit also applies in high-speed
mode, i.e. when General_cfg_reg0.High_speed=1.
When the Int_type field (below) specifies a serial
interface, the value of the TDMn_TSIG_CTS pin--which
behaves as CTS (Clear To Send)—comes from this field.
When the Int_type field (below) specifies a serial
interface, this field is the output enable control for the CD
(Carrier Detect) function of the TDMn_TX_MF_CD pin.
When this pin is active, the output state of the
TDMn_TX_MF_CD pin comes from the CD field (below).
When the Int_type field (below) specifies a serial
interface, the value of the TDMn_TX_MF_CD pin—which
behaves as CD (Carrier Detect)—comes from this field
when the CD_en bit (above) is high.
Loss of sync on TDM port n. Causes the L bit in the
control word to be set for packets in all bundles
associated with TDMoP port n.
Index of the jitter buffer used by the clock recovery block
to generate the clock for TDMoP port n.
In the case where a SF (superframe) formatted T1 is
connected by a structured-with-CAS bundle to an ESF
interface, this field is the source of the C and D CAS bits
for the ESF interface (in the Ethernet-to-TDM direction).
See section 10.6.5.
0 = TSA bank1 is the active bank for Port n.
1 = TSA bank2 is the active bank for Port n.
Swapping banks takes effect at the next sync input
assertion
0 = Incoming TDM traffic to Port n of the TDMoP block is
discarded
1 = Incoming TDM traffic to Port n of the TDMoP block is
enabled
Note: (Port 1 only) This bit also applies in high-speed
mode, i.e. when General_cfg_reg0.High_speed=1.
In one-clock mode (Two_clocks field below is 0) this field
is ignored. In two-clock mode (Two_clocks=1) this field
specifies the TDMn_RCLK edge on which TDMn_RX,
TDMn_RX_SYNC and TDMn_RSIG_RTS are sampled.
0 = falling edge
1 = rising edge
See the timing diagrams in Figure 14-10 through
Figure 14-13.
In one-clock mode (Two-clocks field below is 0) this field
specifies the TDMn_TCLK edge on which
TDMn_TX_SYNC, TDMn_TX_MF_CD, TDMn_RX,
TDMn_RX_SYNC and TDMn_RSIG_RTS are
sampled and the edge on which TDMn_TX and
TDMn_TSIG_CTS are updated.
0 = Inputs sampled on the falling edge, outputs updated
on the rising edge
1 = Inputs sampled on the rising edge, outputs updated
on the falling edge
98 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Port[n]_cfg_reg 0x08+n*4
Bits
[4]
Data Element Name
Two_clocks
R/W
R/W
Reset
Value
0x1
[3:2]
Int_framed_type
R/W
0x0
[1:0]
Int_type
R/W
0x1
Rev: 032609
Description
In two-clock mode (Two-clocks=1) this field specifies the
TDMn_TCLK edge on which TDMn_TX_SYNC,
TDMn_TX_MF_CD are sampled and the edge on which
TDMn_TX and TDMn_TSIG_CTS are updated. The
Rx_sample field (above) specifies the TDMn_RCLK edge
for the Rx-side signals.
0 = Inputs sampled on the falling edge, outputs updated
on the rising edge
1 = Inputs sampled on the rising edge, outputs updated
on the falling edge
See the timing diagrams in Figure 14-8 through
Figure 14-13.
One-clock or two-clock mode.
0 = one-clock mode: TDMn_TCLK is used for both Rx and
transmit interfaces
1 = two-clock mode: TDMn_RCLK is used for the Rx
interface and TDMn_TCLK is used for the transmit
interface.
Note: (Port 1 only) This bit must be set in high-speed
mode (i.e. when General_cfg_reg0.High_speed=1).
Interface Framing Type
00 = Unframed (no frame sync, no multiframe sync)
01 = Frame (frame sync only, no multiframe sync)
10 = Multiframe (E1), SF (T1) (sync and mf sync)
11 = ESF(T1) (frame sync and multiframe sync)
Changing value from 10 or 11 to 00 or 01 must be
performed only after asserting the RST_SYS_N pin.
Interface Type
00 = Serial
01= E1
10 = T1
11 = Reserved
99 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rst_reg 0x2C
Bits
Data Element Name
R/W
[31:28]
Reserved
[27:24]
Rst_tx_port_num
R/W
0x0
[23:18]
Rst_tx_internal_bundle_num
R/W
0x00
[17]
Rst_tx_open/close
R/W
0x0
[16]
Rst_tx
R/W
0x0
[15:7]
[6:1]
Reserved
Rst_rx_internal_bundle_num
R/W
R/W
0x0
0x00
[0]
Rst_rx
R/
set
0x0
Rev: 032609
-
Reset
Value
0x0
Description
Must be set to zero
Port number associated with Rst_tx field (below).
0000 = Port 1
0001 = Port 2
0010 = Port 3
0011 = Port 4
0100 = Port 5
0101 = Port 6
0110 = Port 7
0111 = Port 8
Bundle number associated with Rst_tx field (below)
Valid when Rst_tx is set
0 = When Rst_tx is done during bundle close procedure
1 = When Rst_tx is done during bundle open procedure
This bit is also used in high-speed mode.
If set, the relevant transmit payload type machine resets
its variables (should be given with bundle number and a
proper value of the RST_tx_open/close bit). The CPU
should poll this bit until it is 0 meaning, “reset
acknowledged”. This bit is also used in high-speed mode.
Must be set to zero
Bundle number associated with Rst_rx
1 = Packet classifier generates a reset frame
(Rst_rx_internal_bundle_num is valid). The CPU should
poll this bit until it finds 0; this means “reset
acknowledged”.
100 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
The TDM_cond_data_reg register below holds four octets to be transmitted as conditioning data in the TDM
direction during jitter buffer underrun. This data applies to all bundle types.
TDM_cond_data_reg 0x30
Bits
Data Element Name
R/W
Reset
Value
[31:24]
TDM_cond_octet_a
R/W
0x00
[23:16]
TDM_cond_octet_b
R/W
0x00
[15:8]
TDM_cond_octet_c
R/W
0x00
[7:0]
TDM_cond_octet_d
R/W
0x00
Description
TDM Conditioning Octet A
Must be set to 0x7E for HDLC bundles
Also used in high-speed mode
TDM Conditioning Octet B
Must be set to 0x7E for HDLC bundles
TDM Conditioning Octet C
Must be set to 0x7E for HDLC bundles
TDM Conditioning Octet D
Must be set to 0x7E for HDLC bundles
The ETH_cond_data_reg register below holds four octets to be transmitted as conditioning data towards the packet
network (i.e. toward the Ethernet MAC) when no valid data is available from the TDM port. This applies only to
AAL1 or SAToP/CESoPSN bundles. Tx_cond_octet_type in the Bundle Configuration Tables specifies which of
these octets is used on a per-bundle basis.
ETH_cond_data_reg 0x34
Bits
[31:24]
[23:16]
[15:8]
[7:0]
Data Element Name
ETH_cond_octet_d
ETH_cond_octet_c
ETH_cond_octet_b
ETH_cond_octet_a
R/W
R/W
R/W
R/W
R/W
Packet_classifier_cfg_reg0 0x38
Bits
[31:0]
Data Element Name
Ipv4_add1
R/W
[31:0]
Data Element Name
Ipv4_add2
[31:0]
Data Element Name
MAC_add1
Rev: 032609
Reset
Value
0x0
R/W
Reset
Value
Description
Ethernet Conditioning octet D
Ethernet Conditioning octet C
Ethernet Conditioning octet B
Ethernet Conditioning octet A
Description
This field holds the first of three IPv4 addresses for the
device. The other addresses are held in register
Packet_classifier_cfg_reg1 and
Packet_classifier_cfg_reg8. Relevant only for packets
received from the Ethernet port.
Description
R/W
0x0
This field holds the second of three IPv4 addresses for the
device. The other addresses are held in register
Packet_classifier_cfg_reg0 and
Packet_classifier_cfg_reg8. Relevant only for packets
received from the Ethernet port.
R/W
Reset
Value
Description
Packet_classifier_cfg_reg2 0x40
Bits
0x00
0x00
0x00
0x00
R/W
Packet_classifier_cfg_reg1 0x3C
Bits
Reset
Value
R/W
0x0
This field holds bits 31:0 of the first of two MAC addresses
for the device. The upper bits of this MAC address are in
Packet_classifier_cfg_reg3. The other MAC address is in
Packet_classifier_cfg_reg5 and
101 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Packet_classifier_cfg_reg2 0x40
Bits
Data Element Name
R/W
Packet_classifier_cfg_reg3 0x44
Bits
[31:29]
[28]
Data Element Name
Reserved
Discard_packet_length_
mismatch
R/W
R/W
Reset
Value
Reset
Value
Packet_classifier_cfg_reg6.
Relevant only for packets received from Ethernet port.
Description
0x0
Must be set to zero
0x0
Must be set to zero
[27]
Ip_udp_bn_loc
R/W
0x0
[26:25]
TDMoIP_port_num_loc
R/W
0x0
[24]
Discard_switch_8
R/W
0x0
[23]
Discard_switch_7
R/W
0x0
[22]
Discard_switch_6
R/W
0x0
[21]
Discard_switch_5
R/W
0x0
[20]
Discard_switch_4
R/W
0x0
[19]
Discard_switch_3
R/W
0x0
[18]
Discard_switch_2
R/W
0x0
[17]
Discard_switch_1
R/W
0x0
Rev: 032609
Description
0 = Bundle identifier is located in the source UDP port
number field in IP/UDP packets
1 = Bundle identifier located in the destination UDP port
number field in IP/UDP packets
See section 10.6.13.2.
Used for UDP only:
00 = Packet_classifier_cfg_reg4.TDMoIP_port_num1/2 is
ignored (no checking is performed)
01 = TDMoIP_port_num1/2 should be compared to the
source UDP port number field in IP/UDP packets
10 = TDMoIP_port_num1/2 should be compared to the
destination UDP port number field in IP/UDP packets
11 = Reserved
See section 10.6.13.1.
Packets with Ethertype = CPU_dest_ether_type. See
section 10.6.13.
0 = Forward to CPU
1 = Discard
TDMoP OAM packets. See section 10.6.13.
0 = Forward to CPU
1 = Discard
TDMoP packets whose Rx_Bundle_Identifier doesn’t
match any of the chip’s assigned bundle numbers or OAM
bundle numbers. See section 10.6.13.
0 = Forward to CPU
1 = Discard
IP/UDP packets whose UDP destination/source port
number is different from Packet_classifier_cfg_reg4.
TDMoIP_Port_Num1 or 2. See section 10.6.13.
0 = Forward to CPU
1 = Discard
See TDMoIP_port_num_loc above.
IP packets whose IP protocol field is different from UDP or
L2TPv3. See section 10.6.13.
0 = Forward to CPU
1 = Discard
ARP packets whose IP destination address matches one
of the chip’s IPv4 addresses. See section 10.6.13.
0 = Forward to CPU
1 = Discard
Packets with Ethertype different from IP, MPLS or ARP.
See section 10.6.13.
0 = Forward to CPU
1 = Discard
IP packets whose IP destination address does not match
chip’s IP addresses. See section 10.6.13.
0 = Forward to CPU
1 = Discard
102 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Packet_classifier_cfg_reg3 0x44
Bits
Data Element Name
R/W
Reset
Value
[16]
Discard_switch_0
R/W
0x0
[15:0]
MAC_add1
R/W
0x0000
R/W
Reset
Value
Packet_classifier_cfg_reg4 0x48
Bits
Data Element Name
[31:16]
TDMoIP_port_num2
R/W
0x085E
[15:0]
TDMoIP_port_num1
R/W
0x085E
R/W
Reset
Value
Packet_classifier_cfg_reg5 0x4C
Bits
[31:0]
Data Element Name
MAC_add2
R/W
0x0
R/W
Reset
Value
Packet_classifier_cfg_reg6 0x50
Bits
Data Element Name
[31:16]
Ip_udp_bn_mask_n
R/W
0x0000
[15:0]
MAC_add2
R/W
0x0000
R/W
Reset
Value
Packet_classifier_cfg_reg7 0x54
Bits
[31:16]
Data Element Name
CPU_dest_ether_type
Rev: 032609
R/W
0x0800
Description
ARP packets whose IP destination address does not
match chip’s addresses. See section 10.6.13.
0 = Forward to CPU
1 = Discard
This field holds bits 47:32 of the first of two MAC
addresses for the device. The lower bits of this MAC
address are in Packet_classifier_cfg_reg2. The other
MAC address is in Packet_classifier_cfg_reg5 and
Packet_classifier_cfg_reg6. Relevant only for packets
received from Ethernet port.
Description
Packets with UDP destination port number equal to this
field are recognized as TDMoIP packets. See section
10.6.13.1.
Packets with UDP destination port number equal to this
field are recognized as TDMoIP packets. See section
10.6.13.1.
Description
This field holds bits 31:0 of the second of two MAC
addresses for the device. The upper bits of this MAC
address are in Packet_classifier_cfg_reg6. The other
MAC address is in Packet_classifier_cfg_reg2 and
Packet_classifier_cfg_reg3. Relevant only for packets
received from Ethernet port.
Description
This mask Indicates the width of the bundle identifier. For
example, if the desired width is 8 bits, the following should
be written to this field: 0000000011111111b. See section
10.6.13.2.
This field holds bits 47:32 of the second of two MAC
addresses for the device. The lower bits of this MAC
address are in Packet_classifier_cfg_reg5. The other
MAC address is in Packet_classifier_cfg_reg2 and
Packet_classifier_cfg_reg3. Relevant only for packets
received from Ethernet port.
Description
Ethertype which identifies packets destined for the CPU.
Such packets are sent to CPU or discarded as specified
by Packet_classifier_cfg_reg3.Discard_switch_[8:0].
This field must be set to a value greater than 0x5DC. See
103 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Packet_classifier_cfg_reg7 0x54
Bits
[15:0]
Data Element Name
vlan_2nd_tag_identifier
R/W
R/W
0x8100
R/W
Reset
Value
Packet_classifier_cfg_reg8 0x58
Bits
[31:0]
Data Element Name
Ipv4_add3
R/W
0x0
R/W
Reset
Value
Packet_classifier_cfg_reg9 0x5C
Bits
Data Element Name
Reset
Value
[31:16]
Mef_ether_type
R/W
0x88d8
[15:0]
Mef_oam_ether_type
R/W
0x0800
R/W
Reset
Value
Packet_classifier_cfg_reg10 0x60
Bits
[31:0]
Data Element Name
Ipv6_add1[127:96]
[31:0]
Data Element Name
Ipv6_add1[95:64]
[31:0]
Data Element Name
Ipv6_add1[63:32]
Rev: 032609
Description
This field holds the third of three IPv4 addresses for the
device. The other addresses are held in register
Packet_classifier_cfg_reg0 and
Packet_classifier_cfg_reg1. Relevant only for packets
received from the Ethernet port. If a third IPv4 address is
not needed, this field must be configured to the same
value as Ipv4_add1.
Description
Ethertype for MEF packets. Must be set to a value greater
than 0x5DC. See section 10.6.13.5.
Ethertype for MEF OAM packets. Must be set to a value
greater than 0x5DC. See section 10.6.13.3.
Description
R/W
0x0
R/W
Reset
Value
Description
R/W
0x0
This field holds bits 95:64 of the first of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg14.
Relevant only for packets received from the Ethernet port.
R/W
Reset
Value
Description
Packet_classifier_cfg_reg12 0x68
Bits
section 10.6.13.5.
Second VLAN tag protocol identifier (the first is 0x8100).
See section 10.6.13.4.
This field holds bits 127:96 of the first of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg14.
Relevant only for packets received from the Ethernet port.
Packet_classifier_cfg_reg11 0x64
Bits
Description
R/W
0x0
This field holds bits 63:32 of the first of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg14.
Relevant only for packets received from the Ethernet port.
104 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Packet_classifier_cfg_reg13 0x6C
Bits
[31:0]
Data Element Name
Ipv6_add1[31:0]
R/W
[31:0]
Data Element Name
Ipv6_add2[127:96]
R/W
0x0
R/W
Reset
Value
Description
R/W
0x0
This field holds bits 127:96 of the second of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg10.
Relevant only for packets received from the Ethernet port.
If a second IPv6 address is not needed, this field must be
configured to the same value as Ipv6_add1.
R/W
Reset
Value
Description
Packet_classifier_cfg_reg15 0x74
Bits
[31:0]
Data Element Name
Ipv6_add2[95:64]
R/W
0x0
This field holds bits 95:64 of the second of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg10.
Relevant only for packets received from the Ethernet port.
If a second IPv6 address is not needed, this field must be
configured to the same value as Ipv6_add1.
R/W
Reset
Value
Description
Packet_classifier_cfg_reg16 0x78
Bits
[31:0]
Data Element Name
Ipv6_add2[63:32]
R/W
0x0
This field holds bits 63:32 of the second of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg10.
Relevant only for packets received from the Ethernet port.
If a second IPv6 address is not needed, this field must be
configured to the same value as Ipv6_add1.
R/W
Reset
Value
Description
Packet_classifier_cfg_reg17 0x7C
Bits
[31:0]
Data Element Name
Ipv6_add2[31:0]
R/W
0x0
This field holds bits 31:0 of the second of two IPv6
addresses for the device. The other address is held in
registers starting with Packet_classifier_cfg_reg10.
Relevant only for packets received from the Ethernet port.
If a second IPv6 address is not needed, this field must be
configured to the same value as Ipv6_add1.
R/W
Reset
Value
Description
R/W
0x0000
Packet_classifier_cfg_reg18 0x80
Bits
[31:16]
Data Element Name
VCCV_oam_mask_n
Rev: 032609
Description
This field holds bits 31:0 of the first of two IPv6 addresses
for the device. The other address is held in registers
starting with Packet_classifier_cfg_reg14. Relevant only
for packets received from the Ethernet port.
Packet_classifier_cfg_reg14 0x70
Bits
Reset
Value
Indicates which of the 16 most significant bits of the
control word should be compared to identify VCCV OAM
packets. The values of the bits to be compared are stored
105 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Packet_classifier_cfg_reg18 0x80
Bits
[15:0]
Data Element Name
VCCV_oam_value
R/W
R/W
0x0000
R/W
Reset
Value
R/W
0x00
-
0x0000
R/W
0x000
CPU_rx_arb_max_fifo_level_reg 0xD4
Bits
Data Element Name
[31:25]
Tx_arb_max_fifo_level
[24:10]
Reserved
[9:0]
Rx_arb_max_fifo_level
Rev: 032609
Reset
Value
Description
in the VCCV_oam_value field below. See section
10.6.13.3.
Indicates the value of the 16 most significant bits of the
control word for identifying VCCV OAM packets. The
combination of this field and VCCV_oam_mask_n above
specifies how the device does VCCV OAM identification.
For example, to identify VCCV OAM packets when the 4
most significant bits of the control word are equal to 0x1,
then set this field to 0x1000 and set VCCV_oam_mask_n
to 0xF000. See section 10.6.13.3.
Description
Indicates the maximum level, which the TX_FIFO has
reached (given in dwords) since the last time this register
was read (or since reset). The value of the field is
automatically reset when this register is read by the CPU.
Must be set to zero
Indicates the maximum level, which the RX_FIFO has
reached (given in dwords) since the last time this register
was read (or since reset). The value of the field is
automatically reset when this register is read by the CPU.
106 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.1.2 TDMoP Status Registers
The General_stat_reg register has latched status registers that indicate hardware events. For each bit, the value 1
indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value.
General_stat_reg 0xE0
Bits
Data Element Name
[31:10]
[9]
Reserved
MAC_Rx_fifo_overrun
[8]
Ipver_err_status
[7]
Rx_fifo_sof_err
[6]
TDM_CPU_buff_err
[5]
Rx_fifo_full
[4]
MPLS_err
[3]
OAM_ETH_to_CPU_q_full
[2]
OAM_SW_buff_err
[1]
Non_OAM_ETH_to_CPU_q_full
[0]
Non_OAM_SW_buff_err
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Version_reg 0xE4
Bits
[31:0]
Data Element Name
Chip_version_reg
R/W
R/O
Reset
Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reset
Value
0xABCD
EF01
Description
Must be set to zero
MAC Rx FIFO overflowed
Indicates that a packet was discarded due to IP version
error
Rx FIFO was flushed due to bundle configuration error
Frames received from TDM discarded due to lack of
buffers at TDM TO CPU pool
Packet received from Ethernet discarded because Rx
FIFO is full
Received MPLS packet with more than three labels
OAM packet received from Ethernet and destined to CPU
discarded because ETH TO CPU queue is full.
OAM packet received from Ethernet and destined to CPU
discarded due to lack of SW buffers
Non-OAM packet received from Ethernet and destined to
CPU discarded because ETH TO CPU queue is full.
Non-OAM packet received from Ethernet and destined to
CPU discarded due to lack of SW buffers.
Description
Contains the chip version for the TDMoP block
The Port[n]_sticky_reg1 register has latched status bits that indicate port hardware events. For each bit, the value 1
indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value. The
index n indicates port number: 1-8 for DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Port[n]_sticky_reg1 0xE4+n*4
Bits
Data Element Name
R/W
Reset
Value
[31:8]
[7]
Reserved
Dpll_ovrflow
R/W
[6]
Cdc_detected
R/W
0x0
[5]
[4]
[3]
Smart_self_test_failed
Smart_timeout_expired
Sticky_filter_ovrflow
R/W
R/W
R/W
0x0
0x0
0x0
[2]
Virtual_jitter_buffer_or_ur
R/W
0x0
[1]
[0]
Reacquisition_alarm
Adapt_freeze_state
R/W
R/W
0x0
0x0
Rev: 032609
0x0
0x0
Description
Must be set to zero
Port clock recovery DPLL overflowed
Port clock recovery detected constant delay change in the
network
Provided for debug purposes
Provided for debug purposes
Port clock recovery loop filter overflowed
Port clock recovery virtual jitter buffer reached overrun/
underrun state
Provided for debug purposes
Port clock recovery mechanism is in freeze state
107 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
The Port[n]_stat_reg1 register has real-time (not latched) status fields. The index n indicates port number: 1-8 for
DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Port[n]_stat_reg1 0x100+n*8
Bits
Data Element Name
R/W
Reset
Value
[31:25]
[24]
[23:5]
Reserved
Smart_disabled
DPLL_level
RO
RO
0x0
0x0
0x0
[4:2]
Adapt_current_state
RO
0x0
[1]
RTS
RO
0x0
[0]
TSA_int_act_blk
RO
0x0
Description
Must be set to zero
not documented
not documented
Port n clock recovery current state:
0 = Idle
2 = Acquisition
3 = Tracking1
4 = Tracking2
5 = Recover from Underrun/Overrun
When the Port[n]_cfg_reg.Int_type field specifies a serial
interface, the value of the TDMn_RSIG_RTS pin--which
behaves as RTS (Request To Send)—can be read from
this bit.
Indicates which bank is active:
0 = Port n TSA bank1 is active
1 = Port n TSA bank2 is active
The Port[n]_stat_reg2 register has real-time (not latched) status fields. The index n indicates port number: 1-8 for
DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Port[n]_stat_reg2 0x104+n*8
Bits
[31:29]
[28:4]
[3:0]
Data Element Name
R/W
Bw_tunn
Curr_pdv_std
Convergence_counter
RO
RO
RO
Reset
Value
0x0
0x0
0x0
Description
not documented
not documented
not documented
11.4.2 Bundle Configuration Tables
The base address for the TDMoP bundle configuration tables is 0x8,000. Bundle configurations are 160 bits long
and therefore span five 32-bit words. The least-significant 32-bit word of a bundle configuration is located at
address offset 0x000 + BundleNumber x 4. The most-significant 32-bit word is located at address offset 0x400 +
BundleNumber x 4. There are 64 bundles numbered 0 to 63. In the register descriptions in this section the index n
indicates bundle number: 0 to 63.
Each bundle can be one of three different types: AAL1, HDLC or SAToP/CESoPSN. Subsections 11.4.2.1 through
11.4.2.3 describe the bundle configuration fields for each of the four types. Some fields are common to two or more
of the bundle types. The payload type is specified in the Payload_type_machine field, bits 21:20 of
xxxx_Bundle[n]_cfg[63:32].
11.4.2.1 AAL1 Bundle Configuration
In the register descriptions below, the index n indicates the bundle number: 0 to 63.
AAL1_Bundle[n]_cfg[31:0] 0x000+n*4
Bits
[31:0]
Data Element Name
Rx_bundle_identifier
Rev: 032609
R/W
R/W
Reset
Value
None
Description
Holds the Rx bundle number
108 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
AAL1_Bundle[n]_cfg[63:32] 0x100+n*4
Bits
Data Element Name
R/W
Reset
Value
[31:22]
Rx_max_buff_size
R/W
None
[21:20]
Payload_type_machine
R/W
None
[19]
Tx_RTP
(Tx is toward Ethernet MAC)
R/W
None
[18]
Control_Word_exists
R/W
None
[17:16]
Tx_dest
R/W
None
[15:9]
Rx_max_lost_packets
R/W
None
[8:4]
Number_of_ts
R/W
None
[3]
Rx_ discard_sanity_fail
R/W
None
[2:1]
Header_type
R/W
None
[0]
Tx_R_bit
R/W
None
R/W
Reset
Value
AAL1_Bundle[n]_cfg[95:64] 0x200+n*4
Bits
Data Element Name
[31]
Reserved
R/W
[30]
Tx_cond_data
R/W
None
[29]
Tx_dest_framing
R/W
None
[28]
Tx_CAS_source
R/W
None
[27:13]
[12:11]
Reserved
Tx_AAL1_bundle_type
R/W
None
None
Rev: 032609
None
Description
The size of the jitter buffer. See section 10.6.10. Also the
maximum time interval for which data is stored. The
resolution is determined by the interface type as follows:
For framed E1/T1: 0.5 ms.
For unframed E1/T1 or serial bundles: 1024 bit periods
For high-speed interface: 4096 bit periods.
Allowed values:
For T1-SF: Rx_max_buff_size ≤ 0x2FC
For T1-ESF: Rx_max_buff_size ≤ 0x2F9
For E1-MF: Rx_max_buff_size ≤ 0x3FB
For all interface types, the Rx_max_buff_size must be
greater than Rx_PDVT + PCT (Packet Creation Time).
Note: For unframed, the Rx_max_buff_size resolution is
different than PDVT resolution.
00 = HDLC
01 = AAL1
10 = Reserved
11 = SAToP/CESoPSN
0 = RTP header does not exist in transmitted packets
1 = RTP header exists in transmitted packets
0 = Control word does not exist
1 = Control word exists (default, standard mode)
Destination of packets:
00 = Reserved
01 = Ethernet
10 = CPU
11 = TDM (Cross-connect). See section 10.6.11.10.
The maximum number of Rx packets inserted upon
detection of lost packets
One less than number of assigned timeslots per bundle.
When Rx_AAL1_bundle_type=’00’ (unstructured) then
Number_of_ts=31; this applies also to high speed mode.
0 = Discard AAL1 packets which fail the sanity check
1 = Don’t discard the above packets
See section 10.6.13.8.
00 = MPLS
01 = UDP over IP
10 = L2TPv3 over IP
11 = MEF
0 = Don’t set R bit in header of transmitted packets
1 = Set R bit
Description
Must be set to zero
0 = Regular operation
1 = Use conditioning octet specified by
Tx_cond_octet_type for transmitted packets
Only applies to T1 framed traffic. See section 10.6.5.
0 = Destination framer operates in SF framing
1 = Destination framer operates in ESF framing
Source of transmit CAS bits:
0 = TDMoP block’s RSIG input
1 = Tx software CAS table (section 11.4.9)
Must be set to zero
Bundle type of transmitted payload:
109 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
AAL1_Bundle[n]_cfg[95:64] 0x200+n*4
Bits
Data Element Name
R/W
Reset
Value
[10:6]
Reserved
R/W
None
[5:4]
Tx_cond_octet_type
R/W
None
[3:2]
Rx_AAL1_bundle_type
R/W
None
[1:0]
Protection_mode
R/W
None
AAL1_Bundle[n]_cfg[127:96] 0x300+n*4
Bits
Data Element Name
R/W
Reset
Value
[31]
Reserved
R/W
[30:16]
Rx_PDVT
R/W
None
[15]
Rx_CAS_src
R/W
None
[14]
Rx_cell_chk_ignore
R/W
None
[13]
Reserved
R/W
None
[12]
OAM_ID_in_CW
R/W
None
[11]
Rx_discard
R/W
None
[10]
Rx_dest
R/W
None
[9:8]
Tx_MPLS_labels_l2tpv3_cookies
R/W
None
Rev: 032609
None
Description
00 = Unstructured
01 = Structured
10 = Structured with CAS
11 = Reserved
Must be set to zero
Selects the ETH_cond_octet from ETH_cond_data_reg to
be transmitted towards packet network:
00 = ETH_cond_octet_a
01 = ETH_cond_octet_b
10 = ETH_cond_octet_c
11 = ETH_cond_octet_d
Bundle type of received packets:
00 = Unstructured
01 = Structured
10 = Structured with CAS
11 = Reserved
00 = Stop sending packets
01 = Send each packet once with the first header
10 = Send each packet once with the second header
11 = Send each packet twice: once with the first header
and once with the second header
See section 10.6.16.
Description
Must be set to zero
Packet delay variation time value for AAL1 bundles. See
section 10.6.10. Bits [30:26] are used only when
unframed. The resolution is determined by the interface
type as follows:
For framed E1/T1: 0.5 ms
For unframed E1/T1 or serial bundles: 32 bit periods
For high speed interface: 128 bit periods
Allowed values:
Minimum allowed value: 3 (for all interfaces types)
For T1 SF, ESF: Rx_PDVT < 0x300
Source of signaling conditioning towards TDM:
0 = SDRAM signaling jilter buffer
1 = Rx SW CAS table (section 11.4.13)
0 = Discard AAL1 SAR PDUs with header parity/CRC
errors
1 = Ignore AAL1 SAR PDU header (CRC /parity) checks
Including AAL1 pointer parity error
Must be set to zero
0 = Ignore the OAM packet indication in the control word
1 = Check the OAM packet indication in the control word
See section 10.6.13.3.
0 = Pass through all incoming packets
1 = Discard all incoming packets
0 = TDM
1 = CPU
For MPLS:
00 = Reserved
01 = One label in the TX MPLS stack
10 = Two labels in the TX MPLS stack
11 = Three labels in the TX MPLS stack
For L2TPv3:
110 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
AAL1_Bundle[n]_cfg[127:96] 0x300+n*4
Bits
Data Element Name
R/W
Reset
Value
[7:4]
Port_num
R/W
None
[3:2]
Tx_VLAN_stack
R/W
None
[1]
Rx_bundle_identifier_valid
R/W
None
[0]
Reserved
R/W
None
AAL1_Bundle[n]_cfg[159:128] 0x400+n*4
Bits
Data Element Name
R/W
Reset
Value
[31:23]
Reserved
R/W
None
[22]
Rx_RTP
R/W
None
[21:20]
Rx_L2TPV3_cookies
R/W
None
[19:15]
[14:10]
Reserved
Packet_size_in_cells
R/W
R/W
None
None
[9:5]
Tx_bundle_identifier
R/W
None
[4:0]
Reserved
R/W
None
Description
00 = No cookies in the TX L2TPv3 header
01 = One cookie in the TX L2TPv3 header
10 = Two cookies in the TX L2TPv3 header
11 = Reserved
The port number which the bundle is assigned to:
0000 = Port 1, 0111=Port 8
00 = No VLAN tag in header
01 = One VLAN tag exists in header
10 = Two VLAN tags exist in header
11 = Reserved
Not valid for Rx. Not used by Tx AAL1 but by Ethernet
transmitter block
0 = Rx_bundle_identifier entry isn't valid: If the incoming
frame bundle identifier isn't found in the whole packet
classifier table, the incoming frame is handled
according to packet classifier discard switches in
Packet_classifier_cfg_reg3.
1 = Rx_Bundle_Identifier entry is valid
Must be set to zero
Description
Must be set to zero
0 = RTP header does not exist in received packets
1 = RTP header exists in received packets
For MPLS:
00 = Reserved
01 = One label in the received MPLS stack
10 = Two label in the received MPLS stack
11 = Three label in the received MPLS stack
For L2TPv3:
00 = No cookies in the received L2TPv3 header
01 = One cookie in the received L2TPv3 header
10 = Two cookies in the received L2TPv3 header
11 = Reserved
Must be set to zero.
AAL1 SAR PDUs per frame: 1 - 30
Tx bundle Identifier upper bits
Used only for TX_AAL1 old format
Must be set to zero
11.4.2.2 HDLC Bundle Configuration
In the register descriptions below, the index n indicates the bundle number: 0 to 63.
HDLC_Bundle[n]_cfg[31:0] 0x000+n*4
Bits
[31:0]
Data Element Name
Rx_bundle_identifier
R/W
R/W
HDLC_Bundle[n]_cfg[63:32] 0x100+n*4
Bits
[31:22]
Data Element Name
Reserved
Rev: 032609
R/W
R/W
Reset
Value
None
Reset
Value
None
Description
Holds the Rx bundle number
Description
Must be set to zero
111 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
HDLC_Bundle[n]_cfg[63:32] 0x100+n*4
Bits
Data Element Name
R/W
Reset
Value
[21:20]
Payload_type_machine
R/W
None
[19]
Tx_RTP
R/W
None
[18]
Control_Word_exists
R/W
None
[17:16]
Tx_dest
R/W
None
[15:11]
Reserved
R/W
None
[10:9]
Packet_SN_mode
R/W
None
[8:3]
Reserved
R/W
None
[2:1]
Header_type
R/W
None
[0]
Tx_R_bit
R/W
None
HDLC_Bundle[n]_cfg[95:64] 0x200+n*4
[31:16]
[15:13]
Reserved
Reserved
R/W
R/W
Reset
Value
None
None
[12:2]
Tx_max_frame_size
R/W
None
[1:0]
Reserved
R/W
None
Bits
Data Element Name
R/W
HDLC_Bundle[n]_cfg[127:96] 0x300+n*4
[31:28]
Reserved
R/W
Reset
Value
None
[27]
Tx_stop
R/W
None
[26:13]
Reserved
[12]
OAM_ID_in_CW
R/W
None
[11]
Rx_discard
R/W
None
[10]
Rx_dest
R/W
None
[9:8]
Tx_MPLS_lables_l2tpv3_cookies
R/W
None
Bits
Data Element Name
Rev: 032609
R/W
None
Description
00 = HDLC
01 = AAL1
10 = Reserved
11 = SAToP/CESoPSN
0 = RTP header does not exist in transmitted packets
1 = RTP header exists in transmitted packets
0 = Control word does not exist
1 = Control word exists (default, standard mode)
Destination of packets:
00 = Reserved
01 = Ethernet
10 = CPU
11 = Reserved
Must be set to zero.
Transmitted and expected sequence number is:
00 = Always 0
01 = Incremented normally in wrap-around manner
10 = Reserved
11 = Incremented in wrap-around manner but skips 0
Must be set to zero.
00 = MPLS
01 = UDP over IP
10 = L2TPv3 over IP
11 = MEF
0 = Don’t set R bit in header of transmitted packets
1 = Set R bit
Description
Must be set to zero
Must be set to zero
Tx HDLC maximum transmitted packet size in bytes.
This does not include FCS.
Must be set to zero
Description
Must be set to zero
0 = Send one packet with the 1st header
1 = Stop transmission
Must be set to zero
0 = Ignore the OAM packet indication in the control word
1 = Check the OAM packet indication in the control word
0 = Pass through all incoming packets
1 = Discard all incoming packets
0 = TDM
1 = CPU
For MPLS:
00 = Reserved
01 = One label in the TX MPLS stack
10 = Two labels in the TX MPLS stack
11 = Three labels in the TX MPLS stack
For L2TPv3:
112 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
HDLC_Bundle[n]_cfg[127:96] 0x300+n*4
Bits
Data Element Name
R/W
Reset
Value
[7:4]
Port_num
R/W
None
[3:2]
Tx_VLAN_stack
R/W
None
[1]
Rx_Bundle_Identifier_valid
R/W
None
[0]
Reserved
R/W
None
HDLC_Bundle[n]_cfg[159:128] 0x400+n*4
Bits
Data Element Name
R/W
Reset
Value
0x000
[31:22]
Reserved
[21:20]
Rx_L2TPV3_cookies
R/W
None
[19:16]
Reserved
R/W
None
[15:0]
Tx_IP_checksum
R/W
None
Description
00 = No cookies in the TX L2TPv3 header
01 = One cookie in the TX L2TPv3 header
10 = Two cookies in the TX L2TPv3 header
11 = Reserved
The port number which the bundle is assigned to:
0000 = Port 1, 0111=Port 8
00 = No VLAN tag in header
01 = One VLAN tag exists in header
10 = Two VLAN tags exist in header
11 = Reserved
Not valid for Rx. Not used by Tx AAL1 but by Ethernet
MAC transmit block
0 = Rx_bundle_identifier entry isn't valid: If the incoming
frame bundle identifier isn't found in the whole packet
classifier table, the incoming frame is handled
according to discard switches in
(Packet_classifier_cfg_reg3)
1 = Rx_Bundle_Identifier entry is valid
Must be set to zero
Description
Must be set to zero
For MPLS:
00 = Reserved
01 = One label in the received MPLS stack
10 = Two label in the received MPLS stack
11 = Three label in the received MPLS stack
For L2TPv3:
00 = No cookies in the received L2TPv3 header
01 = One cookie in the received L2TPv3 header
10 = Two cookies in the received L2TPv3 header
11 = Reserved
IP header checksum for IP total length equal to zero
Explain more. Also, why isn’t this in AAL1?
11.4.2.3 SAToP/CESoPSN Bundle Configuration
In the register descriptions below, the index n indicates bundle number: 0 to 63.
SAToP/CESoPSN_Bundle[n]_cfg[31:0] 0x000+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:0]
Rx_bundle_identifier
R/W
None
SAToP/CESoPSN_Bundle[n]_cfg[63:32] 0x100+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:22]
Rx_max_buff_size
Rev: 032609
R/W
None
Description
Holds the Rx bundle number
Description
The size of the jitter buffer. See section 10.6.10. Also the
maximum time interval for which data is stored. The
resolution is determined by the interface type as follows:
For framed E1/T1: 0.5 ms.
113 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
SAToP/CESoPSN_Bundle[n]_cfg[63:32] 0x100+n*4
Reset
Bits
Data Element Name
R/W
Value
[21:20]
Payload_type_machine
R/W
None
[19]
Tx_RTP
R/W
None
[18]
Control_Word_exists
R/W
None
[17:16]
Tx_dest
R/W
None
[15:9]
Rx_max_lost_packets
R/W
None
[8:4]
Number_of_ts
R/W
None
[3]
Rx_ discard_sanity_fail
R/W
None
[2:1]
Header_type
R/W
None
[0]
Tx_R_bit
R/W
None
SAToP/CESoPSN_Bundle[n]_cfg[95:64] 0x200+n*4
Reset
Bits
Data Element Name
R/W
Value
[31]
Reserved
R/W
None
[30]
Tx_cond_data
R/W
None
[29]
Tx_dest_framing
R/W
None
[28]
Tx_CAS_source
R/W
None
[27]
Reserved
R/W
None
[26:16]
TDM_frames_in_packet
or
TDM_bytes_in_packet
R/W
None
Rev: 032609
Description
For unframed E1/T1 or serial bundles: 1024 bit periods
For high speed interface: 4096 bit periods.
Allowed values:
For T1-SF: RX_max_buff_size ≤ 2FChex
For T1-ESF: RX_max_buff_size ≤ 0x2F9
For E1-MF: RX_max_buff_size ≤ 0x3FB
For all interface types the RX_max_buff_size must be
greater than Rx_PDVT + PCT (Packet Creation Time).
Note: For unframed, the RX_max_buff_size resolution is
different than the Rx_PDVT resolution.
00 = HDLC
01 = AAL1
10 = Reserved
11 = SAToP/CESoPSN
0 = RTP header does not exist in transmitted packets
1 = RTP header exists in transmitted packets
0 = Control word does not exist
1 = Control word exists (default, standard mode)
Destination of packets:
01 = Ethernet
10 = CPU
11 = TDM-Rx (cross-connect)
00 = Reserved
The maximum number of Rx packets inserted upon
detection of lost packets
One less than number of assigned timeslots per bundle.
Not relevant for unstructured bundles, or when working in
high speed mode.
0 = Don’t discard the above packets
1 = Discard SAToP/CESoPSN packets which fail the
sanity check
See section 10.6.13.8.
00 = MPLS
01 = UDP over IP
10 = L2TPv3 over IP
11 = MEF
0 = Don’t set R bit in header of transmitted packets
1 = Set R bit
Description
Must be set to zero
0 = Regular operation
1 = Use conditioning octet specified by
Tx_cond_octet_type for transmitted packets
Only applies to T1 framed traffic
0 = Destination framer operates in SF framing
1 = Destination framer operates in ESF framing
Source of transmit CAS bits:
0 = TDMoP block’s RSIG input
1 = Tx software CAS table
See sections See section 10.6.5 and 11.4.9.
Must be set to zero
For structured and structured with CAS CESoPSN
bundles: number of TDM frames included in each packet.
For SAToP bundles: number of TDM bytes included in
each packet.
114 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
SAToP/CESoPSN_Bundle[n]_cfg[95:64] 0x200+n*4
Reset
Bits
Data Element Name
R/W
Value
[15:13]
Reserved
R/W
None
[12:11]
Tx_SATOP_bundle_type
R/W
None
[10:6]
Reserved
R/W
None
[5:4]
Tx_cond_octet_type
R/W
None
[3:2]
Rx_SAToP/CESoPSN_
bundle_type
R/W
None
[1:0]
Protection_mode
R/W
None
SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300+n*4
Reset
Bits
Data Element Name
R/W
Value
[31]
Reserved
R/W
None
[30:16]
Rx_PDVT
R/W
None
[15]
Rx_CAS_src
R/W
None
[14]
Rx_enable_reorder
R/W
None
[13]
Reserved
R/W
None
[12]
OAM_ID_in_CW
R/W
None
[11]
Rx_discard
R/W
None
[10]
Rx_dest
R/W
None
[9:8]
Tx_MPLS_lables_l2tpv3_cookies
R/W
None
Rev: 032609
Description
Note: For Structured with CAS bundles the allowed values
are:
E1 MF: 16, 8, 4, 2, 1
T1 SF/ESF: 24, 12, 8, 6, 4, 3, 2, 1
Must be set to zero
Bundle type of transmitted payload:
00 = Unstructured
01 = Structured
10 = Structured with CAS
11 = Reserved
Must be set to zero.
Selects the ETH_cond_octet from ETH_cond_data_reg to
be transmitted towards packet network:
00 = ETH_cond_octet_a
01 = ETH_cond_octet_b
10 = ETH_cond_octet_c
11 = ETH_cond_octet_d
Bundle type of received packets:
00 = Unstructured
01 = Structured
10 = Structured with CAS
11 = Reserved
00 = Stop sending packets
01 = Send each packet once with the first header
10 = Send each packet once with the second header
11 = Send each packet twice: one with the first header
and one with the second header
Description
Must be set to zero.
Packet delay variation time value for SAToP/CESoPSN
bundles. See section 10.6.10. Bits[30:26] are used only
when unframed. The resolution is determined by the
interface type as follows:
For framed E1/T1: 0.5 ms
For unframed E1/T1 or serial bundles: 32 bit periods
For high speed interface: 128 bit periods
Allowed values:
Minimum allowed value: 3 (for all interface types)
For T1 SF, ESF: Rx_PDVT < 0x300
Source of signaling towards TDM:
0 = SDRAM signaling jitter buffer
1 = Rx SW CAS tables (section 11.4.13)
0 = Disable reorder
1 = Enable reorder
Must be set to zero
0 = Ignore the OAM packet indication in the control word
1 = Check the OAM packet indication in the control word
0 = Pass through all incoming packets
1 = Discard all incoming packets
0 = TDM
1 = CPU
For MPLS:
00 = Reserved
01 = One label in the TX MPLS stack
10 = Two labels in the TX MPLS stack
115 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300+n*4
Reset
Bits
Data Element Name
R/W
Value
[7:4]
Port_num
R/W
None
[3:2]
Tx_VLAN_stack
[1]
Rx_Bundle_Identifier_valid
R/W
None
[0]
Reserved
R/W
None
SAToP/CESoPSN_Bundle[n]_cfg[159:128] 0x400+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:24]
Reserved
[23]
Last_value_insertion
R/W
None
[22]
Rx_RTP
R/W
None
[21:20]
Rx_L2TPV3_cookies
R/W
None
[19:16]
[15:0]
Reserved
Tx_IP_checksum
R/W
R/W
None
None
Rev: 032609
0x00
Description
11 = Three labels in the TX MPLS stack
For L2TPv3:
00 = No cookies in the TX L2TPv3 header
01 = One cookie in the TX L2TPv3 header
10 = Two cookies in the TX L2TPv3 header
11 = Reserved
The port number which the bundle is assigned to:
0000 = Port 1, 0111=Port 8
00 = No VLAN tag in header
01 = One VLAN tag exists in header
10 = Two VLAN tags exist in header
11 = Reserved
Not valid for Rx. Not used by Tx AAL1 but by Ethernet
MAC transmitter block
0 = Rx_bundle_identifier entry isn't valid: If the incoming
frame bundle identifier isn't found in the whole packet
classifier table, the incoming frame is handled
according to packet classifier discard switches in
Packet_classifier_cfg_reg3
1 = Rx_Bundle_Identifier entry is valid
Must be set to zero
Description
Must be set to zero
Enables the insertion of the last received timeslot value in
case packet loss was detected. This insertion is only
performed if 3 frames or less of data per timeslot is lost. If
more than 3 frames of data are lost, the insertion is not
performed and, instead, conditioning is inserted as usual).
0 = last value insertion disabled
1 = last value insertion enabled
0 = RTP header doesn’t exist in received packets
1 = RTP header exists in received packets
For MPLS:
00 = Reserved
01 = One label in the received MPLS stack
10 = Two label in the received MPLS stack
11 = Three label in the received MPLS stack
For L2TPv3:
00 = No cookies in the received L2TPv3 header
01 = One cookie in the received L2TPv3 header
10 = Two cookies in the received L2TPv3 header
11 = Reserved
Must be set to zero
IP header checksum for IP total length equal to zero
116 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.3 Counters
Each counter can be read from two different addresses. Reading from the first address—0x10,000 + offset—does
not affect the counter value. Reading from the second address—0x11,000 + offset—causes the counter to be
cleared after it is read.
Table 11-6. Counters Types
Address
Counter Type
10,000
11,000
Read/Write
Counters – no clear on read
Counters – clear on read
Reset Value
Read Only
Read Only-Clear on Read
None
None
When reading from counters wider than 16 bits in 16-bit mode, use the following procedure:
1. Read from address 2, i.e. H_AD[1]=1. All 32 bits are internally latched and bits 15:0 are output on
H_D[15:0].
2. Read from address 0, i.e. H_AD [1]=0. Bits 31:16 are output on H_D[15:0].
11.4.3.1 Per Bundle Counters
In the register descriptions in this section, the index n indicates the bundle number: 0 to 63.
Ethernet Rx Good Packets Counter 0x000+n*4
Bits
[31:0]
Data Element Name
Good_packets_received
R/W
R
Ethernet Tx Good Packets Counter 0x200+n*4
Bits
[31:0]
Data Element Name
Good_packets_transmitted
R/W
R
Reset
Value
None
Reset
Value
None
Description
Good packets received from Ethernet. Counter wraps
around to 0 from its maximum value.
Description
Good packets transmitted to Ethernet. Counter wraps
around to 0 from its maximum value.
Ethernet Rx Lost/Jump Event Packets Counter 0x300+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:16]
[15:0]
Reserved
Lost_AAL1_packets_Rxd /
Lost_HDLC_packets_Rxd /
Jumped_SAToP/CESoPSN_
packets_Rxd
R
None
None
Description
Must be set to zero
Number of lost/jumped packets encountered by
RX_AAL1, RX_HDLC or RX_SATOP payload machine:
AAL1 and SAToP/CESoPSN – The counter is increased
by the gap between the received packet sequence
number and the expected packet sequence number
(except when this gap is higher than the configured
Rx_max_lost_packets value).
HDLC – The counter is increased by the difference
between the received packet sequence number and the
expected packet sequence number only when this
difference is smaller than 32768.
SAToP/CESoPSN – the CPU can calculate the number of
lost packets using the following equation:
lost packets = (jumped packets –Rxd reordered packets)
Rev: 032609
117 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Ethernet Rx AAL1 Lost Cells / Rx SAToP/CESoPSN Discarded Packets Counter 0x400+n*4
Reset
Bits
Data Element Name
R/W
Description
Value
[31:16]
[15:0]
Reserved
Lost_AAL1_Rxd_cells /
R
None
None
Discarded_SAToP/CESoPSN_
Rxd_packets
SAToP/CESoPSN – Number of received packets that
were discarded by SAToP/CESoPSN hardware machine.
TDM Tx HDLC Frames with Error Counter 0x500+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:16]
[15:0]
Reserved
TDM_HDLC_err_frames
R
None
None
TDM Tx HDLC Good Frames Counter 0x600+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:16]
[31:0]
Reserved
TDM_HDLC_good_frames
Must be set to zero
AAL1 – Number of lost AAL1 SAR PDUs
R
None
None
Description
Must be set to zero
Number of HDLC frames from TDM with any error,
including CRC/alignment/abort/short/long. Counter sticks
at its maximum value and does not roll over to 0.
Description
Must be set to zero
HDLC good frames received from TDM (passed CRC).
Counter wraps around to 0 from its maximum value.
TDM Rx SAToP/CESoPSN Reordered Packets / HDLC/AAL1 Packet SN Error Outside Window Counter
0x100+n*4
Reset
Bits
Data Element Name
R/W
Description
Value
[31:0]
SAToP/CESoPSN_Rxd_re_order
ed_packets /
HDLC_packet_sn_oo_window /
AAL1_packet_sn_oo_window
R
None
SAToP/CESoPSN – Number of received misordered
packets that were successfully reordered by
SAToP/CESoPSN hardware machine. The counter is
incremented each time a miss-ordered packet is received
and saved in the SDRAM.
HDLC – Counter incremented by 1 when SN error outside
window is detected (window of 32,768).
AAL1 – Counter incremented by 1 when SN error outside
window is detected (window configured by
Rx_max_lost_packets).
Counter sticks at its maximum value and does not roll
over to 0.
Rev: 032609
118 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.3.2 Per Jitter Buffer Index Counters
In the register description in this section, the index n indicates the jitter buffer number: 0 to 255.
Jitter Buffer Underrun/Overrun Events Counter 0x800+n*4
Reset
Bits
Data Element Name
R/W
Value
[31:8]
[7:0]
Reserved
JBC_events
R
None
None
Description
Must be set to zero
Number of jitter buffer underrun/overrun events.
AAL1/SAToP/CESoPSN bundles – count of underrun
events. AAL1 counter does not include underruns caused
by pointer mismatches.
HDLC bundles – count of overrun events.
Counter sticks at its maximum value and does not roll
over to 0.
11.4.3.3 General Counters
Received Ethernet Bytes Counter 0xE00
Bits
[31:0]
Data Element Name
ETH_bytes_received
R/W
R
Transmitted Ethernet Bytes Counter 0xE04
Bits
[31:0]
Data Element Name
ETH_bytes_transmitted
R/W
R
Classified Packets Counter 0xE08
Bits
[31:0]
Data Element Name
Classified_packets
R/W
R
Received IP Checksum Errors Counter 0xE0C
Bits
[31:16]
[15:0]
Data Element Name
Reserved
IP_checksum_err_packets
Rev: 032609
R/W
R
Reset
Value
0x0000
0000
Reset
Value
0x0000
0000
Reset
Value
0x0000
0000
Reset
Value
0x0000
0x0000
Description
Total bytes received from Ethernet (good packets which
passed CRC check only). CRC bytes are not counted.
Counter wraps around to 0 from its maximum value.
Description
Total bytes transmitted to Ethernet (good packets which
passed CRC check only). CRC bytes are not counted.
Counter wraps around to 0 from its maximum value.
Description
Counts all packets that pass the packet classifier towards
TDM or CPU and are not discarded.
Counter wraps around to 0 from its maximum value.
Description
Must be set to zero
Counts packets, detected by the packet classifier, as
packets with IP checksum errors.
Counter sticks at its maximum value and does not roll
over to 0.
119 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.4 Status Tables
The TDMoP status tables hold indications of hardware events. Except where noted, these are latched status bits.
For each bit, the value 1 indicates that the event occurred. A bit set to 1 maintains its value unless the host CPU
changes it. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value. The base address for the
TDMoP status tables is 0x12,000.
11.4.4.1 Per Bundle Status Tables
In the register descriptions in this section, the index n indicates the bundle number: 0 to 63.
Rx Payload Type Machine Status 0x000+n*4
Bits
Data Element Name
[31:5]
[4]
Reserved
Rx_SAToP/CESoPSN_frame_
count_err
[3]
Rx_AAL1_cell_hdr_err /
R/W
-
R/W
Reset
Value
None
None
Rx_SAToP/CESoPSN_jump_ove
rflow_err /
[2]
[1]
[0]
Rx_AAL1_packet_sn_oo_
window /
Rx_HDLC_packet_sn_oo_
window /
Rx_SAToP/CESoPSN_packet_
sn_oo_window
R/W
Rx_AAL1_packet_sn_in_
window /
Rx_HDLC_packet_sn_in_
window /
Rx_SAToP/CESoPSN_
overrunn_discard
R/W
Rx_AAL1_ptr_mismatch /
R/W
None
None
R/W
[31:5]
[4]
[3]
Reserved
Tx_HDLC_abort
Tx_HDLC_short
R/W
R/W
[2]
Tx_HDLC_long
R/W
Rev: 032609
SAToP/CESoPSN – Packets received with incorrect
sequence number (higher than the expected sequence
number and within the window allowed by the configured
Rx_max_lost_packets value) and could not be inserted
into the jitter buffer due to insufficient space.
HDLC – Packet SN (Sequence Number) error outside
window (window of 32768)
SAToP/CESoPSN/AAL1 – Packets discarded due to
incorrect Sequence Number (SN equal to the former or
gap between them exceeds limit determined by
Rx_max_lost_packets parameter).
AAL1– Packet sequence number error within window
(determined by Rx_max_lost_packets parameter)
None
SAToP/CESoPSN – Packets discarded because the Jitter
Buffer reached or was in the over-run state.
AAL1 –SAR PDUs received with pointer mismatch
SAToP/CESoPSN – Packets discarded because they
were considered duplicated, or because they were
received too late to be inserted into the Jitter Buffer.
Tx Payload Type Machine Status 0x200+n*4
Data Element Name
Must be set to zero
SAToP/CESoPSN – packets that belong to structuredwith-CAS bundles were received with incorrect number of
frames.
AAL1 – AAL1 SAR PDUs received with incorrect SN
(sequence number), protection fields (CRC/parity),
corrected and not corrected AAL1 SAR PDU header.
HDLC – Packet sequence number error within window
(window of 32768)
Rx_SAToP/CESoPSN_miss_
ordered_discard
Bits
Description
Reset
Value
None
None
None
None
Description
Must be set to zero
HDLC – received frame from TDM with abort indication
HDLC – received frame from TDM shorter than 4 bytes
(including CRC bytes)
HDLC – received frame from TDM longer than maximum
allowed length (Tx_max_frame_size)
120 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Tx Payload Type Machine Status 0x200+n*4
Bits
[1]
[0]
Data Element Name
R/W
Tx_HDLC_align_err
Tx_AAL1_framing_mismatch /
Tx_HDLC_CRC_err /
Tx_SAToP/CESoPSN_framing_
mismatch
R/W
R/W
Tx Buffers Status 0x400+n*4
Bits
[31:1]
[0]
Data Element Name
Reserved
TDM_to_ETH_buff_err
R/W
R/W
Packet Classifier Status 0x600+n*4
Bits
Data Element Name
R/W
Reset
Value
None
None
Reset
Value
None
None
Reset
Value
[31:8]
[7]
Reserved
Packet_length_error
R/W
None
None
[6]
[5]
[4:3]
[2:1]
Rx_sync_loss
Rx_remote_fail
Rx_Lbit_modifier
Fragmentation_bits
RO
RO
RO
RO
None
None
None
None
[0]
Rx_length_mismatch_discard
R/W
None
Description
HDLC – received frame from TDM with alignment error
AAL1 – Start of TDM frame or start of TDM multiframe
mismatch
HDLC – received frame from TDM with CRC error
SAToP/CESoPSN – Start of TDM frame or start of TDM
multiframe mismatch
Description
Must be set to zero
Frames received from TDM were discarded due to lack of
Tx buffers
Description
Must be set to zero
Packet discarded due to mismatch between IP_length/
Control_word_length (for MPLS/MEF) and the actual
length according to the following rules:
IP packets – If IP_length > (actual payload + ip_hdr + CW
+ RTP)
MPLS/MEF packets – If Control_word_length > actual
payload length + CW + RTP
received packet with “L” indication
received packet with “R” indication
received packet with “M” indication
Relevant for SAToP/CESoPSN payload type machine:
00 = Entire (unfragmented) multi-frame structure is carried
in a single packet
01 = Packet carrying the first fragment
10 = Packet carrying the last fragment
11 = Packet carrying an intermediate fragment
Packet discarded due to mismatch between the packet
length and the configuration (for AAL1 and SAToP/
CESoPSN bundles only)
11.4.4.2 Per JBC Index Tables
In the register descriptions in this section, the index n indicates the jitter buffer number: 0 to 255.
Rx JBC Status 0xC00+n*4
Bits
[31:1]
[0]
Data Element Name
Reserved
JBC_overrun
Rev: 032609
R/W
R/W
Reset
Value
None
None
Description
Must be set to zero
AAL1 – overrun has occurred
HDLC – overrun has occurred
SAToP/CESoPSN – overrun has occurred
121 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.5 Timeslot Assignment Tables
Each port has two banks of timeslot assignment (TSA) tables, bank 1 and bank 2. While one bank is actively used
by the TDMoP block, the other bank can be written by the CPU. The active bank for the port is specified by the
TSA_act_blk field in the Port[n]_cfg_reg register.
The base address for the TDMoP status tables is 0x18,000. From this base address:
Bank 1 TSA tables are located at offset 0x000 for ports 1 to 4 and 0x400 for ports 5 to 8.
Bank 2 TSA tables are located at offset 0x200 for ports 1 to 4 and 0x600 for ports 5 to 8.
In the register descriptions in this section, the index port indicates the port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101. The index ts is the timeslot number: 0 to 31.
Rev: 032609
122 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Bank1 Timeslot Assignment Registers
Bank2 Timeslot Assignment Registers
Bits
[31:21]
[20]
[19]
Data Element Name
Reserved
Remote_loop
Local_loop
Ports 1 to 4: 0x000+(port-1)*0x80+ts*4
Ports 5 to 8: 0x400+(port-5)*0x80+ts*4
Ports 1 to 4: 0x200+(port-1)*0x80+ts*4
Ports 5 to 8: 0x600+(port-5)*0x80+ts*4
Reset
R/W
Description
Value
R/W
R/W
None
None
None
[18]
Structured_type
R/W
[17:16]
Timeslot_width
R/W
None
[15]
First_in_bundle
R/W
None
[14]
Rx_assigned
R/W
None
[13]
Transmit_assigned
R/W
None
[12:7]
[6:5]
[4:0]
Bundle_number
Reserved
Jitter_buffer_index
R/W
R/W
R/W
None
None
None
Rev: 032609
Must be set to zero
When set, establishes a loop (per timeslot) between the
data received from the Ethernet port and the data
transmitted towards the Ethernet port.
Notes:
Usually the remote loop is activated on all timeslots
assigned to a bundle.
Only the TDM data is looped back. CAS information is not
looped back.
Available only when interface is configured to single clock
mode (Port[n]_cfg_reg.Two_clocks=0).
When set, establishes a loop (per timeslot) between the
data received from the TDM port and the data transmitted
towards the TDM port. The data transmitted towards the
TDM port is delayed by one TDM frame vs. the received
data.
Notes:
Usually the local loop is activated on all timeslots
assigned to a bundle.
Only the TDM data is looped back. CAS information is not
looped back.
Available only when interface is configured to single clock
mode (Port[n]_cfg_reg.Two_clocks=0).
Must be set for timeslots that are part of AAL1/CESoPSN
bundles whose type is structured or structured-with-CAS.
00 = Reserved
01 =2 bits (only for HDLC bundles)
10 = 7 bits (only for HDLC bundles)
11 = 8 bits
See section 10.6.4 for additional details.
Must be set for the first timeslot of an AAL1 or CESoPSN
bundle. Must be cleared for HDLC bundles.
0 = timeslot is not assigned for the Rx path
1 = timeslot is assigned for the Rx path
0 = timeslot is not assigned for the transmit path
1 = timeslot is assigned for the transmit path
Number of the bundle that the timeslot is assigned to.
Must be set to zero
Jitter buffer index. This field indicates which jitter buffer is
being used for the timeslot or bundle. It is also the index
into the Jitter Buffer Status Table (section 11.4.8).
If a timeslot is assigned to a bundle, the jitter buffer index
must be configured to the number of the first timeslot
assigned to the bundle. Otherwise, it must be configured
to the timeslot number. See section 10.6.10.
123 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.6 CPU Queues
The pools and queue referred to in this section are shown in the block diagram in Figure 10-49. Whenever a queue
or pool level exceeds the associated threshold register, a latched status bit is set in the CPU_Queues_change
register which generates an interrupt unless masked by the associated mask bit in the CPU_Queues_mask
register.
In this section the address offsets in parentheses apply when the CPU data bus is 16 bits wide (pin
DAT_32_16_N=0). The base address for the TDMoP CPU queues is 0x20,000.
Table 11-7. CPU Queues
Addr
Register Name
Offset
0x00 (0x02)
0x04 (0x06)
0x08 (0x0A)
0x0C (0x0E)
0x10 (0x12)
0x14 (0x16)
0x18 (0x1A)
0x1C (0x1E)
0x20 (0x22)
0x24 (0x26)
0x28 (0x2A)
0x2C (0x2E)
0x30 (0x32)
0x34 (0x36)
0x38 (0x3A)
0x54 (0x56)
0x58 (0x5A)
0x5C (0x5E)
0x60 (0x62)
0x64 (0x66)
0x68 (0x6A)
0x6C (0x6E)
0x70 (0x72)
0x74 (0x76)
TDM_to_CPU_pool_insert
TDM_to_CPU_pool_level
TDM_to_CPU_pool_thresh
TDM_to_CPU_q_read
TDM_to_CPU_q_level
TDM_to_CPU_q_thresh
CPU_to_ETH_q_insert
CPU_to_ETH_q_level
CPU_to_ETH_q_thresh
ETH_to_CPU_pool_insert
ETH_to_CPU_pool_level
ETH_to_CPU_pool_thresh
ETH_to_CPU_q_read
ETH_to_CPU_q_level
ETH_to_CPU_q_thresh
CPU_to_TDM_q_insert
CPU_to_TDM_q_level
CPU_to_TDM_q_thresh
Tx_return_q_read
Tx_return_q_level
Tx_return_q_thresh
Rx_return_q_read
Rx_return_q_level
Rx_return_q_thresh
Description
Page
Write to insert a buffer ID into the TDM-to-CPU Pool
Number of buffers stored in the TDM-to-CPU Pool
TDM-to-CPU Pool interrupt threshold
Read to get a buffer ID from the TDM-to-CPU Queue
Number of buffers in the TDM-to-CPU Queue
TDM-to-CPU Queue interrupt threshold
Write to insert a buffer ID into the CPU-to-ETH Queue
Number of buffers in the CPU-to-ETH Queue
CPU-to-ETH Queue interrupt threshold
Write to insert a buffer ID into the ETH-to-CPU Pool
Number of buffers stored in the ETH-to-CPU Pool
ETH-to-CPU Queue interrupt threshold.
Read to get a buffer ID from the ETH-to-CPU Queue
Number of buffers in the ETH-to-CPU Queue.
ETH-to-CPU Queue interrupt threshold
Write to insert a buffer ID into the CPU-to-TDM Queue
Number of buffers stored in the CPU-to-TDM Queue
CPU-to-TDM Queue interrupt threshold
Read to get a buffer ID from the CPU-tx-return Queue
Number of buffers stored in the CPU-tx-return Queue
CPU-tx-return Queue interrupt threshold
Read to get a buffer ID from the CPU-rx-return Queue
Number of buffers stored in the CPU-rx-return Queue
CPU-rx-return Queue interrupt threshold
124
125
125
125
125
125
125
126
126
126
126
126
127
127
127
127
127
127
128
128
128
128
129
129
11.4.6.1 TDM-to-CPU Pool
TDM_to_CPU_pool_insert 0x00 (0x02)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
Rev: 032609
R/W
WO
Reset
Value
0x0
None
Description
Must be set to zero
Writing to this address causes a single 13-bit buffer ID to
be inserted to the TDM-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[23:11]
out of the 24 SDRAM address bits).
124 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
TDM_to_CPU_pool_level 0x04 (0x06)
Bits
[31:8]
[7:0]
Data Element Name
R/W
Reserved
Level
RO
TDM_to_CPU_pool_thresh 0x08 (0x0A)
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Threshold
R/W
RO
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Number of buffers currently stored in the pool. These are
the buffers that are still available to the Tx payload type
machines. Range: 0 to 128.
Description
Must be set to zero
If the number of buffers in the pool is ≤ this threshold, an
interrupt is generated. Range: 0 to 128.
11.4.6.2 TDM-to-CPU Queue
TDM_to_CPU_q_read 0x0C (0x0E)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
R/W
RO
TDM_to_CPU_q_level 0x10 (0x12)
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Level
R/W
RO
TDM_to_CPU_q_thresh 0x14 (0x16)
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Threshold
R/W
RO
Reset
Value
0x0
None
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Reading from this address extracts the first buffer ID from
the TDM-to-CPU queue (bits [12:0]). The buffer ID serves
as the 13 MSbs of the buffer address in the SDRAM (i.e.
corresponds to H_AD[23:11] out of 24 SDRAM address
bits).
Description
Must be set to zero
Number of buffers currently stored in the queue. These
are the buffers still waiting to be handled by the CPU.
Range: 0 to 128.
Description
Must be set to zero
If the number of buffers in the queue is ≥ this threshold,
an interrupt is generated. Range: 0-128
11.4.6.3 CPU-to-ETH Queue
CPU_to_ETH_q_insert 0x18 (0x1A)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
Rev: 032609
R/W
WO
Reset
Value
0x0
None
Description
Must be set to zero
Writing to this address causes a single 13-bit buffer ID to
be inserted to the CPU-to-ETH queue. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[23:11]
out of the 24 SDRAM address bits).
125 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
CPU_to_ETH_q_level 0x1C (0x1E)
Bits
[31:6]
[5:0]
Data Element Name
R/W
Reserved
Level
RO
CPU_to_ETH_q_thresh 0x20 (0x22)
Bits
[31:6]
[5:0]
Data Element Name
R/W
Reserved
Threshold
RO
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Number of buffers currently stored in the queue. Range: 0
to 32.
Description
Must be set to zero
If the number of buffers in the queue is ≤ this threshold,
an interrupt is generated. Range: 0 to 32.
11.4.6.4 ETH-to-CPU Pool
ETH_to_CPU_pool_insert 0x24 (0x26)
Bits
[31:13]
[12:0]
Data Element Name
R/W
Reserved
Buffer ID
WO
ETH_to_CPU_pool_level 0x28 (0x2A)
Bits
[31:8]
[7:0]
Data Element Name
R/W
Reserved
Level
RO
ETH_to_CPU_pool_thresh 0x2C (0x2E)
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Threshold
Rev: 032609
R/W
RO
Reset
Value
0x0
None
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Writing to this address causes a single 13-bit buffer ID to
be inserted to the ETH-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[23:11]
out of the 24 SDRAM address bits).
Description
Must be set to zero
Number of buffers currently stored in the pool. These are
the buffers that are still available to the Rx arbiter. Range:
0 to 128.
Description
Must be set to zero
If the number of buffers in the pool is ≤ this threshold, an
interrupt is generated and only OAM packets are inserted
in the ETH-to-CPU queue (non-OAM packets are
discarded). Range: 0 to 128.
126 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.6.5 ETH- to-CPU Queue
ETH_to_CPU_q_read 0x30 (0x32)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
R/W
RO
ETH_to_CPU_q_level 0x34 (0x36)
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Level
R/W
RO
ETH_to_CPU_q_thresh 0x38 (0x3A)
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Threshold
R/W
RO
Reset
Value
0x0
None
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Reading from this address extracts the first buffer ID from
the ETH-to-CPU queue (bits [12:0]). The buffer ID serves
as the 13 MSbs of the buffer address in the SDRAM (i.e.
corresponds to H_AD[23:11] out of 24 SDRAM address
bits).
Description
Must be set to zero
Number of buffers currently stored in the queue. These
are the buffers still waiting to be handled by the CPU.
Range: 0 to 128.
Description
Must be set to zero
If the number of buffers in the queue is ≥ this threshold,
an interrupt is generated. Range: 0 to 128.
11.4.6.6 CPU-to-TDM Queue
CPU_to_TDM_q_insert 0x54 (0x56)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
R/W
WO
CPU_to_TDM_q_level 0x58 (0x5A)
Bits
[31:6]
[5:0]
Data Element Name
Reserved
Level
R/W
RO
CPU_to_TDM_q_thresh 0x5C (0x5E)
Bits
[31:6]
[5:0]
Data Element Name
Reserved
Threshold
Rev: 032609
R/W
RO
Reset
Value
0x0
None
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Writing to this address causes a single 13-bit buffer ID to
be inserted to the CPU-to-TDM queue. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[23:11]
out of the 24 SDRAM address bits).
Description
Must be set to zero
Number of buffers currently stored in the queue. Range: 0
to 32.
Description
Must be set to zero
If the number of buffers in the queue is ≥ this threshold,
127 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
CPU_to_TDM_q_thresh 0x5C (0x5E)
Bits
Data Element Name
R/W
Reset
Value
Description
an interrupt is generated. Range: 0 to 32.
11.4.6.7 Tx Return Queue
Tx_return_q_read 0x60 (0x62)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
R/W
RO
Tx_return_q_level 0x64 (0x62)
Bits
[31:6]
[5:0]
Data Element Name
Reserved
Level
R/W
RO
Tx_return_q_thresh 0x68 (0x6A)
Bits
[31:6]
[5:0]
Data Element Name
Reserved
Threshold
R/W
RO
Reset
Value
0x0
None
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Reading from this address extracts the first buffer ID from
the CPU Tx return queue (bits [12:0]). The buffer ID
serves as the 13 MSbs of the buffer address in the
SDRAM (i.e. corresponds to H_AD[23:11] out of 24
SDRAM address bits).
Description
Must be set to zero
Number of buffers currently stored in the queue. Range: 0
to 32.
Description
Must be set to zero
If the number of buffers in the queue is ≥ this threshold,
an interrupt is generated. Range: 0 to 32.
11.4.6.8 Rx Return Queue
Rx_return_q_read 0x6C (0x6E)
Bits
[31:13]
[12:0]
Data Element Name
Reserved
Buffer ID
Rev: 032609
R/W
RO
Reset
Value
0x0
None
Description
Must be set to zero
Reading from this address extracts the first buffer ID from
the CPU Rx return queue (bits [12:0]). The buffer ID
serves as the 13 MSbs of the buffer address in the
SDRAM (i.e. corresponds to H_AD[23:11] out of 24
SDRAM address bits).
128 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rx_return_q_level 0x70 (0x72)
Bits
[31:6]
[5:0]
Data Element Name
R/W
Reserved
Level
RO
Rx_return_q_thresh 0x74 (0x76)
Bits
[31:6]
[5:0]
Data Element Name
R/W
Reserved
Threshold
RO
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
Number of buffers currently stored in the queue. Range: 0
to 32.
Description
Must be set to zero
If the number of buffers in the queue is ≥ this threshold,
an interrupt is generated. Range: 0 to 32.
11.4.7 Transmit Buffers Pool
The base address for the TDMoP transmit buffers pool is 0x28,000. See section 10.6.11.7 for details.
11.4.7.1 Per-Bundle Head Pointers
In the register descriptions in this section, the index n indicates the bundle number: 0 to 63.
The RAM should be initialized by CPU software to hold the heads of the linked lists for all open bundles. See
section 10.6.11.7.
Per-Bundle Head[n] 0x800+n*4
Bits
Data Element Name
R/W
Reset
Value
[31:10]
[9]
Reserved
Buffer_valid
R/W
None
None
[8:0]
Buffer_id
R/W
None
Description
Must be set to zero
0 = The head contains non-valid information (i.e. the pool
is empty).
1 = The head points to a valid free buffer.
The full address of the buffer consists of the Tx buffer
base address (specified in General_cfg_reg1.
Tx_buf_base_add) concatenated with the buffer ID and
eleven 0s.
11.4.7.2 Per-Buffer Next-Buffer Pointers
A pointer to the next buffer in the linked list.
In the register descriptions in this section, the index n indicates the buffer number: 0 to 511.
The RAM should be initialized by CPU software to hold the linked lists for all the bundles. See section 10.6.11.7.
Per Buffer Next Buffer[n] 0x000+n*4
Bits
[31:9]
[8:0]
Data Element Name
Reserved
Buffer_offset
Rev: 032609
R/W
R/W
Reset
Value
None
None
Description
Must be set to zero
The offset (ID) of the next buffer in the linked list in the
SDRAM area dedicated to the Tx payload-type machines.
The full address of the buffer consists of the Tx buffer
base address (specified in General_cfg_reg1.
Tx_buf_base_add) concatenated with the buffer offset
and eleven 0s.
129 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.8 Jitter Buffer Control
The base address for the TDMoP jitter buffer control is 0x30,000.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for
DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number: 0 to 31. The index n
indicates the bundle number: 0 to 63. See section 10.6.10 for more information.
Table 11-8. Jitter Buffer Status Tables
Addr
Register Name
Offset
0x000
0x004
(port-1)*0x100+ts*8
(port-1)*0x100+ts*8+4
0x7F8
0x7FC
Status_and_level[1, 0]
Min_and_max_level[1, 0]
Status_and_level[port, ts]
Min_and_max_level[port, ts]
Status_and_level[8, 31]
Min_and_max_level[8, 31]
Description
Page
Jitter buffer port 1 timeslot 0 status and fill level
Jitter buffer port 1 timeslot 0 min / max levels
Jitter buffer status and fill level
Jitter buffer min / max levels
Jitter buffer port 8 timeslot 31 status and fill level
Jitter buffer port 8 timeslot 31 min / max levels
130
131
130
131
130
131
Note 1: In high speed mode, Hs_status_and_level and Hs_min_and_max_level reside in Status_and_level0 and
Min_and_max_level0 registers, respectively.
Note 2: The CPU should never try to read Min_and_max_level from an HDLC bundle. When the CPU performs an access to
these registers, it causes some bits to be changed – bits that are used for other purposes in HDLC bundles and thus
may cause severe problems.
Table 11-9. Bundle Timeslot Tables
Addr
Register Name
Offset
0xF00
0xF00+n*4
0xFFC
Bundle_ts0
Bundle_ts[n]
Bundle_ts63
Description
Page
Assigned timeslots in bundle 0
Assigned timeslots in bundle n
Assigned timeslots in bundle 63
130
130
130
11.4.8.1 Status_and_level Registers
The status_and_level registers have different fields depending on the bundle type: HDLC, Structured
AAL1/CESoPSN, Unstructured AAL1/SAToP or High Speed AAL1/SAToP. The subsections below describe the
status_and_level register fields for each type. In the register descriptions in this section, the index port indicates
port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates
timeslot number: 0 to 31.
11.4.8.1.1 HDLC
Status_and_level (port-1)*0x100+ts*8
Bits
[31:2]
[1:0]
Data Element Name
Reserved
Status
Rev: 032609
R/W
RO
RO
Reset
Value
0x0
None
Description
Always zero
The status of the bundle’s jitter buffer:
00 = jitter buffer is empty
01 = jitter buffer is OK
10 = jitter buffer is full
11 = Reserved
130 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.8.1.2 Structured AAL1/CESoPSN
Status_and_level (port-1)*0x100+ts*8
Bits
Data Element Name
R/W
[31:26]
[25:16]
Reserved
Current_level
RO
RO
[15:2]
[1:0]
Reserved
Status
RO
RO
11.4.8.1.3 Unstructured AAL1/SAToP
Status_and_level (port-1)*0x100
Bits
Data Element Name
R/W
[31]
[30:16]
Reserved
Current_level
RO
RO
[15:2]
[1:0]
Reserved
Status
RO
RO
Reset
Value
0x0
None
0x0
None
Reset
Value
0x0
None
0x0
None
Description
Always zero
The current jitter buffer level for the bundle. The resolution
is 0.5ms.
Always zero
The status of the bundle’s jitter buffer:
00 = jitter buffer is empty
01 = jitter buffer is OK
10 = jitter buffer is full
11 = Reserved
Description
Always zero
The current jitter buffer level for the bundle.
The resolution is 32 interface bit periods.
Always zero
The status of the bundle’s jitter buffer:
00 = jitter buffer is empty
01 = jitter buffer is OK
10 = jitter buffer is full
11 = Reserved
11.4.8.1.4 High Speed AAL1/SAToP
Status_and_level 0x000
Bits
Data Element Name
R/W
Reset
Value
[31:16]
Current_level
RO
0x0000
[15:2]
[1:0]
Reserved
Status
RO
RO
0x0
0x0
Description
The 16 MSbs of the current jitter buffer level (the level is
17 bits wide). The resolution is 64 interface bit periods.
Always zero
The status of the bundle’s jitter buffer:
00 = jitter buffer is empty
01 = jitter buffer is OK
10 = jitter buffer is full
11 = Reserved
11.4.8.2 Min_and_max_level
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for
DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number: 0 to 31..
11.4.8.2.1 Structured AAL1/CESoPSN
Min_and_max_level (port-1)*0x100+ts*8+4
Bits
[31:26]
[25:16]
Data Element Name
Reserved
Minimal_level
Rev: 032609
R/W
RO
RO
Reset
Value
0x0
None
Description
Always zero
The minimal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to all ones. When
underrun is reached, the value of this field remains zero
until it is read by the CPU. The resolution is 0.5 ms..
131 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Min_and_max_level (port-1)*0x100+ts*8+4
Bits
Data Element Name
[15:10]
[9:0]
Reserved
Maximal_level
R/W
RO
RO
Reset
Value
0x00
None
Description
These bits are always zero
The maximal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to zero. When
overrun is reached, the value remains equal to
Rx_max_buff_size until it is read by the CPU. The
resolution is 0.5 ms.
11.4.8.2.2 Unstructured AAL1/SAToP
Min_and_max_level (port-1)*0x100+4
Bits
Data Element Name
R/W
[31]
[30:16]
Reserved
Minimal_level
RO
RO
[15]
[14:0]
Reserved
Maximal_level
RO
RO
Reset
Value
0x0
None
0x0
None
Description
This bit is always zero
The minimal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to all ones. When
underrun is reached, the value of this field remains zero
until it is read by the CPU. The resolution is 32 interface
bit periods.
This bit is always zero
The maximal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to zero. When
overrun is reached, the value remains equal to
Rx_max_buff_size until it is read by the CPU. The
resolution is 32 interface bit periods.
11.4.8.2.3 High Speed AAL1/SAToP
Min_and_max_level 0x004
Bits
Data Element Name
R/W
Reset
Value
[31:16]
Minimal_level
RO
0xFFFF
[15:0]
Maximal_level
RO
0x0000
Description
The 16 MSbs of the minimal level that the jitter buffer has
reached since the last time this register was read. After
this register is read the TDMoP block resets this field to all
ones. When underrun is reached, the value of this field
remains zero until it is read by the CPU. The level is 17
bits wide. The resolution is 64 interface bit periods.
The 16 MSbs of the maximal level that the jitter buffer has
reached since the last time this register was read. After
this register is read the TDMoP block resets this field to
zero. When overrun is reached, the value remains equal
to Rx_max_buff_size until it is read by the CPU. The level
is 17 bits wide. The resolution is 64 interface bit periods.
11.4.8.3 Bundle Timeslot Registers
In this section, the index n indicates the bundle number: 0 to 63.
Bundle_ts[n] 0xF00+n*4
Bits
[31:0]
Data Element Name
Ts_assigned
Rev: 032609
R/W
R/W
Reset
Value
None
Description
Assigned timeslots of the bundle. See section 10.6.10.
1 = Timeslot is assigned to the bundle
0 = Timeslot is not assigned to the bundle
132 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Bundle_ts[n] 0xF00+n*4
Bits
Rev: 032609
Data Element Name
R/W
Reset
Value
Description
Note: When the interface type is Nx64k this field should
be set to all 1s.
133 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.9 Transmit Software CAS
The base address for the TDMoP transmit software CAS register space is 0x38,000. For the CAS information
transmitted in packets in the TDM-to-Ethernet direction, the CAS signaling information stored in these registers can
be used instead of CAS bits coming into the TDMoP block on the TDMn_RSIG_RTS signals. This is configured on
a per-bundle basis using the Tx_CAS_source field in the Bundle Configuration Tables. In the register descriptions
in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1
only for DS34S101.
Table 11-10. Transmit Software CAS Registers
Addr
Offset
Port 1
0x00
0x04
0x08
0x0C
Port 2
0x10
0x14
0x18
0x1C
Port 3
0x20
0x24
0x28
0x2C
Port 4
0x30
0x34
0x38
0x3C
Port 5
0x40
0x44
0x48
0x4C
Port 6
0x50
0x54
0x58
0x5C
Port 7
0x60
0x64
0x68
0x6C
Port 8
0x70
0x74
0x78
0x7C
Rev: 032609
Register Name
Description
Page
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 1
CAS signaling for TS15 to TS8 for Port 1
CAS signaling for TS23 to TS16 for Port 1
CAS signaling for TS31 to TS24 for Port 1
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 2
CAS signaling for TS15 to TS8 for Port 2
CAS signaling for TS23 to TS16 for Port 2
CAS signaling for TS31 to TS24 for Port 2
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 3
CAS signaling for TS15 to TS8 for Port 3
CAS signaling for TS23 to TS16 for Port 3
CAS signaling for TS31 to TS24 for Port 3
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 4
CAS signaling for TS15 to TS8 for Port 4
CAS signaling for TS23 to TS16 for Port 4
CAS signaling for TS31 to TS24 for Port 4
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 5
CAS signaling for TS15 to TS8 for Port 5
CAS signaling for TS23 to TS16 for Port 5
CAS signaling for TS31 to TS24 for Port 5
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 6
CAS signaling for TS15 to TS8 for Port 6
CAS signaling for TS23 to TS16 for Port 6
CAS signaling for TS31 to TS24 for Port 6
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 7
CAS signaling for TS15 to TS8 for Port 7
CAS signaling for TS23 to TS16 for Port 7
CAS signaling for TS31 to TS24 for Port 7
135
135
135
135
Tx_SW_CAS_TS7_TS0
Tx_SW_CAS_TS15_TS8
Tx_SW_CAS_TS23_TS16
Tx_SW_CAS_TS31_TS24
CAS signaling for TS7 to TS0 for Port 8
CAS signaling for TS15 to TS8 for Port 8
CAS signaling for TS23 to TS16 for Port 8
CAS signaling for TS31 to TS24 for Port 8
135
135
135
135
134 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Tx_SW_CAS_TS7_TS0 0x000+(port-1)*0x10
Bits
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
Data Element Name
TS7_CAS_nibble
TS6_CAS_nibble
TS5_CAS_nibble
TS4_CAS_nibble
TS3_CAS_nibble
TS2_CAS_nibble
TS1_CAS_nibble
TS0_CAS_nibble
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Tx_SW_CAS_TS15_TS8 0x004+(port-1)*0x10
Bits
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
Data Element Name
TS15_CAS_nibble
TS14_CAS_nibble
TS13_CAS_nibble
TS12_CAS_nibble
TS11_CAS_nibble
TS10_CAS_nibble
TS9_CAS_nibble
TS8_CAS_nibble
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Tx_SW_CAS_TS23_TS16 0x008+(port-1)*0x10
Bits
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
Data Element Name
TS23_CAS_nibble
TS22_CAS_nibble
TS21_CAS_nibble
TS20_CAS_nibble
TS19_CAS_nibble
TS18_CAS_nibble
TS17_CAS_nibble
TS16_CAS_nibble
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Tx_SW_CAS_TS31_TS24 0x00C+(port-1)*0x10
Bits
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
Data Element Name
TS31_CAS_nibble
TS30_CAS_nibble
TS29_CAS_nibble
TS28_CAS_nibble
TS27_CAS_nibble
TS26_CAS_nibble
TS25_CAS_nibble
TS24_CAS_nibble
Rev: 032609
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Value
None
None
None
None
None
None
None
None
Reset
Value
None
None
None
None
None
None
None
None
Reset
Value
None
None
None
None
None
None
None
None
Reset
Value
None
None
None
None
None
None
None
None
Description
CAS signaling (ABCD) for timeslot 7
CAS signaling (ABCD) for timeslot 6
CAS signaling (ABCD) for timeslot 5
CAS signaling (ABCD) for timeslot 4
CAS signaling (ABCD) for timeslot 3
CAS signaling (ABCD) for timeslot 2
CAS signaling (ABCD) for timeslot 1
CAS signaling (ABCD) for timeslot 0
Description
CAS signaling (ABCD) for timeslot 15
CAS signaling (ABCD) for timeslot 14
CAS signaling (ABCD) for timeslot 13
CAS signaling (ABCD) for timeslot 12
CAS signaling (ABCD) for timeslot 11
CAS signaling (ABCD) for timeslot 10
CAS signaling (ABCD) for timeslot 9
CAS signaling (ABCD) for timeslot 8
Description
CAS signaling (ABCD) for timeslot 23
CAS signaling (ABCD) for timeslot 22
CAS signaling (ABCD) for timeslot 21
CAS signaling (ABCD) for timeslot 20
CAS signaling (ABCD) for timeslot 19
CAS signaling (ABCD) for timeslot 18
CAS signaling (ABCD) for timeslot 17
CAS signaling (ABCD) for timeslot 16
Description
CAS signaling (ABCD) for timeslot 31
CAS signaling (ABCD) for timeslot 30
CAS signaling (ABCD) for timeslot 29
CAS signaling (ABCD) for timeslot 28
CAS signaling (ABCD) for timeslot 27
CAS signaling (ABCD) for timeslot 26
CAS signaling (ABCD) for timeslot 25
CAS signaling (ABCD) for timeslot 24
135 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.10 Receive Line CAS
The base address for the TDMoP Rx line CAS register space is 0x40,000. These read-only registers allow the CPU
to examine the state of the CAS signaling recovered from received packets and transmitted out of the TDMoP
block on the TDMn_TSIG signals. See section 10.6.5.2 for more details. When Rx line CAS bits change, an
interrupt is generated. The Rx_CAS_change registers in the Interrupt Controller indicate which timeslots have
changed CAS bits.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101. The index ts indicates timeslot number: 0 to 31.
Table 11-11. Receive Line CAS Registers
Addr
Register Name
Offset
Port 1
0x000
0x000+ts*4
0x07C
Port 2
0x080
0x080+ts*4
0x0FC
Port 3
0x100
0x100+ts*4
0x17C
Port 4
0x180
0x180+ts*4
0x1FC
Port 5
0x200
0x200+ts*4
0x27C
Port 6
0x280
0x280+ts*4
0x2FC
Port 7
0x300
0x300+ts*4
0x37C
Port 8
0x380
0x380+ts*4
0x3FC
[31:4]
[3:0]
CAS signaling for timeslot 0 for Port 1
CAS signaling for timeslot ts for Port 1
CAS signaling for timeslot 31 for Port 1
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 2
CAS signaling for timeslot ts for Port 2
CAS signaling for timeslot 31 for Port 2
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 3
CAS signaling for timeslot ts for Port 3
CAS signaling for timeslot 31 for Port 3
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 4
CAS signaling for timeslot ts for Port 4
CAS signaling for timeslot 31 for Port 4
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 5
CAS signaling for timeslot ts for Port 5
CAS signaling for timeslot 31 for Port 5
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 6
CAS signaling for timeslot ts for Port 6
CAS signaling for timeslot 31 for Port 6
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 7
CAS signaling for timeslot ts for Port 7
CAS signaling for timeslot 31 for Port 7
136
136
136
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
CAS signaling for timeslot 0 for Port 8
CAS signaling for timeslot ts for Port 8
CAS signaling for timeslot 31 for Port 8
136
136
136
Data Element Name
Reserved
Rx_CAS
Rev: 032609
Page
Rx_Line_CAS_TS0
Rx_Line_CAS_TS[ts]
Rx_Line_CAS_TS31
Rx_Line_CAS 0x000+(port-1)*0x80+ts*4
Bits
Description
R/W
RO
Reset
Value
0x0
None
Description
Must be set to zero
CAS signaling (ABCD) towards TDMn_TSIG
136 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.11 Clock Recovery
The base address for the TDMoP clock recovery register space is 0x48,000. Most of the registers in this section of
the TDMoP block are not documented. The HAL (Hardware Abstraction Layer) software manages these registers.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Table 11-12. Clock Recovery Registers
Addr
Register Name
Offset
Port 1
0x0000
0x0004-00A0
Port 2
0x0400
0x0404-04A0
Port 3
0x0800
0x0804-08A0
Port 4
0x0C00
0x0C04-0CA0
Port 5
0x1000
0x1004-10A0
Port 6
0x1400
0x1404-14A0
Port 7
0x1800
0x1804-18A0
Port 8
0x1C00
0x1C04-1CA0
Description
Page
Control_Word_P1
Clk_recovery_cfg_reg1-40
Port1 clock recovery control bits
Port1 clock recovery configuration registers (not documented)
137
---
Control_Word_P2
Clk_recovery_cfg_reg1-40
Port2 clock recovery control bits
Port2 clock recovery configuration registers (not documented)
137
---
Control_Word_P3
Clk_recovery_cfg_reg1-40
Port3 clock recovery control bits
Port3 clock recovery configuration registers (not documented)
137
---
Control_Word_P4
Clk_recovery_cfg_reg1-40
Port4 clock recovery control bits
Port4 clock recovery configuration registers (not documented)
137
---
Control_Word_P5
Clk_recovery_cfg_reg1-40
Port5 clock recovery control bits
Port5 clock recovery configuration registers (not documented)
137
---
Control_Word_P6
Clk_recovery_cfg_reg1-40
Port6 clock recovery control bits
Port6 clock recovery configuration registers (not documented)
137
---
Control_Word_P7
Clk_recovery_cfg_reg1-40
Port7 clock recovery control bits
Port7 clock recovery configuration registers (not documented)
137
---
Control_Word_P8
Clk_recovery_cfg_reg1-40
Port8 clock recovery control bits
Port8 clock recovery configuration registers (not documented)
137
---
When using the clock recovery mechanism of a certain port, its Rx_PDVT parameter in the bundle configuration
must also be configured.
Clk_Recovery_Control_Word 0x000+(port-1)*0x400
Reset
Bits
Data Element Name
R/W
Value
[31:1]
[0]
Reserved
System_Reset
Rev: 032609
W/O
0x0
0x0
Description
Set according to the HAL function
1 = Reset the clock recovery system
137 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.12 Receive SW Conditioning Octet Select
The base address for the TDMoP Rx software conditioning octet select register space is 0x50,000. These registers
specify which of four conditioning bytes (TDM_cond_octet_a through TDM_cond_octet_d in TDM_cond_data_reg)
the TDMoP block transmits on the TDMn_TX signals during an unassigned timeslot. The specified value is also the
conditioning octet that is inserted into the jitter buffer for lost packet compensation.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101. The index ts indicates timeslot number: 0 to 31.
Table 11-13. Receive SW Conditioning Octet Select Registers
Addr
Register Name
Description
Offset
Port 1
0x000
0x000+ts*4
0x07C
Port 2
0x080
0x080+ts*4
0x0FC
Port 3
0x100
0x100+ts*4
0x17C
Port 4
0x180
0x180+ts*4
0x1FC
Port 5
0x200
0x200+ts*4
0x27C
Port 6
0x280
0x280+ts*4
0x2FC
Port 7
0x300
0x300+ts*4
0x37C
Port 8
0x380
0x380+ts*4
0x3FC
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 1
Rx software conditioning for timeslot ts for Port 1
Rx software conditioning for timeslot 31 for Port 1
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 2
Rx software conditioning for timeslot ts for Port 2
Rx software conditioning for timeslot 31 for Port 2
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 3
Rx software conditioning for timeslot ts for Port 3
Rx software conditioning for timeslot 31 for Port 3
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 4
Rx software conditioning for timeslot ts for Port 4
Rx software conditioning for timeslot 31 for Port 4
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 5
Rx software conditioning for timeslot ts for Port 5
Rx software conditioning for timeslot 31 for Port 5
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 6
Rx software conditioning for timeslot ts for Port 6
Rx software conditioning for timeslot 31 for Port 6
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 7
Rx software conditioning for timeslot ts for Port 7
Rx software conditioning for timeslot 31 for Port 7
138
138
138
Rx_SW_cond_TS0
Rx_SW_cond_TS[ts]
Rx_SW_cond_TS31
Rx software conditioning for timeslot 0 for Port 8
Rx software conditioning for timeslot ts for Port 8
Rx software conditioning for timeslot 31 for Port 8
138
138
138
Rx_SW_cond 0x000+(port-1)*0x80+ts*4
Bits
[31:2]
[1:0]
Data Element Name
Reserved
Cond_octet_sel
Rev: 032609
Page
R/W
R/W
Reset
Value
0x0
None
Description
Must be set to zero
00 = TDM_cond_octet_a
01 = TDM_cond_octet_b
10 = TDM_cond_octet_c
11 = TDM_cond_octet_d
138 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.13 Receive SW CAS
The base address for the TDMoP Rx software CAS register space is 0x58,000. These registers specify the CAS
signaling bits the TDMoP block transmits on the TDMn_TSIG signals during unassigned timeslots and during
timeslots where CAS is not assigned. See section 10.6.5.2 for more details.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101. The index ts indicates timeslot number: 0 to 31.
Table 11-14. Receive SW CAS Registers
Addr
Register Name
Offset
Port 1
0x000
0x000+ts*4
0x07C
Port 2
0x080
0x080+ts*4
0x0FC
Port 3
0x100
0x100+ts*4
0x17C
Port 4
0x180
0x180+ts*4
0x1FC
Port 5
0x200
0x200+ts*4
0x27C
Port 6
0x280
0x280+ts*4
0x2FC
Port 7
0x300
0x300+ts*4
0x37C
Port 8
0x380
0x380+ts*4
0x3FC
Description
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 1
Rx software conditioning for timeslot ts for Port 1
Rx software conditioning for timeslot 31 for Port 1
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 2
Rx software conditioning for timeslot ts for Port 2
Rx software conditioning for timeslot 31 for Port 2
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 3
Rx software conditioning for timeslot ts for Port 3
Rx software conditioning for timeslot 31 for Port 3
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 4
Rx software conditioning for timeslot ts for Port 4
Rx software conditioning for timeslot 31 for Port 4
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 5
Rx software conditioning for timeslot ts for Port 5
Rx software conditioning for timeslot 31 for Port 5
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 6
Rx software conditioning for timeslot ts for Port 6
Rx software conditioning for timeslot 31 for Port 6
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 7
Rx software conditioning for timeslot ts for Port 7
Rx software conditioning for timeslot 31 for Port 7
139
139
139
Rx_SW_CAS_TS0
Rx_SW_CAS_TS[ts]
Rx_SW_CAS_TS31
Rx software conditioning for timeslot 0 for Port 8
Rx software conditioning for timeslot ts for Port 8
Rx software conditioning for timeslot 31 for Port 8
139
139
139
Rx_SW_CAS 0x000+(port-1)*0x80+ts*4
Bits
[31:4]
[3:0]
Data Element Name
Reserved
Rx_CAS
Rev: 032609
Page
R/W
R/W
Reset
Value
0x0
None
Description
Must be set to zero
CAS signaling (ABCD) transmitted towards TDMn_TSIG
when Rx_CAS_src=1 in Bundle Configuration Tables.
Must be different from 0000.
139 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.14 Interrupt Controller
The base address for the interrupt controller register space is 0x68,000.
The Intpend register and the “change” registers listed below have latched status bits that indicate various TDMoP
hardware events. For each bit, the value 1 indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing
0 to a bit does not change its value.
The Intmask register and the other “mask” registers listed below have an interrupt mask bit corresponding to each
bit in the associated “change” register. Each mask bit masks the interrupt when set to 1 and does not mask the
interrupt when set to 0.
The Intpend register is the master interrupt status register. “Change” bits in Intpend indicate that one or more
events of a specific type have occurred. More details about which ports or bundles had that type of event can be
found by reading the change register(s) for that event type.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for
DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Table 11-15. Interrupt Controller Registers
Addr
Register Name
Offset
0x000
0x004
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x080
0x088
0x090
0x098
0x0A0
0x0A8
0x0B0
0x0B8
0x084
0x08C
0x094
0x09C
0x0A4
0x0AC
0x0B4
0x0BC
0x0C0
0x0C8
0x0D0
0x0D8
0x0E0
0x0E8
0x0F0
0x0F8
0x0C4
0x0CC
0x0D4
0x0DC
Intpend
Intmask
Rx_CAS_change_P1
Rx_CAS_change_P2
Rx_CAS_change_P3
Rx_CAS_change_P4
Rx_CAS_change_P5
Rx_CAS_change_P6
Rx_CAS_change_P7
Rx_CAS_change_P8
JBC_underrun_P1
JBC_underrun_P2
JBC_underrun_P3
JBC_underrun_P4
JBC_underrun_P5
JBC_underrun_P6
JBC_underrun_P7
JBC_underrun_P8
JBC_underrun_mask_P1
JBC_underrun_mask_P2
JBC_underrun_mask_P3
JBC_underrun_mask_P4
JBC_underrun_mask_P5
JBC_underrun_mask_P6
JBC_underrun_mask_P7
JBC_underrun_mask_P8
Tx_CAS_change_P1
Tx_CAS_change_P2
Tx_CAS_change_P3
Tx_CAS_change_P4
Tx_CAS_change_P5
Tx_CAS_change_P6
Tx_CAS_change_P7
Tx_CAS_change_P8
Tx_CAS_change_mask_P1
Tx_CAS_change_mask_P2
Tx_CAS_change_mask_P3
Tx_CAS_change_mask_P4
Rev: 032609
Description
Interrupts pending register
Interrupt mask register
Rx CAS change for timeslots in Port 1
Rx CAS change for timeslots in Port 2
Rx CAS change for timeslots in Port 3
Rx CAS change for timeslots in Port 4
Rx CAS change for timeslots in Port 5
Rx CAS change for timeslots in Port 6
Rx CAS change for timeslots in Port 7
Rx CAS change for timeslots in Port 8
JBC underrun in Port 1.
JBC underrun in Port 2
JBC underrun in Port 3
JBC underrun in Port 4
JBC underrun in Port 5
JBC underrun in Port 6
JBC underrun in Port 7
JBC underrun in Port 8
JBC underrun mask for Port 1
JBC underrun mask for Port 2
JBC underrun mask for Port 3
JBC underrun mask for Port 4
JBC underrun mask for Port 5
JBC underrun mask for Port 6
JBC underrun mask for Port 7
JBC underrun mask for Port 8
Tx CAS change for timeslots in Port 1
Tx CAS change for timeslots in Port 2
Tx CAS change for timeslots in Port 3
Tx CAS change for timeslots in Port 4
Tx CAS change for timeslots in Port 5
Tx CAS change for timeslots in Port 6
Tx CAS change for timeslots in Port 7
Tx CAS change for timeslots in Port 8
Tx CAS change mask for Port 1
Tx CAS change mask for Port 1
Tx CAS change mask for Port 1
Tx CAS change mask for Port 1
Page
141
142
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
143
144
144
144
144
144
144
144
144
144
144
144
144
140 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Addr
Offset
0x0E4
0x0EC
0x0F4
0x0FC
0x100
0x104
0x140
0x144
0x148
0x14C
0x180
0x1C0
0x1C4
Register Name
Tx_CAS_change_mask_P5
Tx_CAS_change_mask_P6
Tx_CAS_change_mask_P7
Tx_CAS_change_mask_P8
RTS_change
RTS_mask
CW_bits_change_low_bundles
CW_bits_mask_low_bundles
CW_bits_change_high_bundles
CW_bits_mask_high_bundles
CW_bits_change_mask
CPU_Queues_change
CPU_Queues_mask
Description
Page
Tx CAS change mask for Port 1
Tx CAS change mask for Port 1
Tx CAS change mask for Port 1
Tx CAS change mask for Port 1
RTS change register for Ports 1 to 8
RTS change mask for Ports 1 to 8
CW bits change for bundles 0 to 31
CW bits change mask for bundles 31 to 0
CW bits change for bundles 32 to 63
CW bits change mask for bundles 63 to 32
Which CW fields (L, R, M, FRG) cause interrupts on change
Which CPU pools and queues went above/below thresholds
CPU Queues changed mask
144
144
144
144
144
144
144
144
145
145
145
145
146
Intpend 0x000
Bits
Data Element Name
R/W
Reset
Value
[31:28]
[27]
Reserved
ETH_MAC
R/W
[26]
CPU Queues
R/W
0x0
[25]
CW_bits_change
R/W
0x0
[24]
RTS_changes
R/W
0x0
[23]
Tx_CAS_change_P8
R/W
0x0
[22]
Tx_CAS_change_P7
R/W
0x0
[21]
Tx_CAS_change_P6
R/W
0x0
[20]
Tx_CAS_change_P5
R/W
0x0
[19]
Tx_CAS_change_P4
R/W
0x0
[18]
Tx_CAS_change_P3
R/W
0x0
[17]
Tx_CAS_change_P2
R/W
0x0
[16]
Tx_CAS_change_P1
R/W
0x0
Rev: 032609
0x0
0x0
Description
Must be set to zero
Ethernet MAC interrupt. Read the MAC_interrupt_status
register to determine the interrupt source(s).
The fill level of one or more of the CPU queues and pools
has gone beyond the configured threshold. Read the
CPU_Queues_change register to determine the interrupt
source(s).
At least one of the L, R, M or FRG control Word fields has
changed in one or more bundles. Read the
CW_bits_change_low_bundles and
CW_bits_change_high_bundles registers to determine the
interrupt source(s).
The CW_bits_change_mask register indicates which of
the four CW fields can cause an interrupt when changed.
1 = The state of the RTS pin (TDMn_RSIG_RTS) for one
or more ports has changed. This only applies for port in
asynchronous serial interface mode (Port[n]_cfg_reg.
Int_type=00). Read the RTS_change register to determine
the interrupt source(s).
A change has occurred in the CAS signaling bits for Port8.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port7.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port6.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port5.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port4.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port3.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port2.
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
A change has occurred in the CAS signaling bits for Port1.
141 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Intpend 0x000
Bits
Data Element Name
R/W
Reset
Value
[15]
JBC_underrun_P8
R/W
0x0
[14]
JBC_underrun_P7
R/W
0x0
[13]
JBC_underrun_P6
R/W
0x0
[12]
JBC_underrun_P5
R/W
0x0
[11]
JBC_underrun_P4
R/W
0x0
[10]
JBC_underrun_P3
R/W
0x0
[9]
JBC_underrun_P2
R/W
0x0
[8]
JBC_underrun_P1
R/W
0x0
[7]
Rx_CAS_change_P8
R/W
0x0
[6]
Rx_CAS_change_P7
R/W
0x0
[5]
Rx_CAS_change_P6
R/W
0x0
[4]
Rx_CAS_change_P5
R/W
0x0
[3]
Rx_CAS_change_P4
R/W
0x0
[2]
Rx_CAS_change_P3
R/W
0x0
[1]
Rx_CAS_change_P2
R/W
0x0
[0]
Rx_CAS_change_P1
R/W
0x0
R/W
Reset
Value
Intmask 0x004
Bits
[31:28]
[27]
[26]
Data Element Name
Reserved
ETH_MAC
CPU Queues
Rev: 032609
R/W
R/W
0x0
0x1
0x1
Description
Read the Port7 Tx_CAS_change register to determine the
interrupt source(s).
One of the Port8 Jitter Buffers is in underrun state.
Read the Port8 JBC_underrun register to determine the
interrupt source(s).
One of the Port7 Jitter Buffers is in underrun state.
Read the Port7 JBC_underrun register to determine the
interrupt source(s).
One of the Port6 Jitter Buffers is in underrun state.
Read the Port6 JBC_underrun register to determine the
interrupt source(s).
One of the Port5 Jitter Buffers is in underrun state.
Read the Port5 JBC_underrun register to determine the
interrupt source(s).
One of the Port4 Jitter Buffers is in underrun state.
Read the Port4 JBC_underrun register to determine the
interrupt source(s).
One of the Port3 Jitter Buffers is in underrun state.
Read the Port3 JBC_underrun register to determine the
interrupt source(s).
One of the Port2 Jitter Buffers is in underrun state.
Read the Port2 JBC_underrun register to determine the
interrupt source(s).
One of the Port1 Jitter Buffers is in underrun state.
Read the Port1 JBC_underrun register to determine the
interrupt source(s).
A change has occurred in Port8 Receive Line CAS table.
Read the Port8 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port7 Receive Line CAS table.
Read the Port7 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port6 Receive Line CAS table.
Read the Port6 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port5 Receive Line CAS table.
Read the Port5 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port4 Receive Line CAS table.
Read the Port4 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port 3 Receive Line CAS table.
Read the Port3 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port 2 Receive Line CAS table.
Read the Port2 Rx_CAS_change register to determine the
interrupt source(s).
A change has occurred in Port 1 Receive Line CAS table.
Read the Port1 Rx_CAS_change register to determine the
interrupt source(s).
Description
Must be set to zero
Mask Ethernet MAC interrupt.
Mask CPU Queues change interrupt.
142 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Intmask 0x004
Bits
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Data Element Name
CW_Bits_change
RTS_changes
Tx_CAS_change_P8
Tx_CAS_change_P7
Tx_CAS_change_P6
Tx_CAS_change_P5
Tx_CAS_change_P4
Tx_CAS_change_P3
Tx_CAS_change_P2
Tx_CAS_change_P1
JBC_underrun_P8
JBC_underrun_P7
JBC_underrun_P6
JBC_underrun_P5
JBC_underrun_P4
JBC_underrun_P3
JBC_underrun_P2
JBC_underrun_P1
Rx_CAS_change_P8
Rx_CAS_change_P7
Rx_CAS_change_P6
Rx_CAS_change_P5
Rx_CAS_change_P4
Rx_CAS_change_P3
Rx_CAS_change_P2
Rx_CAS_change_P1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rx_CAS_change 0x40+(port-1)*4
Bits
[31:0]
Data Element Name
Rx_CAS_change
R/W
R/W
JBC_underrun 0x80+(port-1)*4
Bits
[31:0]
Data Element Name
JBC_underrun
R/W
R/W
JBC_underrun_mask 0x84+(port-1)*8
Bits
[31:0]
Data Element Name
JBC_underrun_mask
Rev: 032609
R/W
R/W
Reset
Value
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Reset
Value
0x0000
0000
Reset
Value
0x0000
0000
Reset
Value
0xFFFF
FFFF
Description
Mask Control Word bits change interrupt.
Mask RTS change interrupt.
Mask Tx_CAS_change_P8 interrupt.
Mask Tx_CAS_change_P7 interrupt.
Mask Tx_CAS_change_P6 interrupt.
Mask Tx_CAS_change_P5 interrupt.
Mask Tx_CAS_change_P4 interrupt.
Mask Tx_CAS_change_P3 interrupt.
Mask Tx_CAS_change_P2 interrupt.
Mask Tx_CAS_change_P1 interrupt.
Mask JBC_underrun_P8 interrupt.
Mask JBC_underrun_P7 interrupt.
Mask JBC_underrun_P6 interrupt.
Mask JBC_underrun_P5 interrupt.
Mask JBC_underrun_P4 interrupt.
Mask JBC_underrun_P3 interrupt.
Mask JBC_underrun_P2 interrupt.
Mask JBC_underrun_P1 interrupt.
Mask Rx_CAS_change_P8 interrupt.
Mask Rx_CAS_change_P7 interrupt.
Mask Rx_CAS_change_P6 interrupt.
Mask Rx_CAS_change_P5 interrupt.
Mask Rx_CAS_change_P4 interrupt.
Mask Rx_CAS_change_P3 interrupt.
Mask Rx_CAS_change_P2 interrupt.
Mask Rx_CAS_change_P1 interrupt.
Description
Bit 31 represents timeslot 31 and bit 0 represents timeslot
0 for the port. When a bit is set it indicates a change in
received CAS (from the Ethernet port) in the
corresponding timeslot. The current CAS bits can be read
from the appropriate Rx_Line_CAS register (section
11.4.10). See section.10.6.5.2
Description
Bit 31 represents timeslot 31 and bit 0 represents timeslot
0 for the port. When a bit is set it indicates a jitter buffer
underrun for the corresponding timeslot.
Description
Each bit masks an interrupt caused by the corresponding
bit in the JBC_underrun register.
143 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Tx_CAS_change 0xC0+(port-1)*8
Bits
[31:0]
Data Element Name
Tx_CAS_change
R/W
R/W
Tx_CAS_change_mask 0xC4+(port-1)*8
Bits
[31:0]
Data Element Name
Tx_CAS_change_maxk
R/W
R/W
RTS_change 0x100
Bits
[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Data Element Name
Reserved
RTS8_ change
RTS7_ change
RTS6_ change
RTS5_ change
RTS4_ change
RTS3_ change
RTS2_ change
RTS1_ change
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTS_mask 0x104
Bits
[31:8]
[7:0]
Data Element Name
Reserved
RTS_mask
R/W
R/W
CW_bits_change_low_bundles 0x140
Bits
[31:0]
Data Element Name
CW_bits_change
R/W
R/W
CW_bits_mask_low_bundles 0x144
Bits
[31:0]
Data Element Name
CW_bits_mask
Rev: 032609
R/W
R/W
Reset
Value
0x0000
0000
Reset
Value
Description
Bit 31 represents timeslot 31 and bit 0 represents timeslot
0 for the port. When a bit is set it indicates a change in
transmit (toward the Ethernet port) CAS bits in the
corresponding timeslot. The current CAS bits can be read
from the signaling registers in the neighboring framer IC.
See section 10.6.5.1.
Description
0xFFFF
FFFF
Each bit masks interrupts caused by the corresponding bit
in the Tx_CAS_change register. See section 10.6.5.1.
Reset
Value
Description
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reset
Value
0x0
0xFF
Reset
Value
0xFFFF
FFFF
Reset
Value
0xFFFF
FFFF
Must be set to zero
TDM8_RTS input level
TDM7_RTS input level
TDM6_RTS input level
TDM5_RTS input level
TDM4_RTS input level
TDM3_RTS input level
TDM2_RTS input level
TDM1_RTS input level
changed.
changed.
changed.
changed.
changed.
changed.
changed.
changed.
Description
Must be set to zero
Each bit masks interrupts caused by the corresponding bit
in the RTS_change register.
Description
Bit 31 represents bundle 31 and bit 0 represents bundle 0.
When a bit is set it indicates the corresponding bundle
had a change in one of the bundle’s control word fields: L,
R, M or FRG. The CW_bits_change_mask register
specifies which of the four Control Word fields can cause
an interrupt when changed. The current state of the four
fields can be read from the Packet Classifier Status
register in the per-bundle status tables (section 11.4.4.1).
Description
Bit 31 represents bundle 31 and bit 0 represents bundle 0.
Mask the interrupt from the corresponding bit in the
144 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
CW_bits_mask_low_bundles 0x144
Bits
Data Element Name
R/W
CW_bits_change_high_bundles 0x148
Bits
[31:0]
Data Element Name
CW_bits_change
R/W
R/W
CW_bits_mask_high_bundles 0x14C
Bits
[31:0]
Data Element Name
CW_bits_mask
R/W
R/W
CW_bits_change_mask 0x180
Bits
Data Element Name
R/W
-
Reset
Value
Reset
Value
0xFFFF
FFFF
Reset
Value
0xFFFF
FFFF
Reset
Value
[31:6]
[5]
Reserved
Rx_sync_loss
R/W
0x0
None
[4]
Rx_remote_fail
R/W
None
[3:2]
Rx_Lbit_modifier
R/W
None
[1:0]
Fragmentation_bits
R/W
None
R/W
Reset
Value
CPU_Queues_change 0x1C0
Bits
[31:10]
[9]
[8]
[7]
[6]
[5]
[4:3]
[2]
[1]
[0]
Data Element Name
Reserved
TDM_to_CPU_pool_thresh
TDM_to_CPU_q_thresh
CPU_to_ETH_q_thresh
ETH_to_CPU_pool_thresh
ETH_to_CPU_q_thresh
Reserved
CPU_to_TDM_q_thresh
Tx_return_q_thresh
Rx_ return_q_thresh
Rev: 032609
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
CW_bits_change_low_bundles register.
Description
Bit 31 represents bundle 63 and bit 0 represents bundle
32. When a bit is set it indicates the corresponding bundle
had a change in one of the bundle’s control word fields: L,
R, M or FRG. The CW_bits_change_mask register
specifies which of the four Control Word fields can cause
an interrupt when changed. The current state of the four
fields can be read from the Packet Classifier Status
register in the per-bundle status tables (section 11.4.4.1).
Description
Bit 31 represents bundle 63; bit 0 represents bundle 32.
Mask the interrupt from the corresponding bit in the
CW_bits_change_high_bundles register.
Description
Must be set to zero
Mask interrupts caused by L field changing in Control
Word
Mask interrupts caused by R field changing in Control
Word
Mask interrupts caused by M field changing in Control
Word
Mask interrupts caused by FRG field changing in Control
Word
Description
Must be set to zero
TDM to CPU pool level ≤ threshold.
TDM to CPU queue level ≥ threshold.
CPU to Ethernet queue level ≤ threshold.
Ethernet to CPU pool level ≤ threshold.
Ethernet to CPU queue level ≥ threshold
Must be set to zero
CPU to TDM queue level ≥ threshold.
CPU TX return queue level ≥ threshold.
CPU RX return queue level ≥ threshold.
145 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
CPU_Queues_mask 0x1C4
Bits
[31:10]
[9]
[8]
[7]
[6]
[5]
[4:3]
[2]
[1]
[0]
Data Element Name
Reserved
TDM_to_CPU_pool_thresh
TDM_to_CPU_q_thresh
CPU_to_ETH_q_thresh
ETH_to_CPU_pool_thresh
ETH_to_CPU_q_thresh
Reserved
CPU_to_TDM_q_thresh
Tx_return_q_thresh
Rx_return_q_thresh
Rev: 032609
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Value
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Description
Must be set to zero
Mask TDM_to_CPU_pool_thresh interrupts
Mask TDM_to_CPU_q_thresh interrupts
Mask CPU_to_ETH_q_thresh interrupts
Mask ETH_to_CPU_pool_thresh interrupts
Mask ETH_to_CPU_q_thresh interrupts
Must be set to zero
Mask CPU_to_TDM_q_thresh interrupts
Mask Tx_return_q_thresh interrupts
Mask Rx_return_q_thresh interrupts
146 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.15 Packet Classifier
The base address for the packet classifier register space is 0x70,000. In the register descriptions in this section the
index n indicates register number: 1 to 8. These registers can store eight possible OAM bundle numbers.
Table 11-16. Packet Classifier OAM Identification Registers
Addr
Register Name
Description
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
OAM Identification1
OAM Identification2
OAM Identification3
OAM Identification4
OAM Identification5
OAM Identification6
OAM Identification7
OAM Identification8
OAM Identification Validity1
OAM Identification Validity2
OAM Identification Validity3
OAM Identification Validity4
OAM Identification Validity5
OAM Identification Validity6
OAM Identification Validity7
OAM Identification Validity8
1st Identification for control packets
2nd Identification for control packets
3rd Identification for control packets
4th Identification for control packets
5th Identification for control packets
6th Identification for control packets
7th Identification for control packets
8th Identification for control packets
1st Identification validity for control packets
2nd Identification validity for control packets
3rd Identification validity for control packets
4th Identification validity for control packets
5th Identification validity for control packets
6th Identification validity for control packets
7th Identification validity for control packets
8th Identification validity for control packets
OAM_Identification[n] 0x000+(n-1)*4
Bits
[31:0]
Data Element Name
OAM Identification
R/W
R/W
OAM_Identification_validity[n] 0x080+(n-1)*4
Bits
[31:1]
[0]
Data Element Name
Reserved
OAM Identification Validity
Rev: 032609
Page
R/W
R/W
Reset
Value
None
Reset
Value
0x0
0x0
147
147
147
147
147
147
147
147
147
147
147
147
147
147
147
147
Description
OAM Identification n. If the corresponding validity bit
(below) is set then the packet classifier compares the
bundle identifier of received packets with the value stored
in this register. If they match then the packet classifier
considers the received packet to be an OAM packet. See
section 10.6.13.3.
Description
Must be set to zero
1 = OAM Identification n (above) has a valid value. See
section 10.6.13.3.
147 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.4.16 Ethernet MAC
The base address for the Ethernet MAC register space is 0x72,000.
Configuration and status registers are listed in subsection 11.4.16.1. Counters are listed in subsection 11.4.16.2.
11.4.16.1 Ethernet MAC Configuration and Status Registers
Table 11-17. Ethernet MAC Registers
Addr
Register Name
Offset
0x00
0x04
0x08
0x14
0x24
0x28
0x2C
0x30
0x34
0x38
0x98
0x9C
0xBC
0xC0
MAC_network_control
MAC_network_configuration
MAC_network_status
MAC_transmit_status
MAC_interrupt_status
MAC_interrupt_enable
MAC_interrupt_disable
MAC_interrupt_mask
MAC_PHY_maintenance
MAC_pause_time
MAC_specific_address_lower
MAC_specific_address_upper
MAC_transmit_paulse_quantum
PHY_SMII_status
Description
Page
MAC control register
MAC configuration register
MAC network status register
MAC transmitter status register
MAC interrupt status register
MAC interrupt enable register
MAC interrupt disable register
MAC interrupt mask register
PHY maintenance register
MAC pause time register
MAC specific address register (bits 31:0)
MAC specific address register (bits 47:32)
MAC transmit pause quantum register
PHY SMII status register
148
149
150
150
150
150
151
151
152
152
152
152
153
153
When reading from Ethernet MAC data elements wider than 16 bits in 16-bit mode, use the following procedure:
1. Read from address 2, i.e. H_AD[1]=1. All 32 bits are internally latched and bits 15:0 are output on
H_D[15:0].
2. Read from address 0, i.e. H_AD [1]=0. Bits 31:16 are output on H_D[15:0].
When writing to Ethernet MAC data elements wider than 16 bits in 16-bit mode, use the following procedure:
1. Write to address 2, i.e. H_AD[1]=1. Bits 15:0 are internally latched but not written to the register yet.
2. Write to address 0, i.e. H_AD [1]=0. All 32 bits are written to the register. Bits 31:16 on H_D[15:0] are
written to address 0. Bits 15:0 in the internal latch are written to address 2.
MAC_network_control 0x000
Bits
Data Element Name
R/W
[31:13]
[12]
RO
WO
[11]
Reserved.
Transmit_zero_quantum_pause_
packet
Transmit_pause_packet
[10:9]
[8]
Reserved
Back_pressure
[7]
Reset
Value
0x0
None
WO
None
R/W
0x0
0x0
R/W
0x0
[6]
Write_enable_for_statistics_
registers
Increment_statistics_reg
WO
0x0
[5]
[4]
Clear_statistics_reg
Management_port_enable
WO
R/W
0x0
0x0
Rev: 032609
Description
Read as zero, ignored on write
Writing a 1 to this bit transmits a pause packet with zero
pause quantum at the next available transmitter idle time.
Writing 1 to this bit transmits a pause packet with the
pause quantum in the MAC_transmit_paulse_quantum
register — at the next available transmitter idle time.
Must be set to zero
When set in half duplex mode forces collisions on all
received packets.
Setting this bit to 1 makes the Ethernet MAC counter
registers writable for functional test purposes.
Writing 1 increments all statistics registers by one for test
purposes.
Writing 1 clears the statistics registers.
0 = Disable PHY management port (MDIO high
impedance, MDC forced low.)
1 = Enable the PHY management port
148 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
MAC_network_control 0x000
Bits
Data Element Name
R/W
Reset
Value
[3]
Transmit_enable
R/W
[2]
Rx_enable
R/W
0x0
[1:0]
Reserved
-
0x0
R/W
Reset
Value
MAC_network_configuration 0x004
Bits
Data Element Name
0x0
[31:20]
[19]
Reserved
Ignore_Rx_FCS
R/W
[18]
Enable_half_duplex_Rx
R/W
0x0
[17]
[16]
Reserved
Rx_length_field_checking_enabl
e
R/W
0x0
0x0
[15:14]
[13]
Reserved
Pause_enable
R/W
0x0
0x0
[12]
Retry_test
R/W
0x0
[11:10]
MDC_frequency
R/W
0x2
[9]
[8]
Reserved
Rx_2000_byte_packets
R/W
0x0
0x0
[7:5]
[4]
[3:2]
[1]
Reserved
Reserved
Reserved
Full_duplex
[0]
Speed
Rev: 032609
0x0
0x0
R/W
0x0
0x0
0x0
0x0
R/W
0x0
R/W
Description
0 = Stop transmission immediately, clear the transmit
FIFO and control registers, and reset the transmit
queue pointer register to point to the start of the
transmit descriptor list.
1 = Enable the MAC transmitter to send data.
This bit must be set during normal operation.
0 = Stop packet reception immediately
1 = Enable the MAC receiver to Rx data
Must be set to zero
Description
Read as zero, ignored on write
When set, packets with FCS/CRC errors are not rejected
and no FCS error statistics are counted. For normal
operation, this bit must be set to 0.
Enable packets to be received in half-duplex mode while
transmitting.
Must be set to zero
When set, packets with measured lengths shorter than
their length fields are discarded. Packets containing a
type ID in bytes 13 and 14 (length/type field
≥
not counted as length errors.
Must be set to zero
When set, Ethernet packet transmission pauses when a
valid pause packet is received.
Must be set to zero for normal operation. If set to one, the
back-off between collisions is always one slot time.
Setting this bit to one helps test the ‘too many retries
condition’. Also used in pause packet tests to reduce the
pause counters decrement time from 512 bit times to
every CLK_MII_RX cycle.
Set according to CLK_SYS speed. This field determines
by what number CLK_SYS is divided to generate MDC.
For conformance with 802.3 MDC must not exceed 2.5
MHz. (MDC is only active during MDIO read and write
operations).
Must be set to 0x2.
Must be set to zero
Setting this bit means the MAC receives packets up to
2000 bytes in length.
Normally the MAC rejects any packet above 1518 bytes
Must be set to zero
Must be set to 1
Must be set to zero
If set to 1 the transmit block ignores the state of collision
and carrier sense and allows Rx while transmitting.
0 = 10 Mbit/s operation
1 = 100 Mbit/s operation
Used only for RMII and SMII interfaces.
149 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
MAC_network_status 0x008
Bits
[31:3]
[2]
[1:0]
Data Element Name
Reserved
PHY_access_has_completed
Reserved
R/W
RO
-
MAC_transmit_status 0x014
Bits
Data Element Name
R/W
Reset
Value
0x0
0x1
0x0
Reset
Value
[31:7]
[6]
Reserved
Transmit_underrun
R/W
0x0
0x0
[5:3]
[2]
Reserved
Retry_limit_exceeded
R/W
0x0
0x0
[1]
[0]
Collision_occurred
Reserved
R/W
-
0x0
0x0
Description
Must be set to zero
1 = PHY management logic is idle.
Must be set to zero
Description
Must be set to zero
Set when the MAC transmit FIFO was read while was
empty. If this happens the transmitter forces bad CRC and
forces MII_TX_ERR high. Write 1 to clear this bit.
Must be set to zero
Set when the retry limit has been exceeded. Write 1 to
clear this bit.
Set when a collision occurs. Write 1 to clear this bit.
Must be set to zero
The MAC generates a single interrupt, the ETH_MAC bit in the Intpend register. The MAC_interrupt_status register
below indicates the source of this interrupt. For test purposes each bit can be set or reset by directly writing to this
register regardless of the state of the mask register. Otherwise the corresponding bit in the MAC_interrupt_mask
register must be cleared for a bit to be set in the MAC_interrupt_status register. All bits are reset to zero on read. If
any bit is set in the MAC_interrupt_status register, the ETH_MAC bit is asserted.
At reset all MAC interrupts are disabled. Writing a one to the relevant bit location in the MAC_interrupt_enable
register below enables the associated interrupt. Writing a one to the relevant bit location in the
MAC_interrupt_disable register below disables the associated interrupt. MAC_interrupt_enable and
MAC_interrupt_disable are not registers but merely mechanisms for setting and clearing bits in the read-only
MAC_interrupt_mask register.
MAC_interrupt_status 0x024
Bits
Data Element Name
R/W
Reset
Value
[31:14]
[13]
Reserved
Pause_time_zero
RO
R/W
[12]
Pause_packet_ Rxd
R/W
0x0
[11:6]
[5]
[4]
Reserved
Retry_limit_exceeded
Ethernet_transmit_underrun
R/W
R/W
0x0
0x0
0x0
[3:1]
[0]
Reserved
Management_packet_sent
R/W
0x0
0x0
MAC_interrupt_enable 0x028
Bits
[31:14]
[13]
[12]
[11:6]
Data Element Name
Reserved
Pause_time_zero
Pause_packet_ Rxd
Reserved
Rev: 032609
R/W
WO
WO
-
0x0
0x0
Reset
Value
0x0
0x0
0x0
0x0
Description
Read 0, ignored on write
Set when the MAC_pause_time register decrements to
zero. Cleared when read.
Indicates a valid pause packet has been received.
Cleared when read.
Must be set to zero
Transmit error. Cleared when read.
Set when the MAC transmit FIFO was read while was
empty. If this happens the transmitter forces bad CRC and
forces MII_TX_ERR high. Cleared when read.
Must be set to zero
The PHY maintenance register has completed its
operation. Cleared when read.
Description
Must be set to zero
1 = Enable Pause_time_zero interrupt
1 = Enable Pause_packet_Rxd interrupt
Must be set to zero
150 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
MAC_interrupt_enable 0x028
Bits
[5]
[4]
[3:1]
[0]
Data Element Name
R/W
Retry_limit_exceeded
Ethernet_transmit_underrun
Reserved
Management_packet_sent
WO
WO
WO
MAC_interrupt_disable 0x02C
Bits
[31:14]
[13]
[12]
[11:6]
[5]
[4]
[3:1]
[0]
Data Element Name
R/W
Reserved
Pause_time_zero
Pause_packet_ Rxd
Reserved
Retry_limit_exceeded
Ethernet_transmit_underrun
Reserved
Management_packet_sent
WO
WO
WO
WO
WO
MAC_interrupt_mask 0x030
Bits
[31:14]
[13]
[12]
[11:6]
[5]
[4]
[3:1]
[0]
Data Element Name
Reserved
Pause_time_zero
Pause_packet_ Rxd
Reserved
Retry_limit_exceeded
Ethernet_transmit_underrun
Reserved
Management_packet_sent
Rev: 032609
R/W
RO
RO
RO
RO
RO
Reset
Value
0x0
0x0
0x0
0x0
Reset
Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reset
Value
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x1
Description
1 = Enable Retry_limit_exceeded interrupt
1 = Enable Ethernet_transmit_underrun interrupt
Must be set to zero
1 = Enable Management_packet_sent interrupt
Description
Must be set to zero
1 = Disable Pause_time_zero interrupt
1 = Disable Pause_packet_Rxd interrupt
Must be set to zero
1 = Disable Retry_limit_exceeded interrupt
1 = Disable Ethernet_transmit_underrun interrupt
Must be set to zero
1 = Disable Management_packet_sent interrupt
Description
Must be set to zero
1 = Mask Pause_time_zero interrupt
1 = Mask Pause_packet_Rxd interrupt
Must be set to zero
1 = Mask Retry_limit_exceeded interrupt
1 = Mask Ethernet_transmit_underrun interrupt
Must be set to zero
1 = Mask Management_packet_sent interrupt
151 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
The MAC_PHY_maintenance register below enables the MAC to communicate with a PHY by means of the MDIO
interface. It is used during auto negotiation to ensure that the MAC and the PHY are configured for the same speed
and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation
which is signaled as complete when the PHY_access_has_completed bit is set in the MAC_network_status register
(about 2000 CLK_SYS cycles later). An interrupt is generated as this bit is set. During this time, the MSB of the
register is output on the MDIO pin and the LSB is updated from the MDIO pin with each MDC cycle. In this way a
PHY management packet is transmitted on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading
during the shift operation (not recommended) returns the current contents of the shift register.
At the end of the shift operation, the bits have shifted back to their original locations. For a read operation, the data
bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a
valid PHY management packet is produced.
MAC_PHY_maintenance 0x034
Bits
Data Element Name
R/W
Reset
Value
[31:30]
[29:28]
Start_of_packet
Operation
R/W
R/W
[27:23]
[22:18]
[17:16]
[15:0]
PHY_address
Register_address
Must_be_written_to_10
PHY_data
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0000
R/W
Reset
Value
MAC_pause_time 0x038
Bits
[31:16]
[15:0]
Data Element Name
Reserved
Pause time
RO
RO
0x0000
0x0000
Reset
Value
MAC_specific_address_lower 0x098
Bits
Data Element Name
R/W
[31:0]
MAC Specific Address [31:0]
R/W
MAC_specific_address_upper 0x09C
Bits
[31:16]
[15:0]
Data Element Name
Reserved
MAC Specific Address [47:32]
Rev: 032609
0x0
0x0
R/W
RO
R/W
0x0
Reset
Value
0x0000
0x0000
Description
Must be written 01 for a valid packet
00 = Reserved
01 = Write
10 = Read
11 = Reserved
Specifies the PHY to access
Specifies the register in the PHY to access
Read as written
For a write operation this field is the data to be written to
the PHY. After a read operation this field contains the data
read from the PHY
Description
Read 0, ignored on write
Stores the current value of the pause time register, which
is decremented every 512 bit times.
Description
Least significant bits of the MAC specific address, i.e. bits
31:0. This field is used for transmission of pause packets
as described in section 10.6.12.2.
Description
Read 0, ignored on write
Most significant bits of the MAC specific address, i.e. bits
47:32. See MAC_specific_address_lower for details.
152 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
MAC_transmit_paulse_quantum 0x0BC
Bits
[31:16]
[15:0]
Data Element Name
Reserved
Pause_time
R/W
R/W
0x0000
0xFFFF
R/W
Reset
Value
PHY_SMII_status 0x0C0
Bits
Data Element Name
Reset
Value
[31:21]
[20]
Reserved
SMII_speed
RO
RO
0x0000
None
[19]
SMII_Duplex
RO
None
[18]
SMII_Link
RO
None
[17]
SMII_Jabber
RO
None
[16]
SMII_False_Carrier
RO
None
[15:0]
Reserved
RO
0x0000
Description
Must be set to zero
Transmit pause quantum. Used in hardware generation of
transmitted pause packets as value for pause quantum.
Description
Must be set to zero
Speed recovered from receive SMII
0=10Mbps, 1=100Mbps
Duplex recovered from receive SMII
0=Half Duplex, 1=Full Duplex
Link recovered from receive SMII
0=Link is Down, 1=Link is Up
Jabber recovered from receive SMII
0=OK, 1=Error
False carrier recovered from receive SMII
0=OK, 1=False carrier detected
Must be set to zero
11.4.16.2 Ethernet MAC Counters
Table 11-18. Ethernet MAC Counters
Addr
Register Name
Offset
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x74
0x78
0x7C
0x80
0x84
0x8C
Pause_packets_Rxd_OK
Packets_transmitted_OK
Single_collision_packets
Multiple_collision_packets
Packets_Rxd_OK
Packet_check_sequence_errors
Alignment_errors
Deferred_transmission_packets
Late_collisions
Excessive_collisions
Transmit_underrun_errors
Carrier_sense_errors
Rx_symbol_errors
Excessive_length_errors
Rx_jabbers
Undersize_packets
SQE_test_errors
Transmitted_pause_packets
Description
Pause packets received OK counter
Packets transmitted OK counter
Single collision packets counter
Multiple collision packets counter
Packets received OK counter
Packet check sequence errors counter
Alignment errors counter
Deferred transmission packets counter
Late collisions counter
Excessive collisions counter
Transmit underrun errors counter
Carrier sense errors counter
Rx symbol errors counter
Excessive length errors counter
Rx jabbers counter
Undersize packets counter
SQE test errors counter
Transmitted pause packets counter
Page
154
154
154
154
154
154
155
155
155
155
155
156
156
156
156
156
157
157
These counters stick at their maximum value and do not roll over. They also reset to zero when read and therefore
should be read frequently enough to prevent loss of data. The Rx counters are only incremented when the
Rx_enable bit is set in the MAC_network_control register.
Rev: 032609
153 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Pause_packets_Rxd_OK 0x03C
Bits
[31:16]
[15:0]
Data Element Name
Reserved
Pause_packets_Rxd_OK
R/W
R/W
Packets_transmitted_OK 0x040
Bits
[31:0]
Data Element Name
Packets_transmitted_OK
R/W
R/W
Single_collision_packets 0x044
Bits
[31:16]
[15:0]
Data Element Name
Reserved
Single_collision_packets
R/W
R/W
Multiple_collision_packets 0x048
Bits
[31:16]
[15:0]
Data Element Name
Reserved
Multiple_collision_packets
R/W
R/W
Packets_Rxd_OK 0x04C
Bits
[31:24]
[23:0]
Data Element Name
Reserved
Packets_Rxd_OK
R/W
R/W
Packet_check_sequence_errors 0x050
Bits
[31:8]
[7:0]
Data Element Name
R/W
Reserved
Packet_check_sequence_errors
R/W
Rev: 032609
Reset
Value
0x0
0x0
Reset
Value
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
A 16-bit register counting the number of good pause
packets received. A good packet has a length of 64 to
1518 (2000 if Rx_2000_byte_packets is set in the
MAC_network_configuration register) and has no FCS,
alignment or Rx symbol errors.
Description
A 32-bit register counting the number of packets
successfully transmitted, i.e. no underrun and not too
many retries.
Description
Must be set to zero
A 16-bit register counting the number of packets
experiencing a single collision before being successfully
transmitted, i.e. no underrun.
Description
Must be set to zero
A 16-bit register counting the number of packets
experiencing between two and fifteen collisions prior to
being successfully transmitted, i.e. no underrun and not
too many retries.
Description
Must be set to zero
A 24-bit register counting the number of good packets
received, i.e. packet length is 64 to 1518 bytes (2000 if
Rx_2000_byte_packets is set in the
MAC_network_configuration register) and has no FCS,
alignment or Rx symbol errors.
Description
Must be set to zero
An 8-bit register counting packets that are an integral
number of bytes, have bad CRC and are between 64 and
1518 bytes in length (2000 if Rx_2000_byte_packets is
set in the MAC_network_configuration register).
154 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Alignment_errors 0x054
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Alignment_errors
R/W
R/W
Deferred_transmission_packets 0x058
Bits
[31:16]
[15:0]
Data Element Name
Reserved
Deferred_transmission_packets
R/W
R/W
Late_collisions 0x05C
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Late_collisions
R/W
R/W
Excessive_collisions 0x060
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Excessive_collisions
R/W
R/W
Transmit_underrun_errors 0x064
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Transmit_underruns
Rev: 032609
R/W
R/W
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
An 8-bit register counting packets that are not an integral
number of bytes long and have bad CRC when their
length is truncated to an integral number of bytes and are
between 64 and 1518 bytes in length (2000 if
Rx_2000_byte_packets is set in the
MAC_network_configuration register).
Description
Must be set to zero
A 16-bit register counting the number of packets
experiencing deferral due to carrier sense being active on
their first attempt at transmission. Packets involved in any
collision are not counted nor are packets that experienced
a transmit underrun.
Description
Must be set to zero
An 8-bit register counting the number of packets that
experience a collision after the slot time (512 bits) has
expired. A late collision is counted twice i.e. both as a
collision and a late collision.
Description
Must be set to zero
An 8-bit register counting the number of packets that
failed to be transmitted because they experienced 16
collisions.
Description
Must be set to zero
An 8-bit register counting the number of packets not
transmitted due to a transmit FIFO underrun. If this
register is incremented, no other Ethernet MAC counter is
incremented.
155 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Carrier_sense_errors 0x068
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Carrier_sense_errors
R/W
R/W
Rx_symbol_errors 0x074
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Rx_symbol_errors
R/W
R/W
Excessive_length_errors 0x078
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Excessive_length_packets
R/W
R/W
Rx_jabbers 0x07C
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Rx_jabbers
R/W
R/W
Undersize_packets 0x080
Bits
[31:8]
[7:0]
Data Element Name
Reserved
Undersize_packets
Rev: 032609
R/W
R/W
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Reset
Value
0x0
0x00
Reset
Value
0x0
0x0
Description
Must be set to zero
An 8-bit register counting the number of packets
transmitted where carrier sense was not seen during
transmission or where carrier sense was deasserted after
being asserted in a transmit packet without collision (no
underrun). Only incremented in half-duplex mode. The
only effect of a carrier sense error is to increment this
register. The behavior of the other Ethernet MAC counters
is unaffected by the detection of a carrier sense error.
Description
Must be set to zero
An 8-bit register counting the number of packets that had
MII_RX_ERR asserted during reception.
Description
Must be set to zero
An 8-bit register counting the number of packets received
exceeding 1518 bytes in length (2000 if
Rx_2000_byte_packets is set in the
MAC_network_configuration register) but do not have a
CRC error, an alignment error nor a Rx symbol error.
Description
Must be set to zero
An 8-bit register counting the number of packets received
exceeding 1518 bytes in length (2000 if
Rx_2000_byte_packets is set in the
MAC_network_configuration register) and have either a
CRC error, an alignment error or a Rx symbol error.
Description
Must be set to zero
An 8-bit register counting the number of packets received
less than 64 bytes in length, that do not have either a
CRC error or an alignment error.
156 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
SQE_test_errors 0x084
Bits
[31:8]
[7:0]
Data Element Name
Reserved
SQE_test_errors
R/W
R/W
Transmitted_pause_packets 0x08C
Bits
[31:16]
[15:0]
Data Element Name
R/W
Reserved
Transmitted_pause_packets
R/W
Rev: 032609
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
Description
Must be set to zero
An 8-bit register counting the number of packets where
collision was not asserted within 96 bit times (an
interpacket gap) of MII_TX_EN being deasserted in half
duplex mode.
Description
Must be set to zero
A 16-bit register counting the number of pause packets
transmitted.
157 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
12. JTAG Information
For the latest JTAG model, search under http://www.maxim-ic.com/tools/bsdl/.
JTAG Description
The device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP and IDCODE. See Figure 12-1 for a block diagram. The device contains
the following items which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture:
Test Access Port (TAP)
Instruction Register
Boundary Scan Register
TAP Controller
Bypass Register
Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTRST_N, JTDI, JTDO, and JTMS.
Details on these pins can be found in Table 9-7. Details on the Boundary Scan Architecture and the Test Access
Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 12-1. JTAG Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
MUX
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
Vdd
10K
Vdd
10K
JTDI
SELECT
OUTPUT ENABLE
Vdd
10K
JTMS
JTCLK
JTRST
JTDO
JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See
Figure 12-2 for details on each of the states described below. The TAP controller is a finite state machine which
responds to the logic level at JTMS on the rising edge of JTCLK.
Rev: 032609
158 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 12-2. JTAG TAP Controller State Machine
Test-Logic-Reset
1
0
0
Run-Test/Idle
1
Select
DR-Scan
1
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
Exit1-IR
0
0
Pause-DR
1
Pause-IR
0
0
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
1
1
Exit1-DR
0
1
Select
IR-Scan
0
Update-IR
1
0
Test-Logic-Reset. Upon power-up of the device, the TAP controller starts in the Test-Logic-Reset state. The
Instruction Register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register
and Test Register remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the SelectIR-SCAN state.
Capture-DR. Data may be parallel loaded into the Test Data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test Register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low
or it to the Exit1-DR state if JTMS is high.
Shift-DR. The Test Data Register selected by the current instruction is connected between JTDI and JTDO and
shifts data one stage towards its serial output on each rising edge of JTCLK. If a Test Register selected by the
current instruction is not placed in the serial path, it maintains its previous state.
Rev: 032609
159 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the PauseDR state.
Pause-DR. Shifting of the Test registers is halted while in this state. All Test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
and terminate the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes in the
shift register. A rising edge on JTCLK with JTMS low, puts the controller in the Run-Test-Idle state. With JTMS
high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All Test registers retain their previous state. The Instruction register remains unchanged during
this state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a
scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the controller back into
the Test-Logic-Reset state.
Capture-IR. The Capture-IR state is used to load the shift register in the Instruction register with a fixed value.
This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller
enters the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the shift register in the Instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all Test
registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1IR state. A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state while moving data one
stage through the Instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the
rising edge of JTCLK, the controller enters the Update-IR state and terminate the scanning process.
Pause-IR. Shifting of the Instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts
the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge
on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high put the controller in the Update-IR state. The controller loops
back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the Instruction shift register is latched into the parallel output on the falling
edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A
rising edge on JTCLK with JTMS low, puts the controller in the Run-Test-Idle state. With JTMS high, the controller
enters the Select-DR-Scan state.
JTAG Instruction Register and Instructions
The Instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage towards the serial output at
JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to
the Update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the
instruction parallel output. Instructions supported by the device and their respective operational binary codes are
shown in Table 12-1.
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Table 12-1. JTAG Instruction Codes
Instructions
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
Selected Register
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
Instruction Codes
010
111
000
011
100
001
SAMPLE/PRELOAD. A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the device can be sampled at the Boundary Scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift
data into the Boundary Scan register via JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in
the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of
all digital output pins are driven. The Boundary Scan register is connected between JTDI and JTDO. The CaptureDR samples all digital inputs into the Boundary Scan register.
BYPASS. When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the device’s
normal operation.
IDCODE. When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code is loaded into the Identification register on the rising edge of
JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially
via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output.
The device ID code always has a one in the LSB position. The device ID codes are listed in Table 12-2.
Table 12-2. JTAG ID Code
Device
DS34S101
DS34S102
DS34S104
DS34S108
Rev[31:28]
0
0
0
0
ID Code (hex)
Device ID [27:12]
0098
0099
009A
009B
Manu[11:0]
143
143
143
143
HIGHZ. All digital outputs are placed into a high impedance state. The Bypass Register is connected between
JTDI and JTDO.
CLAMP. All digital outputs pins output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
JTAG Test Registers
IEEE 1149.1 requires a minimum of two Test registers; the Bypass register and the Boundary Scan register. An
optional Test register has been included in the device design. This Test register is the Identification register and is
used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register. This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Rev: 032609
161 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Identification Register. The Identification register contains a 32-bit shift register and a 32-bit latched parallel
output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state.
Boundary Scan Register. This register contains both a shift register path and a latched parallel output for all
control cells and digital I/O cells and is 32 bits in length. The BSDL file found at http://www.maximic.com/tools/bsdl/ shows the entire cell bit locations and definitions.
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
13. DC Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input, Bi-directional or Open Drain
Output Lead with Respect to DVSS .............................................................................................-0.5V to +5.5V
Supply Voltage (DVDDIO) with Respect to DVSS...............................................................................-0.5V to +3.6V
Supply Voltage (DVDDC, ACVDD1, ACVDD2) with Respect to DVSS................................................-0.5V to +2.0V
Ambient Operating Temperature Range ........................................................................................... -40°C to +85°C
Junction Operating Temperature Range......................................................................................... -40°C to +125°C
Storage Temperature Range.......................................................................................................... -55°C to +125°C
Soldering Temperature Range ................................................................. See IPC/JEDEC J-STD-020 Specification
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect reliability. Ambient Operating Temperature Range is assuming the
device is mounted on a JEDEC standard test board in a convection cooled JEDEC test enclosure.
Note: The typical values listed below are not production tested.
Table 13-1. Recommended DC Operating Conditions
(Tj = -40°C to +85°C.)
Parameter
Symbol
Conditions
Output Logic 1
VIH
Output Logic 0
VIL
Power Supply Voltage
DVDDIO
DVDDC, ACVDD1,
Power Supply Voltage
ACVDD2
Table 13-2. DC Electrical Characteristics
(Tj = -40°C to +85°C.)
Parameter
Symbol
3.3V Supply Current (@ 3.465V)
DS34S108
IDDIO
DS34S104
DS34S102
DS34S101
1.8V Supply Current (@1.89V)
IDDC
Lead Capacitance
CIO
Input Leakage
IIL
Input Leakage, Internal Pull-Down
IILP
Output Leakage (when Hi-Z)
ILO
Output Voltage (IOH = -4.0mA)
VOH
Output Voltage (IOL = +4.0mA)
VOL
Output Voltage (IOH = -8.0mA)
VOH
Output Voltage (IOL = -8.0mA)
VOL
Output Voltage (IOH = -12.0mA)
VOH
Output Voltage (IOL = +12.0mA)
VOL
Input Voltage Logic 1
VIH
Input Voltage Logic 0
VIL
Conditions
Min
2.4
-0.3
3.135
3.300
Max
3.465
+0.8
3.465
Units
V
V
V
1.71
1.8
1.89
V
Min
Typ
Max
Units
50
50
TBD
TBD
225
7
65
65
TBD
TBD
280
Note 1
Note 1
4 mA output
4 mA output
8 mA output
8 mA output
12 mA output
12 mA output
-10
-100
-10
2.4
2.4
2.4
2.0
Typ
+10
-10
+10
0.4
0.4
0.4
0.8
NOTES:
1. All outputs loaded with rated capacitance; all inputs between DVDDIO and DVSS; inputs with pull-ups connected to DVDDIO.
Rev: 032609
mA
mA
pF
µA
µA
µA
V
V
V
V
V
V
V
V
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14. AC Timing Characteristics
Table 14-1. Input Pin Transition Time Requirements
PARAMETER
SYMBOL
CONDITIONS
Rise Time
tr
Fall Time
tf
MIN
TYP
MAX
UNITS
10 to 90% of DVDDIO
6
ns
90 to 10% of DVDDIO
6
ns
14.1 CPU Interface Timing
Table 14-2. CPU Interface AC characteristics
PARAMETER
RST_SYS_N Active Low Pulse Width
H_CS_N Deasserted or H_R_W_N Low to H_D[31:0]
High-Z
H_READY_N Active Pull-Up Pulse Width
Latest of H_WR_BEx_N Asserted or H_CS_N Asserted
to H_D[31:0] Valid
H_CS_N Deasserted to H_D[31:0] Not Valid
H_CS_N Asserted to H_AD[24:1] Valid
H_CS_N Deasserted to H_AD[24:1] Not Valid
H_CS_N Asserted to H_R_W_N Valid
H_CS_N Deasserted to H_R_W_N Not Valid
H_CS_N Deasserted to H_READY_N High
H_CS_N Deasserted to H_WR_BEx_N[3:0] Not Valid
Delay Between Two Successive Accesses
H_D[31:0] Valid before H_READY_N Active Low
NOTE: The output timing specified assumes 50 pF load.
SYMBOL
T5
T22
T26
T31
MIN
50
2.9
T32
T33
T34
T35
T36
T37
T40
T43
1.5
T44
1.5
TYP
MAX
UNITS
16.2
µs
ns
6.8
0
ns
ns
0
0
0
0
0
12
0
ns
ns
ns
ns
ns
ns
ns
Internal
CLK_SYS
cycles
ns
Figure 14-1. RST_SYS_N Timing
T5
RST_SYS_N
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-2. CPU Interface Write Cycle Timing
T43
H_CS_N
T35
T36
T33
T34
H_R_W_N
H_AD[24:1]
T40
H_WR_BEx_N[3:0]
T31
T32
H_D[31:0](input)
T26
T37
H_READY_N
Figure 14-3. CPU Interface Read Cycle Timing
T43
H_CS_N
T35
T36
T33
T34
H_R_W_N
H_AD[24:1]
T22
H_D[31:0](output)
T26
T44
T37
H_READY_N
14.2 SPI Interface Timing
Table 14-3. SPI Interface AC Characteristics
PARAMETER
SPI_SEL_N Deasserted to SPI_SEL_N Asserted
SPI_CLK Frequency
SPI_CLK Period
SPI_CLK to SPI_MISO Output Hold
SPI_CLK to SPI_MISO Output Valid
SPI_MOSI Input Hold After SPI_CLK Edge
SPI_MOSI Input Setup Prior to SPI_CLK Edge
SPI_SEL_N Asserted to SPI_MISO Active
SPI_SEL_N Deasserted to SPI_MISO High-Z
NOTE: The output timing specified assumes 50pf load.
Rev: 032609
SYMBOL
T230
T231
T231
T232
T233
T234
T235
T236
T237
MIN
70
82.7
5.3
5
5
TYP
MAX
12.09
17.5
15
12
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-4. SPI interface Timing (SPI_CP = 0)
T230
SPI_SEL_N
T231
SPI_CLK(CI=0)
SPI_CLK(CI=1)
T236
T233
T233
T232
T232
T237
SPI_MISO(output)
T235
T234
SPI_MOSI(input)
Figure 14-5. SPI interface Timing (SPI_CP = 1)
T230
SPI_SEL_N
T231
SPI_CLK(CI=0)
SPI_CLK(CI=1)
T233
T236
T232
T233
T237
SPI_MISO(output)
T235
T234
SPI_MOSI(input)
14.3 SDRAM Interface Timing
Table 14-4. SDRAM Interface AC Characteristics
PARAMETER
SD_CLK to
SD_CS_N, SD_RAS_N, SD_CAS_N, SD_WE_N,
SD_DQM[3:0], SD_A[11:0], SD_BA[1:0] Output Hold
SD_CLK to
SD_CS_N, SD_RAS_N, SD_CAS_N, SD_WE_N,
SD_DQM[3:0], SD_A[11:0], SD_BA[1:0] Output Valid
SD_CLK to SD_D[31:0] Output Hold
SD_CLK to SD_D[31:0] Output Valid
SD_D[31:0] Input Setup Prior to SD_CLK
SD_D[31:0] Input Hold After SD_CLK
NOTE: The output timing specified assumes 30 pF load.
Rev: 032609
SYMBOL
T51
MIN
1.9
T52
T59
T60
T69
T70
2
4
1
TYP
MAX
UNITS
8
ns
8
ns
ns
ns
ns
ns
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-6. SDRAM Interface Write Cycle Timing
SD_CLK
T52
T52
T51
T51
SD_CS_N
T52
T51
T52
T52
T51
T51
T52
T51
SD_RAS_N
T52
T52
T51
T51
SD_CAS_N
T52
T52
T51
T51
SD_WE_N
T60
T60
SD_D[31:0](output)
T59
OUT
T52
T51
T59
OUT
T52
T51
SD_DQM[3:0]
T52
T51
SD_A[11:0]
T51
ROW
T52
T51
SD_BA[1:0]
Rev: 032609
ACTIVE
T52
T51
COLUMN
T52
T51
BANK
IDLE
T52
T52
T51
BANK
WRITE
WRITE
PRECHARGE
167 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-7. SDRAM Interface Read Cycle Timing
SD_CLK
T52
T52
T51
T51
SD_CS_N
T52
T51
T51
T51
T51
T52
T52
T52
SD_RAS_N
T52
T52
T51
T51
SD_CAS_N
SD_WE_N
T70
T69
IN
SD_D[31:0](input)
T52
T52
T51
T51
SD_DQM[3:0]
T52
ROW
T52
SD_BA[1:0]
BANK
IDLE
Rev: 032609
COLUMN
T52
ACTIVE
T52
T51
T51
T51
T52
T51
T51
T51
SD_A[11:0]
T52
BANK
READ
NOP
NOP
168 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
14.4 TDM-over-Packet TDM Interface Timing
Table 14-5. TDMoP TDM Interface AC Characteristics
PARAMETER
SYMBOL
TDMn_TX_SYNC, TDMn_TX_MF_CD, TDMn_RX,
TDMn_RX_SYNC, TDMn_RSIG_RTS Input Setup Prior
to TDMn_TCLK for E1/T1/Serial Interface
TDMn_TX_SYNC, TDMn_TX_MF_CD, TDMn_RX,
TDMn_RX_SYNC, TDMn_RSIG_RTS Input Hold After
TDMn_TCLK for E1/T1/Serial Interface
TDMn_TCLK to TDMn_TX, TDMn_TSIG_CTS Output
Hold for E1/T1/Serial Interface
TDMn_TCLK to TDMn_TX, TDMn_TSIG_CTS Output
Valid for E1/T1/Serial Interface
TDM1_TCLK to TDM1_TX Output Hold for High Speed
\Interface
TDM1_TCLK to TDM1_TX Output Valid for High Speed
\Interface
TDMn_RX, TDMn_RX_SYNC, TDMn_RSIG_RTS Input
Setup Prior to TDMn_RCLK for E1/T1/Serial Interface
TDMn_RX, TDMn_RX_SYNC, TDMn_RSIG_RTS Input
Hold After TDMn_RCLK for E1/T1/Serial Interface
TDM1_RX Input Setup Prior to TDM1_RCLK for High
Speed Interface
TDM1_RX Input Hold After TDM1_RCLK for High Speed
Interface
T101
MIN
1.8
TYP
MAX
UNITS
ns
T102
1.1
ns
T103
2.8
ns
T104
T103
T104
13.3
4.5
(Note 1)
ns
ns
12.5
(Note 1)
ns
T109
1.8
ns
T110
0
ns
T109
1.8
ns
T110
1.1
ns
NOTES:
1. The output timing specified for TDM1_TX assumes 20 pF load.
Table 14-6. TDMoP TDM Clock AC Characteristics
PARAMETER
SYMBOL
TDMn_TCLK Frequency for E1 Interface
TDMn_TCLK Frequency for T1 Interface
TDMn_RCLK, TDMn_TCLK Frequency for Serial
Interface
TDM1_RCLK, TDM1_TCLK Frequency for High Speed
Interface
TDMn_RCLK, TDMn_TCLK Duty Cycle for 1/T1 Serial
Interface
TDM1_RCLK, TDM1_TCLK Duty Cycle for High Speed
Interface
T100
T100
T106
MIN
16k
TYP
2.048
1.544
MAX
UNITS
4.65M
MHz
MHz
Hz
T106
16k
51.84M
Hz
T107
40
60
%
T107
40
60
%
NOTE: The output timing specified for TDM interfaces assumes 30 pF load.
Figure 14-8. TDMoP TDM Timing, One-Clock Mode (Two_clocks=0, Tx_sample=1)
T100
TDMn_TCLK
T101
T102
T101
T102
DMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
TDMn_TX_MF_CD,TDMn_TX_SYNC
T104
T103
TDMn_TX,TDMn_TSIG_CTS
Rev: 032609
169 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-9. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0)
T105
T100
TDMn_TCLK
T101
T102
T101
T102
DMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
TDMn_TX_MF_CD,TDMn_TX_SYNC
T104
T103
TDMn_TX,TDMn_TSIG_CTS
Figure 14-10. TDMoP TDM Timing, Two Clock Mode (Two_clocks=1, Tx_sample=1, Rx_sample=1)
T106
T107
TDMn_RCLK
T109
T110
DMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
T106
T107
TDMn_TCLK
T104
T103
TDMn_TX,TDMn_TSIG_CTS
T101
T102
TDMn_TX_MF_CD,TDMn_TX_SYNC
Figure 14-11. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=0)
TDMn_RCLK
T109
T110
TDMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
TDMn_TCLK
T104
T103
TDMn_TX,TDMn_TSIG_CTS
T101
T102
TDMn_TX_MF_CD,TDMn_TX_SYNC
Rev: 032609
170 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-12. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1)
T106
T107
TDMn_RCLK
T109
T110
TDMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
T106
TDMn_TCLK
T104
T103
TDMn_TX,TDMn_TSIG_CTS
T101
T102
TDMn_TX_MF_CD,TDMn_TX_SYNC
Figure 14-13. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=1, Rx_sample=0)
T107
T106
TDMn_RCLK
T109
T110
TDMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC
T106
T107
TDMn_TCLK
T104
T103
TDMn_TX,TDMn_TSIG_CTS
T102
T101
TDMn_TX_MF_CD,TDMn_TX_SYNC
Rev: 032609
171 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
14.5 Ethernet MII/RMII/SSMII Interface Timing
Table 14-7. MII Management Interface AC Characteristics
PARAMETER
SYMBOL
MDC Period (Note 1)
MDC to MDIO Output Hold (Note 1)
MDC to MDIO Output Valid (Note 1)
MDIO Input Setup Prior to MDC Rising
MDIO Input Hold After MDC Rising
T150
T151
T152
T153
T154
NOTES:
1. Valid for 50 MHz CLK_SYS and MDC_frequency = 0x02.
MIN
10
TYP
320
20
0
MAX
UNITS
180
ns
ns
ns
ns
ns
MAX
UNITS
25
ns
Figure 14-14. MII Management Interface Timing
T150
MDC
T152
T151
MDIO(output)
T153
T154
MDIO(input)
Table 14-8. MII Interface AC Characteristics
PARAMETER
CLK_MII_TX Rising to MII_TXD, MII_TX_ERR,
MII_TX_EN Output Hold
CLK_MII_TX Rising to MII_TXD, MII_TX_ERR,
MII_TX_EN Output Valid
MII_RXD, MII_RX_DV, MII_RX_ERR Input Setup Prior
to CLK_MII_RX Rising
MII_RXD, MII_RX_DV, MII_RX_ERR Input Hold After to
CLK_MII_RX Rising
Table 14-9. MII Clock Timing
PARAMETER
CLK_MII_TX Frequency
CLK_MII_RX Frequency
CLK_MII_TX Duty Cycle
CLK_MII_RX duty Cycle
SYMBOL
T156
MIN
0
TYP
T157
ns
T159
10
ns
T160
0
ns
SYMBOL
MIN
T158
T158
T180
T180
40
40
TYP
25
25
MAX
60
60
UNITS
MHz
MHz
%
%
Figure 14-15. MII Interface Output Signal Timing
T158
T180
CLK_MII_TX
T157
T156
MII_TXD,MII_TX_EN,MII_TX_ERR
Rev: 032609
172 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-16. MII Interface Input Signal Timing
T158
T180
CLK_MII_RX
T159
T160
MII_RXD,MII_RX_DV,MII_RX_ERR
Table 14-10. RMII Interface AC Characteristics
PARAMETER
CLK_MII_TX Rising to MII_TXD[3:2], MII_TX_EN Output
Hold
CLK_MII_TX Rising to MII_TXD[3:2], MII_TX_EN Output
Valid
MII_RXD[3:2], MII_RX_DV, MII_RX_ERR Input Setup
Prior to CLK_MII_TX Rising
MII_RXD(3:2], MII_RX_DV, MII_RX_ERR Input Hold
After CLK_MII_TX Rising
Table 14-11. RMII Clock Timing
PARAMETER
CLK_MII_TX Frequency
CLK_MII_TX Duty Cycle
SYMBOL
T162
MIN
2
TYP
T163
MAX
UNITS
13.5
ns
ns
T164
7
ns
T165
0
ns
SYMBOL
MIN
T161
T183
40
TYP
50
MAX
60
UNITS
MHz
%
Figure 14-17. RMII Interface Output Signal Timing
T161
CLK_MII_TX(RMII_REF_CLK)
T163
T162
MII_TXD(3:2),MII_TX_EN
Figure 14-18. RMII Interface Input Signal Timing
T183
CLK_MII_TX(RMII_REF_CLK)
T164
T165
II_RXD(3:2),MII_RX_DV,MII_RX_ERR
Table 14-12. SSMII Interface AC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Table 14-13. SSMII Clock Timing
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CLK_SSMII_TX Rising to MII_TXD[1:0] Output
MII_RXD[1:0] Input Setup Prior to CLK_MII_RX Rising
MII_RXD[1:0] Input Hold After CLK_MII_RX Rising
CLK_SSMII_TX Frequency
CLK_SSMII_TX Duty Cycle
CLK_MII_RX Frequency
CLK_MII_RX Duty Cycle
Rev: 032609
T172
T175
T176
T171
T189
T171
T189
1.5
1.5
1.3
40
40
125
125
5
60
60
ns
ns
ns
MHz
%
MHz
%
173 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 14-19. SSMII Interface Output Signal Timing
T171
T189
CLK_SSMII_TX
T172
MII_TXD_0(SSMII_TXD)
T172
MII_TXD_1(SSMII_TX_SYNC)
Figure 14-20. SSMII Interface Input Signal Timing
T171
T189
CLK_MII_RX(CLK_SSMII_RX)
T175
T176
T175
T176
MII_RXD_0(SSMII_RXD)
MII_RXD_1(SSMII_RX_SYNC)
NOTES FOR SECTION 14.5:
1. The output timing specified for MII/RMII/SSMII interfaces assumes 20pf load for MII_TXD[3:0], MII_TX_EN, and MII_TX_ERR.
2. The output timing specified for MII/RMII/SSMII interfaces assumes 30pf load for MDC and MDIO.
3. The output timing specified for SSMII interface assumes 25pf load for CLK_SSMII_TX.
14.6 CLAD and System Clock Timing
Table 14-14. CLAD1 and CLAD2 Input Clock Specifications
PARAMETER
MIN
TYP
CLK_SYS Frequency
25 or 50
CLK_SYS Duty Cycle
40
CLK_HIGH Frequency
10.00
19.44
38.88
77.76
CLK_HIGH Duty Cycle
40
MCLK Frequency
1.544
2.048
MCLK Duty Cycle
40
CLK_SYS Frequency
25
50
75
CLK_SYS Duty Cycle
40
Rev: 032609
MAX
60
UNITS
MHz
%
MHz
60
%
MHz
60
%
MHz
60
%
ACCURACY
±50ppm
Traceable to
Stratum 3E or higher
±32ppm
±50ppm
±50ppm
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
14.7 JTAG Interface Timing
Table 14-15. JTAG Interface Timing
PARAMETER
JTCLK Clock Period
JTCLK Clock High / Low Time
JTCLK to JTDI, JTMS Setup Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
JTCLK to JTDO Hi-Z Delay
JTRST_N Width Low Time
NOTES:
1. Clock can be stopped high or low.
2. Not tested during production test.
SYMBOL
t1
t2 / t3
t4
t5
t6
t7
t8
MIN
TYP
1000
500
100
5
2
2
2
100
MAX
50
50
UNITS
ns
ns
ns
ns
ns
ns
NOTES
1
2
Figure 14-21. JTAG Interface Timing Diagram
t1
t2
t3
JTCLK
t4
t5
t4
t5
JTDI
JTMS
t7
t6
JTDO
t8
JTRST_N
Rev: 032609
175 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
15. Applications
15.1 Connecting a Serial Interface Transceiver
Figure 15-1 below shows the connection of one port of a DS34S10x chip to a serial interface transceiver such as
V.35 or RS-530. The figure shows one port in a DCE (Data Communications Equipment) application. All other ports
can be connected in the same way.
Each direction (Tx and Rx) has its own clock. However, TDM1_RCLK is optional, as the DS34S10x chip may work
in one clock mode (GCR1.CLKMODE=0) in which both directions are clocked by TDM1_TCLK. The clock source of
TDM1_RCLK or TDM1_TCLK can be:
•
•
•
Internal (from the local oscillator)
External
Recovered from the packet network (provided by the chip on TDM1_ACLK).
The control input signal TDMn_RSIG_RTS does not affect the data reception, but its value can be read by the CPU
from register field Port[n]_stat_reg1.RTS.
The TDMn_TSIG_CTS and TDMn_TX_MF_CD outputs can be controlled by software using registers fields CTS
and CD in the Port[n]_cfg_reg register.
Figure 15-1. Connecting Port 1 to a Serial Transceiver
SERIAL
INTERTFACE
TRANSCEIVER
(DCE MODE)
TX
TDM
RX
TDM 1 _ RX
TCLK
TDM 1 _ TCLK
RCLK
TDM 1 _ RCLK
DS34S10x
CTS
TDM 1 _ TSIG _ CTS
RTS
TDM 1 _ RSIG _ RTS
CD
TDM 1 _ TX _ MF _ CD
TDM 1 _ ACLK
EXTERNAL
CLOCK
Rev: 032609
INTERNAL
CLOCK
176 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
15.2 Connecting an Ethernet PHY or MAC
The figures below show the connection of the Ethernet port to a PHY or MAC device, in MII, RMII, and SSMII
modes.
Figure 15-2. Connecting the Ethernet Port to a PHY in MII Mode
DS34S10x
MII_TXD[3:0]
TXD [3:0]
MII _RXD[3:0]
RXD [3:0]
MII_TX_EN
TX_EN
MII _RX_DV
RX _DV
MII_TX _ERR
TX _ERR
MII _RX _ERR
RX _ERR
MII_COL
COL
MII _CRS
CRS
CLK_MII _TX
CLK _TX
CLK _MII _RX
CLK _RX
PHY
Figure 15-3. Connecting the Ethernet Port to a MAC in MII Mode
MII _ TXD [3 : 0 ]
TXD [3:0 ]
MII _ RXD [3 : 0 ]
RXD [ 3 :0 ]
DS34S10x
MII _ TX _ EN
TX _ EN
MII _ RX _ DV
RX _ DV
MII _ TX _ ERR
x
x
MAC
TX _ ERR
MII _ RX _ ERR
RX _ ERR
MII _ COL
COL
MII _ CRS
CRS
CLK _ MII _ TX
CLK _ TX
CLK _ MII _ RX
CLK _ RX
25 MHz
OSC .
Figure 15-4. Connecting the Ethernet Port to a PHY in RMII Mode
DS34S10x
Rev: 032609
MII _TXD[3:2]
TXD [1:0]
MII _RXD[3:2]
RXD [1:0]
MII _TX_EN
TX _EN
MII _RX_DV
RX _DV
MII _RX_ERR
RX _ERR
CLK_MII_TX
CLK
PHY
177 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode
MII _TXD[3:2]
TXD [1:0]
MII _RXD[3:2]
RXD [1:0]
MII _TX_EN
TX_EN
MII _RX_DV
RX_DV
DS34S10x
MII _RX _ERR
RX_ERR
CLK_MII _TX
CLK
MAC
50 MHz
OSC.
Figure 15-6. Connecting the Ethernet Port to a PHY in SSMII Mode
MII _TXD[0]
TXD
MII _TXD[1]
TXSYNC
MII _RXD[0]
RXD
MII _RXD[1]
RXSYNC
PHY
DS34S10x
CLK _SSMII_TX
CLK _TX
CLK _MII _RX
CLK _RX
CLK_MII _TX
CLK _REF
125 MHz
OSC.
Figure 15-7. Connecting the Ethernet Port to a MAC in SSMII Mode
MII _TXD[0]
TXD
MII _TXD[1]
TXSYNC
MII _RXD[0]
RXD
MII _RXD[1]
RXSYNC
DS34S10x
MAC
CLK _SSMII_TX
CLK _TX
CLK _MII _RX
CLK _RX
CLK_MII _TX
CLK _REF
125 MHz
OSC.
Rev: 032609
178 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
For the applications above, apply the following layout considerations:
•
•
•
•
•
Provide termination on all high-speed interface signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Keep the clock traces away from all other signals to minimize mutual interference.
In RMII mode, a very low skew clock buffer/driver is recommended to maximize the timing budget. In this
mode it is recommended to keep all traces as short as possible.
In SSMII mode there are two clock signals, one for each direction (Rx and Tx), routed together with the
sync and data signals. Since the delay between the clock and these signals is lower, the designer can
apply a longer trace delay in this mode. Keep data/sync traces and clock traces at the same length to
maximize the timing budget.
15.3 Implementing Clock Recovery in High Speed Applications
For the high-speed interface (up to 51.84 MHz), an external clock multiplier and jitter attenuator are needed. Clock
recovery in high-speed applications is depicted below:
Figure 15-8. External Clock Multiplier for High Speed Applications
LIU
with Jitter Attenuator
Tx CLK
DS34S10x
Clock Multiplier
Out
In
ACLK
The clock multiplier converts the low speed clock at ACLK to a clock at the frequency of the emulated high-speed
circuit. The multiplication factor in the external clock multiplier must be 12 for an E3 or T3 interface and 10 for an
STS-1 interface. The clock multiplier should be tuned to add minimal jitter. The jitter attenuator can be part of the
LIU or an independent component.
15.4 Connecting a Motorola MPC860 Processor
The device is easily connected to a Motorola MPC860 processor by means of the MPC860 GPCM (General
Purpose Chip Select Machine) module.
15.4.1 Connecting the Bus Signals
Since the MPC860 address bus MSb is always 0 while the DS34S10x address bus LSb is always 0, the signal
order can be reversed as shown in the following figures.
Rev: 032609
179 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 15-9. 32-Bit CPU Bus Connections
A[0:6]
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
LSB
A31
H_AD 24
H_AD 23
H _AD 22
H_AD 21
H _AD 20
H _AD 19
H_AD 18
H _AD 17
H _AD 16
H_AD 15
H _AD 14
H_AD 13
H_AD 12
H_AD 11
H_AD 10
H_AD 9
H _AD8
H _AD 7
H _AD6
H _AD 5
H _AD4
H _AD3
H _AD 2
H _AD 1
MSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D 10
D 11
D 12
D13
D14
D 15
D16
D17
D18
D 19
D 20
D 21
D 22
D 23
D 24
D 25
D 26
D 27
D 28
D 29
D 30
D31
H _D31
H _D 30
H _D 29
H _D28
H _D27
H_D 26
H_D 25
H_D 24
H _D 23
H_D 22
H_D 21
H_D 20
H_D 19
H_D 18
H_D 17
H_D 16
H_D 15
H _D 14
H_D 13
H _D 12
H _D 11
H _D 10
H_D 9
H_D 8
H_D 7
H_D 6
H _D 5
H_D 4
H_D 3
H _D2
H _D 1
H _D 0
MSB
BE0
BE1
BE2
BE3
H _WR_BE3_N
H _WR_BE 2_N
H _WR_BE1_N
H _WR_BE0_N
MSB
MSB
MPC860
LSB
Rev: 032609
GND
LSB
DS34T10x
LSB
180 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 15-10. 16-Bit CPU Bus Connections
MSB
LSB
A[6:0]
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
H _AD 24
H _AD 23
H _AD 22
H _AD 21
H _AD 20
H_AD 19
H_AD 18
H_AD 17
H _AD 16
H _AD 15
H _AD 14
H _AD 13
H _AD 12
H _AD 11
H_AD 10
H_AD 9
H_AD 8
H_AD 7
H_AD 6
H_AD 5
H _AD 4
H _AD 3
H _AD 2
H _AD 1
MSB
LSB
VCC
H _D31
H _D30
H _D29
H _D28
H _D27
H _D26 DS 34T 10x
H _D25
H _D24
H _D23
H _D22
H _D21
H _D20
H _D19
H _D18
H _D17
H _D16
H_D 15 MSB
H_D 14
H _D13
H _D12
H _D11
H _D 10
H_D 9
H_D 8
H_D 7
H _D 6
H _D 5
H _D 4
H _D 3
H _D 2
H _D 1
H_D 0 LSB
MC860
MSB
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VCC
BE 0
BE1
Rev: 032609
VCC
H _WR_BE3_N
H _WR_BE2_N
H _WR_BE1_N
H _WR_BE0_N
181 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
15.4.2 Connecting the H_READY_N Signal
The H_READY_N output should be connected to the MPC860 TA input. The CPU bus operates asynchronously.
The TA of the MPC860 is a synchronous input (i.e., needs to meet set-up and hold times). The designer should
synchronize H_READY_N to the MPC860 clock by means of a CPLD, which uses the MPC860 reference clock.
The internal logic in the CPLD also uses the MPC860 CS (chip select) output. Both the H_READY_N output and
the MPC860 TA input should have a 1kΩ pull-up resistor.
Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin
VCC
MPC860
TA
CLKOUT
CS
R/W
VCC
1K
1K
CPLD
DS34S108
H_READY_N
H_CS_N
H_R_W_N
Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock
Another alternative for connecting the H_READY_N signal is using the MPC860 UPM. In this option the
H_READY_N output should be connected to the MPC860 UPWAIT (GPL4) signal, and no external timing
adjustment is needed. The H_READY_N output should have a 1kΩ pull-up resistor. Refer to the MPC860 user
manual for additional details.
Rev: 032609
182 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
15.5 Working in SPI Mode
The following table shows the I/O connections for operating in SPI mode.
Table 15-1. SPI Mode I/O Connections
Signal name
Connect to
H_CPU_SPI_N
DAT_32_16_N
H_CS_N
H_AD[24:1]
H_D[31:1]
H_D[0] / SPI_MISO
H_WR_BE0_N / SPI_CLK
H_WR_BE1_N / SPI_MOSI
H_WR_BE2_N / SPI_SEL_N
H_WR_BE3_N / SPI_CI
H_R_W_N / SPI_CP
VSS (logic 0)
DVDDIO or DVSS
DVDDIO or DVSS
DVDDIO or DVSS
DVDDIO or DVSS
Master MISO
Master SPI clock
Master MOSI
Master SPI select
DVDDIO (logic 1) or DVSS (logic 0)
DVDDIO (logic 1) or DVSS (logic 0)
Comments
Selects SPI mode.
Ignored in SPI mode.
Ignored in SPI mode.
Ignored in SPI mode.
Ignored in SPI mode.
According to required SPI mode
According to required SPI mode
15.6 Connecting SDRAM Devices
The following table lists suggested SDRAM devices to use in conjunction with the DS34S10x devices.
Table 15-2. List of Suggested SDRAM Devices
Vendor
64 Mb Device
128 Mb Device
Micron
Samsung
Hynix
Elpida
Winbond
ICSI
ISSI
MT48LC2M32B2TG-6
K4S643232H-TC/L60
HY57V653220BTC-6 or
HY57V643220CT-6
N/A
W986432DH-6
IC42S32200/L-6T or
IC42S32200/L-6TI
IS42S32200C1-6T
MT48LC4M32B2TG-6
K4S283232E-TC/L60
HY57V283220T-6
EDS1232AATA-60
N/A
N/A
IS42S32400B-6T
When connecting the device to an external SDRAM, it is advised to connect SD_CLK through a serial termination
resistor.
When connecting the device to a 64 Mb external SDRAM, it is advised to connect SD_A[11] through a serial
resistor to the SDRAM “NC” pin that is used for address pin A11 for a 128 Mb SDRAM. In this way, the 64Mb
SDRAM could be replaced by a 128 Mb SDRAM later, if needed.
Rev: 032609
183 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
16. PIN ASSIGNMENTS
16.1 Board Design for Multiple DS34S101/2/4 Devices
The DS34S101, DS34S102 and DS34S104 require the same footprint on the board. It is recommended that
boards be design to support the use of higher port-count devices in a lower port-count socket. If this is done,
unused inputs, input/outputs, and outputs must be biased appropriately. Generally, unused inputs are tied directly
to the ground plane, unused outputs are not connected, and unused input/outputs are tied to ground through a
10kΩ resistor. Unused inputs with internal pull-ups or pull-downs are not connected. Table 16-1 designates how
each ball on the package should be connected to implement a common board design. Shading indicates balls for
the unused inputs, input/outputs, and outputs of higher port-count devices.
If a common board design is not done, the balls for the unused inputs, input/outputs, and outputs need not be
connected, and the stuffing of higher port-count devices into a lower port-count socket is not recommended.
Note: When a higher port-count device is used in a socket, the BSDL file of the higher port-count device must be
used. BSDL files are available from the factory upon request.
Table 16-1. Common Board Design Connections for DS34S101/2/4 (Sorted by Signal Name)
Ball
DS34S104 Socket
DS34S102 Socket
DS34S101 Socket
R8
T8
P8
T9
M14
P9
A16
D15
E15
T12
R9
M4
F10
F11
F6
ACVDD1
ACVDD2
ACVSS1
ACVSS2
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS
CLK_SYS_S
DAT_32_16_N
DVDDC
DVDDC
DVDDC
ACVDD1
ACVDD2
ACVSS1
ACVSS2
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
DVDDC
DVDDC
ACVDD1
ACVDD2
ACVSS1
ACVSS2
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
DVDDC
DVDDC
F7
F8
F9
M10
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
M11
M6
M7
M8
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
M9
G12
H12
J12
DVDDC
DVDDIO
DVDDIO
DVDDIO
DVDDC
DVDDIO
DVDDIO
DVDDIO
DVDDC
DVDDIO
DVDDIO
DVDDIO
J5
K12
K5
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
Rev: 032609
184 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Ball
DS34S104 Socket
DS34S102 Socket
DS34S101 Socket
L12
L5
M5
N10
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
N7
N8
N9
G10
DVDDIO
DVDDIO
DVDDIO
DVSS
DVDDIO
DVDDIO
DVDDIO
DVSS
DVDDIO
DVDDIO
DVDDIO
DVSS
G11
G6
G7
G8
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
G9
H10
H11
H5
H6
H7
H8
H9
J10
J11
J6
J7
J8
J9
K10
K11
K6
K7
K8
K9
L10
L11
L6
L7
L8
L9
R13
C10
E12
A12
T15
C12
D12
T16
B13
R14
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
H_AD[17]
H_AD[18]
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
H_AD[17]
H_AD[18]
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
H_AD[17]
H_AD[18]
Rev: 032609
185 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Ball
DS34S104 Socket
DS34S102 Socket
DS34S101 Socket
B10
D13
P14
A10
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
B11
N14
A11
P13
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
D10
E13
D11
N13
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
A13
T14
L4
E11
K13
M12
M13
P16
K14
M15
J14
M16
L14
L16
J15
K16
R15
N16
B12
J16
F12
F13
G13
H13
F14
G14
H14
L13
H16
H15
K15
P15
J13
N15
L15
R16
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[30]
H_D[31]
H_D[4]
H_D[5]
H_D[6]
H_D[7]
H_D[8]
H_D[9]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[30]
H_D[31]
H_D[4]
H_D[5]
H_D[6]
H_D[7]
H_D[8]
H_D[9]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[30]
H_D[31]
H_D[4]
H_D[5]
H_D[6]
H_D[7]
H_D[8]
H_D[9]
Rev: 032609
186 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Ball
DS34S104 Socket
DS34S102 Socket
DS34S101 Socket
T13
N12
R12
C13
H_INT[0]
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_INT[0]
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_INT[0]
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
P12
E10
C11
N11
H_WR_BE1_N/SPI_MOSI
H_WR_BE2_N/SPI_SEL_N
H_WR_BE3_N/SPI_CI
HIZ_N
H_WR_BE1_N/SPI_MOSI
H_WR_BE2_N/SPI_SEL_N
H_WR_BE3_N/SPI_CI
HIZ_N
H_WR_BE1_N/SPI_MOSI
H_WR_BE2_N/SPI_SEL_N
H_WR_BE3_N/SPI_CI
HIZ_N
R10
P10
P11
T10
JTCLK
JTDI
JTDO
JTMS
JTCLK
JTDI
JTDO
JTMS
JTCLK
JTDI
JTDO
JTMS
T11
N5
N6
R4
G16
G15
B15
C15
F16
A15
B16
C16
D16
E16
D14
E14
F15
A14
B14
C14
R11
J4
D2
C3
A4
F2
E1
A3
E2
B3
E3
C4
B4
D3
D1
A2
JTRST_N
MBIST_DONE
MBIST_EN
MBIST_FAIL
MDC
MDIO
MII_COL
MII_CRS
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
RST_SYS_N
SCEN
SD_A[0]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
JTRST_N
MBIST_DONE
MBIST_EN
MBIST_FAIL
MDC
MDIO
MII_COL
MII_CRS
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
RST_SYS_N
SCEN
SD_A[0]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
JTRST_N
MBIST_DONE
MBIST_EN
MBIST_FAIL
MDC
MDIO
MII_COL
MII_CRS
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
RST_SYS_N
SCEN
SD_A[0]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
Rev: 032609
187 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Ball
DS34S104 Socket
DS34S102 Socket
DS34S101 Socket
C1
B2
C2
E4
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
B5
B6
F3
A6
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
F4
B8
D7
F5
SD_D[13]
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[13]
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[13]
SD_D[14]
SD_D[15]
SD_D[16]
C7
A7
D8
F1
G2
E8
G3
A8
B9
G4
E9
G5
A9
D9
C6
C9
C8
G1
B7
D5
D6
E7
E5
C5
D4
E6
A5
A1
B1
H4
R5
T7
P7
T5
P5
T6
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_RX_SYNC
TDM1_TCLK
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_RX_SYNC
TDM1_TCLK
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_RX_SYNC
TDM1_TCLK
Rev: 032609
188 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Ball
DS34S104 Socket
DS34S102 Socket
DS34S101 Socket
P6
T4
R7
R6
TDM1_TSIG_CTS
TDM1_TX
TDM1_TX_MF_CD
TDM1_TX_SYNC
TDM1_TSIG_CTS
TDM1_TX
TDM1_TX_MF_CD
TDM1_TX_SYNC
TDM1_TSIG_CTS
TDM1_TX
TDM1_TX_MF_CD
TDM1_TX_SYNC
R1
P4
T3
P2
TDM2_ACLK
TDM2_RCLK
TDM2_RSIG_RTS
TDM2_RX
TDM2_ACLK
TDM2_RCLK
TDM2_RSIG_RTS
TDM2_RX
NC
NC
NC
NC
T1
P3
T2
P1
TDM2_RX_SYNC
TDM2_TCLK
TDM2_TSIG_CTS
TDM2_TX
TDM2_RX_SYNC
TDM2_TCLK
TDM2_TSIG_CTS
TDM2_TX
NC
NC
NC
NC
R3
R2
M2
M1
N4
L2
N2
L3
N3
L1
N1
M3
J2
J1
K4
H2
K2
H3
K3
H1
K1
J3
TDM2_TX_MF_CD
TDM2_TX_SYNC
TDM3_ACLK
TDM3_RCLK
TDM3_RSIG_RTS
TDM3_RX
TDM3_RX_SYNC
TDM3_TCLK
TDM3_TSIG_CTS
TDM3_TX
TDM3_TX_MF_CD
TDM3_TX_SYNC
TDM4_ACLK
TDM4_RCLK
TDM4_RSIG_RTS
TDM4_RX
TDM4_RX_SYNC
TDM4_TCLK
TDM4_TSIG_CTS
TDM4_TX
TDM4_TX_MF_CD
TDM4_TX_SYNC
TDM2_TX_MF_CD
TDM2_TX_SYNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Rev: 032609
189 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
16.2 DS34S101 Pin Assignment
Figure 16-1. DS34S101 Pin Assignment (TE-CSBGA Package)
1
2
3
4
5
SD_RAS_N
SD_BA[1]
SD_A[3]
SD_A[10]
SD_DQM[3]
A
SD_WE_N
SD_CLK
SD_A[5]
SD_A[8]
SD_D[1]
B
SD_CAS_N
SD_CS_N
SD_A[1]
SD_A[7]
SD_DQM[0]
C
SD_BA[0]
SD_A[0]
SD_A[9]
SD_DQM[1]
SD_D[6]
D
SD_A[2]
SD_A[4]
SD_A[6]
SD_D[0]
SD_D[9]
E
SD_D[2]
SD_A[11]
SD_D[11]
SD_D[13]
SD_D[16]
F
SD_D[4]
SD_D[20]
SD_D[22]
SD_D[25]
SD_D[27]
G
NC
NC
NC
STMD
DVSS
H
NC
NC
NC
SCAN_EN
DVDDIO
J
NC
NC
NC
NC
DVDDIO
K
NC
NC
NC
H_CPU_SPI_N
DVDDIO
L
NC
NC
NC
DAT_32_16_N
DVDDIO
M
NC
NC
NC
NC
MBIST_DONE
N
NC
NC
NC
NC
TDM1_RX_SYNC
P
NC
NC
NC
MBIST_FAIL
TDM1_ACLK
R
NC
NC
NC
TDM1_TX
TDM1_RX
T
1
2
3
4
5
6
7
8
SD_D[12]
SD_D[18]
SD_D[23]
SD_D[10]
SD_D[5]
SD_D[14]
SD_D[3]
SD_D[17]
SD_D[31]
SD_D[7]
SD_D[15]
SD_D[19]
SD_DQM[2]
SD_D[8]
SD_D[21]
DVDDC
DVDDC
DVDDC
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVDDC
DVDDC
DVDDC
MBIST_EN
DVDDIO
DVDDIO
TDM1_TSIG_CTS
TDM1_RSIG_RTS
ACVSS1
TDM1_TX_SYNC
TDM1_TX_MF_CD
ACVDD1
TDM1_TCLK
TDM1_RCLK
ACVDD2
6
7
8
9
10
11
12
13
14
15
16
SD_D[28]
H_AD[21]
H_AD[24]
H_AD[12]
H_AD[8]
MII_TXD[1]
MII_RX_ERR
CLK_MII_RX
SD_D[24]
H_AD[19]
H_AD[22]
H_D[21]
H_AD[17]
MII_TXD[2]
MII_COL
MII_RXD[0]
SD_D[30]
H_AD[10]
H_WR_BE3_N/
SPI_CI
H_AD[14]
H_WR_BE0_N/
SPI_CLK
MII_TXD[3]
MII_CRS
MII_RXD[1]
SD_D[29]
H_AD[4]
H_AD[6]
H_AD[15]
H_AD[2]
MII_TX_EN
CLK_MII_TX
MII_RXD[2]
SD_D[26]
H_WR_BE2_N/
SPI_SEL_N
H_CS_N
H_AD[11]
H_AD[5]
MII_TX_ERR
CLK_SSMII_TX
MII_RXD[3]
DVDDC
DVDDC
DVDDC
H_D[23]
H_D[24]
H_D[27]
MII_TXD[0]
MII_RX_DV
DVSS
DVSS
DVSS
DVDDIO
H_D[25]
H_D[28]
MDIO
MDC
DVSS
DVSS
DVSS
DVDDIO
H_D[26]
H_D[29]
H_D[31]
H_D[30]
DVSS
DVSS
DVSS
DVDDIO
H_D[6]
H_D[14]
H_D[18]
H_D[22]
DVSS
DVSS
DVSS
DVDDIO
H_D[0]/SPI_MISO
H_D[12]
H_D[4]
H_D[19]
DVSS
DVSS
DVSS
DVDDIO
H_D[3]
H_D[16]
H_D[8]
H_D[17]
DVDDC
DVDDC
DVDDC
H_D[1]
H_D[10]
CLK_CMN
H_D[13]
H_D[15]
DVDDIO
DVDDIO
HiZ_N
H_R_W_N/SPI_CP
H_AD[7]
H_AD[23]
H_D[7]
H_D[20]
CLK_HIGH
JTDI
JTDO
H_WR_BE1_N/
SPI_MOSI
H_AD[3]
H_AD[20]
H_D[5]
H_D[11]
CLK_SYS_S
JTCLK
RST_SYS_N
H_READY_N
H_AD[1]
H_AD[18]
H_D[2]
H_D[9]
ACVSS2
JTMS
JTRST_N
CLK_SYS/SCCLK
H_INT[0]
H_AD[9]
H_AD[13]
H_AD[16]
9
10
11
12
13
14
15
16
Rev: 032609
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
190 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
16.3 DS34S102 Pin Assignment
Figure 16-2. DS34S102 Pin Assignment (TE-CSBGA Package)
1
2
3
4
5
SD_RAS_N
SD_BA[1]
SD_A[3]
SD_A[10]
SD_DQM[3]
A
SD_WE_N
SD_CLK
SD_A[5]
SD_A[8]
SD_D[1]
B
SD_CAS_N
SD_CS_N
SD_A[1]
SD_A[7]
SD_DQM[0]
C
SD_BA[0]
SD_A[0]
SD_A[9]
SD_DQM[1]
SD_D[6]
D
SD_A[2]
SD_A[4]
SD_A[6]
SD_D[0]
SD_D[9]
E
SD_D[2]
SD_A[11]
SD_D[11]
SD_D[13]
SD_D[16]
F
SD_D[4]
SD_D[20]
SD_D[22]
SD_D[25]
SD_D[27]
G
NC
NC
NC
STMD
DVSS
H
NC
NC
NC
SCAN_EN
DVDDIO
J
NC
NC
NC
NC
DVDDIO
K
NC
NC
NC
H_CPU_SPI_N
DVDDIO
L
NC
NC
NC
DAT_32_16_N
DVDDIO
M
NC
NC
NC
NC
MBIST_DONE
N
TDM2_TX
TDM2_RX
TDM2_TCLK
TDM2_RCLK
TDM1_RX_SYNC
P
TDM2_ACLK
TDM2_TX_SYNC TDM2_TX_MF_CD
MBIST_FAIL
TDM1_ACLK
R
TDM2_RX_SYNC
TDM2_TSIG_CTS
TDM2_RSIG_RTS
TDM1_TX
TDM1_RX
T
1
2
3
4
5
6
7
8
SD_D[12]
SD_D[18]
SD_D[23]
SD_D[10]
SD_D[5]
SD_D[14]
SD_D[3]
SD_D[17]
SD_D[31]
SD_D[7]
SD_D[15]
SD_D[19]
SD_DQM[2]
SD_D[8]
SD_D[21]
DVDDC
DVDDC
DVDDC
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVDDC
DVDDC
DVDDC
MBIST_EN
DVDDIO
DVDDIO
TDM1_TSIG_CTS
TDM1_RSIG_RTS
ACVSS1
TDM1_TX_SYNC
TDM1_TX_MF_CD
ACVDD1
TDM1_TCLK
TDM1_RCLK
ACVDD2
6
7
8
9
10
11
12
13
14
15
16
SD_D[28]
H_AD[21]
H_AD[24]
H_AD[12]
H_AD[8]
MII_TXD[1]
MII_RX_ERR
CLK_MII_RX
SD_D[24]
H_AD[19]
H_AD[22]
H_D[21]
H_AD[17]
MII_TXD[2]
MII_COL
MII_RXD[0]
SD_D[30]
H_AD[10]
H_WR_BE3_N/
SPI_CI
H_AD[14]
H_WR_BE0_N/
SPI_CLK
MII_TXD[3]
MII_CRS
MII_RXD[1]
SD_D[29]
H_AD[4]
H_AD[6]
H_AD[15]
H_AD[2]
MII_TX_EN
CLK_MII_TX
MII_RXD[2]
SD_D[26]
H_WR_BE2_N/
SPI_SEL_N
H_CS_N
H_AD[11]
H_AD[5]
MII_TX_ERR
CLK_SSMII_TX
MII_RXD[3]
DVDDC
DVDDC
DVDDC
H_D[23]
H_D[24]
H_D[27]
MII_TXD[0]
MII_RX_DV
DVSS
DVSS
DVSS
DVDDIO
H_D[25]
H_D[28]
MDIO
MDC
DVSS
DVSS
DVSS
DVDDIO
H_D[26]
H_D[29]
H_D[31]
H_D[30]
DVSS
DVSS
DVSS
DVDDIO
H_D[6]
H_D[14]
H_D[18]
H_D[22]
DVSS
DVSS
DVSS
DVDDIO
H_D[0]/SPI_MISO
H_D[12]
H_D[4]
H_D[19]
DVSS
DVSS
DVSS
DVDDIO
H_D[3]
H_D[16]
H_D[8]
H_D[17]
DVDDC
DVDDC
DVDDC
H_D[1]
H_D[10]
CLK_CMN
H_D[13]
H_D[15]
DVDDIO
DVDDIO
HiZ_N
H_R_W_N/SPI_CP
H_AD[7]
H_AD[23]
H_D[7]
H_D[20]
CLK_HIGH
JTDI
JTDO
H_WR_BE1_N/
SPI_MOSI
H_AD[3]
H_AD[20]
H_D[5]
H_D[11]
CLK_SYS_S
JTCLK
RST_SYS_N
H_READY_N
H_AD[1]
H_AD[18]
H_D[2]
H_D[9]
ACVSS2
JTMS
JTRST_N
CLK_SYS/SCCLK
H_INT[0]
H_AD[9]
H_AD[13]
H_AD[16]
9
10
11
12
13
14
15
16
Rev: 032609
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
191 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
16.4 DS34S104 Pin Assignment
Figure 16-3. DS34S104 Pin Assignment (TE-CSBGA Package)
1
2
3
4
5
SD_RAS_N
SD_BA[1]
SD_A[3]
SD_A[10]
SD_DQM[3]
A
SD_WE_N
SD_CLK
SD_A[5]
SD_A[8]
SD_D[1]
B
SD_CAS_N
SD_CS_N
SD_A[1]
SD_A[7]
SD_DQM[0]
C
SD_BA[0]
SD_A[0]
SD_A[9]
SD_DQM[1]
SD_D[6]
D
SD_A[2]
SD_A[4]
SD_A[6]
SD_D[0]
SD_D[9]
E
SD_D[2]
SD_A[11]
SD_D[11]
SD_D[13]
SD_D[16]
F
SD_D[4]
SD_D[20]
SD_D[22]
SD_D[25]
SD_D[27]
G
TDM4_TX
TDM4_RX
TDM4_TCLK
STMD
DVSS
H
TDM4_RCLK
TDM4_ACLK
TDM4_TX_SYNC
SCAN_EN
DVDDIO
J
DVDDIO
K TDM4_TX_MF_CD TDM4_RX_SYNC TDM4_TSIG_CTS TDM4_RSIG_RTS
TDM3_TX
TDM3_RX
TDM3_TCLK
H_CPU_SPI_N
DVDDIO
L
TDM3_RCLK
TDM3_ACLK
TDM3_TX_SYNC
DAT_32_16_N
DVDDIO
M
TDM3_TX_MF_CD
TDM3_RX_SYNC
TDM3_TSIG_CTS
TDM3_RSIG_RTS
MBIST_DONE
N
TDM2_TX
TDM2_RX
TDM2_TCLK
TDM2_RCLK
TDM1_RX_SYNC
P
TDM2_ACLK
TDM2_TX_SYNC TDM2_TX_MF_CD
MBIST_FAIL
TDM1_ACLK
R
TDM2_RX_SYNC
TDM2_TSIG_CTS
TDM2_RSIG_RTS
TDM1_TX
TDM1_RX
T
1
2
3
4
5
6
7
8
SD_D[12]
SD_D[18]
SD_D[23]
SD_D[10]
SD_D[5]
SD_D[14]
SD_D[3]
SD_D[17]
SD_D[31]
SD_D[7]
SD_D[15]
SD_D[19]
SD_DQM[2]
SD_D[8]
SD_D[21]
DVDDC
DVDDC
DVDDC
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVDDC
DVDDC
DVDDC
MBIST_EN
DVDDIO
DVDDIO
TDM1_TSIG_CTS
TDM1_RSIG_RTS
ACVSS1
TDM1_TX_SYNC
TDM1_TX_MF_CD
ACVDD1
TDM1_TCLK
TDM1_RCLK
ACVDD2
6
7
8
9
10
11
12
13
14
15
16
SD_D[28]
H_AD[21]
H_AD[24]
H_AD[12]
H_AD[8]
MII_TXD[1]
MII_RX_ERR
CLK_MII_RX
SD_D[24]
H_AD[19]
H_AD[22]
H_D[21]
H_AD[17]
MII_TXD[2]
MII_COL
MII_RXD[0]
SD_D[30]
H_AD[10]
H_WR_BE3_N/
SPI_CI
H_AD[14]
H_WR_BE0_N/
SPI_CLK
MII_TXD[3]
MII_CRS
MII_RXD[1]
SD_D[29]
H_AD[4]
H_AD[6]
H_AD[15]
H_AD[2]
MII_TX_EN
CLK_MII_TX
MII_RXD[2]
SD_D[26]
H_WR_BE2_N/
SPI_SEL_N
H_CS_N
H_AD[11]
H_AD[5]
MII_TX_ERR
CLK_SSMII_TX
MII_RXD[3]
DVDDC
DVDDC
DVDDC
H_D[23]
H_D[24]
H_D[27]
MII_TXD[0]
MII_RX_DV
DVSS
DVSS
DVSS
DVDDIO
H_D[25]
H_D[28]
MDIO
MDC
DVSS
DVSS
DVSS
DVDDIO
H_D[26]
H_D[29]
H_D[31]
H_D[30]
DVSS
DVSS
DVSS
DVDDIO
H_D[6]
H_D[14]
H_D[18]
H_D[22]
DVSS
DVSS
DVSS
DVDDIO
H_D[0]/SPI_MISO
H_D[12]
H_D[4]
H_D[19]
DVSS
DVSS
DVSS
DVDDIO
H_D[3]
H_D[16]
H_D[8]
H_D[17]
DVDDC
DVDDC
DVDDC
H_D[1]
H_D[10]
CLK_CMN
H_D[13]
H_D[15]
DVDDIO
DVDDIO
HiZ_N
H_R_W_N/SPI_CP
H_AD[7]
H_AD[23]
H_D[7]
H_D[20]
CLK_HIGH
JTDI
JTDO
H_WR_BE1_N/
SPI_MOSI
H_AD[3]
H_AD[20]
H_D[5]
H_D[11]
CLK_SYS_S
JTCLK
RST_SYS_N
H_READY_N
H_AD[1]
H_AD[18]
H_D[2]
H_D[9]
ACVSS2
JTMS
JTRST_N
CLK_SYS/SCCLK
H_INT[0]
H_AD[9]
H_AD[13]
H_AD[16]
9
10
11
12
13
14
15
16
Rev: 032609
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
192 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
16.5 DS34S108 Pin Assignment
Table 16-2. DS34S108 Pin Assignment (Sorted by Signal Name)
Signal Name
Ball Signal Name
Ball Signal Name
ACVDD1
ACVDD2
ACVSS1
ACVSS2
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
Rev: 032609
M2
K2
M1
K1
P1
L1
V16
AA18
Y19
J1
J2
L21
A12
B11
C20
C4
E18
E20
E5
G18
G5
L2
T18
T5
V18
V20
V5
Y10
Y20
AA11
AA13
AA15
AA2
AA9
B10
B14
B16
B2
B8
C3
D1
F2
H2
J10
J11
J12
J13
K14
K9
L14
H_AD[18]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[30]
H_D[31]
H_D[4]
H_D[5]
H_D[6]
H_D[7]
H_D[8]
H_D[9]
H_INT[0]
M19
N21
M21
M17
P20
R22
N17
T21
K16
M22
T20
M18
M16
M20
L16
K19
L17
T22
U21
V22
P18
W22
Y21
P19
Y22
AA21
AA22
AB21
U20
N18
R19
AB22
P17
V21
R17
V19
T19
W21
U16
R18
R20
W20
U19
T17
P16
U18
R16
U22
T16
J17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Ball
C1
C10
C2
C5
C6
C7
C8
C9
D3
D5
D6
D7
D8
D9
E1
E2
E4
E6
E7
E8
F3
F4
F5
F7
F8
G1
G2
G4
G6
G7
G8
H4
H5
H6
H7
J4
J5
J6
J7
J8
K4
K5
K6
K7
K8
L22
L4
L5
L6
L7
Signal Name
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[13]
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_RX_SYNC
TDM1_TCLK
TDM1_TSIG_CTS
TDM1_TX
TDM1_TX_MF_CD
TDM1_TX_SYNC
TDM2_ACLK
TDM2_RCLK
Ball
F21
B22
H20
C21
H18
C22
D21
G20
D22
J20
G21
G19
J21
E22
J19
H21
F22
K21
G22
K20
H22
G16
A21
K22
J22
C16
A22
A18
B21
E21
H19
A20
E19
B20
D20
D16
C17
K15
E10
D12
C11
D10
D11
F12
E11
C12
F13
E13
E9
E12
193 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Signal Name
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
Rev: 032609
Ball
L9
M14
M9
N14
N9
P10
P11
P12
P13
R2
U2
V3
W1
A10
A14
A16
A8
AA1
AB11
AB13
AB15
AB9
B1
B12
D19
D2
D4
E3
F1
F17
F6
H1
H15
H8
K10
K11
K12
K13
L10
L11
L12
L13
M10
M11
M12
M13
N10
N11
N12
N13
N2
R1
R15
R8
U1
Signal Name
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_WR_BE1_N/SPI_MOSI
H_WR_BE2_N/SPI_SEL_N
H_WR_BE3_N/SPI_CI
HiZ_N
JTCLK
JTDI
JTDO
JTMS
JTRST_N
MBIST_DONE
MBIST_EN
MBIST_FAIL
MCLK
MDC
MDIO
MII_COL
MII_CRS
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Ball
K17
K18
L19
J16
J18
L20
T3
L3
M3
N3
K3
P3
M15
P15
N15
N1
AB17
AA20
AA17
Y18
Y17
V17
AA16
W16
AB16
Y16
W17
AB20
AB18
W18
AA19
AB19
A1
A11
A13
A15
A2
A3
A4
A5
A6
A7
A9
AA10
AA12
AA14
AA3
AA4
AA5
AA6
AA7
AA8
AB1
AB10
AB12
Signal Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RST_SYS_N
SCEN
SD_A[0]
SD_A[1]
Ball
L8
M4
M5
M6
M7
M8
N4
N5
N6
N7
N8
P4
P5
P6
P7
P8
P9
R3
R4
R5
R6
R7
T1
T2
T4
T6
T7
T8
U3
U4
U5
U7
U8
V1
V2
V4
V6
V7
V8
W3
W5
W6
W7
W8
Y1
Y2
Y4
Y5
Y6
Y7
Y8
P2
J15
A17
F18
Signal Name
TDM2_RSIG_RTS
TDM2_RX
TDM2_RX_SYNC
TDM2_TCLK
TDM2_TSIG_CTS
TDM2_TX
TDM2_TX_MF_CD
TDM2_TX_SYNC
TDM3_ACLK
TDM3_RCLK
TDM3_RSIG_RTS
TDM3_RX
TDM3_RX_SYNC
TDM3_TCLK
TDM3_TSIG_CTS
TDM3_TX
TDM3_TX_MF_CD
TDM3_TX_SYNC
TDM4_ACLK
TDM4_RCLK
TDM4_RSIG_RTS
TDM4_RX
TDM4_RX_SYNC
TDM4_TCLK
TDM4_TSIG_CTS
TDM4_TX
TDM4_TX_MF_CD
TDM4_TX_SYNC
TDM5_ACLK
TDM5_RCLK
TDM5_RSIG_RTS
TDM5_RX
TDM5_RX_SYNC
TDM5_TCLK
TDM5_TSIG_CTS
TDM5_TX
TDM5_TX_MF_CD
TDM5_TX_SYNC
TDM6_ACLK
TDM6_RCLK
TDM6_RSIG_RTS
TDM6_RX
TDM6_RX_SYNC
TDM6_TCLK
TDM6_TSIG_CTS
TDM6_TX
TDM6_TX_MF_CD
TDM6_TX_SYNC
TDM7_ACLK
TDM7_RCLK
TDM7_RSIG_RTS
TDM7_RX
TDM7_RX_SYNC
TDM7_TCLK
TDM7_TSIG_CTS
Ball
C14
D13
C13
G10
F11
G11
F10
E14
G14
C15
G13
D15
D14
G9
G12
E15
F9
F14
H12
J14
F15
H9
H14
H11
G15
J9
H13
H10
V11
V9
T9
R11
U14
T13
P14
R12
R10
R14
W14
T12
R9
V12
T15
V15
V13
W15
U15
T10
V14
U13
T14
U12
R13
Y11
W9
194 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Signal Name
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
H_AD[17]
Rev: 032609
Ball
U17
U6
W19
W2
W4
Y12
Y3
L18
N22
L15
P21
N16
N20
P22
N19
R21
Signal Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Ball
AB14
AB2
AB3
AB4
AB5
AB6
AB7
AB8
B13
B15
B3
B4
B5
B6
B7
B9
Signal Name
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
Ball
B19
D17
F16
B18
E17
A19
H17
F19
F20
D18
G17
C19
E16
H16
B17
C18
Signal Name
TDM7_TX
TDM7_TX_MF_CD
TDM7_TX_SYNC
TDM8_ACLK
TDM8_RCLK
TDM8_RSIG_RTS
TDM8_RX
TDM8_RX_SYNC
TDM8_TCLK
TDM8_TSIG_CTS
TDM8_TX
TDM8_TX_MF_CD
TDM8_TX_SYNC
TEST_CLK
TST_CLD
NC
Ball
W12
Y15
U11
Y13
U9
Y9
V10
T11
Y14
W11
W10
W13
U10
J3
G3
H3
195 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 16-4. DS34S108 Pin Assignment (HSBGA Package)
1
2
3
4
5
6
7
8
9
10
A
NC
NC
NC
NC
NC
NC
NC
DVSS
NC
DVSS
11
NC
B
DVSS
DVDDIO
NC
NC
NC
NC
NC
DVDDIO
NC
DVDDIO
DVDDC
TDM1_RSIG_RTS
C
NC
NC
DVDDIO
DVDDC
NC
NC
NC
NC
NC
NC
D
DVDDIO
DVSS
NC
DVSS
NC
NC
NC
NC
NC
TDM1_RX
TDM1_RX_SYNC
E
NC
NC
DVSS
NC
DVDDC
NC
NC
NC
TDM2_ACLK
TDM1_ACLK
TDM1_TSIG_CTS
F
DVSS
DVDDIO
NC
NC
NC
DVSS
NC
NC
TDM3_TX_MF_CD
TDM2_TX_MF_CD
TDM2_TSIG_CTS
G
NC
NC
TST_CLD
NC
DVDDC
NC
NC
NC
TDM3_TCLK
TDM2_TCLK
TDM2_TX
H
DVSS
DVDDIO
NC
NC
NC
NC
NC
DVSS
TDM4_RX
TDM4_TX_SYNC
TDM4_TCLK
J
CLK_SYS/SCCLK
CLK_SYS_S
TEST_CLK
NC
NC
NC
NC
NC
TDM4_TX
DVDDIO
DVDDIO
K
ACVSS2
ACVDD2
JTMS
NC
NC
NC
NC
NC
DVDDIO
DVSS
DVSS
L
CLK_HIGH
DVDDC
JTCLK
NC
NC
NC
NC
NC
DVDDIO
DVSS
DVSS
M
ACVSS1
ACVDD1
JTDI
NC
NC
NC
NC
NC
DVDDIO
DVSS
DVSS
N
MCLK
DVSS
JTDO
NC
NC
NC
NC
NC
DVDDIO
DVSS
DVSS
P
CLK_CMN
RST_SYS_N
JTRST_N
NC
NC
NC
NC
NC
NC
DVDDIO
DVDDIO
R
DVSS
DVDDIO
NC
NC
NC
NC
NC
DVSS
TDM6_RSIG_RTS
TDM5_TX_MF_CD
TDM5_RX
T
NC
NC
HiZ_N
NC
DVDDC
NC
NC
NC
TDM5_RSIG_RTS
TDM6_TX_SYNC
TDM8_RX_SYNC
U
DVSS
DVDDIO
NC
NC
NC
DVSS
NC
NC
TDM8_RCLK
TDM8_TX_SYNC
TDM7_TX_SYNC
V
NC
NC
DVDDIO
NC
DVDDC
NC
NC
NC
TDM5_RCLK
TDM8_RX
TDM5_ACLK
W
DVDDIO
DVSS
NC
DVSS
NC
NC
NC
NC
TDM7_TSIG_CTS
TDM8_TX
TDM8_TSIG_CTS
Y
NC
NC
DVSS
NC
NC
NC
NC
NC
TDM8_RSIG_RTS
DVDDC
TDM7_TCLK
AA
DVSS
DVDDIO
NC
NC
NC
NC
NC
NC
DVDDIO
NC
DVDDIO
AB
NC
NC
NC
NC
NC
NC
NC
NC
DVSS
NC
DVSS
1
2
3
4
5
6
7
8
9
10
12
13
14
15
DVDDC
DVSS
NC
DVSS
NC
NC
DVDDIO
NC
TDM1_TX
TDM2_RX_SYNC
TDM2_RSIG_RTS
TDM3_RCLK
TDM1_RCLK
TDM2_RX
TDM3_RX_SYNC
TDM2_RCLK
TDM1_TX_SYNC
TDM1_TCLK
16
17
18
DVSS
SD_A[0]
DVDDIO
SD_CS_N
SD_D[4]
TDM3_RX
TDM2_TX_SYNC
TDM1_TX_MF_CD
TDM3_TSIG_CTS
11
19
20
21
SD_D[6]
SD_A[5]
SD_DQM[0]
SD_D[3]
SD_D[5]
A
SD_A[3]
SD_A[10]
SD_DQM[2]
SD_D[7]
SD_D[10]
B
SD_WE_N
SD_D[0]
SD_BA[1]
DVDDC
SD_D[12]
SD_D[14]
C
SD_RAS_N
SD_A[11]
SD_A[9]
DVSS
SD_DQM[3]
SD_D[15]
SD_D[17]
D
TDM3_TX
SD_CAS_N
SD_A[4]
DVDDC
SD_DQM[1]
DVDDC
SD_D[8]
SD_D[21]
E
TDM3_TX_SYNC
TDM4_RSIG_RTS
SD_A[2]
DVSS
SD_A[1]
SD_A[7]
SD_A[8]
SD_D[1]
SD_D[24]
F
TDM3_RSIG_RTS
TDM3_ACLK
TDM4_TSIG_CTS
SD_D[29]
SD_BA[0]
DVDDC
SD_D[2]
SD_D[16]
SD_D[19]
SD_D[26]
G
TDM4_ACLK
TDM4_TX_MF_CD
TDM4_RX_SYNC
DVSS
SD_CLK
SD_A[6]
SD_D[13]
SD_D[9]
SD_D[11]
SD_D[23]
SD_D[28]
H
DVDDIO
DVDDIO
TDM4_RCLK
SCEN
H_WR_BE1_N/SPI_MOS
H_INT[0]
SD_D[22]
SD_D[18]
SD_D[20]
SD_D[31]
J
DVSS
DVSS
DVDDIO
STMD
H_AD[3]
H_R_W_N/SPI_CP
H_READY_N
H_CPU_SPI_N
SD_D[27]
DVSS
DVSS
DVDDIO
H_AD[11]
H_AD[9]
H_CS_N
H_AD[1]
DVSS
DVSS
DVDDIO
MBIST_DONE
H_AD[7]
H_AD[20]
H_AD[6]
H_AD[18]
DVSS
DVSS
DVDDIO
MBIST_FAIL
H_AD[13]
H_AD[23]
H_D[2]
DVDDIO
DVDDIO
TDM5_TSIG_CTS
MBIST_EN
H_D[5]
H_D[22]
TDM5_TX
TDM7_RX_SYNC
TDM5_TX_SYNC
DVSS
H_D[7]
TDM6_RCLK
TDM5_TCLK
TDM7_RSIG_RTS
TDM6_RX_SYNC
TDM7_RX
TDM7_RCLK
TDM5_RX_SYNC
TDM6_RX
TDM6_TSIG_CTS
TDM7_TX
H_WR_BE2_N/SPI_SEL_
22
SD_D[25]
SD_D[30]
K
DAT_32_16_N
NC
L
H_AD[8]
H_AD[2]
H_AD[4]
M
H_AD[16]
H_AD[14]
H_AD[19]
H_AD[10]
N
H_D[11]
H_D[14]
H_AD[21]
H_AD[12]
H_AD[15]
P
H_D[24]
H_D[29]
H_D[20]
H_D[3]
H_AD[17]
H_AD[22]
R
H_D[9]
H_D[4]
DVDDC
H_D[26]
H_AD[5]
H_AD[24]
H_D[0]/SPI_MISO
T
TDM6_TX_MF_CD
H_D[28]
DVSS
H_D[6]
H_D[31]
H_D[19]
H_D[1]
H_D[8]
U
TDM7_ACLK
TDM6_TCLK
CLK_MII_RX
MII_RX_ERR
DVDDC
H_D[25]
DVDDC
H_D[23]
H_D[10]
V
TDM8_TX_MF_CD
TDM6_ACLK
TDM6_TX
MII_RXD[1]
MII_TX_EN
MII_TXD[1]
DVSS
H_D[30]
H_D[27]
H_D[12]
W
DVSS
TDM8_ACLK
TDM8_TCLK
TDM7_TX_MF_CD
MII_RXD[3]
MII_RX_DV
MII_CRS
CLK_SSMII_TX
DVDDC
H_D[13]
H_D[15]
Y
NC
DVDDIO
NC
DVDDIO
MII_RXD[0]
MII_COL
CLK_MII_TX
MII_TXD[2]
MDIO
H_D[16]
H_D[17]
AA
NC
DVSS
NC
DVSS
MII_RXD[2]
MDC
MII_TXD[0]
MII_TXD[3]
MII_TX_ERR
H_D[18]
H_D[21]
AB
12
13
14
15
16
17
18
19
20
21
22
Rev: 032609
H_WR_BE0_N/SPI_CLK H_WR_BE3_N/SPI_CI
196 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
17. Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
DS34S101, DS34S102 and DS34S108 have a 256-lead thermally enhanced chip-scale ball grid array (TECSBGA)
package. The TECSBGA package dimensions are shown in Maxim document 21-0353.
DS34S108 has a 484-lead thermally enhanced ball grid array (TEBGA) package. The TEBGA package dimensions
are shown in Maxim document 21-0365.
18. Thermal Information
Parameter
Target Ambient Temperature Range
Die Junction Temperature Range
Theta Jc (junction to top of case)
Theta Jb (junction to bottom pins)
Theta Ja, Still Air (Note 1)
TECSBGA-256
DS34S101
DS34S102
DS34S104
-40 to 85°C
-40 to 125°C
3.7 °C/W
13.1 °C/W
26.2 °C/W
TEBGA-484
DS34S108
-40 to 85°C
-40 to 125°C
4.5 °C/W
7.1 °C/W
15.0 °C/W
Note 1: These numbers are estimates using JEDEC standard PCB and enclosure dimensions.
Rev: 032609
197 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
19. Data Sheet Revision History
REVISION
DATE
071108
100108
DESCRIPTION
Initial release.
In the Ordering Information table on page 1, removed the asterisks and footnotes that indicated
DS34S101, DS34S102 and DS34S104 were future products.
In Table 11-11, Table 11-13, Table 11-14 and Table 11-15, corrected the index variable in the
Description column from n to ts to match the other columns.
Updated Figure 6-1 to show all CPU interface pins including SPI bus pin names.
In section 11.4.8, changed the index into the jitter buffer control registers from j = 0 to 255 to port
= 1 to 8 and ts = 0 to 31 for additional clarity.
Removed all references to AAL2 mode.
Replaced the incorrect terms “cell” and “cells” with “AAL1 SAR PDU” throughout the document
except in register names and register field names.
101408
032609
Edited section 10.6.6 for additional clarity about the AAL1 mapping methods.
Corrected some spelling errors and other minor typos.
In Table 9-1, change note on TST_CLD pin from “DS34S104 only” to “DS34S108 only”.
Corrected Table 16-1, which previously was missing a large section from the middle.
Added future status for DS34S101 and DS34S102 to the Ordering Information table.
Removed future status for the DS34S101 and DS34S102 in the Ordering Information table.
Rev: 032609
198 of 198
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0
2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products.
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