DS3922T+T

EVALUATION KIT AVAILABLE DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller General Description The DS3922 high-speed current mirror integrates highvoltage devices necessary for monitoring the burst mode receive power signal in avalanche photodiode (APD) biasing and OLT applications. The device has two small and one large gain current mirror outputs to monitor the APD current. An adjustable current clamp limits current through the APD. The clamp also features an external shutdown. An integrated FET is also provided that can be used to quickly clamp the high-voltage bias to ground in the case of high optical input power. Integrated low-voltage FET circuits can be used to create buck, boost, and inverting DC-DC converters for efficient laser bias and EML bias applications. The DS3922 is available in a 24-pin TQFN package and operates over an extended -40°C to +95°C temperature range. Benefits and Features ●● Accurate Burst-Mode RSSI Measurement with Two Current Mirror Outputs Improves Dynamic Range • • • • ●● Low-Noise APD Bias with Shutdown Options Reduces Receiver Sensitivity • 15V to 76V APD Bias • External Capacitor Connection for Controlled RC Time Constant of APD Voltage Filter • Current Clamp with Adjustable Limit and External Shutdown with Limit Status • High-Voltage Switch FET for APD Fast Shutdown ●● Supports Additional DC-DC Functions • Low-Voltage Synchronous Buck FETs for Efficient DFB Bias • Low-Voltage pMOSFET for Generating Negative Bias Voltage for EMLs LOW-VOLTAGE FET CIRCUITS LVCC DS3922 VCC VIP2 VIP1 IOUT Block Diagram AVCC 0.8I1 0.2I1 0.1I1 MIRCAP CURRENT LIMIT 200µA TEMP LIMIT LVCC HIGH-POWER DML, DFB, LDD, TXVCC LVGND LVGND LVOUT3 (0 TO 4V) OPEN-DRAIN nMOS LVIN3 EML NEGATIVE BIAS INVERTING SWITCHER LVIN2 LVCC ISRC/SHDN LVCC 1.8V AVCC 0.5V/V APDV MIRIN MIROUT HVD GND LVOUT2 (-3.7V TO LVCC) OPEN-DRAIN pMOS LVGND EML, DFB, APC HIGH-EFFICIENCY BIAS LVIN1 LVCC LVCC pMOS HVGND VCC HVG nMOS LVGND 19-7400; Rev 1; 3/15 LVOUT1 (0 TO LVCC) NONOVERLAP DRIVER LVGND ● ● ● ● ● Avalanche Photodiode (APD) Monitoring GPON OLT 10GPON OLT EML Bias 10G EPON Ordering Information appears at end of data sheet. pMOS MIROUT • 3.5mm x 3.5mm, 24-Pin TQFN Package with Exposed Pad Applications AVCC 4V RLIM ●● Small Package Reduces Total Solution Size and Cost LVGND I1 ILIMS (2.85V TO 3.63V) (WITHIN ±0.1V OF HVGND AND GND) HIGH-VOLTAGE AND MIRROR CIRCUITS MIRIN -32dBm to -5dBm Optical Input Range ±0.5dB Accuracy Sampling Period as Short as 300ns Pin Discharge Option For related parts and recommended products to use with this part, refer to www.maximintegrated.com/DS3922.related. DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Absolute Maximum Ratings Voltage on HVD, MIRIN, MIRCAP, and MIROUT Relative to HVGND.............................-0.3V to +79V Voltage on MIROUT Relative to HVGND....-0.3V to (VMIRIN + 0.3V) Voltage on LVOUT1 Relative to LVGND...........................................-0.3V to (VLVCC + 0.3V) Voltage on LVOUT2 Relative to LVGND...-4V to (VLVCC + 0.3V) Voltage on LVOUT3 Relative to LVGND..................-0.3V to +5V Voltage on LVCC Relative to VCC.......................................±0.1V Voltage on All Other Pins Relative to GND......... -0.3V to (VCC + 0.3V) not to exceed +4V Continuous Power Dissipation (TA = +70°C) TQFN (derate 15.4mW/°C above +70°C)...............1228.9mW Storage Temperature Range............................. -55°C to +135°C Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature, Lead(Pb)-Free Reflow................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TQFN Junction-to-Ambient Thermal Resistance (θJA)..........5.4°C/W Junction-to-Case Thermal Resistance (θJC).............65.1°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Low-Voltage Supply VCC Low-Voltage Current ICC MIRIN Quiescent Current IMIRIN MIRIN Voltage VMIRIN HV FET Turn-On Time tON:HV HV FET On-Resistance RDSONHV HVG Voltage VGSHV HVD Voltage VDHV HVD Leakage IILHV Logic Input Thresholds: HVG, LVIN1, LVIN2, LVIN3 ISRC/SHDN Resistor www.maximintegrated.com MIN TYP MAX UNITS 3.63 V 1.5 3.0 mA IMIROUT = 0µA 1 2 IMIROUT = 1mA 3.2 4.5 2.85 (Note 3) VMIRIN = 60V, ISRC/SHDN = 30kΩ to GND 15 VDHV falling from 90% to 10% of peak voltage 76 30 VGS = 3.0V, ID = 170mA 0.85 2 Ω 0 V 76 V -1 +1 µA 0.65 x VCC VIH SHDN RISRC Note: Compatible with 2.5V and 3.3V CMOS logic levels (Note 4) V ns 0.25 x VCC VIH mA VCC + 0.3 VIL VIL SHDN ISRC/SHDN Threshold CONDITIONS V 1.4 V VCC 0.2 29.7 30 30.3 kΩ Maxim Integrated │  2 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Electrical Characteristics (continued) (VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, unless otherwise noted.) (Note 2) PARAMETER Maximum MIROUT Current SYMBOL ICLAMP CONDITIONS ISRC/SHDN = low MIN TYP MAX RLIM = 40kΩ 1.37 2.1 3.21 RLIM = 25kΩ 2.55 3.3 4.45 ISRC/SHDN = high MIROUT Capacitive Load CMIROUT Total capacitance on MIROUT to achieve accuracy specification UNITS mA 0.01 330 500 VCC 0.4 pF VOH IILIMS = +2mA VOL IILIMS = -2mA ILIMS Output Time tILMS (Note 5) IOUT-to-MIROUT Ratio KIOUT IMIROUT = 1mA 0.090 0.100 0.110 A/A VIP1-to-MIROUT Ratio KVIP1 IMIROUT = 1mA 0.720 0.800 0.880 A/A VIP2-to-MIROUT Ratio KVIP2 IMIROUT = 1mA 0.180 0.200 0.220 A/A KIOUT, KVIP1, and KVIP2 Voltage Variation KVAR VMIRIN = 40V ±10% ±0.3 ±2.5 % 50 250 pF -1% +1% V Logic Output Levels: ILIMS Mirror Voltage-Drop Monitor Load Capacitance VAPDV:CAP External capacitance required on APDV Mirror Voltage-Drop Monitor Output Voltage Variance VAPDV:VAR VMIRIN = 40V ±10% Current limit not exceeded, VSHDN = 0V, IMIRIN = 1mA V 0.4 1 µs Mirror Voltage Drop VMIRIN VMIROUT Mirror Voltage Drop vs. Current Change (VMIROUT 10µA VMIROUT 2.5mA) 40 Shutdown Temperature TSHDN 150 °C Hysteresis Temperature THYS 20 °C 4 V 110 mV VIP1 Offset Current IVIP1OFF RISRC = 30kΩ 20 40 µA VIP2 Offset Current IVIP2OFF RISRC = 30kΩ 19 30 µA IOUT Offset Current IOUTOFF RISRC = 30kΩ 18 25 µA www.maximintegrated.com Maxim Integrated │  3 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Low-Voltage FET Parameters (VLVCC = 2.85V to 3.63V, TA = -40°C to +95°C, unless otherwise noted.) (Note 2) PARAMETER LVFET1P On-Resistance SYMBOL CONDITIONS MIN TYP MAX UNITS LV1PON LV1NON VLVCC = 3.3V 1 Ω VLVCC = 3.3V 1 Ω LVFET2P On-Resistance LV2PON VLVCC = 3.3V 1.5 Ω LVFET3N On-Resistance LV3NON VLVCC = 3.3V 1 Ω LVOUT1 Voltage LVOUT1 LVGND to VLVCC V LVOUT2 Voltage LVOUT2 -3.7 to VLVCC V LVOUT3 Voltage LVOUT3 LVGND to +4 V LVFET1N On-Resistance Note 2: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage rating are guaranteed by design and characterization. Note 3: ISRC/SHDN: Not connected. HV FET: 250kHz driven by 100Ω source with 2.97V square wave. HVD connected to GND. Note 4: External resistor connected to GND. This value guarantees accuracy of the DS3922. Note 5: Resistor connected to RLIM for 1mA clamp limit. IMIROUT step from 10µA to 10mA. Time measured from IMIROUT step to IMIROUT < 1.1mA. See the Typical Application Circuit: C11 = 47pF, C1 = C2 = 0.1µF, VC1 = 30V; R1 = 100Ω. www.maximintegrated.com Maxim Integrated │  4 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ICC vs. VCC toc01 1.04 1.03 Icc (mA) Icc (mA) 1.0164 1.01 1 1.0101 0.98 TA = +25 ºC 2.8 3 3.2 Vcc (V) -5 3.6 0.1µF MIRCAP CAPACITOR -25 TA = +25ºC, VCC = 3.3V 50 -40 NOISE FREQUENCY (Hz) 50000 85 110 toc04 0.6 0.5 TA = +25ºC, VCC = 3.3V 0.4 0.3 KVIP2 0.2 0 5000 10 35 60 TEMPERATURE (º C) KVIP1 0.7 KIOUT 0.1 500 -15 0.9 0.8 -10 -20 VCC = 3.3V CURRENT MIRROR RATIO vs. MIROUT CURRENT toc03 0.01µF MIRCAP CAPACITOR -15 1.008 CURRENT MIRROR RATIO NOISE TRANSFER (dB) 3.4 CURRENT MIRROR FILTER FREQUENCY RESPONSE 0 www.maximintegrated.com 1.0143 1.0122 0.99 -30 toc02 1.0185 1.02 0.97 ICC vs. TEMPERATURE 1.0206 0.01 0.1 1 MIROUT CURRENT (mA) 10 Maxim Integrated │  5 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller RLIM APDV ILIMS ISRC/SHDN GND LVIN3 Pin Configuration 18 17 16 15 14 13 TOP VIEW MIROUT 19 12 LVIN2 HVG 20 11 LVOUT3 10 LVGND 9 LVCC 8 LVOUT2 7 LVOUT1 MIRCAP 21 DS3922 MIRIN 22 HVGND 23 *EP + 1 2 3 4 5 6 V CC AVCC VIP2 VIP1 IOUT LVIN1 HVD 24 TQFN (3.5mm x 3.5mm x 0.8mm) Pin Description PIN NAME 1 VCC FUNCTION 2 AVCC Analog 3.3V (Nominal) Supply 3 VIP2 20% Current Mirror Output. Connect to resistor to ground. 4 VIP1 80% Current Mirror Output. Connect to resistor to ground. 5 IOUT 10% Current Mirror Output. If not used, do not connect. 6 LVIN1 Digital Input. Connect to an external PWM output to create buck DC-DC converter. Controls output LVOUT1. 7 LVOUT1 Push-Pull Output 8 LVOUT2 Open-Drain pMOS Output. This output does not have a diode connection to LVGND and can go a few volts below LVGND for inverter application. 9 LVCC Digital 3.3V (Nominal) Supply Low-Voltage Supply Voltage 10 LVGND Low-Voltage Ground 11 LVOUT3 Open-Drain nMOS Output 12 LVIN2 Digital Input. Connect to an external PWM output to create buck or inverting DC-DC converter. Controls output LVOUT2. 13 LVIN3 Digital Input. Connect to an external PWM output to boost DC-DC converter. Controls output LVOUT3. 14 GND Ground www.maximintegrated.com Maxim Integrated │  6 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Pin Description (continued) PIN 15 NAME ISRC/SHDN FUNCTION Dual-purpose pin: ISRC: A resistor connected to this pin controls the amount of current flowing through a current source connected to MIROUT. Note: During this mode of operation, the microcontroller pin (if connected) should be high impedance. SHDN: If pulled high, sets MIROUT to high impedance. 16 ILIMS Current-Limit Status. Active-low signal indicating that the current-limit threshold is exceeded. 17 APDV APD Voltage Monitor. Provides output voltage used to calculate the voltage on the APD. 18 RLIM Resistor Limit. Connect resistor between RLIM and GND to set the current clamp limit. 19 MIROUT 20 HVG 21 MIRCAP 22 MIRIN 23 HVGND 24 HVD — EP Current Mirror Output. Connect to the APD. High-Voltage nMOS FET Gate. Connect to ground if not used. Mirror Filter. Connect external capacitor to filter voltage at MIROUT. Current Mirror Input. Connect to high-voltage supply. High-Voltage nMOS FET Source High-Voltage nMOS FET Drain. Connect to HVGND if not used. Exposed Pad. Connect to ground with a minimum of nine vias for thermal conductivity improvement. It is acceptable to use a solder mask between the IC and the ground pad. However, using a solder mask between the IC and the ground pad may cause thermal conductivity issue. It is not necessary to electrically connect the exposed pad to ground. www.maximintegrated.com Maxim Integrated │  7 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Typical Application Circuit R1 100Ω BOOST DC-DC C1 GPIO SHDN VREF 0.1µF PWM C2 0.1µF MIRIN GPIO LVIN1– LVIN3 MIRCAP C10 0.1µF DAC APD SHUTDOWN GPIO HVG DS3922 HVD DS4830A HVGND R2 330kΩ ADC_HV_OUT L VOUT1 R3 5kΩ ADC_LVOUT1 VREFOUT L2 4.7µH AVCC,VCC L VOUT2 C4 1µF L3 2.5mH R4 10kΩ C5 1µF 3.3V C9 0.1µF EP D2 GND ADC_LVOUT2 R5 100kΩ D3 R6 10kΩ C6 1µF ADC_LVOUT3 R7 10kΩ RLIM L VOUT3 R12 40kΩ L4 4.7µH VCC ADC_APDV ADC_IOUT APDV IOUT R8 5kΩ LVCC VIP1 Sample/ Hold[1:0] R9 1kΩ LVGND 3.3V C8 0.1µF VIP2 R10 1kΩ GPIO APD SHUTDOWN → GPIO ILIMS ISRC/SHDN R11 30kΩ MIROUT C11 330pF TO 500pF APD TIA www.maximintegrated.com Maxim Integrated │  8 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Detailed Description The DS3922 contains high-voltage (HV) components required to monitor the APD bias current. The device’s mirror outputs are a current that is a precise ratio of the output current across a large dynamic range. The mirror response time is fast enough to comply with GPON Rx burst-mode monitoring requirements. The device has a built-in current-limiting feature to protect APDs. This current limit is adjustable using an external resistor. The APD current can also be shut down by ISRC/SHDN or thermal shutdown. The internal HV FET may be used as a fast APD shutdown. Low-voltage FETs can be used to create various DC-DC converters. Current Mirrors The device includes three current mirrors, as shown in Figure 1. One is a 10:1 (10%) mirror connected at IOUT. The other two are a 1.25:1 (80%) and the 5:1 (20%) mirror connected to VIP1 and VIP2. On pins VIP1 and VIP2, resistors to ground should be selected such that the maximum voltage should be below the external ADC full scale. For example, if the maximum monitored current through the APD is 1mA, the mirror is 1.25:1 ratio, and then the correct resistor is approximately 780Ω for the external ADC having full scale of 0.625V. Current Mirror Filter The device includes a filter to stabilize the MIROUT voltage. An external capacitor must be connected to the MIRCAP pin. Current Source for Mirror Bias The current mirror response time is improved by providing a continuous current source. This source is adjustable by changing the resistor connected to the ISRC/SHDN pin. However, only one value is allowed to guarantee performance (see the Electrical Characteristics section): ISRC = (6/RISRC) ±6% Current Mirror Voltage-Drop Monitor The device includes a voltage monitor that indicates the voltage drop across the current mirror. This signal is output on APDV. This signal should be used to accurately maintain the correct APD bias voltage in conjunction with the feedback resistors for the APD bias boost converter: APDV = (VMIRIN - VMIROUT)/2 Current Clamp The device has a current-clamping circuit to protect the APD by limiting the amount of current from MIROUT. The current limit is defined by a resistor connected between RLIM and ground. A larger RLIM results in a lower current clamp limit (see the Electrical Characteristics table). Shutdown The MIROUT output can be set to a high-impedance state using the ISRC/SHDN pin, effectively disabling the APD. The ISRC/SHDN pin is active high. MIRIN Low-Voltage FETs 1.0I1 MIRCAP 0.8I1 0.2I1 0.1I1 HV BIAS High-Voltage Switching FET An HV switching FET is included to optionally be used to quickly turn off the bias voltage to the APD. The strong HV FET can quickly discharge the capacitance on the MIRIN pin.. CURRENT LIMIT RLIM DS3922 These FETs can be used to create DC-DC converters for EML bias, high-efficiency DFB bias, and other possible applications. TEMPERATURE LIMIT MIROUT VIP1 VIP2 IOUT Figure 1. Current Mirrors www.maximintegrated.com Maxim Integrated │  9 DS3922 Applications Information Layout Considerations Proper PCB layout helps to reduce switching noise in the system. Keeping all PCB traces as short as possible reduces radiated noise, stray capacitance, and trace resistance. High-Speed Current Mirror and Integrated FETs for DC-DC Controller Ordering Information TEMP RANGE PIN-PACKAGE DS3922T+ PART -40°C to +95°C 24 TQFN-EP** DS3922T+T* -40°C to +95°C 24 TQFN-EP** +Denotes a lead(Pb)-free/RoHS-compliant package. *Second T denotes tape and reel. First T denotes package type. **EP = Exposed pad. Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN-EP T243A3+1 21-0188 90-0122 Maxim Integrated │  10 DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 5/14 Initial release 1 3/15 Revised recommended usage of HV FET. Revised General Description, Features, Applications, Pin Description, Detailed Description, and Typical Application Circuit. Updated Benefits and Features section. DESCRIPTION — 1, 7–10 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │  11 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: DS3922T+ DS3922T+T