DS4026S+HCN

Rev 2; 4/08 10MHz to 51.84MHz TCXO Features The DS4026 is a temperature-compensated crystal oscillator (TCXO) that provides ±1ppm frequency stability over the -40°C to +85°C industrial temperature range. The DS4026 is also available in Stratum 3 versions (see the Ordering Information—Stratum 3 table). Each device is factory calibrated over temperature to achieve the ±1ppm frequency stability. Standard frequencies for the device include 10, 12.8, 19.44, 20, 38.88, 40, and 51.84MHz. Contact the factory for custom frequencies. The DS4026 provides excellent phase-noise characteristics. The output is a push-pull CMOS square wave with symmetrical rise and fall times. In addition, the DS4026 is designed to provide a maximum frequency deviation of less than ±4.6ppm over 20 years. The device also provides an I2C interface to allow pushing and pulling of the output frequency by a minimum of ±8ppm (±5ppm for 10MHz) with typical 1ppb resolution. The DS4026 implements a temperature-to-voltage conversion with a nonlinear relationship. The output from the temperature-to-voltage converter is used to drive the voltage-controlled crystal oscillator to compensate for frequency change. ♦ ±1ppm Frequency Accuracy Over -40°C to +85°C ♦ Standard Frequencies: 10, 12.8, 19.44, 20, 38.88, 40, 51.84MHz ♦ Stratum 3 Frequencies: 10, 12.8, 19.2, 20MHz ♦ Maximum ±4.6ppm Deviation Over 20 Years ♦ Minimum ±8ppm (±5ppm for 10MHz) Digital Frequency Tuning Through I2C Interface ♦ Surface-Mount 16-Pin SO Package ♦ Pb Free/RoHS Compliant Pin Configuration TOP VIEW + GNDA 1 16 VCCD VREF 2 15 FOUT VCC 3 14 GNDD The device implements an on-chip temperature sensor lookup table, and a digital-to-analog converter (DAC) to adjust the frequency. An I2C interface used to communicate with the DS4026 performs temperature readings and frequency push-pull. GNDOSC 5 Applications Reference Clock Generation Wireless Telecom/Datacom/SATCOM Test and Measurement VOSC 4 13 SCL DS4026 12 SDA N.C. 6 11 GND N.C. 7 10 N.C. N.C. 8 9 N.C. Ordering Information TEMP RANGE OUTPUT (fC) (MHz, CMOS) DS4026S+ACC 0°C to +70°C DS4026S+ACN -40°C to +85°C DS4026S+BCC DS4026S+BCN DS4026S+ECC DS4026S+ECN DS4026S+FCC DS4026S+FCN PART PIN-PACKAGE TOP MARK* 10.00 16 SO DS4026-ACC 10.00 16 SO DS4026-ACN 0°C to +70°C 12.80 16 SO DS4026-BCC -40°C to +85°C 12.80 16 SO DS4026-BCN 0°C to +70°C 16.80 16 SO DS4026-ECC -40°C to +85°C 16.80 16 SO DS4026-ECN 0°C to +70°C 16.384 16 SO DS4026-FCC -40°C to +85°C 16.384 16 SO DS4026-FCN Ordering Information continued at end of data sheet. +Denotes a lead(Pb)-free/RoHS-compliant package. *The top mark will include a “+” for a lead(Pb)-free/RoHS-compliant device. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4026 General Description DS4026 10MHz to 51.84MHz TCXO ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC, VCCD, and VOSC Relative to Ground..............................................-0.3V to +3.8V Voltage Range on SDA, SCL, and FOUT Relative to Ground...................................-0.3V to (VCC + 0.3V) Operating Temperature Range (noncondensing)....-40°C to +85°C Storage Temperature Range ...............................-40°C to +85°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Power-Supply Voltage SYMBOL CONDITIONS MIN TYP MAX UNITS V VCC 3.135 3.3 3.465 Oscillator Power Supply VOSC 3.135 3.3 3.465 V Driver Power Supply VCCD 3.135 3.3 3.465 V MIN TYP MAX UNITS mA DC ELECTRICAL CHARACTERISTICS (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER VCC Active-Supply Current VOSC Oscillator Active-Supply Current VCCD Driver Active-Supply Current SYMBOL ICC I OSC ICCD SCL Input Leakage ILI SDA Leakage ILO SCL, SDA High Input Voltage SCL, SDA Low Input Voltage CONDITIONS 1.5 2.5 FOUT CMOS output on, CL = 10pF, frequency < 25MHz (Note 4) 3 4 FOUT CMOS output on, CL = 10pF, frequency
25MHz 5 9 FOUT CMOS output on, CL = 10pF, frequency < 25MHz 2 3 mA FOUT CMOS output on, CL = 10pF, frequency
25MHz 5 +1 μA -1 +1 μA VIH 0.7 x VCC VCC + 0.3 V VIL -0.3 +0.3 x VCC V 3 mA I OL VCC = 3.0V, VOL = 0.4V FOUT High Output Voltage VOH VCCD = 3V, I OH = -2mA FOUT Low Output Voltage VOL FOUT Rise/Fall Time tR/tF VCCD = 3V, I OL = 2.0mA (0.1 x VCCD) - (0.9 x VCCD) 2 3 -1 Output off SDA Logic 0 Output FOUT Duty Cycle mA tD 0.5 x VCCD (Note 5) 2.4 V 0.4 2 45 _______________________________________________________________________________________ V ns 55 % 10MHz to 51.84MHz TCXO DS4026 AC ELECTRICAL CHARACTERISTICS—TCXO (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER Frequency Stability vs. Temperature Frequency Stability vs. Voltage First Year Aging Years 2–20 Frequency Pull Range Except 10MHz 10MHz Frequency Pull Resolution SYMBOL
f/fC CONDITIONS CL = 10pF to ground MIN TYP MAX UNITS fC – 1ppm fC fC + 1ppm ppm -2 +2 ppm/V -1 +1 -2 +2
f VOLTAGE CL = 10pF to ground, +25°C /fC
fAGING/fC (Note 5)
f/fC FTUNEH = 3Fh and FTUNEL = FFh; FTUNEH = 40h and FTUNEL = 00h at +25°C ±8 ±15 ±5 ±10
fRES/fC ppm ppm 1 ppb AC ELECTRICAL CHARACTERISTICS—STRATUM 3 (VCC = +3.135V to +3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -0.28 +0.28 ppm STRATUM 3 FREQUENCY STABILITY Frequency Stability vs. Temperature
fTEMP/fC -40°C to +85°C (Note 6) Initial Tolerance and Reflow
f INITIAL /fC TA = +25°C, ±3°C and VDD = 3.3V -0.8 +0.8 ppm Frequency Stability vs. Voltage
f VOLTAGE VCC = 3.3V ±5%, CL = 10pF to ground, /fC +25°C (Note 7) -0.33 +0.33 ppm Frequency Stability vs. Aging/20 Years
fAGING/fC fC = Nominal (Note 8) -3.0 +3.0 ppm Frequency Stability vs. Load Change
fLOAD/fC Load = 10pF ±5%, +25°C (Note 5) -0.1 +0.1 ppm Operating temperature, load, supply, and initial tolerance, aging (20 years) (Notes 5, 8) -4.6 +4.6 ppm -0.32 +0.32 ppm Free-Run Accuracy Holdover Stability (24 Hours)
f24HOURS 24-hour elapsed time (Notes 5, 9) /fC PHASE NOISE PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, 3.3V) CARRIER FREQUENCY OFFSET (MHz) 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 12.80 19.44 20.00 38.88 40.00 51.84 10.0 16.384 16.8 24.0 -88.41 -82.63 -83.71 -79.01 -80.80 -74.09 -92.52 -87.44 -89.6 -83.98 -130.16 -125.12 -120.76 -120.06 -115.44 -120.39 -134.83 -128.53 -126.20 -119.45 -147.84 -145.03 -145.44 -141.75 -141.17 -142.33 -147.22 -147.67 -146.88 -143.08 -150.84 -146.87 -150.96 -150.59 -151.59 -151.14 -150.84 -150.78 -151.90 -150.33 -151.71 -151.69 -151.18 -152.50 -152.37 -153.21 -151.25 -152.72 -152.28 -150.34 -151.87 -151.52 -151.45 -153.06 -153.00 -153.94 -150.84 -151.75 -151.93 -150.67 _______________________________________________________________________________________ 3 DS4026 10MHz to 51.84MHz TCXO TEMPERATURE SENSOR ELECTRICAL CHARACTERISTICS (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER Temperature Sensor Accuracy SYMBOL CONDITIONS MIN
T TYP -3 MAX UNITS +3 °C Temperature Sensor Conversion Time tCONVT 11 ms Temperature Sensor Resolution N2 12 Bits MAX UNITS AC ELECTRICAL CHARACTERISTICS—I2C SERIAL INTERFACE (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL SCL Clock Frequency f SCL Bus Free Time Between STOP and START Conditions tBUF Hold Time (Repeated) START Condition (Note 10) tHD:STA Low Period of SCL Clock tLOW High Period of SCL Clock tHIGH Data Hold Time (Notes 11, 12) tHD:DAT Data Setup Time (Note 13) t SU:DAT START Setup Time t SU:STA Rise Time of Both SDA and SCL Signals (Note 14) tR Fall Time of Both SDA and SCL Signals (Note 14) tF Setup Time for STOP Condition t SU:STO Pin Capacitance SDA, SCL (Note 5) 4 CONDITIONS Standard mode MIN TYP 0 100 Fast mode 100 400 Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 0.6 Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 0.6 μs μs μs μs Standard mode 0 0.9 Fast mode 0 0.9 Standard mode 250 Fast mode 100 Standard mode 4.7 Fast mode 0.6 Standard mode μs 1000 Fast mode Standard mode 20 + 0.1CB 300 Fast mode 20 + 0.1CB 4.7 300 Fast mode 300 _______________________________________________________________________________________ ns ns μs 0.6 CI/O μs ns 20 + 0.1CB 20 + 0.1CB Standard mode kHz 10 pF 10MHz to 51.84MHz TCXO DS4026 AC ELECTRICAL CHARACTERISTICS—I2C SERIAL INTERFACE (continued) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Capacitive Load for Each Bus Line (Note 14) CB Pulse Width of Spikes That Must Be Suppressed by the Input Filter t SP CONDITIONS MIN Fast mode TYP MAX UNITS 400 pF 30 ns Typical values are at +25°C, nominal supply voltages, unless otherwise indicated. Voltages referenced to ground. Limits at -40°C are guaranteed by design and not production tested. Specified with I2C bus inactive. Guaranteed by design and not production tested. Frequency stability vs. temperature is defined as (ΔfMAX - ΔfMIN)/2. Maximum power-supply variations to meet the specification are 5%. Crystal vendor specification. Holdover is defined as (fMAX - fMIN)/2 as measured within a 24-hour period. Warmup time = 1 hour. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 12: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 13: A fast-mode device can be used in a standard-mode system, but the requirement that tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does not stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 14: CB—total capacitance of one bus line in pF. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Data Transfer on I2C Serial Bus SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT _______________________________________________________________________________________ 5 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 51.84 8.0 3.5 3.0 2.5 12.8 2.0 6.0 4.0 1.5 12.8 1.0 2.0 0.5 0 3.3 3.4 3.5 -0.1 3.0 3.6 3.1 3.2 FREQUENCY vs. FTUNE DS4026 toc04 51.84 10 DEVIATION (ppm) 5 12.8 -5 -10 -15 -20 -25 -30 4000h 000h VC (V) 3.5 3.6 3.0 3.1 3.2 3.3 3FFFh 20 18 15 13 10 8 5 3 0 -3 -5 -8 -10 -13 -15 3.4 3.5 3.6 VCCD (V) PHASE NOISE (TYP) FREQUENCY vs. TEMPERATURE 20 0 3.4 VOSC (V) VCC (V) 15 3.3 DCOMP = 1 DCOMP = 0 DS4026 toc06 3.2 -5.0 -30.0 PHASE NOISE (dBc/Hz) 3.1 DS4026 toc05 3.0 6 51.84 DS4026 toc03 51.84 4.0 10.0 CURRENT (mA) 12.8 4.5 DS4026 toc02 DS4026 toc01 5.0 CURRENT (mA) CURRENT (mA) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ACTIVE-SUPPLY CURRENT vs. DRIVER POWER SUPPLY ACTIVE-SUPPLY CURRENT vs. OSCILLATOR POWER SUPPLY ACTIVE-SUPPLY CURRENT vs. POWER-SUPPLY CURRENT OFFSET (ppm) DS4026 10MHz to 51.84MHz TCXO -55.0 51.84MHz 19.44MHz -80.0 -105.0 38.88MHz -130.0 12.8MHz -155.0 -180.0 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 10 100 1000 10,000 100,000 1,000,000 OFFSET (Hz) _______________________________________________________________________________________ 10MHz to 51.84MHz TCXO PIN NAME FUNCTION 1 GNDA 2 VREF Voltage Reference Output. This pin must be decoupled with a 100μF ceramic capacitor to ground. 3 VCC Power Supply for Digital Control and Temperature Sensor. This pin must be decoupled with a 100nF capacitor to ground. 4 VOSC Ground for DAC Power Supply for Oscillator Circuit. This pin must be decoupled with a 0.1μF capacitor to ground. 5 GNDOSC 6–10 N.C. No Connection. Must be connected to ground. Ground for Oscillator Circuit 11 GND Ground for Digital Control, Temperature Sensor, and Controller Substrate 12 SDA Serial Data Input/Output. SDA is the data input/output for the I2C interface. This open-drain pin requires an external pullup resistor. 13 SCL Serial Clock Input. SCL is the clock input for the I2C Interface and is used to synchronize data movement on the serial interface. 14 GNDD Ground for Oscillator Output Driver 15 FOUT Frequency Output, CMOS Push-Pull 16 VCCD Power Supply for Oscillator Output Driver. This pin must be decoupled with a 0.1μF capacitor to ground. A 20
resistor must be placed in series between the power supply and VCCD. 20Ω GNDA VCCD 100μF ±20% CERAMIC FOUT VREF 0.1μF 3.3V ±5% GNDD DS4026 3.3V VCC SCL VOSC SDA GNDOSC GND N.C. N.C. N.C. N.C. 0.1μF 3.3V 0.1μF N.C. Figure 1. Typical Operating Circuit _______________________________________________________________________________________ 7 DS4026 Pin Description DS4026 10MHz to 51.84MHz TCXO VCC VCC TEMP SENSOR GND GND VCC SCL SDA EEPROM ARRAY A/D VCC VREF I2C INTERFACE CONTROLLER GND GND DAC DS4026 GNDA VCCD VOSC CMOS BUFFER GNDOSC FOUT GNDD Figure 2. Functional Diagram Detailed Description The DS4026 is a TCXO capable of operating at 3.3V ±5%, and it allows digital tuning of the fundamental frequency. The device is calibrated in the factory to achieve an accuracy of ±1ppm over the industrial temperature range, and its minimum pullability is ±8ppm with a typical resolution of 1ppb (typ) per LSB. The DS4026 contains the following blocks: • Oscillator block with variable capacitor for compensation • Output driver block • Temperature sensor 8 • Controller to read the temperature, control lookup table, and adjust the DAC input • DAC output to adjust the capacitive load • I2C interface to communicate with the chip The oscillator block consists of an amplifier and variable capacitor in a Pierce crystal oscillator with a crystal resonator of fundamental mode. The oscillator amplifier is a single transistor amplifier and its transconductance is temperature compensated. The variable capacitor is adjusted by the DAC to provide temperature compensation. With the FTUNEH and FTUNEL registers, a minimum pullability of ±8ppm (±5ppm for 10MHz) is achieved with a typical resolution of 1ppb (typ) per LSB. _______________________________________________________________________________________ 10MHz to 51.84MHz TCXO Address Map The temperature sensor provides a 12-bit temperature reading with a resolution of 0.0625°C. The sensor is in continuous conversion mode. If DCOMP is set, conversions continue but temperature updates are inhibited. The controller coordinates the conversion of temperature into digital codes. When the temperature reading is different from the previous one or the frequency tuning register is changed, the controller looks up the two corresponding capacitance trim codes from the lookup table at a 0.5°C increment. The trim codes are interpolated to 0.0625°C resolution. DCOMP is bit 7 of the frequency tuning register (see the Frequency Tuning Register (00h–01h), POR = 00h table). When set to logic 1, this bit’s temperature-compensation function is disabled. This disabling prevents the variable capacitor in the oscillator block from changing. However, the temperature register still performs temperature conversions. The temperature trim code from the last temperature conversion before DCOMP is enabled is used for temperature compensation. The FTUNE registers are still functional when DCOMP is disabled. Disable Compensation Update (DCOMP) The result is added with the tuning value from the frequency tuning register and loaded into the DAC registers to adjust voltage output. The monotonic DAC provides an analog voltage based on temperature compensation to drive the variable capacitor. The DS4026 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The frequency tuning registers adjust the base frequency. The frequency tuning value is represented in two’s complement data. Bit 6 of FTUNEH is the sign, bit 5 is the MSB, and bit 0 of FTUNEL is the LSB (see Table 1). When the tuning register low (01h) is programmed with a value, the next temperature update cycle sums the programmed value with the factory compensated value. This allows the user to digitally control the base frequency using the I2C protocol. These frequency tuning register bits allow the tuning of the base frequency. Each bit typically represents about 1ppb (typ). For FTUNEH = 3Fh and FTUNEL = FFh, the device pushes the base frequency by approximately +15ppm. Frequency Tuning Register (00h–01h), POR = 00h ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h DCOMP Sign Data Data Data Data Data Data POR 0 0 0 0 0 0 0 0 01h Data Data Data Data Data Data Data Data POR 0 0 0 0 0 0 0 0 Temperature Register (02h–03h) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data 02h Sign Data Data Data Data Data Data POR 0 0 0 0 0 0 0 0 03h Data Data Data Data 0 0 0 0 POR 0 0 0 0 0 0 0 0 _______________________________________________________________________________________ 9 DS4026 The output driver is a CMOS square-wave output with symmetrical rise and fall time. DS4026 10MHz to 51.84MHz TCXO Table 1. Register Map ADDRESS BIT 7 BIT 6 00 DCOMP SIGN BIT 5 BIT 4 BIT 3 01 02 SIGN 03 BIT 2 BIT 1 BIT 0 FUNCTION FTUNEH Frequency Tuning High FTUNEL Frequency Tuning Low TREGH Temperature MSB TREGL Temperature LSB I2C Serial Data Bus Read Mode In the temperature register (see the Temperature Register (02h–03h) table), temperature is represented as a 12-bit code and is accessible at location 02h and 03h. The upper 8 bits are at location 02h and the lower 4 bits are in the upper nibble of the byte at location 03h. Upon power reset, the registers are set to a +25°C default temperature and the controller starts a temperature conversion. The temperature register stores new temperature readings. The current temperature is loaded into the (user) temperature registers when a valid I2C slave address and write is received and when a word address is received. Consequently, if the two temperature registers are read in individual I2C transactions, it is possible for a temperature conversion to occur between reads, and the results can be inaccurate. To prevent this from occurring, the registers should be read using a single, multibyte read operation (Figure 5). I2C reads do not affect the internal temperature registers. The DS4026 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is defined as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS4026 operates as a slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS4026 works in both modes. The following bus protocol has been defined (Figure 3): • Data transfer can be initiated only when the bus is not busy. SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED Figure 3. I2C Data Transfer Overview 10 ______________________________________________________________________________________ STOP CONDITION OR REPEATED START CONDITION 10MHz to 51.84MHz TCXO STOP data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge (ACK) after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. S 1000001 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P S = START DATA TRANSFERRED A = ACKNOWLEDGE (X + 1 BYTES + ACKNOWLEDGE) P = STOP R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge (ACK) bit after each received byte. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge (NACK) is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Because a repeated START condition is also the beginning of the next serial transfer, the bus is not released. START data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Figures 4 and 5 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: S 1000001 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P DATA TRANSFERRED S = START (X + 1 BYTES + ACKNOWLEDGE) A = ACKNOWLEDGE NOTE: LAST DATA BYTE IS FOLLOWED BY P = STOP A NOT ACKNOWLEDGE (A) SIGNAL A = NOT ACKNOWLEDGE R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h Figure 4. Slave Receiver Mode (Write Mode) Figure 5. Slave Transmitter Mode (Read Mode) ______________________________________________________________________________________ 11 DS4026 • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. DS4026 10MHz to 51.84MHz TCXO The DS4026 can operate in the following two modes: Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. After the DS4026 acknowledges the slave address and write bit, the master transmits a word address to the DS4026. This sets the register pointer on the DS4026, with the DS4026 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS4026 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 12 Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS4026 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. The DS4026 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS4026 must receive a not acknowledge to end a read. ______________________________________________________________________________________ 10MHz to 51.84MHz TCXO TEMP RANGE OUTPUT (fC) (MHz, CMOS) DS4026S+HCC 0°C to +70°C DS4026S+HCN DS4026S+JCC DS4026S+JCN PART PIN-PACKAGE TOP MARK* 19.44 16 SO DS4026-HCC -40°C to +85°C 19.44 16 SO DS4026-HCN 0°C to +70°C 20.00 16 SO DS4026-JCC -40°C to +85°C 20.00 16 SO DS4026-JCN DS4026S+MCC 0°C to +70°C 38.88 16 SO DS4026-MCC DS4026S+MCN -40°C to +85°C 38.88 16 SO DS4026-MCN DS4026S+PCC 0°C to +70°C 40.00 16 SO DS4026-PCC DS4026S+PCN -40°C to +85°C 40.00 16 SO DS4026-PCN DS4026S+QCC 0°C to +70°C 51.84 16 SO DS4026-QCC DS4026S+QCN -40°C to +85°C 51.84 16 SO DS4026-QCN DS4026S+RCC 0°C to +70°C 24.00 16 SO DS4026-RCC DS4026S+RCN -40°C to +85°C 24.00 16 SO DS4026-RCN +Denotes a lead(Pb)-free/RoHS-compliant package. *The top mark will include a “+” for a lead(Pb)-free/RoHS-compliant device. Ordering Information—Stratum 3 PART TEMP RANGE OUTPUT (fC) (MHz, CMOS) PIN-PACKAGE TOP MARK* DS4026S3+ACN -40°C to +85°C 10.00 16 SO DS4026S3-ACN DS4026S3+BCN -40°C to +85°C 12.80 16 SO DS4026S3-BCN DS4026S3+GCN -40°C to +85°C 19.20 16 SO DS4026S3-GCN DS4026S3+JCN -40°C to +85°C 20.00 16 SO DS4026S3-JCN +Denotes a lead(Pb)-free/RoHS-compliant package. *The top mark will include a “+” for a lead(Pb)-free/RoHS-compliant device. Package Information Chip Information TRANSISTOR COUNT: 77, 712 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 SO (300 mils) W16+H1 21-0042 ______________________________________________________________________________________ 13 DS4026 Ordering Information (continued) DS4026 10MHz to 51.84MHz TCXO Revision History REVISION NUMBER REVISION DATE 0 2/07 Initial release. 1 9/07 Changed device from 12.8MHz to 51.84MHz to 10MHz to 51.84MHz; added ±5ppm (min, typ) digital frequency tuning for the 10MHz option; added new ordering information and phase noise data; changed capacitor value designators from 10nF to 0.1μF; changed push-pull value from ±15ppm (typ) to ±8ppm (min). 1–12 2 4/08 Changed maximum frequency deviation from over 10 years to over 20 years; Added Stratum 3 electrical characteristics table; added ordering information for Stratum 3 parts. 1, 5, 13 DESCRIPTION PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.