19-4541; Rev 1; 7/09
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
The DS4426 contains four I2C-adjustable current DACs
capable of sinking or sourcing current. External resistors set the full-scale range of each output. Each DAC
output has 127 sink and 127 source steps that are programmed by the I2C interface. Power-supply tracking
functionality is provided for three channels using dedicated control inputs. Once power-supply tracking is
accomplished, the current outputs default to zero. Two
address pins allow up to four DS4426 devices to exist
on the same I2C bus.
Applications
Power-Supply Adjustment
Features
♦ Four Current DACs
50µA to 200µA Adjustable Full-Scale Range
127 Settings Each for Sink and Source
♦ Power-Supply Tracking
Power-Supply Sequencing
Ramp-Up and Ramp-Down Tracking Control
Ratiometric Tracking Support
♦ +2.7V to +5.5V Operation
♦ I2C-Compatible Serial Interface
♦ Two Address Input Pins Allow Up to Four Devices
on Same I2C Bus
Power-Supply Tracking
♦ Lead-Free, 28-Pin TQFN Package (4mm x 4mm)
with Exposed Pad
Adjustable Current Sink or Source
♦ Industrial Temperature Range: -40°C to +85°C
Power-Supply Margining
Ordering Information
Pin Configuration
FS0
THR1
THR2
DNC
THR3
INN3
INP3
TOP VIEW
21
20
19
18
17
16
15
FS1 22
14
INN2
FS2 23
13
INP2
FS3 24
12
INN1
11
INP1
10
A1
9
A0
8
GND
GAIN3 25
DS4426
GAIN2 26
GAIN1 27
*EP
+
4
5
6
7
OUT1
OUT2
OUT3
SCL
3
OUT0
2
VCC
1
SDA
N.C. 28
PART
TEMP RANGE
PIN-PACKAGE
DS4426T+
-40°C to +85°C
28 TQFN-EP*
DS4426T+T&R
-40°C to +85°C
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
Functional Diagram appears at end of data sheet.
THIN QFN
(4mm × 4mm)
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS4426
General Description
DS4426
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Voltage Range on SDA, SCL Relative to GND ......-0.5V to +6.0V
Voltage Range on VCC Relative to GND ...............-0.5V to +6.0V
Voltage Range on A0, A1, FS[3:0], GAIN[3:1],
INN[3:1], INP[3:1], THR[3:1], and OUT[3:0]
Relative to GND ......................................-0.5V to (VCC + 0.5V)*
*Not to exceed +6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MAX
UNITS
2.7
5.5
V
VIH
0.7 x
VCC
VCC +
0.3
V
VIL
-0.3
0.3 x
VCC
V
40
160
k
MAX
UNITS
0.9
mA
+1
μA
1.040
V
Supply Voltage
VCC
Input Logic 1
(SDA, SCL, A0, A1)
Input Logic 0
(SDA, SCL, A0, A1)
Full-Scale Resistor Values
RFS[3:0]
CONDITIONS
(Note 1)
(Note 2)
MIN
TYP
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Current
ICC
VCC = +5.5V (Note 3)
Input Leakage Current
(SDA, SCL)
I IL
VCC = +5.5V
-1
RFS Voltage
VRFS
TA = +25°C
0.940
Reference Voltage
VREF
Temperature Coefficient
Output Leakage Current (SDA)
IL
Output-Current Low (SDA)
I OL
I/O Capacitance
CI/O
TYP
0.990
1.24
V
±100
ppm/°C
-1
VOL = +0.4V
3
VOL = +0.6V
6
+1
μA
mA
10
pF
MAX
UNITS
DAC OUTPUT CURRENT CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output Current Variation Due to
Power-Supply Change
DC source, V OUT measured at +1.2V
0.33
DC sink, VOUT measured at +1.2V
0.33
Output Current Variation Due to
Output-Voltage Change
DC source, VCC = +3.6V
DC sink, VCC = +3.6V
0.15
2
0.30
_______________________________________________________________________________________
%/V
%/V
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
Output Voltage for Sinking
Current
Output Voltage for Sourcing
Current
Full-Scale Sink Output Current
Full-Scale Source Output Current
SYMBOL
VOUT:SINK
CONDITIONS
(Note 4)
VOUT:SOURCE (Note 4)
IOUT:SINK
(Note 4)
IOUT:SOURCE (Note 4)
Output-Current Full-Scale
Accuracy
I OUT:FS
TA = +25°C
Output-Current Temperature
Coefficient
I OUT:TC
(Note 5)
MIN
MAX
UNITS
0.5
3.5
V
0
VCC 0.75
V
50
200
μA
-200
-50
μA
±5
%
Output-Current Power-Supply
Rejection Ratio
Output-Leakage Current at Zero
Current Setting
I ZERO
TYP
±130
ppm/°C
0.33
%/V
-1
+1
μA
Output-Current Differential
Linearity
DNL
(Note 6)
0.5
LSB
Output-Current Integral Linearity
INL
(Note 7)
1
LSB
MAX
UNITS
400
kHz
I2C ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C. Timing referenced to VIL(MAX) and VIH(MIN). See Figure 6.)
PARAMETER
SYMBOL
CONDITIONS
0
TYP
SCL Clock Frequency
f SCL
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
μs
Hold Time (Repeated) START
Condition
tHD:STA
0.6
μs
Low Period of SCL
tLOW
1.3
μs
High Period of SCL
tHIGH
0.6
tHD:DAT
0
Data Setup Time
t SU:DAT
100
ns
START Setup Time
t SU:STA
0.6
μs
Data Hold Time
(Note 8)
MIN
μs
0.9
μs
SDA and SCL Rise Time
tR
(Note 9)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 9)
20 +
0.1CB
300
ns
STOP Setup Time
t SU:STO
SDA and SCL Capacitive
Loading
CB
0.6
(Note 9)
μs
400
pF
_______________________________________________________________________________________
3
DS4426
DAC OUTPUT CURRENT CHARACTERISTICS (continued)
DS4426
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
POWER-SUPPLY TRACKING CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, see Figure 5.)
PARAMETER
Input Divider Ratio
Output Load
Feedback Resistor Ratio
Gain Resistor
Gain Setting Ratio
Power-Supply Tracking Gain
SYMBOL
RDIV
MIN
TYP
MAX
0.5
1
1
20
RF/RB
0.5
4.5
RG
0.8
10
RL/RG
1.4
5
RL
GVI
Power-Supply Tracking Input
Bias Current
IB
Power-Supply Tracking Input
Voltage
VIN
Unity Gain Bandwidth
CONDITIONS
GBW
RA /RB and RC/RD
RL = (RF x RE )/(RF+RE)
RL/RG = 2, RL = 5k, VCC = +3.6V,
TA = +25°C
RL/RG = 5, RL = 5k, VCC = +3.6V,
TA = +25°C
INP[3:1] and INN[3:1]
VOUT:TRK
Switch closed, VCC = +3.0V, measured at
OUT[3:1], RL = 5k
Output Current While Tracking
I OUT:TRK
RL/RG = 1.4, R G = 1k, VCC = +3.0V,
VFB = +0.8V
k
k
2.4
mA/V
3.8
6.2
0
RL/RG = 1.4; RL = 5k
Output Voltage While Tracking
UNITS
10
1
μA
VCC 1.4
V
12
0
Tracking Accuracy
1.5
V
1
mA
±600
mV
Output Leakage
IBC
Comparator Input Bias Current
IOFF
Comparator Input Offset
VOS
±5
Switch Delay
tDC
5
μs
VHYS
12.5
mV
Comparator Hysteresis
Switch open
MHz
0.5
μA
1
μA
mV
Note 1: All voltages are referenced to GND. Current entering the IC is specified positive, and current exiting the IC is negative.
Note 2: Input resistors (RFS[3:0]) must be between the specified values to ensure the device meets its accuracy and linearity specifications.
Note 3: Supply current specified with all outputs set to zero current setting and with all inputs at VCC or GND. SDA and SCL are
connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS).
Note 4: The output-voltage full-scale ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Only applies to current DAC operation, not power-supply tracking operation.
Note 5: Temperature drift excludes drift caused by external resistors.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 8: Timing shown is for fast-mode operation (400kHz). This device is also backward-compatible with I2C standard-mode timing.
Note 9: CB—Total capacitance of one bus line in pF.
4
_______________________________________________________________________________________
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
525
500
475
450
40kΩ LOAD ON FS[3:0].
VCC = +5.5V
VCC = +3.3V
550
-175
525
500
VCC = +2.7V
-225
SDA = SCL = THR[3:1] = VCC
GAIN[3:1] = OPEN
INP[3:1] = INN[3:1] = GND
SDA = SCL = THR[3:1] = VCC
GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN
INP[3:1] = INN[3:1] = GND
425
400
-250
400
3.0
3.5
4.0
4.5
5.0
5.5
-40
-20
0
20
40
60
0
80
3
4
VOUT (V)
VOLTCO (SINK)
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
175
SDA = SCL = THR[3:1] = VCC
GAIN[3:1] = OPEN
INP[3:1] = INN[3:1] = GND
150
200
150
+25°C TO -40°C
100
50
0
+25°C TO +85°C
1.5
2.0
2.5
3.0
3.5
4.0
0
25
VOUT (V)
50
75
100
50
+25°C TO +85°C
-50
-150
0
25
50
0.6
0.2
DNL (LSB)
0.4
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
-1.0
100
125
0
-0.6
75
100
-0.2
-0.4
50
125
RANGE FOR THE 50μA TO 200μA
CURRENT SOURCE AND SINK RANGE
0.8
0.2
SETTING (DEC)
75
DIFFERENTIAL LINEARITY
1.0
0.4
25
DS4426 toc06
+25°C TO -40°C
150
SETTING (DEC)
DS4426 toc07
RANGE FOR THE 50μA TO 200μA
CURRENT SOURCE AND SINK RANGE
0.6
INL (LSB)
250
125
INTEGRAL LINEARITY
0
350
SETTING (DEC)
1.0
0.8
450
-250
-50
1.0
RANGE FOR THE 50μA TO 200μA
CURRENT SINK RANGE
550
5
DS4426 toc08
200
TEMPERATURE COEFFICIENT (°C/ppm)
225
RANGE FOR THE 50μA TO 200μA
CURRENT SOURCE RANGE
250
650
DS4426 toc05
300
DS4426 toc04
40kΩ LOAD ON FS[3:0].
VCC = +5.5V
0.5
2
TEMPERATURE (°C)
250
0
1
SUPPLY VOLTAGE (V)
TEMPERATURE COEFFICIENT (°C/ppm)
2.5
-200
475
450
425
IOUT (μA)
VCC = +5.5V
IOUT (μA)
550
SUPPLY CURRENT (μA)
SUPPLY CURRENT (μA)
575
-150
DS4426 toc02
SDA = SCL = THR[3:1] = VCC
GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN
INP[3:1] = INN[3:1] = GND
575
VOLTCO (SOURCE)
600
DS4426 toc01
600
SUPPLY CURRENT
vs. TEMPERATURE
DS4426 toc03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0
25
50
75
100
125
SETTING (DEC)
_______________________________________________________________________________________
5
DS4426
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS4426
Pin Description
PIN
NAME
1
SDA
Serial Data Input/Output. I2C data pin.
FUNCTION
2
SCL
Serial Clock Input. I2C clock input.
3
VCC
Voltage Supply
4
OUT0
5, 6, 7
OUT1, OUT2, OUT3
8
GND
9
A0
I2C Address Input 0
10
A1
I2C Address Input 1
Current DAC Output
Current DAC and Tracking Control Output
Ground
11, 13, 15
INP1, INP2, INP3
Power-Supply Tracking Positive Input
12, 14, 16
INN1, INN2, INN3
Power-Supply Tracking Negative Input
17, 19, 20
THR3, THR2, THR1
18
DNC
21–24
FS0, FS1, FS2, FS3
25, 26, 27
GAIN3, GAIN2,
GAIN1
28
N.C.
—
EP
Threshold Input. Comparator input used to set threshold for tracking
enable/disable based on VREF/2.
Do Not Connect
Full-Scale Calibration Input. A resistor-to-ground on this input determines fullscale output current on the associated output.
Gain Adjustment Pin. Connect a resistor between this pin and VCC.
No Connection
Exposed Pad. No connection.
Detailed Description
The DS4426 contains four I 2 C-adjustable current
sources that are each capable of sinking and sourcing
current. Three of the current outputs (OUT[3:1]) also
have power-supply tracking circuitry that allows additional current to be sourced during power-up.
Adjustable Current DACs
Each output (OUT[3:0]) has 127 sink and 127 source
settings that are programmed through the I2C interface.
The full-scale current ranges (and corresponding step
sizes) of the outputs are determined by external resistors connected to the corresponding FS pins (see
Figure 1). The formula to determine the external resistor
values (RFS) for each output is given by:
R FS =
VRFS
× 127
16 × IFS
where IFS is the desired full-scale current value, VRFS is
the RFS voltage (see the DC Electrical Characteristics
table), and RFS is the external resistor value.
6
To calculate the output-current value (IOUT) based on the
corresponding DAC value (see Table 2 for corresponding memory addresses), use the following equation:
IOUT =
DACValue(dec)
× IFS
127
On power-up, the DS4426 current DAC outputs are set
to zero current. This is done to prevent the device from
sinking or sourcing an incorrect current before the system host controller has a chance to modify its setting.
Note, however, that if power-supply tracking is enabled
(see the Power-Supply Tracking Circuit section), then
the DS4426 can still source current at power-up.
When used in adjustable power-supply applications
(see Figure 8), the DS4426 does not affect the initial
power-up voltage of the supply because it defaults to
providing zero output current on power-up unless
power-supply tracking is enabled. As it sources or
sinks current into the feedback voltage node, it
changes the amount of output voltage required by the
regulator to reach its steady-state operating point.
_______________________________________________________________________________________
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
MSB
TRACKING
OUT[3:1] ONLY
LSB
SOURCE
OR
SINK MODE
127 POSITIONS
EACH FOR SOURCE
AND SINK MODE
CURRENT
DAC[3:0]
FS[3:0]
Power-Supply Tracking Circuit
OUT[3:0]
By making use of the power-supply tracking circuitry,
the DS4426 has the ability to source current on powerup. This current is additive with the current DAC
source/sink currents and is determined by the value of
the gain resistor, RG, and the supply voltage, VCC. This
current is controlled by the voltages presented to the
corresponding INP and INN pins, and the voltages presented to the corresponding threshold (THR) pins.
RFS[3:0]
Figure 1. Current DAC Detail
VCC
Maximum Source Current
RG
GAIN
INP
+
INN
-
GVI
OUT
SLAVE
FEEDBACK
NODE
The maximum current the DS4426 can source at
power-up using the power-supply tracking circuitry
depends on the value of the supply voltage, VCC, and
the gain resistor, RG, connected from the corresponding GAIN pin to VCC. The maximum current (IMAX) that
can be sourced to the corresponding OUT pin can be
estimated using the following equation:
SHUTDOWN
IMAX ≅
DAC
RG
The power-supply tracking circuit can be estimated
with Figure 2.
Figure 2. Gain Stage
Inputs for Power-Supply Tracking:
INP and INN
I
AT VCC = +5.0V
IMAX
GVI
-0.2
( VCC − VOUT )
+0.3
Figure 3. INP and INN Differential Inputs
V
(VINP - VINN)
Each pair of power-supply tracking inputs, INP and
INN, determines if and how much of the IMAX current is
sourced when the power-supply tracking circuit is
enabled. When the difference between the voltage presented to INP (V INP ) and INN (V INN ) is more than
approximately +0.3V, then the maximum source current, as determined by the value IMAX, is sourced into
the OUT pin connection. When the difference between
VINP and VINN is less than approximately -0.2V, then no
current is sourced into the corresponding OUT pin. The
change in current from no current to IMAX can be estimated by the power-supply tracking gain, GVI (see the
Power-Supply Tracking Characteristics table).
Figure 3 shows the typical current behavior of the
power-supply tracking circuit with respect to the voltage difference seen at the INP and INN inputs.
_______________________________________________________________________________________
7
DS4426
I2C CONTROL
Using the external resistors RFS[3:0] to set the outputcurrent range, the DS4426 provides some flexibility for
adjusting the impedances of the feedback network or
the range over which the power supply can be controlled or margined.
As a source for biasing instrumentation or other circuits,
the DS4426 provides a simple and inexpensive current
source with an I2C interface for control. The adjustable,
full-scale range allows the application to get the most
out of its 7-bit sink or source resolution.
DS4426
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
V
VMASTER
VSLAVE
DS4426 TRACKING DISABLED
VTHRESHOLD
GAIN
ERROR
TRACKING RANGE: DS4426 OVERRIDES SLAVE'S FEEDBACK LOOP
t
Figure 4. Enabling Power-Supply Tracking Using the THR Input
THR Inputs for Enabling
Power-Supply Tracking
Comparators are used to individually enable/disable
power-supply tracking based on the voltage presented
to the corresponding THR pin relative to a fixed internal
reference (VREF/2 = +0.62V). Figure 4 shows a typical
startup and shutdown plot based on the voltage presented to the THR pin. Tracking can be disabled by
connecting the corresponding THR pin to a voltage
greater than VREF/2. Below this threshold, the tracking
circuit is active.
Power-Supply Tracking in DC-DC
Power Applications
The DS4426 provides several options for power-supply
tracking control of DC-DC power supplies. In many
cases, it is desirable to prevent certain DC-DC supplies
from exceeding the voltage of other supplies. This is
often the case with the voltages applied to a digital
core and I/O. Each DS4426 supports one master with
three slave DC-DCs. See Figure 5 for more information.
8
Loop Bandwidth Consideration
Power-supply tracking is used to override each slave
DC-DC’s feedback loop during power-up and powerdown. Power-supply tracking is capable of slewing at a
much faster rate than most DC-DC converters. Care
must be exercised when selecting the loop bandwidth
of the master DC-DC, slave DC-DC, and power-supply
tracking control loop such that oscillations and overshoot are minimized.
While the slave DC-DC supplies are tracking the master
DC-DC supply, there are three time constants of concern:
1) Master BW. The master DC-DC control loop bandwidth, power-up ramp rate, and power-down ramp
rate.
2) Slave BW. The slave DC-DC supplies control loop
bandwidths.
3) Tracking BW. The DS4426 tracking circuit bandwidth.
To ensure stable operation and minimize peaking, the
bandwidths should follow the following rule:
Master BW and Slave BW < (Tracking BW/10)
_______________________________________________________________________________________
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS4426
5.0V
VCC
VCC
VOUT
0.1μF
10kΩ
10kΩ
10kΩ
MASTER
DC-DC
CONVERTER
SDA
SCL
A0
A1
I 2C
I2C CONTROL
INTERFACE
RF0
FB
FS0
VREF
REF
1.24V
RE0
RFS0
OUT0
x3
FS[3:1]
RFS[3:1]
INP[3:1]
5.0V
OUT[3:1]
INN[3:1]
RB[3:1]
RG[3:1]
VOUT
GAIN[3:1]
RA[3:1]
VREF/2
10kΩ
DS4426
SLAVE
DC-DC
CONVERTER
COMP
THR[3:1]
RF[3:1]
FB
RE[3:1]
RTHR[3:1]
RD[3:1]
RC[3:1]
Figure 5. Typical DC-DC Power-Supply Tracking Application
Ratiometric Tracking
The DS4426 can maintain a defined ratio between a
slave voltage and the master voltage where:
KSM = VSLAVE/VMASTER.
In Figure 5, this ratio is given by the following:
KSM = [RB[3:1]/(RA[3:1] + RB[3:1])]/[RD[3:1]/(RC[3:1]
+ RD[3:1])].
Nonratiometric tracking is the special case where KSM = 1.
Power-Supply Tracking Loop Gain Stability
Slave DC-DC output tracking is controlled by the
DS4426 sourcing current into the slave DC-DC's feedback loop. This changes the stability of the loop during
tracking. The amount of gain used can be adjusted by
changing the ratio of R L /R G . If oscillations occur,
increasing RG reduces gain and increases the system’s
phase margin. If the slave DC-DC has a compensation
pin, the RC network connected to this pin can also be
adjusted to improve phase margin. This pin is often
labeled COMP or ITH. A larger compensation time constant (increased R and/or increased C) often increases
the stability of the system during tracking; however, this
also modifies the DC-DC's transient response. In order
to prevent modification of the slave DC-DC’s transient
response after power-supply tracking is complete, RG
should first be modified before adjusting the compensation network. The higher the gain, the less the gain
error. Reducing the gain increases the gain error during
tracking. See Figure 4 for more information.
_______________________________________________________________________________________
9
DS4426
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
Table 1. Slave Addresses
Table 2. Memory Addresses
A1
A0
SLAVE ADDRESS (HEX)
MEMORY ADDRESS (HEX)
CURRENT SOURCE
GND
GND
90h
F8h
OUT0
GND
VCC
92h
F9h
OUT1
VCC
GND
94h
FAh
OUT2
VCC
VCC
96h
FBh
OUT3
Inputs for Tracking in DC-DC Power
Applications
When enabling/disabling the power-supply tracking, a
resistor-divider connected to the THR input sets the disable threshold (see VTHRESHOLD in Figure 4). The top
of the resistor-divider must be connected to the master
DC-DC voltage for correct operation. Below this threshold, the tracking circuit is active.
Power-Supply Sequencing
The DS4426 can be used to perform power-supply
sequencing. This is a subset of power-supply tracking
with modifications to the external resistor network. The
basic concept is that the DS4426 sources maximum
current into the slave power supply's feedback node
until a voltage in the system has risen above a specific
voltage level. By sourcing the maximum current into the
feedback node, the power supply's output is held off.
Maximum sourcing current is achieved with two steps:
1) Apply the maximum allowed input voltage across
INP and INN. Connect INP to VCC - 1.4V using a
voltage-divider to ground. Connect INN to ground.
2) Set the gain to the maximum allowed (RL/RG = 5).
The slave power supply is allowed to turn on once the
voltage on THR is greater than VREF/2. Use a resistordivider connected to the rising system voltage to scale
the trip point to VREF/2.
I2C Slave Address
The DS4426 responds to one of four I2C slave addresses determined by the state of the input on the two
address inputs. The two input states are connected to
VCC or connected to ground.
10
Memory Organization
The DS4426’s current sources are controlled by writing
to memory addresses listed in Table 2.
The format of each of the output control registers is
given by:
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
S
D6
D5
D4
D3
D2
D1
D0
where:
BIT
NAME
DESCRIPTION
POWER-ON
DEFAULT
S
Sign
Bit
Determines if DAC sources or
sinks current. For sink, S = 0.
For source, S = 1.
0b
Data
7-bit data word controlling DAC
output. Setting 0000000b
outputs zero current regardless
of the state of the sign bit.
0000000b
DX
For example:
RFS0 = 80kΩ and register 0xF8h is written to a value of
0xAAh. Use the following formula to calculate the output current:
IFS = (1.0V/80kΩ) x (127/16) = 99.22µA
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 2Ah (42
decimal). The magnitude of the output current is equal
to the following:
99.22µA x (42/127) = 32.8125µA
______________________________________________________________________________________
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers:
I 2 C Slave Address: The slave address of the
DS4426 is determined by the state of the A0 and A1
pins (see Table 1).
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 3 for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 3 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 6 for applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup-and-hold time requirements (Figure
6). Data is shifted into the device during the rising
edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 6) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse, and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses, including
when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a 1 during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 6). An
ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a
read sequence or as an indication that the device is
not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write definition, and the acknowledgement is read using the
bit-read definition.
Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
DS4426’s slave address is determined by the state
of the A0 and A1 pins (see Table 1). When the R/W
bit is 0 (such as in 90h), the master is indicating it
will write data to the slave. If R/W = 1 (91h in this
case), the master is indicating it wants to read from
the slave. If an incorrect slave address is written, the
DS4426 assumes the master is communicating with
another I2C device and ignores the communication
until the next START condition is sent.
Memory Address: During an I2C write operation,
the master must transmit a memory address to identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
______________________________________________________________________________________
11
DS4426
I2C Serial Interface Description
DS4426
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
SDA
tBUF
tF
tSP
tHD:STA
tLOW
SCL
tHIGH
tHD:STA
tSU:STA
tR
tHD:DAT
STOP
tSU:STO
tSU:DAT
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 6. I2C Timing Diagram
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
0
0
1
0
A1
A0
R/W
MSB
SLAVE
ACK
READ/
WRITE
SLAVE
ADDRESS*
b7
LSB
b6
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
b5
b4
REGISTER/MEMORY ADDRESS
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED)
90h
A) SINGLE-BYTE WRITE
-WRITE REGISTER F9h TO 00h
START
10010000
B) SINGLE-BYTE READ
-READ REGISTER F8h
START
10010000
90h
F9h
SLAVE
11111 001
ACK
SLAVE
SLAVE
00000000
ACK
ACK
F8h
SLAVE
SLAVE
11111 000
ACK
ACK
STOP
DATA
91h
REPEATED
START
10010 001
SLAVE
ACK
MASTER
NACK
STOP
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
Figure 7. I2C Communication Examples
I2C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and generate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
12
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
______________________________________________________________________________________
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
Example Calculations for an Adjustable
Power Supply
In this example, the circuit shown in Figure 8 is used to
margin a +2.0V supply by ±20%. The margined power
supply has a DC-DC converter output voltage, VOUT, of
+2.0V and a DC-DC converter feedback voltage, VFB,
of +0.8V. To determine the relationship of R0A and R0B,
start with the equation:
IOUT0 is chosen to be 100µA (midrange source/sink
current for the DS4426). Summing the currents into the
feedback node, we have the following:
IOUT0 = IR0B - IR0A
where:
IR0B =
and
R 0B
VFB =
× VOUT
R 0 A + R 0B
IR0 A =
Substituting VFB = +0.8V and VOUT = +2.0V, the relationship between R0A and R0B is determined to be:
R0A = 1.5 x R0B
4.7kΩ
VOUT − VFB
R 0A
To create a ±20% margin in the supply voltage, the
value of V OUT is set to +2.4V. With these values in
place, R 0B is calculated to be 2.67kΩ, and R 0A is
VCC
4.7kΩ
VFB
R 0B
VOUT = 2.0V*
OUT
VCC
SDA
SCL
DC-DC
CONVERTER
DS4426
OUT0
IR0A
R0A = 4kΩ
FB
VFB = 0.8V*
IR0B
GND
R0B = 2.67kΩ
FS0
IOUT0
RFS0 = 80kΩ
*VOUT AND VFB VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH VOUT AND VREF OF THE DS4426.
Figure 8. Example Typical Application Circuit
______________________________________________________________________________________
13
DS4426
Applications Information
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS4426
Functional Diagram
VCC
calculated to be 4.00kΩ. The current DAC in this configuration allows the output voltage to be moved linearly
from +1.6V to +2.4V using 127 settings. This corresponds to a resolution of 6.3mV/step.
VCC Decoupling
VCC
SDA
SCL
A0
A1
I2C CONTROL
INTERFACE
FS0
VREF
REF
1.24V
OUT0
To achieve the best results when using the DS4426,
decouple the power supply with a 0.01µF (or 0.1µF)
capacitor. Use a high-quality, ceramic, surface-mount
capacitor if possible. Surface-mount components minimize lead inductance, which improves performance.
Ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
FS1
INP1
OUT1
INN1
GAIN1
VREF/2
THR1
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 TQFN
T2844+1
21-0139
FS2
INP2
OUT2
INN2
GAIN2
VREF/2
THR2
FS3
INP3
OUT3
INN3
GAIN3
VREF/2
DS4426
THR3
GND
14
______________________________________________________________________________________
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
4/08
Initial release.
—
1
7/09
Added OUT[3:0] to the Absolute Maximum Ratings for the following condition:
Voltage Range on A0, A1, FS[3:0], GAIN[3:1], INN[3:1], INP[3:1], and THR[3:1].
2
DESCRIPTION
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
DS4426
Revision History
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