DS4M200P+33

Rev 0; 12/07 3.3V Margining Clock Oscillator with LVPECL/LVDS Output The DS4M125/DS4M133/DS4M200 are margining clock oscillators with LVPECL or LVDS outputs. They are designed to fit in a 5mm x 3.2mm ceramic package with an AT-cut fundamental-mode crystal to form a complete clock oscillator. The circuit can generate the following frequencies and their ±5% frequency deviations: 125MHz, 133.33MHz, and 200MHz. The DS4M125/ DS4M133/DS4M200 employ a low-jitter PLL to generate the frequencies. The typical phase jitter is less than 0.9ps RMS from 12kHz to 20MHz. Frequency margining is a circuit operation to change the output frequency to 5% higher or 5% lower than the nominal frequency. Frequency margining is accomplished through the margining select pin, MS. This three-state input pin accepts a three-level voltage signal to control the output frequency. In a low-level state, the output frequency is set to the nominal frequency. When set to a high-level state, the frequency output is set to the nominal frequency plus 5%. When set to the midlevel state, the frequency output is equal to the nominal frequency minus 5%. If left open, the MS pin is pulled low by an internal 100kΩ (nominal) pulldown resistor. The DS4M125/DS4M133/DS4M200 are available with either an LVPECL or LVDS output. The output can be disabled by pulling the OE pin low. When disabled, both OUTP and OUTN levels of the LVPECL driver go to the LVPECL bias voltage, while the output of the LVDS driver is a logical one. The OE input is an active-high logic signal and has an internal 100kΩ pullup resistor. When OE is in a logic-high state, the OUTP and OUTN outputs are enabled. The devices operate from a single 3.3V supply voltage. Applications Features ♦ Frequency Margining: ±5% ♦ Nominal Clock Output Frequencies: 125MHz, 133.33MHz, and 200MHz ♦ Jitter < 0.9ps RMS from 12kHz to 20MHz ♦ LVPECL or LVDS Output ♦ 3.3V Operating Voltage ♦ Operating Temperature Range: -40°C to +85°C ♦ Supply Current: < 100mA at 3.3V ♦ Excellent Power-Supply Noise Rejection ♦ 5mm x 3.2mm Ceramic LCCC Package ♦ Output Enable/Disable Ordering Information PART TEMP RANGE PIN-PACKAGE DS4M125P+33 -40°C to +85°C 10 LCCC DS4M125D+33 -40°C to +85°C 10 LCCC DS4M133P+33 -40°C to +85°C 10 LCCC DS4M133D+33 -40°C to +85°C 10 LCCC DS4M200P+33 -40°C to +85°C 10 LCCC DS4M200D+33 -40°C to +85°C 10 LCCC +Denotes a lead(Pb)-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. Pin Configuration and Selector Guide appear at end of data sheet. Memory Clocks RAID Systems Typical Operating Circuit VCC 0.1μF OUTP VCC 0.01μF 0.1μF DS4M125/ MS DS4M133/ OE DS4M200 GND OUTN LVDS OPTION 100Ω OUTP 0.01μF 50Ω DS4M125/ MS DS4M133/ OE DS4M200 GND PECL_BIAS AT VCC - 2.0V 50Ω OUTN LVPECL OPTION ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4M125/DS4M133/DS4M200 General Description DS4M125/DS4M133/DS4M200 3.3V Margining Clock Oscillator with LVPECL/LVDS Output ABSOLUTE MAXIMUM RATINGS Storage Temperature Range ...............................-55°C to +85°C Soldering Temperature (3 passes max of reflow)..........................................Refer to the IPC/JEDEC J-STD-020 Specification. Power-Supply Voltage Range (VCC) .....................-0.3V to +4.0V Continuous Power Dissipation (TA = +70°C) ...................330mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) PARAMETER Operating Voltage Range Operating Current Inactive Current SYMBOL VCC CONDITIONS (Note 1) MIN TYP MAX UNITS 3.135 3.3 3.465 V ICC_D LVDS, output loaded or unloaded 52 75 ICC_PU LVPECL, output unloaded 49 70 ICC_PI LVPECL, output loaded 74 100 VOE = V IL 52 85 MS = 0, OE = 1 125 MS = 0, OE = 1 133.33 MS = 0, OE = 1 200 ICC_OEZ mA mA OUTPUT FREQUENCY SPECIFICATIONS DS4M125 Frequency DS4M133 fO DS4M200 Frequency Stability Frequency Stability Over Temperature Initial Tolerance
fTOTAL/f O
fTEMP/f
f INITIAL/f V Frequency Change Due to
VCC
f VCC/f Frequency Change Due to Load Variation
fLOAD/f O Aging (15 Years) Phase Jitter Over temperature range, aging, load, supply, and initial tolerance (Note 3) -50 +50 ppm VCC = 3.3V -35 +35 ppm +3 ppm/V VCC = 3.3V, TA = +25°C VCC = 3.3V ±5% Accumulated Deterministic Jitter Due to Reference Spurs Accumulated Deterministic Jitter Due to Power-Supply Noise ±20 -3 ±10% variation in termination resistance
fAGING JRMS Frequency Switch Time Input-Voltage High (OE) -7 Integrated phase RMS; 12kHz to 80MHz, VCC = 3.3V, TA = +25°C 2 ppm +7 ppm < 0.9 ps No margin 155.52MHz output 0.6 ps 10kHz 12.9 100kHz (Note 4) 26.3 200kHz (Note 4) 20.1 tSWITCH (Note 5) ps 6.4 t STRT VIH ppm ±1 1MHz (Note 4) Startup Time MHz 1.0 ms 0.5 ms 0.7 x VCC _______________________________________________________________________________________ VCC V 3.3V Margining Clock Oscillator with LVPECL/LVDS Output (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) PARAMETER Input-Voltage Low (OE) Input-Leakage High (OE) SYMBOL VIL ILEAKH CONDITIONS MIN TYP MAX UNITS (Note 5) 0 0.3 x VCC V OE voltage = VCC -5 +5 μA Input-Leakage Low (OE) ILEAKL OE voltage = GND -20 -50 μA Input-Leakage High (MS) ILEAKH MS voltage = VCC 20 50 μA Input-Leakage Low (MS) ILEAKL MS voltage = GND -5 +5 μA Input Voltage: High Level (MS) VIH (Note 5) 0.75 x VCC + 0.15V VCC V Input Voltage: Mid Level (MS) VIM (Note 5) 0.25 x VCC + 0.15V 0.75 x VCC 0.15V V Input Voltage: Low Level (MS) VIL (Note 5) 0 0.25 x VCC 0.15V V 1.475 V LVDS Output High Voltage VOH 100 differential load (Notes 2, 5) Output Low Voltage VOL 100 differential load (Notes 2, 5) Differential Output Voltage |VOD| 100 differential load
|VOD| 100 differential load Change in VOD for Complementary States Offset Output Voltage Change in VOS for Complementary States Differential Output Impedance VOS
|VOS| 100 differential load (Note 2) V 250 1.125 100 differential load R OLVDS L VSSLVDSO 0.925 80 OUTN or OUTP shorted to ground and measure the current in the shorting path 425 mV 25 mV 1.275 V 150 mV 140  40 Output Current mA Output Rise Time (Differential) Output Fall Time (Differential) Duty Cycle LLVDSO OUTN and OUTP shorted together and measure the change in ICC 6.5 tRLVDSO 20% to 80% 175 tFLVDSO 80% to 20% DCYCLE_LVDS ps 175 45 ps 55 % Propagation Delay from OE Going LOW to Logical 1 at OUTP t PA1 (Figure 2) 200 ns Propagation Delay from OE Going HIGH to Output Active t P1A (Figure 2) 200 ns _______________________________________________________________________________________ 3 DS4M125/DS4M133/DS4M200 ELECTRICAL CHARACTERISTICS (continued) DS4M125/DS4M133/DS4M200 3.3V Margining Clock Oscillator with LVPECL/LVDS Output ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage (Note 2) VOH Output connected to 50 at PECL_BIAS at VCC - 2.0V Output Low Voltage (Note 2) VOL VDIFF_PECL TYP MAX UNITS VCC 1.085 VCC 0.88 V Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC 1.825 VCC 1.62 V Output connected to 50 at PECL_BIAS at VCC - 2.0V 0.595 LVPECL Differential Voltage 0.710 V Rise Time tR-PECL 20% to 80% 200 ps Fall Time tF-PECL 80% to 20% 200 ps Duty Cycle DCYCLE_PECL 45 55 % Propagation Delay from OE Going LOW to Output Three-Stated t PAZ (Figure 3) 200 ns Propagation Delay from OE Going HIGH to Output Active t PZA (Figure 3) 200 ns Note 1: Limits at -40°C are guaranteed by design and are not production tested. Typical values are at +25°C and 3.3V, unless otherwise noted. Note 2: AC parameters are guaranteed by design and characterization and are not production tested. Note 3: Frequency stability is calculated as: ΔfTOTAL = ΔfINITIAL + ΔfTEMP + (ΔfVCC x 0.165) + ΔfLOAD + ΔfAGING. Note 4: Supply induced jitter is measured with a 50mVP-P sine wave forced on VCC. Deterministic jitter is calculated by measuring the power of the resulting tone seen on a spectrum analyzer. Note 5: Voltage referenced to ground. SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM fM = 4 SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM (dBc/Hz) 125MHz 133.33MHz 200MHz 10Hz -70 -75 -70 100Hz -100 -105 -100 1kHz -118 -121 -115 10kHz -118 -122 -117 100kHz -124 -126 -122 1MHz -142 -141 -138 10MHz -150 -150 -150 20MHz -150 -150 -150 _______________________________________________________________________________________ 3.3V Margining Clock Oscillator with LVPECL/LVDS Output PIN NAME 1 OE FUNCTION Active-High Output Enable. Has an internal pullup 100k
resistor. 2 MS 3 GND Ground Margin Select. Three-level input with a 100k
pulldown resistor. 4 OUTP Positive Output for LVPECL or LVDS 5 OUTN Negative Output for LVPECL or LVDS 6 VCC Supply Voltage 7–10 N.C. No Connection. Must be floated. — EP Exposed Paddle. The exposed pad must be used for thermal relief. This pad must be connected to ground. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) CURRENT vs. TEMPERATURE 0 -3 -5 fO + 5% 57 55 53 51 -8 fO - 5% -10 59 ICC (mA) DS4M125/DS4M133/DS4M200 toc01 fOUT DEVIATION (ppm) 3 DS4M125/DS4M133/DS4M200 toc02 FREQUENCY vs. TEMPERATURE 5 49 fO 47 -13 -15 45 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) _______________________________________________________________________________________ 5 DS4M125/DS4M133/DS4M200 Pin Description DS4M125/DS4M133/DS4M200 3.3V Margining Clock Oscillator with LVPECL/LVDS Output VCC X1 THREESTATE PHASE DET X2 OE LC-VCO FILTER DIVP OUTP DIVOUT OUTSELN OUTDRV OUTN DS4M125/ DS4M133/ DS4M200 DIVFB FREQUENCY SELECTION THREELEVEL DECODER MS GND Figure 1. Functional Diagram Detailed Description The DS4M125/DS4M133/DS4M200 consist of an oscillator designed to oscillate with a fundamental-mode crystal and a PLL to synthesize the base frequency with its ±5% deviations. The output interface is either LVPECL or LVDS. The ±5% frequency deviation is controlled through a three-level margining select (MS) pin. This three-state input pin accepts a three-level voltage signal to control the output frequency. In a low-level state, the output frequency is set to the nominal frequency. When set to a high-level state, the frequency output is set to the nominal frequency plus 5%. When set to the mid-level state, the frequency output is equal to the nominal frequency minus 5%. The MS pin has an internal 100kΩ pulldown resistor. When the pin is left floating, the devices output a nominal frequency. The devices are available with either LVDS or LVPECL output drivers. When the OE signal is low, the LVPECL output driver is turned off and the output voltage goes to the PECL_BIAS level of VCC - 2.0V, while the LVDS outputs are a logical one. The OE pin has an internal 100kΩ pullup resistor. When the pin is left floating, the device output is active. 0.7 x VCC OE 0.7 x VCC 0.3 x VCC tP1A tPA1 OE 0.3 x VCC tPZA tPAZ OUTP OUTP OUTN Figure 2. LVDS Output Timing Diagram When OE Is Enabled and Disabled 6 OUTN PECL_BIAS PECL_BIAS PECL_BIAS PECL_BIAS Figure 3. LVPECL Output Timing Diagram When OE Is Enabled and Disabled _______________________________________________________________________________________ 3.3V Margining Clock Oscillator with LVPECL/LVDS Output PART FREQUENCY (NOM) (MHz) OUTPUT TYPE TOP MARK Chip Information SUBSTRATE CONNECTED TO GROUND PROCESS: BiPOLAR SiGe DS4M125P+33 125 LVPECL MEP DS4M125D+33 125 LVDS MED DS4M133P+33 133.33 LVPECL MFP DS4M133D+33 133.33 LVDS MFD THETA-JA (°C/W) DS4M200P+33 200 LVPECL MJP 90 DS4M200D+33 200 LVDS MJD +Denotes a lead-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. A + appears anywhere on the top mark. Pin Configuration Thermal Information Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 LCCC L1053+H2 21-0389 TOP VIEW N.C. N.C. + OE 1 MS 2 GND 3 DS4M125/ DS4M133/ DS4M200 *EP N.C. 6 VCC 5 OUTN 4 OUTP N.C. (5.00mm × 3.20mm × 1.49mm) *EXPOSED PAD Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. DS4M125/DS4M133/DS4M200 Selector Guide